Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 1 | #include <linux/bitops.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | #include <linux/serial_core.h> |
Paul Mundt | edad1f2 | 2009-11-25 16:23:35 +0900 | [diff] [blame] | 3 | #include <linux/io.h> |
Magnus Damm | 69edbba | 2008-12-25 18:17:34 +0900 | [diff] [blame] | 4 | #include <linux/gpio.h> |
Markus Brunner | 3ea6bc3 | 2007-08-20 08:59:33 +0900 | [diff] [blame] | 5 | |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 6 | #define SCI_MAJOR 204 |
| 7 | #define SCI_MINOR_START 8 |
| 8 | |
| 9 | |
| 10 | /* |
| 11 | * SCI register subset common for all port types. |
| 12 | * Not all registers will exist on all parts. |
| 13 | */ |
| 14 | enum { |
| 15 | SCSMR, /* Serial Mode Register */ |
| 16 | SCBRR, /* Bit Rate Register */ |
| 17 | SCSCR, /* Serial Control Register */ |
| 18 | SCxSR, /* Serial Status Register */ |
| 19 | SCFCR, /* FIFO Control Register */ |
| 20 | SCFDR, /* FIFO Data Count Register */ |
| 21 | SCxTDR, /* Transmit (FIFO) Data Register */ |
| 22 | SCxRDR, /* Receive (FIFO) Data Register */ |
| 23 | SCLSR, /* Line Status Register */ |
| 24 | SCTFDR, /* Transmit FIFO Data Count Register */ |
| 25 | SCRFDR, /* Receive FIFO Data Count Register */ |
| 26 | SCSPTR, /* Serial Port Register */ |
| 27 | HSSRR, /* Sampling Rate Register */ |
Geert Uytterhoeven | c097abc | 2015-04-30 18:21:27 +0200 | [diff] [blame] | 28 | SCPCR, /* Serial Port Control Register */ |
| 29 | SCPDR, /* Serial Port Data Register */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 30 | |
| 31 | SCIx_NR_REGS, |
| 32 | }; |
| 33 | |
| 34 | |
| 35 | /* SCSMR (Serial Mode Register) */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 36 | #define SCSMR_CHR BIT(6) /* 7-bit Character Length */ |
| 37 | #define SCSMR_PE BIT(5) /* Parity Enable */ |
| 38 | #define SCSMR_ODD BIT(4) /* Odd Parity */ |
| 39 | #define SCSMR_STOP BIT(3) /* Stop Bit Length */ |
| 40 | #define SCSMR_CKS 0x0003 /* Clock Select */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 41 | |
| 42 | /* Serial Control Register, SCIFA/SCIFB only bits */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 43 | #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */ |
| 44 | #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 45 | |
| 46 | /* SCxSR (Serial Status Register) on SCI */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 47 | #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */ |
| 48 | #define SCI_RDRF BIT(6) /* Receive Data Register Full */ |
| 49 | #define SCI_ORER BIT(5) /* Overrun Error */ |
| 50 | #define SCI_FER BIT(4) /* Framing Error */ |
| 51 | #define SCI_PER BIT(3) /* Parity Error */ |
| 52 | #define SCI_TEND BIT(2) /* Transmit End */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 53 | |
| 54 | #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) |
| 55 | |
| 56 | /* SCxSR (Serial Status Register) on SCIF, HSCIF */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 57 | #define SCIF_ER BIT(7) /* Receive Error */ |
| 58 | #define SCIF_TEND BIT(6) /* Transmission End */ |
| 59 | #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */ |
| 60 | #define SCIF_BRK BIT(4) /* Break Detect */ |
| 61 | #define SCIF_FER BIT(3) /* Framing Error */ |
| 62 | #define SCIF_PER BIT(2) /* Parity Error */ |
| 63 | #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */ |
| 64 | #define SCIF_DR BIT(0) /* Receive Data Ready */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 65 | |
| 66 | #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| 67 | |
| 68 | /* SCFCR (FIFO Control Register) */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 69 | #define SCFCR_MCE BIT(3) /* Modem Control Enable */ |
| 70 | #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ |
| 71 | #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ |
| 72 | #define SCFCR_LOOP BIT(0) /* Loopback Test */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 73 | |
| 74 | /* SCSPTR (Serial Port Register), optional */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 75 | #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */ |
| 76 | #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */ |
| 77 | #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */ |
| 78 | #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */ |
| 79 | #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */ |
| 80 | #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 81 | |
| 82 | /* HSSRR HSCIF */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 83 | #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 84 | |
Geert Uytterhoeven | c097abc | 2015-04-30 18:21:27 +0200 | [diff] [blame] | 85 | /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 86 | #define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */ |
| 87 | #define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */ |
Geert Uytterhoeven | c097abc | 2015-04-30 18:21:27 +0200 | [diff] [blame] | 88 | |
| 89 | /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */ |
Geert Uytterhoeven | d94a0a3 | 2015-04-30 18:21:29 +0200 | [diff] [blame^] | 90 | #define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */ |
| 91 | #define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */ |
Geert Uytterhoeven | c097abc | 2015-04-30 18:21:27 +0200 | [diff] [blame] | 92 | |
Geert Uytterhoeven | c27ffc1 | 2015-04-30 18:21:25 +0200 | [diff] [blame] | 93 | |
Paul Mundt | 15c73aa | 2008-10-02 19:47:12 +0900 | [diff] [blame] | 94 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
Paul Mundt | 15c73aa | 2008-10-02 19:47:12 +0900 | [diff] [blame] | 95 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) |
| 96 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) |
| 97 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) |
| 98 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) |
| 99 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) |
Paul Mundt | debf950 | 2011-06-08 18:19:37 +0900 | [diff] [blame] | 100 | |
Laurent Pinchart | 3ae988d | 2013-12-06 10:59:17 +0100 | [diff] [blame] | 101 | #define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask) |
Paul Mundt | 15c73aa | 2008-10-02 19:47:12 +0900 | [diff] [blame] | 102 | |
Markus Brunner | 3ea6bc3 | 2007-08-20 08:59:33 +0900 | [diff] [blame] | 103 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
Yoshihiro Shimoda | 31a49c4 | 2007-12-26 11:45:06 +0900 | [diff] [blame] | 104 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
Magnus Damm | 8a77b8d | 2010-02-05 11:15:33 +0000 | [diff] [blame] | 105 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
Magnus Damm | 6d9598e | 2010-11-17 10:59:31 +0000 | [diff] [blame] | 106 | defined(CONFIG_ARCH_SH73A0) || \ |
Kuninori Morimoto | 6c01ba4 | 2011-11-10 18:45:52 -0800 | [diff] [blame] | 107 | defined(CONFIG_ARCH_R8A7740) |
| 108 | |
Paul Mundt | b12bb29 | 2012-03-30 19:50:15 +0900 | [diff] [blame] | 109 | # define SCxSR_RDxF_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfffc) |
| 110 | # define SCxSR_ERROR_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfd73) |
| 111 | # define SCxSR_TDxE_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffdf) |
| 112 | # define SCxSR_BREAK_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffe3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
| 115 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) |
| 116 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) |
| 117 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) |
| 118 | #endif |
| 119 | |