blob: 5282738375ae309d225c06ba5689f881759c0a14 [file] [log] [blame]
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +02001#include <linux/bitops.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07002#include <linux/serial_core.h>
Paul Mundtedad1f22009-11-25 16:23:35 +09003#include <linux/io.h>
Magnus Damm69edbba2008-12-25 18:17:34 +09004#include <linux/gpio.h>
Markus Brunner3ea6bc32007-08-20 08:59:33 +09005
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +02006#define SCI_MAJOR 204
7#define SCI_MINOR_START 8
8
9
10/*
11 * SCI register subset common for all port types.
12 * Not all registers will exist on all parts.
13 */
14enum {
15 SCSMR, /* Serial Mode Register */
16 SCBRR, /* Bit Rate Register */
17 SCSCR, /* Serial Control Register */
18 SCxSR, /* Serial Status Register */
19 SCFCR, /* FIFO Control Register */
20 SCFDR, /* FIFO Data Count Register */
21 SCxTDR, /* Transmit (FIFO) Data Register */
22 SCxRDR, /* Receive (FIFO) Data Register */
23 SCLSR, /* Line Status Register */
24 SCTFDR, /* Transmit FIFO Data Count Register */
25 SCRFDR, /* Receive FIFO Data Count Register */
26 SCSPTR, /* Serial Port Register */
27 HSSRR, /* Sampling Rate Register */
Geert Uytterhoevenc097abc2015-04-30 18:21:27 +020028 SCPCR, /* Serial Port Control Register */
29 SCPDR, /* Serial Port Data Register */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020030
31 SCIx_NR_REGS,
32};
33
34
35/* SCSMR (Serial Mode Register) */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020036#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
37#define SCSMR_PE BIT(5) /* Parity Enable */
38#define SCSMR_ODD BIT(4) /* Odd Parity */
39#define SCSMR_STOP BIT(3) /* Stop Bit Length */
40#define SCSMR_CKS 0x0003 /* Clock Select */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020041
42/* Serial Control Register, SCIFA/SCIFB only bits */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020043#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
44#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020045
46/* SCxSR (Serial Status Register) on SCI */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020047#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
48#define SCI_RDRF BIT(6) /* Receive Data Register Full */
49#define SCI_ORER BIT(5) /* Overrun Error */
50#define SCI_FER BIT(4) /* Framing Error */
51#define SCI_PER BIT(3) /* Parity Error */
52#define SCI_TEND BIT(2) /* Transmit End */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020053
54#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
55
56/* SCxSR (Serial Status Register) on SCIF, HSCIF */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020057#define SCIF_ER BIT(7) /* Receive Error */
58#define SCIF_TEND BIT(6) /* Transmission End */
59#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
60#define SCIF_BRK BIT(4) /* Break Detect */
61#define SCIF_FER BIT(3) /* Framing Error */
62#define SCIF_PER BIT(2) /* Parity Error */
63#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
64#define SCIF_DR BIT(0) /* Receive Data Ready */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020065
66#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
67
68/* SCFCR (FIFO Control Register) */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020069#define SCFCR_MCE BIT(3) /* Modem Control Enable */
70#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
71#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
72#define SCFCR_LOOP BIT(0) /* Loopback Test */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020073
74/* SCSPTR (Serial Port Register), optional */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020075#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */
76#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */
77#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */
78#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */
79#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
80#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020081
82/* HSSRR HSCIF */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020083#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020084
Geert Uytterhoevenc097abc2015-04-30 18:21:27 +020085/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020086#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */
87#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */
Geert Uytterhoevenc097abc2015-04-30 18:21:27 +020088
89/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
Geert Uytterhoevend94a0a32015-04-30 18:21:29 +020090#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */
91#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */
Geert Uytterhoevenc097abc2015-04-30 18:21:27 +020092
Geert Uytterhoevenc27ffc12015-04-30 18:21:25 +020093
Paul Mundt15c73aa2008-10-02 19:47:12 +090094#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
Paul Mundt15c73aa2008-10-02 19:47:12 +090095#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
96#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
97#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
98#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
99#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
Paul Mundtdebf9502011-06-08 18:19:37 +0900100
Laurent Pinchart3ae988d2013-12-06 10:59:17 +0100101#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
Paul Mundt15c73aa2008-10-02 19:47:12 +0900102
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900103#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900104 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
Magnus Damm8a77b8d2010-02-05 11:15:33 +0000105 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
Magnus Damm6d9598e2010-11-17 10:59:31 +0000106 defined(CONFIG_ARCH_SH73A0) || \
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -0800107 defined(CONFIG_ARCH_R8A7740)
108
Paul Mundtb12bb292012-03-30 19:50:15 +0900109# define SCxSR_RDxF_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfffc)
110# define SCxSR_ERROR_CLEAR(port) (serial_port_in(port, SCxSR) & 0xfd73)
111# define SCxSR_TDxE_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffdf)
112# define SCxSR_BREAK_CLEAR(port) (serial_port_in(port, SCxSR) & 0xffe3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
115# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
116# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
117# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
118#endif
119