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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
Jeff Garzik03a8c662006-06-27 07:57:22 -040028 [link no longer provides useful info -jgarzik]
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30*/
31
32#define DRV_NAME "via-rhine"
Andy Gospodarekd5b20692006-09-11 17:39:18 -040033#define DRV_VERSION "1.4.2"
34#define DRV_RELDATE "Sept-11-2006"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36
37/* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
39
40static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41static int max_interrupt_work = 20;
42
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
45static int rx_copybreak;
46
Roger Luethib933b4d2006-08-14 23:00:21 -070047/* Work-around for broken BIOSes: they are unable to get the chip back out of
48 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
49static int avoid_D3;
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051/*
52 * In case you are looking for 'options[]' or 'full_duplex[]', they
53 * are gone. Use ethtool(8) instead.
54 */
55
56/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
57 The Rhine has a 64 element 8390-like hash table. */
58static const int multicast_filter_limit = 32;
59
60
61/* Operational parameters that are set at compile time. */
62
63/* Keep the ring sizes a power of two for compile efficiency.
64 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
65 Making the Tx ring too large decreases the effectiveness of channel
66 bonding and packet priority.
67 There are no ill effects from too-large receive rings. */
68#define TX_RING_SIZE 16
69#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
Roger Luethi633949a2006-08-14 23:00:17 -070070#ifdef CONFIG_VIA_RHINE_NAPI
71#define RX_RING_SIZE 64
72#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070073#define RX_RING_SIZE 16
Roger Luethi633949a2006-08-14 23:00:17 -070074#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76
77/* Operational parameters that usually are not changed. */
78
79/* Time in jiffies before concluding the transmitter is hung. */
80#define TX_TIMEOUT (2*HZ)
81
82#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
83
84#include <linux/module.h>
85#include <linux/moduleparam.h>
86#include <linux/kernel.h>
87#include <linux/string.h>
88#include <linux/timer.h>
89#include <linux/errno.h>
90#include <linux/ioport.h>
91#include <linux/slab.h>
92#include <linux/interrupt.h>
93#include <linux/pci.h>
Domen Puncer1e7f0bd2005-06-26 18:22:14 -040094#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070095#include <linux/netdevice.h>
96#include <linux/etherdevice.h>
97#include <linux/skbuff.h>
98#include <linux/init.h>
99#include <linux/delay.h>
100#include <linux/mii.h>
101#include <linux/ethtool.h>
102#include <linux/crc32.h>
103#include <linux/bitops.h>
104#include <asm/processor.h> /* Processor type for cache alignment. */
105#include <asm/io.h>
106#include <asm/irq.h>
107#include <asm/uaccess.h>
108
109/* These identify the driver base version and may not be removed. */
110static char version[] __devinitdata =
111KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
112
113/* This driver was written to use PCI memory space. Some early versions
114 of the Rhine may only work correctly with I/O space accesses. */
115#ifdef CONFIG_VIA_RHINE_MMIO
116#define USE_MMIO
117#else
118#endif
119
120MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
121MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
122MODULE_LICENSE("GPL");
123
124module_param(max_interrupt_work, int, 0);
125module_param(debug, int, 0);
126module_param(rx_copybreak, int, 0);
Roger Luethib933b4d2006-08-14 23:00:21 -0700127module_param(avoid_D3, bool, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
129MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
130MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
Roger Luethib933b4d2006-08-14 23:00:21 -0700131MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133/*
134 Theory of Operation
135
136I. Board Compatibility
137
138This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
139controller.
140
141II. Board-specific settings
142
143Boards with this chip are functional only in a bus-master PCI slot.
144
145Many operational settings are loaded from the EEPROM to the Config word at
146offset 0x78. For most of these settings, this driver assumes that they are
147correct.
148If this driver is compiled to use PCI memory space operations the EEPROM
149must be configured to enable memory ops.
150
151III. Driver operation
152
153IIIa. Ring buffers
154
155This driver uses two statically allocated fixed-size descriptor lists
156formed into rings by a branch from the final descriptor to the beginning of
157the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
158
159IIIb/c. Transmit/Receive Structure
160
161This driver attempts to use a zero-copy receive and transmit scheme.
162
163Alas, all data buffers are required to start on a 32 bit boundary, so
164the driver must often copy transmit packets into bounce buffers.
165
166The driver allocates full frame size skbuffs for the Rx ring buffers at
167open() time and passes the skb->data field to the chip as receive data
168buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
169a fresh skbuff is allocated and the frame is copied to the new skbuff.
170When the incoming frame is larger, the skbuff is passed directly up the
171protocol stack. Buffers consumed this way are replaced by newly allocated
172skbuffs in the last phase of rhine_rx().
173
174The RX_COPYBREAK value is chosen to trade-off the memory wasted by
175using a full-sized skbuff for small frames vs. the copying costs of larger
176frames. New boards are typically used in generously configured machines
177and the underfilled buffers have negligible impact compared to the benefit of
178a single allocation size, so the default value of zero results in never
179copying packets. When copying is done, the cost is usually mitigated by using
180a combined copy/checksum routine. Copying also preloads the cache, which is
181most useful with small frames.
182
183Since the VIA chips are only able to transfer data to buffers on 32 bit
184boundaries, the IP header at offset 14 in an ethernet frame isn't
185longword aligned for further processing. Copying these unaligned buffers
186has the beneficial effect of 16-byte aligning the IP header.
187
188IIId. Synchronization
189
190The driver runs as two independent, single-threaded flows of control. One
191is the send-packet routine, which enforces single-threaded use by the
192dev->priv->lock spinlock. The other thread is the interrupt handler, which
193is single threaded by the hardware and interrupt handling software.
194
195The send packet thread has partial control over the Tx ring. It locks the
196dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
197is not available it stops the transmit queue by calling netif_stop_queue.
198
199The interrupt handler has exclusive control over the Rx ring and records stats
200from the Tx ring. After reaping the stats, it marks the Tx queue entry as
201empty by incrementing the dirty_tx mark. If at least half of the entries in
202the Rx ring are available the transmit queue is woken up if it was stopped.
203
204IV. Notes
205
206IVb. References
207
208Preliminary VT86C100A manual from http://www.via.com.tw/
209http://www.scyld.com/expert/100mbps.html
210http://www.scyld.com/expert/NWay.html
211ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
212ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
213
214
215IVc. Errata
216
217The VT86C100A manual is not reliable information.
218The 3043 chip does not handle unaligned transmit or receive buffers, resulting
219in significant performance degradation for bounce buffer copies on transmit
220and unaligned IP headers on receive.
221The chip does not pad to minimum transmit length.
222
223*/
224
225
226/* This table drives the PCI probe routines. It's mostly boilerplate in all
227 of the drivers, and will likely be provided by some future kernel.
228 Note the matching code -- the first table entry matchs all 56** cards but
229 second only the 1234 card.
230*/
231
232enum rhine_revs {
233 VT86C100A = 0x00,
234 VTunknown0 = 0x20,
235 VT6102 = 0x40,
236 VT8231 = 0x50, /* Integrated MAC */
237 VT8233 = 0x60, /* Integrated MAC */
238 VT8235 = 0x74, /* Integrated MAC */
239 VT8237 = 0x78, /* Integrated MAC */
240 VTunknown1 = 0x7C,
241 VT6105 = 0x80,
242 VT6105_B0 = 0x83,
243 VT6105L = 0x8A,
244 VT6107 = 0x8C,
245 VTunknown2 = 0x8E,
246 VT6105M = 0x90, /* Management adapter */
247};
248
249enum rhine_quirks {
250 rqWOL = 0x0001, /* Wake-On-LAN support */
251 rqForceReset = 0x0002,
252 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
253 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
254 rqRhineI = 0x0100, /* See comment below */
255};
256/*
257 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
258 * MMIO as well as for the collision counter and the Tx FIFO underflow
259 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
260 */
261
262/* Beware of PCI posted writes */
263#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
264
Jeff Garzik46009c82006-06-27 09:12:38 -0400265static const struct pci_device_id rhine_pci_tbl[] = {
266 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
267 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
268 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
269 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 { } /* terminate list */
271};
272MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
273
274
275/* Offsets to the device registers. */
276enum register_offsets {
277 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
278 ChipCmd1=0x09,
279 IntrStatus=0x0C, IntrEnable=0x0E,
280 MulticastFilter0=0x10, MulticastFilter1=0x14,
281 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
282 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
283 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
284 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
285 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
286 StickyHW=0x83, IntrStatus2=0x84,
287 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
288 WOLcrClr1=0xA6, WOLcgClr=0xA7,
289 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
290};
291
292/* Bits in ConfigD */
293enum backoff_bits {
294 BackOptional=0x01, BackModify=0x02,
295 BackCaptureEffect=0x04, BackRandom=0x08
296};
297
298#ifdef USE_MMIO
299/* Registers we check that mmio and reg are the same. */
300static const int mmio_verify_registers[] = {
301 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
302 0
303};
304#endif
305
306/* Bits in the interrupt status/mask registers. */
307enum intr_status_bits {
308 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
309 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
310 IntrPCIErr=0x0040,
311 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
312 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
313 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
314 IntrRxWakeUp=0x8000,
315 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
316 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
317 IntrTxErrSummary=0x082218,
318};
319
320/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
321enum wol_bits {
322 WOLucast = 0x10,
323 WOLmagic = 0x20,
324 WOLbmcast = 0x30,
325 WOLlnkon = 0x40,
326 WOLlnkoff = 0x80,
327};
328
329/* The Rx and Tx buffer descriptors. */
330struct rx_desc {
331 s32 rx_status;
332 u32 desc_length; /* Chain flag, Buffer/frame length */
333 u32 addr;
334 u32 next_desc;
335};
336struct tx_desc {
337 s32 tx_status;
338 u32 desc_length; /* Chain flag, Tx Config, Frame length */
339 u32 addr;
340 u32 next_desc;
341};
342
343/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
344#define TXDESC 0x00e08000
345
346enum rx_status_bits {
347 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
348};
349
350/* Bits in *_desc.*_status */
351enum desc_status_bits {
352 DescOwn=0x80000000
353};
354
355/* Bits in ChipCmd. */
356enum chip_cmd_bits {
357 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
358 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
359 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
360 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
361};
362
363struct rhine_private {
364 /* Descriptor rings */
365 struct rx_desc *rx_ring;
366 struct tx_desc *tx_ring;
367 dma_addr_t rx_ring_dma;
368 dma_addr_t tx_ring_dma;
369
370 /* The addresses of receive-in-place skbuffs. */
371 struct sk_buff *rx_skbuff[RX_RING_SIZE];
372 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
373
374 /* The saved address of a sent-in-place packet/buffer, for later free(). */
375 struct sk_buff *tx_skbuff[TX_RING_SIZE];
376 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
377
Roger Luethi4be5de22006-04-04 20:49:16 +0200378 /* Tx bounce buffers (Rhine-I only) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 unsigned char *tx_buf[TX_RING_SIZE];
380 unsigned char *tx_bufs;
381 dma_addr_t tx_bufs_dma;
382
383 struct pci_dev *pdev;
384 long pioaddr;
385 struct net_device_stats stats;
386 spinlock_t lock;
387
388 /* Frequently used values: keep some adjacent for cache effect. */
389 u32 quirks;
390 struct rx_desc *rx_head_desc;
391 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
392 unsigned int cur_tx, dirty_tx;
393 unsigned int rx_buf_sz; /* Based on MTU+slack. */
394 u8 wolopts;
395
396 u8 tx_thresh, rx_thresh;
397
398 struct mii_if_info mii_if;
399 void __iomem *base;
400};
401
402static int mdio_read(struct net_device *dev, int phy_id, int location);
403static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
404static int rhine_open(struct net_device *dev);
405static void rhine_tx_timeout(struct net_device *dev);
406static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100407static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408static void rhine_tx(struct net_device *dev);
Roger Luethi633949a2006-08-14 23:00:17 -0700409static int rhine_rx(struct net_device *dev, int limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410static void rhine_error(struct net_device *dev, int intr_status);
411static void rhine_set_rx_mode(struct net_device *dev);
412static struct net_device_stats *rhine_get_stats(struct net_device *dev);
413static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
Jeff Garzik7282d492006-09-13 14:30:00 -0400414static const struct ethtool_ops netdev_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415static int rhine_close(struct net_device *dev);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -0700416static void rhine_shutdown (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417
418#define RHINE_WAIT_FOR(condition) do { \
419 int i=1024; \
420 while (!(condition) && --i) \
421 ; \
422 if (debug > 1 && i < 512) \
423 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
424 DRV_NAME, 1024-i, __func__, __LINE__); \
425} while(0)
426
427static inline u32 get_intr_status(struct net_device *dev)
428{
429 struct rhine_private *rp = netdev_priv(dev);
430 void __iomem *ioaddr = rp->base;
431 u32 intr_status;
432
433 intr_status = ioread16(ioaddr + IntrStatus);
434 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
435 if (rp->quirks & rqStatusWBRace)
436 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
437 return intr_status;
438}
439
440/*
441 * Get power related registers into sane state.
442 * Notify user about past WOL event.
443 */
444static void rhine_power_init(struct net_device *dev)
445{
446 struct rhine_private *rp = netdev_priv(dev);
447 void __iomem *ioaddr = rp->base;
448 u16 wolstat;
449
450 if (rp->quirks & rqWOL) {
451 /* Make sure chip is in power state D0 */
452 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
453
454 /* Disable "force PME-enable" */
455 iowrite8(0x80, ioaddr + WOLcgClr);
456
457 /* Clear power-event config bits (WOL) */
458 iowrite8(0xFF, ioaddr + WOLcrClr);
459 /* More recent cards can manage two additional patterns */
460 if (rp->quirks & rq6patterns)
461 iowrite8(0x03, ioaddr + WOLcrClr1);
462
463 /* Save power-event status bits */
464 wolstat = ioread8(ioaddr + PwrcsrSet);
465 if (rp->quirks & rq6patterns)
466 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
467
468 /* Clear power-event status bits */
469 iowrite8(0xFF, ioaddr + PwrcsrClr);
470 if (rp->quirks & rq6patterns)
471 iowrite8(0x03, ioaddr + PwrcsrClr1);
472
473 if (wolstat) {
474 char *reason;
475 switch (wolstat) {
476 case WOLmagic:
477 reason = "Magic packet";
478 break;
479 case WOLlnkon:
480 reason = "Link went up";
481 break;
482 case WOLlnkoff:
483 reason = "Link went down";
484 break;
485 case WOLucast:
486 reason = "Unicast packet";
487 break;
488 case WOLbmcast:
489 reason = "Multicast/broadcast packet";
490 break;
491 default:
492 reason = "Unknown";
493 }
494 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
495 DRV_NAME, reason);
496 }
497 }
498}
499
500static void rhine_chip_reset(struct net_device *dev)
501{
502 struct rhine_private *rp = netdev_priv(dev);
503 void __iomem *ioaddr = rp->base;
504
505 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
506 IOSYNC;
507
508 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
509 printk(KERN_INFO "%s: Reset not complete yet. "
510 "Trying harder.\n", DRV_NAME);
511
512 /* Force reset */
513 if (rp->quirks & rqForceReset)
514 iowrite8(0x40, ioaddr + MiscCmd);
515
516 /* Reset can take somewhat longer (rare) */
517 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
518 }
519
520 if (debug > 1)
521 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
522 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
523 "failed" : "succeeded");
524}
525
526#ifdef USE_MMIO
527static void enable_mmio(long pioaddr, u32 quirks)
528{
529 int n;
530 if (quirks & rqRhineI) {
531 /* More recent docs say that this bit is reserved ... */
532 n = inb(pioaddr + ConfigA) | 0x20;
533 outb(n, pioaddr + ConfigA);
534 } else {
535 n = inb(pioaddr + ConfigD) | 0x80;
536 outb(n, pioaddr + ConfigD);
537 }
538}
539#endif
540
541/*
542 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
543 * (plus 0x6C for Rhine-I/II)
544 */
545static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
546{
547 struct rhine_private *rp = netdev_priv(dev);
548 void __iomem *ioaddr = rp->base;
549
550 outb(0x20, pioaddr + MACRegEEcsr);
551 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
552
553#ifdef USE_MMIO
554 /*
555 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
556 * MMIO. If reloading EEPROM was done first this could be avoided, but
557 * it is not known if that still works with the "win98-reboot" problem.
558 */
559 enable_mmio(pioaddr, rp->quirks);
560#endif
561
562 /* Turn off EEPROM-controlled wake-up (magic packet) */
563 if (rp->quirks & rqWOL)
564 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
565
566}
567
568#ifdef CONFIG_NET_POLL_CONTROLLER
569static void rhine_poll(struct net_device *dev)
570{
571 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +0100572 rhine_interrupt(dev->irq, (void *)dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 enable_irq(dev->irq);
574}
575#endif
576
Roger Luethi633949a2006-08-14 23:00:17 -0700577#ifdef CONFIG_VIA_RHINE_NAPI
578static int rhine_napipoll(struct net_device *dev, int *budget)
579{
580 struct rhine_private *rp = netdev_priv(dev);
581 void __iomem *ioaddr = rp->base;
582 int done, limit = min(dev->quota, *budget);
583
584 done = rhine_rx(dev, limit);
585 *budget -= done;
586 dev->quota -= done;
587
588 if (done < limit) {
589 netif_rx_complete(dev);
590
591 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
592 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
593 IntrTxDone | IntrTxError | IntrTxUnderrun |
594 IntrPCIErr | IntrStatsMax | IntrLinkChange,
595 ioaddr + IntrEnable);
596 return 0;
597 }
598 else
599 return 1;
600}
601#endif
602
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603static void rhine_hw_init(struct net_device *dev, long pioaddr)
604{
605 struct rhine_private *rp = netdev_priv(dev);
606
607 /* Reset the chip to erase previous misconfiguration. */
608 rhine_chip_reset(dev);
609
610 /* Rhine-I needs extra time to recuperate before EEPROM reload */
611 if (rp->quirks & rqRhineI)
612 msleep(5);
613
614 /* Reload EEPROM controlled bytes cleared by soft reset */
615 rhine_reload_eeprom(pioaddr, dev);
616}
617
618static int __devinit rhine_init_one(struct pci_dev *pdev,
619 const struct pci_device_id *ent)
620{
621 struct net_device *dev;
622 struct rhine_private *rp;
623 int i, rc;
624 u8 pci_rev;
625 u32 quirks;
626 long pioaddr;
627 long memaddr;
628 void __iomem *ioaddr;
629 int io_size, phy_id;
630 const char *name;
631#ifdef USE_MMIO
632 int bar = 1;
633#else
634 int bar = 0;
635#endif
636
637/* when built into the kernel, we only print version if device is found */
638#ifndef MODULE
639 static int printed_version;
640 if (!printed_version++)
641 printk(version);
642#endif
643
644 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
645
646 io_size = 256;
647 phy_id = 0;
648 quirks = 0;
649 name = "Rhine";
650 if (pci_rev < VTunknown0) {
651 quirks = rqRhineI;
652 io_size = 128;
653 }
654 else if (pci_rev >= VT6102) {
655 quirks = rqWOL | rqForceReset;
656 if (pci_rev < VT6105) {
657 name = "Rhine II";
658 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
659 }
660 else {
661 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
662 if (pci_rev >= VT6105_B0)
663 quirks |= rq6patterns;
664 if (pci_rev < VT6105M)
665 name = "Rhine III";
666 else
667 name = "Rhine III (Management Adapter)";
668 }
669 }
670
671 rc = pci_enable_device(pdev);
672 if (rc)
673 goto err_out;
674
675 /* this should always be supported */
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400676 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 if (rc) {
678 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
679 "the card!?\n");
680 goto err_out;
681 }
682
683 /* sanity check */
684 if ((pci_resource_len(pdev, 0) < io_size) ||
685 (pci_resource_len(pdev, 1) < io_size)) {
686 rc = -EIO;
687 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
688 goto err_out;
689 }
690
691 pioaddr = pci_resource_start(pdev, 0);
692 memaddr = pci_resource_start(pdev, 1);
693
694 pci_set_master(pdev);
695
696 dev = alloc_etherdev(sizeof(struct rhine_private));
697 if (!dev) {
698 rc = -ENOMEM;
699 printk(KERN_ERR "alloc_etherdev failed\n");
700 goto err_out;
701 }
702 SET_MODULE_OWNER(dev);
703 SET_NETDEV_DEV(dev, &pdev->dev);
704
705 rp = netdev_priv(dev);
706 rp->quirks = quirks;
707 rp->pioaddr = pioaddr;
708 rp->pdev = pdev;
709
710 rc = pci_request_regions(pdev, DRV_NAME);
711 if (rc)
712 goto err_out_free_netdev;
713
714 ioaddr = pci_iomap(pdev, bar, io_size);
715 if (!ioaddr) {
716 rc = -EIO;
717 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
718 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
719 goto err_out_free_res;
720 }
721
722#ifdef USE_MMIO
723 enable_mmio(pioaddr, quirks);
724
725 /* Check that selected MMIO registers match the PIO ones */
726 i = 0;
727 while (mmio_verify_registers[i]) {
728 int reg = mmio_verify_registers[i++];
729 unsigned char a = inb(pioaddr+reg);
730 unsigned char b = readb(ioaddr+reg);
731 if (a != b) {
732 rc = -EIO;
733 printk(KERN_ERR "MMIO do not match PIO [%02x] "
734 "(%02x != %02x)\n", reg, a, b);
735 goto err_out_unmap;
736 }
737 }
738#endif /* USE_MMIO */
739
740 dev->base_addr = (unsigned long)ioaddr;
741 rp->base = ioaddr;
742
743 /* Get chip registers into a sane state */
744 rhine_power_init(dev);
745 rhine_hw_init(dev, pioaddr);
746
747 for (i = 0; i < 6; i++)
748 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400749 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400751 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 rc = -EIO;
753 printk(KERN_ERR "Invalid MAC address\n");
754 goto err_out_unmap;
755 }
756
757 /* For Rhine-I/II, phy_id is loaded from EEPROM */
758 if (!phy_id)
759 phy_id = ioread8(ioaddr + 0x6C);
760
761 dev->irq = pdev->irq;
762
763 spin_lock_init(&rp->lock);
764 rp->mii_if.dev = dev;
765 rp->mii_if.mdio_read = mdio_read;
766 rp->mii_if.mdio_write = mdio_write;
767 rp->mii_if.phy_id_mask = 0x1f;
768 rp->mii_if.reg_num_mask = 0x1f;
769
770 /* The chip-specific entries in the device structure. */
771 dev->open = rhine_open;
772 dev->hard_start_xmit = rhine_start_tx;
773 dev->stop = rhine_close;
774 dev->get_stats = rhine_get_stats;
775 dev->set_multicast_list = rhine_set_rx_mode;
776 dev->do_ioctl = netdev_ioctl;
777 dev->ethtool_ops = &netdev_ethtool_ops;
778 dev->tx_timeout = rhine_tx_timeout;
779 dev->watchdog_timeo = TX_TIMEOUT;
780#ifdef CONFIG_NET_POLL_CONTROLLER
781 dev->poll_controller = rhine_poll;
782#endif
Roger Luethi633949a2006-08-14 23:00:17 -0700783#ifdef CONFIG_VIA_RHINE_NAPI
784 dev->poll = rhine_napipoll;
785 dev->weight = 64;
786#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787 if (rp->quirks & rqRhineI)
788 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
789
790 /* dev->name not defined before register_netdev()! */
791 rc = register_netdev(dev);
792 if (rc)
793 goto err_out_unmap;
794
795 printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
796 dev->name, name,
797#ifdef USE_MMIO
798 memaddr
799#else
800 (long)ioaddr
801#endif
802 );
803
804 for (i = 0; i < 5; i++)
805 printk("%2.2x:", dev->dev_addr[i]);
806 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
807
808 pci_set_drvdata(pdev, dev);
809
810 {
811 u16 mii_cmd;
812 int mii_status = mdio_read(dev, phy_id, 1);
813 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
814 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
815 if (mii_status != 0xffff && mii_status != 0x0000) {
816 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
817 printk(KERN_INFO "%s: MII PHY found at address "
818 "%d, status 0x%4.4x advertising %4.4x "
819 "Link %4.4x.\n", dev->name, phy_id,
820 mii_status, rp->mii_if.advertising,
821 mdio_read(dev, phy_id, 5));
822
823 /* set IFF_RUNNING */
824 if (mii_status & BMSR_LSTATUS)
825 netif_carrier_on(dev);
826 else
827 netif_carrier_off(dev);
828
829 }
830 }
831 rp->mii_if.phy_id = phy_id;
Roger Luethib933b4d2006-08-14 23:00:21 -0700832 if (debug > 1 && avoid_D3)
833 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
834 dev->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835
836 return 0;
837
838err_out_unmap:
839 pci_iounmap(pdev, ioaddr);
840err_out_free_res:
841 pci_release_regions(pdev);
842err_out_free_netdev:
843 free_netdev(dev);
844err_out:
845 return rc;
846}
847
848static int alloc_ring(struct net_device* dev)
849{
850 struct rhine_private *rp = netdev_priv(dev);
851 void *ring;
852 dma_addr_t ring_dma;
853
854 ring = pci_alloc_consistent(rp->pdev,
855 RX_RING_SIZE * sizeof(struct rx_desc) +
856 TX_RING_SIZE * sizeof(struct tx_desc),
857 &ring_dma);
858 if (!ring) {
859 printk(KERN_ERR "Could not allocate DMA memory.\n");
860 return -ENOMEM;
861 }
862 if (rp->quirks & rqRhineI) {
863 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
864 PKT_BUF_SZ * TX_RING_SIZE,
865 &rp->tx_bufs_dma);
866 if (rp->tx_bufs == NULL) {
867 pci_free_consistent(rp->pdev,
868 RX_RING_SIZE * sizeof(struct rx_desc) +
869 TX_RING_SIZE * sizeof(struct tx_desc),
870 ring, ring_dma);
871 return -ENOMEM;
872 }
873 }
874
875 rp->rx_ring = ring;
876 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
877 rp->rx_ring_dma = ring_dma;
878 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
879
880 return 0;
881}
882
883static void free_ring(struct net_device* dev)
884{
885 struct rhine_private *rp = netdev_priv(dev);
886
887 pci_free_consistent(rp->pdev,
888 RX_RING_SIZE * sizeof(struct rx_desc) +
889 TX_RING_SIZE * sizeof(struct tx_desc),
890 rp->rx_ring, rp->rx_ring_dma);
891 rp->tx_ring = NULL;
892
893 if (rp->tx_bufs)
894 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
895 rp->tx_bufs, rp->tx_bufs_dma);
896
897 rp->tx_bufs = NULL;
898
899}
900
901static void alloc_rbufs(struct net_device *dev)
902{
903 struct rhine_private *rp = netdev_priv(dev);
904 dma_addr_t next;
905 int i;
906
907 rp->dirty_rx = rp->cur_rx = 0;
908
909 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
910 rp->rx_head_desc = &rp->rx_ring[0];
911 next = rp->rx_ring_dma;
912
913 /* Init the ring entries */
914 for (i = 0; i < RX_RING_SIZE; i++) {
915 rp->rx_ring[i].rx_status = 0;
916 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
917 next += sizeof(struct rx_desc);
918 rp->rx_ring[i].next_desc = cpu_to_le32(next);
919 rp->rx_skbuff[i] = NULL;
920 }
921 /* Mark the last entry as wrapping the ring. */
922 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
923
924 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
925 for (i = 0; i < RX_RING_SIZE; i++) {
926 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
927 rp->rx_skbuff[i] = skb;
928 if (skb == NULL)
929 break;
930 skb->dev = dev; /* Mark as being used by this device. */
931
932 rp->rx_skbuff_dma[i] =
David S. Miller689be432005-06-28 15:25:31 -0700933 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 PCI_DMA_FROMDEVICE);
935
936 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
937 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
938 }
939 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
940}
941
942static void free_rbufs(struct net_device* dev)
943{
944 struct rhine_private *rp = netdev_priv(dev);
945 int i;
946
947 /* Free all the skbuffs in the Rx queue. */
948 for (i = 0; i < RX_RING_SIZE; i++) {
949 rp->rx_ring[i].rx_status = 0;
950 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
951 if (rp->rx_skbuff[i]) {
952 pci_unmap_single(rp->pdev,
953 rp->rx_skbuff_dma[i],
954 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
955 dev_kfree_skb(rp->rx_skbuff[i]);
956 }
957 rp->rx_skbuff[i] = NULL;
958 }
959}
960
961static void alloc_tbufs(struct net_device* dev)
962{
963 struct rhine_private *rp = netdev_priv(dev);
964 dma_addr_t next;
965 int i;
966
967 rp->dirty_tx = rp->cur_tx = 0;
968 next = rp->tx_ring_dma;
969 for (i = 0; i < TX_RING_SIZE; i++) {
970 rp->tx_skbuff[i] = NULL;
971 rp->tx_ring[i].tx_status = 0;
972 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
973 next += sizeof(struct tx_desc);
974 rp->tx_ring[i].next_desc = cpu_to_le32(next);
Roger Luethi4be5de22006-04-04 20:49:16 +0200975 if (rp->quirks & rqRhineI)
976 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977 }
978 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
979
980}
981
982static void free_tbufs(struct net_device* dev)
983{
984 struct rhine_private *rp = netdev_priv(dev);
985 int i;
986
987 for (i = 0; i < TX_RING_SIZE; i++) {
988 rp->tx_ring[i].tx_status = 0;
989 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
990 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
991 if (rp->tx_skbuff[i]) {
992 if (rp->tx_skbuff_dma[i]) {
993 pci_unmap_single(rp->pdev,
994 rp->tx_skbuff_dma[i],
995 rp->tx_skbuff[i]->len,
996 PCI_DMA_TODEVICE);
997 }
998 dev_kfree_skb(rp->tx_skbuff[i]);
999 }
1000 rp->tx_skbuff[i] = NULL;
1001 rp->tx_buf[i] = NULL;
1002 }
1003}
1004
1005static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1006{
1007 struct rhine_private *rp = netdev_priv(dev);
1008 void __iomem *ioaddr = rp->base;
1009
1010 mii_check_media(&rp->mii_if, debug, init_media);
1011
1012 if (rp->mii_if.full_duplex)
1013 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1014 ioaddr + ChipCmd1);
1015 else
1016 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1017 ioaddr + ChipCmd1);
Roger Luethi00b428c2006-03-28 20:53:56 +02001018 if (debug > 1)
1019 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1020 rp->mii_if.force_media, netif_carrier_ok(dev));
1021}
1022
1023/* Called after status of force_media possibly changed */
Adrian Bunk0761be42006-04-10 23:22:21 -07001024static void rhine_set_carrier(struct mii_if_info *mii)
Roger Luethi00b428c2006-03-28 20:53:56 +02001025{
1026 if (mii->force_media) {
1027 /* autoneg is off: Link is always assumed to be up */
1028 if (!netif_carrier_ok(mii->dev))
1029 netif_carrier_on(mii->dev);
1030 }
1031 else /* Let MMI library update carrier status */
1032 rhine_check_media(mii->dev, 0);
1033 if (debug > 1)
1034 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1035 mii->dev->name, mii->force_media,
1036 netif_carrier_ok(mii->dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037}
1038
1039static void init_registers(struct net_device *dev)
1040{
1041 struct rhine_private *rp = netdev_priv(dev);
1042 void __iomem *ioaddr = rp->base;
1043 int i;
1044
1045 for (i = 0; i < 6; i++)
1046 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1047
1048 /* Initialize other registers. */
1049 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1050 /* Configure initial FIFO thresholds. */
1051 iowrite8(0x20, ioaddr + TxConfig);
1052 rp->tx_thresh = 0x20;
1053 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1054
1055 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1056 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1057
1058 rhine_set_rx_mode(dev);
1059
Stephen Hemmingerab197662006-08-14 23:00:18 -07001060 netif_poll_enable(dev);
1061
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062 /* Enable interrupts by setting the interrupt mask. */
1063 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1064 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1065 IntrTxDone | IntrTxError | IntrTxUnderrun |
1066 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1067 ioaddr + IntrEnable);
1068
1069 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1070 ioaddr + ChipCmd);
1071 rhine_check_media(dev, 1);
1072}
1073
1074/* Enable MII link status auto-polling (required for IntrLinkChange) */
1075static void rhine_enable_linkmon(void __iomem *ioaddr)
1076{
1077 iowrite8(0, ioaddr + MIICmd);
1078 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1079 iowrite8(0x80, ioaddr + MIICmd);
1080
1081 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1082
1083 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1084}
1085
1086/* Disable MII link status auto-polling (required for MDIO access) */
1087static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1088{
1089 iowrite8(0, ioaddr + MIICmd);
1090
1091 if (quirks & rqRhineI) {
1092 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1093
John W. Linville38bb6b22006-05-19 10:51:21 -04001094 /* Can be called from ISR. Evil. */
1095 mdelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096
1097 /* 0x80 must be set immediately before turning it off */
1098 iowrite8(0x80, ioaddr + MIICmd);
1099
1100 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1101
1102 /* Heh. Now clear 0x80 again. */
1103 iowrite8(0, ioaddr + MIICmd);
1104 }
1105 else
1106 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1107}
1108
1109/* Read and write over the MII Management Data I/O (MDIO) interface. */
1110
1111static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1112{
1113 struct rhine_private *rp = netdev_priv(dev);
1114 void __iomem *ioaddr = rp->base;
1115 int result;
1116
1117 rhine_disable_linkmon(ioaddr, rp->quirks);
1118
1119 /* rhine_disable_linkmon already cleared MIICmd */
1120 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1121 iowrite8(regnum, ioaddr + MIIRegAddr);
1122 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1123 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1124 result = ioread16(ioaddr + MIIData);
1125
1126 rhine_enable_linkmon(ioaddr);
1127 return result;
1128}
1129
1130static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1131{
1132 struct rhine_private *rp = netdev_priv(dev);
1133 void __iomem *ioaddr = rp->base;
1134
1135 rhine_disable_linkmon(ioaddr, rp->quirks);
1136
1137 /* rhine_disable_linkmon already cleared MIICmd */
1138 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1139 iowrite8(regnum, ioaddr + MIIRegAddr);
1140 iowrite16(value, ioaddr + MIIData);
1141 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1142 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1143
1144 rhine_enable_linkmon(ioaddr);
1145}
1146
1147static int rhine_open(struct net_device *dev)
1148{
1149 struct rhine_private *rp = netdev_priv(dev);
1150 void __iomem *ioaddr = rp->base;
1151 int rc;
1152
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001153 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 dev);
1155 if (rc)
1156 return rc;
1157
1158 if (debug > 1)
1159 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1160 dev->name, rp->pdev->irq);
1161
1162 rc = alloc_ring(dev);
1163 if (rc) {
1164 free_irq(rp->pdev->irq, dev);
1165 return rc;
1166 }
1167 alloc_rbufs(dev);
1168 alloc_tbufs(dev);
1169 rhine_chip_reset(dev);
1170 init_registers(dev);
1171 if (debug > 2)
1172 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1173 "MII status: %4.4x.\n",
1174 dev->name, ioread16(ioaddr + ChipCmd),
1175 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1176
1177 netif_start_queue(dev);
1178
1179 return 0;
1180}
1181
1182static void rhine_tx_timeout(struct net_device *dev)
1183{
1184 struct rhine_private *rp = netdev_priv(dev);
1185 void __iomem *ioaddr = rp->base;
1186
1187 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1188 "%4.4x, resetting...\n",
1189 dev->name, ioread16(ioaddr + IntrStatus),
1190 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1191
1192 /* protect against concurrent rx interrupts */
1193 disable_irq(rp->pdev->irq);
1194
1195 spin_lock(&rp->lock);
1196
1197 /* clear all descriptors */
1198 free_tbufs(dev);
1199 free_rbufs(dev);
1200 alloc_tbufs(dev);
1201 alloc_rbufs(dev);
1202
1203 /* Reinitialize the hardware. */
1204 rhine_chip_reset(dev);
1205 init_registers(dev);
1206
1207 spin_unlock(&rp->lock);
1208 enable_irq(rp->pdev->irq);
1209
1210 dev->trans_start = jiffies;
1211 rp->stats.tx_errors++;
1212 netif_wake_queue(dev);
1213}
1214
1215static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1216{
1217 struct rhine_private *rp = netdev_priv(dev);
1218 void __iomem *ioaddr = rp->base;
1219 unsigned entry;
1220
1221 /* Caution: the write order is important here, set the field
1222 with the "ownership" bits last. */
1223
1224 /* Calculate the next Tx descriptor entry. */
1225 entry = rp->cur_tx % TX_RING_SIZE;
1226
Herbert Xu5b057c62006-06-23 02:06:41 -07001227 if (skb_padto(skb, ETH_ZLEN))
1228 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229
1230 rp->tx_skbuff[entry] = skb;
1231
1232 if ((rp->quirks & rqRhineI) &&
Patrick McHardy84fa7932006-08-29 16:44:56 -07001233 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234 /* Must use alignment buffer. */
1235 if (skb->len > PKT_BUF_SZ) {
1236 /* packet too long, drop it */
1237 dev_kfree_skb(skb);
1238 rp->tx_skbuff[entry] = NULL;
1239 rp->stats.tx_dropped++;
1240 return 0;
1241 }
Craig Brind3e0d1672006-04-27 02:30:46 -07001242
1243 /* Padding is not copied and so must be redone. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
Craig Brind3e0d1672006-04-27 02:30:46 -07001245 if (skb->len < ETH_ZLEN)
1246 memset(rp->tx_buf[entry] + skb->len, 0,
1247 ETH_ZLEN - skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 rp->tx_skbuff_dma[entry] = 0;
1249 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1250 (rp->tx_buf[entry] -
1251 rp->tx_bufs));
1252 } else {
1253 rp->tx_skbuff_dma[entry] =
1254 pci_map_single(rp->pdev, skb->data, skb->len,
1255 PCI_DMA_TODEVICE);
1256 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1257 }
1258
1259 rp->tx_ring[entry].desc_length =
1260 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1261
1262 /* lock eth irq */
1263 spin_lock_irq(&rp->lock);
1264 wmb();
1265 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1266 wmb();
1267
1268 rp->cur_tx++;
1269
1270 /* Non-x86 Todo: explicitly flush cache lines here. */
1271
1272 /* Wake the potentially-idle transmit channel */
1273 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1274 ioaddr + ChipCmd1);
1275 IOSYNC;
1276
1277 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1278 netif_stop_queue(dev);
1279
1280 dev->trans_start = jiffies;
1281
1282 spin_unlock_irq(&rp->lock);
1283
1284 if (debug > 4) {
1285 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1286 dev->name, rp->cur_tx-1, entry);
1287 }
1288 return 0;
1289}
1290
1291/* The interrupt handler does all of the Rx thread work and cleans up
1292 after the Tx thread. */
David Howells7d12e782006-10-05 14:55:46 +01001293static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294{
1295 struct net_device *dev = dev_instance;
1296 struct rhine_private *rp = netdev_priv(dev);
1297 void __iomem *ioaddr = rp->base;
1298 u32 intr_status;
1299 int boguscnt = max_interrupt_work;
1300 int handled = 0;
1301
1302 while ((intr_status = get_intr_status(dev))) {
1303 handled = 1;
1304
1305 /* Acknowledge all of the current interrupt sources ASAP. */
1306 if (intr_status & IntrTxDescRace)
1307 iowrite8(0x08, ioaddr + IntrStatus2);
1308 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1309 IOSYNC;
1310
1311 if (debug > 4)
1312 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1313 dev->name, intr_status);
1314
1315 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
Roger Luethi633949a2006-08-14 23:00:17 -07001316 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1317#ifdef CONFIG_VIA_RHINE_NAPI
1318 iowrite16(IntrTxAborted |
1319 IntrTxDone | IntrTxError | IntrTxUnderrun |
1320 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1321 ioaddr + IntrEnable);
1322
1323 netif_rx_schedule(dev);
1324#else
1325 rhine_rx(dev, RX_RING_SIZE);
1326#endif
1327 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328
1329 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1330 if (intr_status & IntrTxErrSummary) {
1331 /* Avoid scavenging before Tx engine turned off */
1332 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1333 if (debug > 2 &&
1334 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1335 printk(KERN_WARNING "%s: "
1336 "rhine_interrupt() Tx engine"
1337 "still on.\n", dev->name);
1338 }
1339 rhine_tx(dev);
1340 }
1341
1342 /* Abnormal error summary/uncommon events handlers. */
1343 if (intr_status & (IntrPCIErr | IntrLinkChange |
1344 IntrStatsMax | IntrTxError | IntrTxAborted |
1345 IntrTxUnderrun | IntrTxDescRace))
1346 rhine_error(dev, intr_status);
1347
1348 if (--boguscnt < 0) {
1349 printk(KERN_WARNING "%s: Too much work at interrupt, "
1350 "status=%#8.8x.\n",
1351 dev->name, intr_status);
1352 break;
1353 }
1354 }
1355
1356 if (debug > 3)
1357 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1358 dev->name, ioread16(ioaddr + IntrStatus));
1359 return IRQ_RETVAL(handled);
1360}
1361
1362/* This routine is logically part of the interrupt handler, but isolated
1363 for clarity. */
1364static void rhine_tx(struct net_device *dev)
1365{
1366 struct rhine_private *rp = netdev_priv(dev);
1367 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1368
1369 spin_lock(&rp->lock);
1370
1371 /* find and cleanup dirty tx descriptors */
1372 while (rp->dirty_tx != rp->cur_tx) {
1373 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1374 if (debug > 6)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001375 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 entry, txstatus);
1377 if (txstatus & DescOwn)
1378 break;
1379 if (txstatus & 0x8000) {
1380 if (debug > 1)
1381 printk(KERN_DEBUG "%s: Transmit error, "
1382 "Tx status %8.8x.\n",
1383 dev->name, txstatus);
1384 rp->stats.tx_errors++;
1385 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1386 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1387 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1388 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1389 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1390 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1391 rp->stats.tx_fifo_errors++;
1392 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1393 break; /* Keep the skb - we try again */
1394 }
1395 /* Transmitter restarted in 'abnormal' handler. */
1396 } else {
1397 if (rp->quirks & rqRhineI)
1398 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1399 else
1400 rp->stats.collisions += txstatus & 0x0F;
1401 if (debug > 6)
1402 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1403 (txstatus >> 3) & 0xF,
1404 txstatus & 0xF);
1405 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1406 rp->stats.tx_packets++;
1407 }
1408 /* Free the original skb. */
1409 if (rp->tx_skbuff_dma[entry]) {
1410 pci_unmap_single(rp->pdev,
1411 rp->tx_skbuff_dma[entry],
1412 rp->tx_skbuff[entry]->len,
1413 PCI_DMA_TODEVICE);
1414 }
1415 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1416 rp->tx_skbuff[entry] = NULL;
1417 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1418 }
1419 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1420 netif_wake_queue(dev);
1421
1422 spin_unlock(&rp->lock);
1423}
1424
Roger Luethi633949a2006-08-14 23:00:17 -07001425/* Process up to limit frames from receive ring */
1426static int rhine_rx(struct net_device *dev, int limit)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427{
1428 struct rhine_private *rp = netdev_priv(dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001429 int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430 int entry = rp->cur_rx % RX_RING_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431
1432 if (debug > 4) {
1433 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1434 dev->name, entry,
1435 le32_to_cpu(rp->rx_head_desc->rx_status));
1436 }
1437
1438 /* If EOP is set on the next entry, it's a new packet. Send it up. */
Roger Luethi633949a2006-08-14 23:00:17 -07001439 for (count = 0; count < limit; ++count) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 struct rx_desc *desc = rp->rx_head_desc;
1441 u32 desc_status = le32_to_cpu(desc->rx_status);
1442 int data_size = desc_status >> 16;
1443
Roger Luethi633949a2006-08-14 23:00:17 -07001444 if (desc_status & DescOwn)
1445 break;
1446
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447 if (debug > 4)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001448 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449 desc_status);
Roger Luethi633949a2006-08-14 23:00:17 -07001450
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1452 if ((desc_status & RxWholePkt) != RxWholePkt) {
1453 printk(KERN_WARNING "%s: Oversized Ethernet "
1454 "frame spanned multiple buffers, entry "
1455 "%#x length %d status %8.8x!\n",
1456 dev->name, entry, data_size,
1457 desc_status);
1458 printk(KERN_WARNING "%s: Oversized Ethernet "
1459 "frame %p vs %p.\n", dev->name,
1460 rp->rx_head_desc, &rp->rx_ring[entry]);
1461 rp->stats.rx_length_errors++;
1462 } else if (desc_status & RxErr) {
1463 /* There was a error. */
1464 if (debug > 2)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001465 printk(KERN_DEBUG "rhine_rx() Rx "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466 "error was %8.8x.\n",
1467 desc_status);
1468 rp->stats.rx_errors++;
1469 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1470 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1471 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1472 if (desc_status & 0x0002) {
1473 /* this can also be updated outside the interrupt handler */
1474 spin_lock(&rp->lock);
1475 rp->stats.rx_crc_errors++;
1476 spin_unlock(&rp->lock);
1477 }
1478 }
1479 } else {
1480 struct sk_buff *skb;
1481 /* Length should omit the CRC */
1482 int pkt_len = data_size - 4;
1483
1484 /* Check if the packet is long enough to accept without
1485 copying to a minimally-sized skbuff. */
1486 if (pkt_len < rx_copybreak &&
1487 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1488 skb->dev = dev;
1489 skb_reserve(skb, 2); /* 16 byte align the IP header */
1490 pci_dma_sync_single_for_cpu(rp->pdev,
1491 rp->rx_skbuff_dma[entry],
1492 rp->rx_buf_sz,
1493 PCI_DMA_FROMDEVICE);
1494
1495 eth_copy_and_sum(skb,
David S. Miller689be432005-06-28 15:25:31 -07001496 rp->rx_skbuff[entry]->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001497 pkt_len, 0);
1498 skb_put(skb, pkt_len);
1499 pci_dma_sync_single_for_device(rp->pdev,
1500 rp->rx_skbuff_dma[entry],
1501 rp->rx_buf_sz,
1502 PCI_DMA_FROMDEVICE);
1503 } else {
1504 skb = rp->rx_skbuff[entry];
1505 if (skb == NULL) {
1506 printk(KERN_ERR "%s: Inconsistent Rx "
1507 "descriptor chain.\n",
1508 dev->name);
1509 break;
1510 }
1511 rp->rx_skbuff[entry] = NULL;
1512 skb_put(skb, pkt_len);
1513 pci_unmap_single(rp->pdev,
1514 rp->rx_skbuff_dma[entry],
1515 rp->rx_buf_sz,
1516 PCI_DMA_FROMDEVICE);
1517 }
1518 skb->protocol = eth_type_trans(skb, dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001519#ifdef CONFIG_VIA_RHINE_NAPI
1520 netif_receive_skb(skb);
1521#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522 netif_rx(skb);
Roger Luethi633949a2006-08-14 23:00:17 -07001523#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 dev->last_rx = jiffies;
1525 rp->stats.rx_bytes += pkt_len;
1526 rp->stats.rx_packets++;
1527 }
1528 entry = (++rp->cur_rx) % RX_RING_SIZE;
1529 rp->rx_head_desc = &rp->rx_ring[entry];
1530 }
1531
1532 /* Refill the Rx ring buffers. */
1533 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1534 struct sk_buff *skb;
1535 entry = rp->dirty_rx % RX_RING_SIZE;
1536 if (rp->rx_skbuff[entry] == NULL) {
1537 skb = dev_alloc_skb(rp->rx_buf_sz);
1538 rp->rx_skbuff[entry] = skb;
1539 if (skb == NULL)
1540 break; /* Better luck next round. */
1541 skb->dev = dev; /* Mark as being used by this device. */
1542 rp->rx_skbuff_dma[entry] =
David S. Miller689be432005-06-28 15:25:31 -07001543 pci_map_single(rp->pdev, skb->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 rp->rx_buf_sz,
1545 PCI_DMA_FROMDEVICE);
1546 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1547 }
1548 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1549 }
Roger Luethi633949a2006-08-14 23:00:17 -07001550
1551 return count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552}
1553
1554/*
1555 * Clears the "tally counters" for CRC errors and missed frames(?).
1556 * It has been reported that some chips need a write of 0 to clear
1557 * these, for others the counters are set to 1 when written to and
1558 * instead cleared when read. So we clear them both ways ...
1559 */
1560static inline void clear_tally_counters(void __iomem *ioaddr)
1561{
1562 iowrite32(0, ioaddr + RxMissed);
1563 ioread16(ioaddr + RxCRCErrs);
1564 ioread16(ioaddr + RxMissed);
1565}
1566
1567static void rhine_restart_tx(struct net_device *dev) {
1568 struct rhine_private *rp = netdev_priv(dev);
1569 void __iomem *ioaddr = rp->base;
1570 int entry = rp->dirty_tx % TX_RING_SIZE;
1571 u32 intr_status;
1572
1573 /*
1574 * If new errors occured, we need to sort them out before doing Tx.
1575 * In that case the ISR will be back here RSN anyway.
1576 */
1577 intr_status = get_intr_status(dev);
1578
1579 if ((intr_status & IntrTxErrSummary) == 0) {
1580
1581 /* We know better than the chip where it should continue. */
1582 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1583 ioaddr + TxRingPtr);
1584
1585 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1586 ioaddr + ChipCmd);
1587 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1588 ioaddr + ChipCmd1);
1589 IOSYNC;
1590 }
1591 else {
1592 /* This should never happen */
1593 if (debug > 1)
1594 printk(KERN_WARNING "%s: rhine_restart_tx() "
1595 "Another error occured %8.8x.\n",
1596 dev->name, intr_status);
1597 }
1598
1599}
1600
1601static void rhine_error(struct net_device *dev, int intr_status)
1602{
1603 struct rhine_private *rp = netdev_priv(dev);
1604 void __iomem *ioaddr = rp->base;
1605
1606 spin_lock(&rp->lock);
1607
1608 if (intr_status & IntrLinkChange)
John W. Linville38bb6b22006-05-19 10:51:21 -04001609 rhine_check_media(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610 if (intr_status & IntrStatsMax) {
1611 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1612 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1613 clear_tally_counters(ioaddr);
1614 }
1615 if (intr_status & IntrTxAborted) {
1616 if (debug > 1)
1617 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1618 dev->name, intr_status);
1619 }
1620 if (intr_status & IntrTxUnderrun) {
1621 if (rp->tx_thresh < 0xE0)
1622 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1623 if (debug > 1)
1624 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1625 "threshold now %2.2x.\n",
1626 dev->name, rp->tx_thresh);
1627 }
1628 if (intr_status & IntrTxDescRace) {
1629 if (debug > 2)
1630 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1631 dev->name);
1632 }
1633 if ((intr_status & IntrTxError) &&
1634 (intr_status & (IntrTxAborted |
1635 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1636 if (rp->tx_thresh < 0xE0) {
1637 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1638 }
1639 if (debug > 1)
1640 printk(KERN_INFO "%s: Unspecified error. Tx "
1641 "threshold now %2.2x.\n",
1642 dev->name, rp->tx_thresh);
1643 }
1644 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1645 IntrTxError))
1646 rhine_restart_tx(dev);
1647
1648 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1649 IntrTxError | IntrTxAborted | IntrNormalSummary |
1650 IntrTxDescRace)) {
1651 if (debug > 1)
1652 printk(KERN_ERR "%s: Something Wicked happened! "
1653 "%8.8x.\n", dev->name, intr_status);
1654 }
1655
1656 spin_unlock(&rp->lock);
1657}
1658
1659static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1660{
1661 struct rhine_private *rp = netdev_priv(dev);
1662 void __iomem *ioaddr = rp->base;
1663 unsigned long flags;
1664
1665 spin_lock_irqsave(&rp->lock, flags);
1666 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1667 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1668 clear_tally_counters(ioaddr);
1669 spin_unlock_irqrestore(&rp->lock, flags);
1670
1671 return &rp->stats;
1672}
1673
1674static void rhine_set_rx_mode(struct net_device *dev)
1675{
1676 struct rhine_private *rp = netdev_priv(dev);
1677 void __iomem *ioaddr = rp->base;
1678 u32 mc_filter[2]; /* Multicast hash filter */
1679 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1680
1681 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682 rx_mode = 0x1C;
1683 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1684 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1685 } else if ((dev->mc_count > multicast_filter_limit)
1686 || (dev->flags & IFF_ALLMULTI)) {
1687 /* Too many to match, or accept all multicasts. */
1688 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1689 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1690 rx_mode = 0x0C;
1691 } else {
1692 struct dev_mc_list *mclist;
1693 int i;
1694 memset(mc_filter, 0, sizeof(mc_filter));
1695 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1696 i++, mclist = mclist->next) {
1697 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1698
1699 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1700 }
1701 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1702 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1703 rx_mode = 0x0C;
1704 }
1705 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1706}
1707
1708static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1709{
1710 struct rhine_private *rp = netdev_priv(dev);
1711
1712 strcpy(info->driver, DRV_NAME);
1713 strcpy(info->version, DRV_VERSION);
1714 strcpy(info->bus_info, pci_name(rp->pdev));
1715}
1716
1717static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1718{
1719 struct rhine_private *rp = netdev_priv(dev);
1720 int rc;
1721
1722 spin_lock_irq(&rp->lock);
1723 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1724 spin_unlock_irq(&rp->lock);
1725
1726 return rc;
1727}
1728
1729static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1730{
1731 struct rhine_private *rp = netdev_priv(dev);
1732 int rc;
1733
1734 spin_lock_irq(&rp->lock);
1735 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1736 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001737 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738
1739 return rc;
1740}
1741
1742static int netdev_nway_reset(struct net_device *dev)
1743{
1744 struct rhine_private *rp = netdev_priv(dev);
1745
1746 return mii_nway_restart(&rp->mii_if);
1747}
1748
1749static u32 netdev_get_link(struct net_device *dev)
1750{
1751 struct rhine_private *rp = netdev_priv(dev);
1752
1753 return mii_link_ok(&rp->mii_if);
1754}
1755
1756static u32 netdev_get_msglevel(struct net_device *dev)
1757{
1758 return debug;
1759}
1760
1761static void netdev_set_msglevel(struct net_device *dev, u32 value)
1762{
1763 debug = value;
1764}
1765
1766static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1767{
1768 struct rhine_private *rp = netdev_priv(dev);
1769
1770 if (!(rp->quirks & rqWOL))
1771 return;
1772
1773 spin_lock_irq(&rp->lock);
1774 wol->supported = WAKE_PHY | WAKE_MAGIC |
1775 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1776 wol->wolopts = rp->wolopts;
1777 spin_unlock_irq(&rp->lock);
1778}
1779
1780static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1781{
1782 struct rhine_private *rp = netdev_priv(dev);
1783 u32 support = WAKE_PHY | WAKE_MAGIC |
1784 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1785
1786 if (!(rp->quirks & rqWOL))
1787 return -EINVAL;
1788
1789 if (wol->wolopts & ~support)
1790 return -EINVAL;
1791
1792 spin_lock_irq(&rp->lock);
1793 rp->wolopts = wol->wolopts;
1794 spin_unlock_irq(&rp->lock);
1795
1796 return 0;
1797}
1798
Jeff Garzik7282d492006-09-13 14:30:00 -04001799static const struct ethtool_ops netdev_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800 .get_drvinfo = netdev_get_drvinfo,
1801 .get_settings = netdev_get_settings,
1802 .set_settings = netdev_set_settings,
1803 .nway_reset = netdev_nway_reset,
1804 .get_link = netdev_get_link,
1805 .get_msglevel = netdev_get_msglevel,
1806 .set_msglevel = netdev_set_msglevel,
1807 .get_wol = rhine_get_wol,
1808 .set_wol = rhine_set_wol,
1809 .get_sg = ethtool_op_get_sg,
1810 .get_tx_csum = ethtool_op_get_tx_csum,
John W. Linvilleb81e8e12005-09-12 10:48:58 -04001811 .get_perm_addr = ethtool_op_get_perm_addr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001812};
1813
1814static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1815{
1816 struct rhine_private *rp = netdev_priv(dev);
1817 int rc;
1818
1819 if (!netif_running(dev))
1820 return -EINVAL;
1821
1822 spin_lock_irq(&rp->lock);
1823 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1824 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001825 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001826
1827 return rc;
1828}
1829
1830static int rhine_close(struct net_device *dev)
1831{
1832 struct rhine_private *rp = netdev_priv(dev);
1833 void __iomem *ioaddr = rp->base;
1834
1835 spin_lock_irq(&rp->lock);
1836
1837 netif_stop_queue(dev);
Roger Luethi633949a2006-08-14 23:00:17 -07001838 netif_poll_disable(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839
1840 if (debug > 1)
1841 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1842 "status was %4.4x.\n",
1843 dev->name, ioread16(ioaddr + ChipCmd));
1844
1845 /* Switch to loopback mode to avoid hardware races. */
1846 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1847
1848 /* Disable interrupts by clearing the interrupt mask. */
1849 iowrite16(0x0000, ioaddr + IntrEnable);
1850
1851 /* Stop the chip's Tx and Rx processes. */
1852 iowrite16(CmdStop, ioaddr + ChipCmd);
1853
1854 spin_unlock_irq(&rp->lock);
1855
1856 free_irq(rp->pdev->irq, dev);
1857 free_rbufs(dev);
1858 free_tbufs(dev);
1859 free_ring(dev);
1860
1861 return 0;
1862}
1863
1864
1865static void __devexit rhine_remove_one(struct pci_dev *pdev)
1866{
1867 struct net_device *dev = pci_get_drvdata(pdev);
1868 struct rhine_private *rp = netdev_priv(dev);
1869
1870 unregister_netdev(dev);
1871
1872 pci_iounmap(pdev, rp->base);
1873 pci_release_regions(pdev);
1874
1875 free_netdev(dev);
1876 pci_disable_device(pdev);
1877 pci_set_drvdata(pdev, NULL);
1878}
1879
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001880static void rhine_shutdown (struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882 struct net_device *dev = pci_get_drvdata(pdev);
1883 struct rhine_private *rp = netdev_priv(dev);
1884 void __iomem *ioaddr = rp->base;
1885
1886 if (!(rp->quirks & rqWOL))
1887 return; /* Nothing to do for non-WOL adapters */
1888
1889 rhine_power_init(dev);
1890
1891 /* Make sure we use pattern 0, 1 and not 4, 5 */
1892 if (rp->quirks & rq6patterns)
1893 iowrite8(0x04, ioaddr + 0xA7);
1894
1895 if (rp->wolopts & WAKE_MAGIC) {
1896 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1897 /*
1898 * Turn EEPROM-controlled wake-up back on -- some hardware may
1899 * not cooperate otherwise.
1900 */
1901 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1902 }
1903
1904 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1905 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1906
1907 if (rp->wolopts & WAKE_PHY)
1908 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1909
1910 if (rp->wolopts & WAKE_UCAST)
1911 iowrite8(WOLucast, ioaddr + WOLcrSet);
1912
1913 if (rp->wolopts) {
1914 /* Enable legacy WOL (for old motherboards) */
1915 iowrite8(0x01, ioaddr + PwcfgSet);
1916 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1917 }
1918
1919 /* Hit power state D3 (sleep) */
Roger Luethib933b4d2006-08-14 23:00:21 -07001920 if (!avoid_D3)
1921 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001922
1923 /* TODO: Check use of pci_enable_wake() */
1924
1925}
1926
1927#ifdef CONFIG_PM
1928static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1929{
1930 struct net_device *dev = pci_get_drvdata(pdev);
1931 struct rhine_private *rp = netdev_priv(dev);
1932 unsigned long flags;
1933
1934 if (!netif_running(dev))
1935 return 0;
1936
1937 netif_device_detach(dev);
1938 pci_save_state(pdev);
1939
1940 spin_lock_irqsave(&rp->lock, flags);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001941 rhine_shutdown(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942 spin_unlock_irqrestore(&rp->lock, flags);
1943
1944 free_irq(dev->irq, dev);
1945 return 0;
1946}
1947
1948static int rhine_resume(struct pci_dev *pdev)
1949{
1950 struct net_device *dev = pci_get_drvdata(pdev);
1951 struct rhine_private *rp = netdev_priv(dev);
1952 unsigned long flags;
1953 int ret;
1954
1955 if (!netif_running(dev))
1956 return 0;
1957
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001958 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1960
1961 ret = pci_set_power_state(pdev, PCI_D0);
1962 if (debug > 1)
1963 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1964 dev->name, ret ? "failed" : "succeeded", ret);
1965
1966 pci_restore_state(pdev);
1967
1968 spin_lock_irqsave(&rp->lock, flags);
1969#ifdef USE_MMIO
1970 enable_mmio(rp->pioaddr, rp->quirks);
1971#endif
1972 rhine_power_init(dev);
1973 free_tbufs(dev);
1974 free_rbufs(dev);
1975 alloc_tbufs(dev);
1976 alloc_rbufs(dev);
1977 init_registers(dev);
1978 spin_unlock_irqrestore(&rp->lock, flags);
1979
1980 netif_device_attach(dev);
1981
1982 return 0;
1983}
1984#endif /* CONFIG_PM */
1985
1986static struct pci_driver rhine_driver = {
1987 .name = DRV_NAME,
1988 .id_table = rhine_pci_tbl,
1989 .probe = rhine_init_one,
1990 .remove = __devexit_p(rhine_remove_one),
1991#ifdef CONFIG_PM
1992 .suspend = rhine_suspend,
1993 .resume = rhine_resume,
1994#endif /* CONFIG_PM */
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001995 .shutdown = rhine_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996};
1997
1998
1999static int __init rhine_init(void)
2000{
2001/* when a module, this is printed whether or not devices are found in probe */
2002#ifdef MODULE
2003 printk(version);
2004#endif
Jeff Garzik29917622006-08-19 17:48:59 -04002005 return pci_register_driver(&rhine_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002006}
2007
2008
2009static void __exit rhine_cleanup(void)
2010{
2011 pci_unregister_driver(&rhine_driver);
2012}
2013
2014
2015module_init(rhine_init);
2016module_exit(rhine_cleanup);