Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <ttm/ttm_bo_api.h> |
| 33 | #include <ttm/ttm_bo_driver.h> |
| 34 | #include <ttm/ttm_placement.h> |
| 35 | #include <ttm/ttm_module.h> |
Pauli Nieminen | 8d7cddc | 2010-04-01 12:44:59 +0000 | [diff] [blame] | 36 | #include <ttm/ttm_page_alloc.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | #include <drm/drmP.h> |
| 38 | #include <drm/radeon_drm.h> |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 39 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 40 | #include <linux/slab.h> |
Chris Metcalf | 4cfe762 | 2013-02-01 13:44:33 -0500 | [diff] [blame] | 41 | #include <linux/swiotlb.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 42 | #include "radeon_reg.h" |
| 43 | #include "radeon.h" |
| 44 | |
| 45 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
| 46 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 47 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev); |
| 48 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 49 | static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) |
| 50 | { |
| 51 | struct radeon_mman *mman; |
| 52 | struct radeon_device *rdev; |
| 53 | |
| 54 | mman = container_of(bdev, struct radeon_mman, bdev); |
| 55 | rdev = container_of(mman, struct radeon_device, mman); |
| 56 | return rdev; |
| 57 | } |
| 58 | |
| 59 | |
| 60 | /* |
| 61 | * Global memory. |
| 62 | */ |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 63 | static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | { |
| 65 | return ttm_mem_global_init(ref->object); |
| 66 | } |
| 67 | |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 68 | static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 69 | { |
| 70 | ttm_mem_global_release(ref->object); |
| 71 | } |
| 72 | |
| 73 | static int radeon_ttm_global_init(struct radeon_device *rdev) |
| 74 | { |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 75 | struct drm_global_reference *global_ref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 76 | int r; |
| 77 | |
| 78 | rdev->mman.mem_global_referenced = false; |
| 79 | global_ref = &rdev->mman.mem_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 80 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 81 | global_ref->size = sizeof(struct ttm_mem_global); |
| 82 | global_ref->init = &radeon_ttm_mem_global_init; |
| 83 | global_ref->release = &radeon_ttm_mem_global_release; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 84 | r = drm_global_item_ref(global_ref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 85 | if (r != 0) { |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 86 | DRM_ERROR("Failed setting up TTM memory accounting " |
| 87 | "subsystem.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 88 | return r; |
| 89 | } |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 90 | |
| 91 | rdev->mman.bo_global_ref.mem_glob = |
| 92 | rdev->mman.mem_global_ref.object; |
| 93 | global_ref = &rdev->mman.bo_global_ref.ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 94 | global_ref->global_type = DRM_GLOBAL_TTM_BO; |
Thomas Hellstrom | 7f5f4db | 2009-08-20 10:29:08 +0200 | [diff] [blame] | 95 | global_ref->size = sizeof(struct ttm_bo_global); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 96 | global_ref->init = &ttm_bo_global_init; |
| 97 | global_ref->release = &ttm_bo_global_release; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 98 | r = drm_global_item_ref(global_ref); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 99 | if (r != 0) { |
| 100 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 101 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 102 | return r; |
| 103 | } |
| 104 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | rdev->mman.mem_global_referenced = true; |
| 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | static void radeon_ttm_global_fini(struct radeon_device *rdev) |
| 110 | { |
| 111 | if (rdev->mman.mem_global_referenced) { |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 112 | drm_global_item_unref(&rdev->mman.bo_global_ref.ref); |
| 113 | drm_global_item_unref(&rdev->mman.mem_global_ref); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 114 | rdev->mman.mem_global_referenced = false; |
| 115 | } |
| 116 | } |
| 117 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) |
| 119 | { |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, |
| 124 | struct ttm_mem_type_manager *man) |
| 125 | { |
| 126 | struct radeon_device *rdev; |
| 127 | |
| 128 | rdev = radeon_get_rdev(bdev); |
| 129 | |
| 130 | switch (type) { |
| 131 | case TTM_PL_SYSTEM: |
| 132 | /* System memory */ |
| 133 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
| 134 | man->available_caching = TTM_PL_MASK_CACHING; |
| 135 | man->default_caching = TTM_PL_FLAG_CACHED; |
| 136 | break; |
| 137 | case TTM_PL_TT: |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 138 | man->func = &ttm_bo_manager_func; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 139 | man->gpu_offset = rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 140 | man->available_caching = TTM_PL_MASK_CACHING; |
| 141 | man->default_caching = TTM_PL_FLAG_CACHED; |
Michel Dänzer | 55c9327 | 2009-06-15 16:56:11 +0200 | [diff] [blame] | 142 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 143 | #if __OS_HAS_AGP |
| 144 | if (rdev->flags & RADEON_IS_AGP) { |
Daniel Vetter | d990675 | 2013-12-11 11:34:35 +0100 | [diff] [blame^] | 145 | if (!rdev->ddev->agp) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 146 | DRM_ERROR("AGP is not enabled for memory type %u\n", |
| 147 | (unsigned)type); |
| 148 | return -EINVAL; |
| 149 | } |
Michel Dänzer | 55c9327 | 2009-06-15 16:56:11 +0200 | [diff] [blame] | 150 | if (!rdev->ddev->agp->cant_use_aperture) |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 151 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 152 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
| 153 | TTM_PL_FLAG_WC; |
| 154 | man->default_caching = TTM_PL_FLAG_WC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 155 | } |
Jerome Glisse | 0c321c7 | 2010-04-07 10:21:27 +0000 | [diff] [blame] | 156 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | break; |
| 158 | case TTM_PL_VRAM: |
| 159 | /* "On-card" video ram */ |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 160 | man->func = &ttm_bo_manager_func; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 161 | man->gpu_offset = rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 162 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | TTM_MEMTYPE_FLAG_MAPPABLE; |
| 164 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; |
| 165 | man->default_caching = TTM_PL_FLAG_WC; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 166 | break; |
| 167 | default: |
| 168 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); |
| 169 | return -EINVAL; |
| 170 | } |
| 171 | return 0; |
| 172 | } |
| 173 | |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 174 | static void radeon_evict_flags(struct ttm_buffer_object *bo, |
| 175 | struct ttm_placement *placement) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 176 | { |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 177 | struct radeon_bo *rbo; |
| 178 | static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; |
| 179 | |
| 180 | if (!radeon_ttm_bo_is_radeon_bo(bo)) { |
| 181 | placement->fpfn = 0; |
| 182 | placement->lpfn = 0; |
| 183 | placement->placement = &placements; |
| 184 | placement->busy_placement = &placements; |
| 185 | placement->num_placement = 1; |
| 186 | placement->num_busy_placement = 1; |
| 187 | return; |
| 188 | } |
| 189 | rbo = container_of(bo, struct radeon_bo, tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 190 | switch (bo->mem.mem_type) { |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 191 | case TTM_PL_VRAM: |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 192 | if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) |
Dave Airlie | 9270eb1 | 2010-01-13 09:21:49 +1000 | [diff] [blame] | 193 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
| 194 | else |
| 195 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 196 | break; |
| 197 | case TTM_PL_TT: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 198 | default: |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 199 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 200 | } |
Jerome Glisse | eaa5fd1 | 2009-12-09 21:57:37 +0100 | [diff] [blame] | 201 | *placement = rbo->placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) |
| 205 | { |
David Herrmann | acb4652 | 2013-08-25 18:28:59 +0200 | [diff] [blame] | 206 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 207 | |
| 208 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static void radeon_move_null(struct ttm_buffer_object *bo, |
| 212 | struct ttm_mem_reg *new_mem) |
| 213 | { |
| 214 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 215 | |
| 216 | BUG_ON(old_mem->mm_node != NULL); |
| 217 | *old_mem = *new_mem; |
| 218 | new_mem->mm_node = NULL; |
| 219 | } |
| 220 | |
| 221 | static int radeon_move_blit(struct ttm_buffer_object *bo, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 222 | bool evict, bool no_wait_gpu, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 223 | struct ttm_mem_reg *new_mem, |
| 224 | struct ttm_mem_reg *old_mem) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | { |
| 226 | struct radeon_device *rdev; |
| 227 | uint64_t old_start, new_start; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 228 | struct radeon_fence *fence; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 229 | int r, ridx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 230 | |
| 231 | rdev = radeon_get_rdev(bo->bdev); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 232 | ridx = radeon_copy_ring_index(rdev); |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 233 | old_start = old_mem->start << PAGE_SHIFT; |
| 234 | new_start = new_mem->start << PAGE_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 235 | |
| 236 | switch (old_mem->mem_type) { |
| 237 | case TTM_PL_VRAM: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 238 | old_start += rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | break; |
| 240 | case TTM_PL_TT: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 241 | old_start += rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 242 | break; |
| 243 | default: |
| 244 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
| 245 | return -EINVAL; |
| 246 | } |
| 247 | switch (new_mem->mem_type) { |
| 248 | case TTM_PL_VRAM: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 249 | new_start += rdev->mc.vram_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | break; |
| 251 | case TTM_PL_TT: |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 252 | new_start += rdev->mc.gtt_start; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 253 | break; |
| 254 | default: |
| 255 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
| 256 | return -EINVAL; |
| 257 | } |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 258 | if (!rdev->ring[ridx].ready) { |
Alex Deucher | 3000bf3 | 2012-01-05 22:11:07 -0500 | [diff] [blame] | 259 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 260 | return -EINVAL; |
| 261 | } |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 262 | |
| 263 | BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); |
| 264 | |
Alex Deucher | 3000bf3 | 2012-01-05 22:11:07 -0500 | [diff] [blame] | 265 | /* sync other rings */ |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 266 | fence = bo->sync_obj; |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 267 | r = radeon_copy(rdev, old_start, new_start, |
| 268 | new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 269 | &fence); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | /* FIXME: handle copy error */ |
Maarten Lankhorst | b03640b | 2012-10-12 15:03:11 +0000 | [diff] [blame] | 271 | r = ttm_bo_move_accel_cleanup(bo, (void *)fence, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 272 | evict, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 273 | radeon_fence_unref(&fence); |
| 274 | return r; |
| 275 | } |
| 276 | |
| 277 | static int radeon_move_vram_ram(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 278 | bool evict, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 279 | bool no_wait_gpu, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 280 | struct ttm_mem_reg *new_mem) |
| 281 | { |
| 282 | struct radeon_device *rdev; |
| 283 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 284 | struct ttm_mem_reg tmp_mem; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 285 | u32 placements; |
| 286 | struct ttm_placement placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 287 | int r; |
| 288 | |
| 289 | rdev = radeon_get_rdev(bo->bdev); |
| 290 | tmp_mem = *new_mem; |
| 291 | tmp_mem.mm_node = NULL; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 292 | placement.fpfn = 0; |
| 293 | placement.lpfn = 0; |
| 294 | placement.num_placement = 1; |
| 295 | placement.placement = &placements; |
| 296 | placement.num_busy_placement = 1; |
| 297 | placement.busy_placement = &placements; |
| 298 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
| 299 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 300 | interruptible, no_wait_gpu); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 301 | if (unlikely(r)) { |
| 302 | return r; |
| 303 | } |
Dave Airlie | df67bed | 2009-10-30 13:31:26 +1000 | [diff] [blame] | 304 | |
| 305 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); |
| 306 | if (unlikely(r)) { |
| 307 | goto out_cleanup; |
| 308 | } |
| 309 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | r = ttm_tt_bind(bo->ttm, &tmp_mem); |
| 311 | if (unlikely(r)) { |
| 312 | goto out_cleanup; |
| 313 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 314 | r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 315 | if (unlikely(r)) { |
| 316 | goto out_cleanup; |
| 317 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 318 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 319 | out_cleanup: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 320 | ttm_bo_mem_put(bo, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | return r; |
| 322 | } |
| 323 | |
| 324 | static int radeon_move_ram_vram(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 325 | bool evict, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 326 | bool no_wait_gpu, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 327 | struct ttm_mem_reg *new_mem) |
| 328 | { |
| 329 | struct radeon_device *rdev; |
| 330 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 331 | struct ttm_mem_reg tmp_mem; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 332 | struct ttm_placement placement; |
| 333 | u32 placements; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 334 | int r; |
| 335 | |
| 336 | rdev = radeon_get_rdev(bo->bdev); |
| 337 | tmp_mem = *new_mem; |
| 338 | tmp_mem.mm_node = NULL; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 339 | placement.fpfn = 0; |
| 340 | placement.lpfn = 0; |
| 341 | placement.num_placement = 1; |
| 342 | placement.placement = &placements; |
| 343 | placement.num_busy_placement = 1; |
| 344 | placement.busy_placement = &placements; |
| 345 | placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 346 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, |
| 347 | interruptible, no_wait_gpu); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 348 | if (unlikely(r)) { |
| 349 | return r; |
| 350 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 351 | r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 352 | if (unlikely(r)) { |
| 353 | goto out_cleanup; |
| 354 | } |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 355 | r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | if (unlikely(r)) { |
| 357 | goto out_cleanup; |
| 358 | } |
| 359 | out_cleanup: |
Ben Skeggs | 42311ff | 2010-08-04 12:07:08 +1000 | [diff] [blame] | 360 | ttm_bo_mem_put(bo, &tmp_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 361 | return r; |
| 362 | } |
| 363 | |
| 364 | static int radeon_bo_move(struct ttm_buffer_object *bo, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 365 | bool evict, bool interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 366 | bool no_wait_gpu, |
Jerome Glisse | 9d87fa2 | 2010-04-07 10:21:19 +0000 | [diff] [blame] | 367 | struct ttm_mem_reg *new_mem) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 368 | { |
| 369 | struct radeon_device *rdev; |
| 370 | struct ttm_mem_reg *old_mem = &bo->mem; |
| 371 | int r; |
| 372 | |
| 373 | rdev = radeon_get_rdev(bo->bdev); |
| 374 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { |
| 375 | radeon_move_null(bo, new_mem); |
| 376 | return 0; |
| 377 | } |
| 378 | if ((old_mem->mem_type == TTM_PL_TT && |
| 379 | new_mem->mem_type == TTM_PL_SYSTEM) || |
| 380 | (old_mem->mem_type == TTM_PL_SYSTEM && |
| 381 | new_mem->mem_type == TTM_PL_TT)) { |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 382 | /* bind is enough */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | radeon_move_null(bo, new_mem); |
| 384 | return 0; |
| 385 | } |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 386 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
| 387 | rdev->asic->copy.copy == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 388 | /* use memcpy */ |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 389 | goto memcpy; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | if (old_mem->mem_type == TTM_PL_VRAM && |
| 393 | new_mem->mem_type == TTM_PL_SYSTEM) { |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 394 | r = radeon_move_vram_ram(bo, evict, interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 395 | no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 396 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && |
| 397 | new_mem->mem_type == TTM_PL_VRAM) { |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 398 | r = radeon_move_ram_vram(bo, evict, interruptible, |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 399 | no_wait_gpu, new_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 400 | } else { |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 401 | r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 402 | } |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 403 | |
| 404 | if (r) { |
| 405 | memcpy: |
Maarten Lankhorst | 97a875c | 2012-11-28 11:25:44 +0000 | [diff] [blame] | 406 | r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
Michel Dänzer | 1ab2e10 | 2009-07-28 12:30:56 +0200 | [diff] [blame] | 407 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 408 | return r; |
| 409 | } |
| 410 | |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 411 | static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 412 | { |
| 413 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; |
| 414 | struct radeon_device *rdev = radeon_get_rdev(bdev); |
| 415 | |
| 416 | mem->bus.addr = NULL; |
| 417 | mem->bus.offset = 0; |
| 418 | mem->bus.size = mem->num_pages << PAGE_SHIFT; |
| 419 | mem->bus.base = 0; |
| 420 | mem->bus.is_iomem = false; |
| 421 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) |
| 422 | return -EINVAL; |
| 423 | switch (mem->mem_type) { |
| 424 | case TTM_PL_SYSTEM: |
| 425 | /* system memory */ |
| 426 | return 0; |
| 427 | case TTM_PL_TT: |
| 428 | #if __OS_HAS_AGP |
| 429 | if (rdev->flags & RADEON_IS_AGP) { |
| 430 | /* RADEON_IS_AGP is set only if AGP is active */ |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 431 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 432 | mem->bus.base = rdev->mc.agp_base; |
Michel Dänzer | 365048f | 2010-05-19 12:46:22 +0200 | [diff] [blame] | 433 | mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 434 | } |
| 435 | #endif |
| 436 | break; |
| 437 | case TTM_PL_VRAM: |
Ben Skeggs | d961db7 | 2010-08-05 10:48:18 +1000 | [diff] [blame] | 438 | mem->bus.offset = mem->start << PAGE_SHIFT; |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 439 | /* check if it's visible */ |
| 440 | if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) |
| 441 | return -EINVAL; |
| 442 | mem->bus.base = rdev->mc.aper_base; |
| 443 | mem->bus.is_iomem = true; |
Jay Estabrook | ffb57c4 | 2011-07-06 23:57:13 +0000 | [diff] [blame] | 444 | #ifdef __alpha__ |
| 445 | /* |
| 446 | * Alpha: use bus.addr to hold the ioremap() return, |
| 447 | * so we can modify bus.base below. |
| 448 | */ |
| 449 | if (mem->placement & TTM_PL_FLAG_WC) |
| 450 | mem->bus.addr = |
| 451 | ioremap_wc(mem->bus.base + mem->bus.offset, |
| 452 | mem->bus.size); |
| 453 | else |
| 454 | mem->bus.addr = |
| 455 | ioremap_nocache(mem->bus.base + mem->bus.offset, |
| 456 | mem->bus.size); |
| 457 | |
| 458 | /* |
| 459 | * Alpha: Use just the bus offset plus |
| 460 | * the hose/domain memory base for bus.base. |
| 461 | * It then can be used to build PTEs for VRAM |
| 462 | * access, as done in ttm_bo_vm_fault(). |
| 463 | */ |
| 464 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + |
| 465 | rdev->ddev->hose->dense_mem_base; |
| 466 | #endif |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 467 | break; |
| 468 | default: |
| 469 | return -EINVAL; |
| 470 | } |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) |
| 475 | { |
| 476 | } |
| 477 | |
Maarten Lankhorst | dedfdff | 2012-10-12 15:04:00 +0000 | [diff] [blame] | 478 | static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 479 | { |
| 480 | return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); |
| 481 | } |
| 482 | |
Maarten Lankhorst | dedfdff | 2012-10-12 15:04:00 +0000 | [diff] [blame] | 483 | static int radeon_sync_obj_flush(void *sync_obj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 484 | { |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | static void radeon_sync_obj_unref(void **sync_obj) |
| 489 | { |
| 490 | radeon_fence_unref((struct radeon_fence **)sync_obj); |
| 491 | } |
| 492 | |
| 493 | static void *radeon_sync_obj_ref(void *sync_obj) |
| 494 | { |
| 495 | return radeon_fence_ref((struct radeon_fence *)sync_obj); |
| 496 | } |
| 497 | |
Maarten Lankhorst | dedfdff | 2012-10-12 15:04:00 +0000 | [diff] [blame] | 498 | static bool radeon_sync_obj_signaled(void *sync_obj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 499 | { |
| 500 | return radeon_fence_signaled((struct radeon_fence *)sync_obj); |
| 501 | } |
| 502 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 503 | /* |
| 504 | * TTM backend functions. |
| 505 | */ |
| 506 | struct radeon_ttm_tt { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 507 | struct ttm_dma_tt ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 508 | struct radeon_device *rdev; |
| 509 | u64 offset; |
| 510 | }; |
| 511 | |
| 512 | static int radeon_ttm_backend_bind(struct ttm_tt *ttm, |
| 513 | struct ttm_mem_reg *bo_mem) |
| 514 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 515 | struct radeon_ttm_tt *gtt = (void*)ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 516 | int r; |
| 517 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 518 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
| 519 | if (!ttm->num_pages) { |
| 520 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", |
| 521 | ttm->num_pages, bo_mem, ttm); |
| 522 | } |
| 523 | r = radeon_gart_bind(gtt->rdev, gtt->offset, |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 524 | ttm->num_pages, ttm->pages, gtt->ttm.dma_address); |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 525 | if (r) { |
| 526 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", |
| 527 | ttm->num_pages, (unsigned)gtt->offset); |
| 528 | return r; |
| 529 | } |
| 530 | return 0; |
| 531 | } |
| 532 | |
| 533 | static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) |
| 534 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 535 | struct radeon_ttm_tt *gtt = (void *)ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 536 | |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 537 | radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) |
| 542 | { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 543 | struct radeon_ttm_tt *gtt = (void *)ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 544 | |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 545 | ttm_dma_tt_fini(>t->ttm); |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 546 | kfree(gtt); |
| 547 | } |
| 548 | |
| 549 | static struct ttm_backend_func radeon_backend_func = { |
| 550 | .bind = &radeon_ttm_backend_bind, |
| 551 | .unbind = &radeon_ttm_backend_unbind, |
| 552 | .destroy = &radeon_ttm_backend_destroy, |
| 553 | }; |
| 554 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 555 | static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 556 | unsigned long size, uint32_t page_flags, |
| 557 | struct page *dummy_read_page) |
| 558 | { |
| 559 | struct radeon_device *rdev; |
| 560 | struct radeon_ttm_tt *gtt; |
| 561 | |
| 562 | rdev = radeon_get_rdev(bdev); |
| 563 | #if __OS_HAS_AGP |
| 564 | if (rdev->flags & RADEON_IS_AGP) { |
| 565 | return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, |
| 566 | size, page_flags, dummy_read_page); |
| 567 | } |
| 568 | #endif |
| 569 | |
| 570 | gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); |
| 571 | if (gtt == NULL) { |
| 572 | return NULL; |
| 573 | } |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 574 | gtt->ttm.ttm.func = &radeon_backend_func; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 575 | gtt->rdev = rdev; |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 576 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { |
| 577 | kfree(gtt); |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 578 | return NULL; |
| 579 | } |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 580 | return >t->ttm.ttm; |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 581 | } |
| 582 | |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 583 | static int radeon_ttm_tt_populate(struct ttm_tt *ttm) |
| 584 | { |
| 585 | struct radeon_device *rdev; |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 586 | struct radeon_ttm_tt *gtt = (void *)ttm; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 587 | unsigned i; |
| 588 | int r; |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 589 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 590 | |
| 591 | if (ttm->state != tt_unpopulated) |
| 592 | return 0; |
| 593 | |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 594 | if (slave && ttm->sg) { |
| 595 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, |
| 596 | gtt->ttm.dma_address, ttm->num_pages); |
| 597 | ttm->state = tt_unbound; |
| 598 | return 0; |
| 599 | } |
| 600 | |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 601 | rdev = radeon_get_rdev(ttm->bdev); |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 602 | #if __OS_HAS_AGP |
| 603 | if (rdev->flags & RADEON_IS_AGP) { |
| 604 | return ttm_agp_tt_populate(ttm); |
| 605 | } |
| 606 | #endif |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 607 | |
| 608 | #ifdef CONFIG_SWIOTLB |
| 609 | if (swiotlb_nr_tbl()) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 610 | return ttm_dma_populate(>t->ttm, rdev->dev); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 611 | } |
| 612 | #endif |
| 613 | |
| 614 | r = ttm_pool_populate(ttm); |
| 615 | if (r) { |
| 616 | return r; |
| 617 | } |
| 618 | |
| 619 | for (i = 0; i < ttm->num_pages; i++) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 620 | gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], |
| 621 | 0, PAGE_SIZE, |
| 622 | PCI_DMA_BIDIRECTIONAL); |
| 623 | if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 624 | while (--i) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 625 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 626 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 627 | gtt->ttm.dma_address[i] = 0; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 628 | } |
| 629 | ttm_pool_unpopulate(ttm); |
| 630 | return -EFAULT; |
| 631 | } |
| 632 | } |
| 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) |
| 637 | { |
| 638 | struct radeon_device *rdev; |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 639 | struct radeon_ttm_tt *gtt = (void *)ttm; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 640 | unsigned i; |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 641 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
| 642 | |
| 643 | if (slave) |
| 644 | return; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 645 | |
| 646 | rdev = radeon_get_rdev(ttm->bdev); |
Jerome Glisse | dea7e0a | 2012-01-03 17:37:37 -0500 | [diff] [blame] | 647 | #if __OS_HAS_AGP |
| 648 | if (rdev->flags & RADEON_IS_AGP) { |
| 649 | ttm_agp_tt_unpopulate(ttm); |
| 650 | return; |
| 651 | } |
| 652 | #endif |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 653 | |
| 654 | #ifdef CONFIG_SWIOTLB |
| 655 | if (swiotlb_nr_tbl()) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 656 | ttm_dma_unpopulate(>t->ttm, rdev->dev); |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 657 | return; |
| 658 | } |
| 659 | #endif |
| 660 | |
| 661 | for (i = 0; i < ttm->num_pages; i++) { |
Jerome Glisse | 8e7e705 | 2011-11-09 17:15:26 -0500 | [diff] [blame] | 662 | if (gtt->ttm.dma_address[i]) { |
| 663 | pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 664 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 665 | } |
| 666 | } |
| 667 | |
| 668 | ttm_pool_unpopulate(ttm); |
| 669 | } |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 670 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 671 | static struct ttm_bo_driver radeon_bo_driver = { |
Jerome Glisse | 649bf3c | 2011-11-01 20:46:13 -0400 | [diff] [blame] | 672 | .ttm_tt_create = &radeon_ttm_tt_create, |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 673 | .ttm_tt_populate = &radeon_ttm_tt_populate, |
| 674 | .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 675 | .invalidate_caches = &radeon_invalidate_caches, |
| 676 | .init_mem_type = &radeon_init_mem_type, |
| 677 | .evict_flags = &radeon_evict_flags, |
| 678 | .move = &radeon_bo_move, |
| 679 | .verify_access = &radeon_verify_access, |
| 680 | .sync_obj_signaled = &radeon_sync_obj_signaled, |
| 681 | .sync_obj_wait = &radeon_sync_obj_wait, |
| 682 | .sync_obj_flush = &radeon_sync_obj_flush, |
| 683 | .sync_obj_unref = &radeon_sync_obj_unref, |
| 684 | .sync_obj_ref = &radeon_sync_obj_ref, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 685 | .move_notify = &radeon_bo_move_notify, |
| 686 | .fault_reserve_notify = &radeon_bo_fault_reserve_notify, |
Jerome Glisse | 0a2d50e | 2010-04-09 14:39:24 +0200 | [diff] [blame] | 687 | .io_mem_reserve = &radeon_ttm_io_mem_reserve, |
| 688 | .io_mem_free = &radeon_ttm_io_mem_free, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 689 | }; |
| 690 | |
| 691 | int radeon_ttm_init(struct radeon_device *rdev) |
| 692 | { |
| 693 | int r; |
| 694 | |
| 695 | r = radeon_ttm_global_init(rdev); |
| 696 | if (r) { |
| 697 | return r; |
| 698 | } |
| 699 | /* No others user of address space so set it to 0 */ |
| 700 | r = ttm_bo_device_init(&rdev->mman.bdev, |
Thomas Hellstrom | a987fca | 2009-08-18 16:51:56 +0200 | [diff] [blame] | 701 | rdev->mman.bo_global_ref.ref.object, |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 702 | &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, |
| 703 | rdev->need_dma32); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 704 | if (r) { |
| 705 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); |
| 706 | return r; |
| 707 | } |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 708 | rdev->mman.initialized = true; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 709 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 710 | rdev->mc.real_vram_size >> PAGE_SHIFT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 711 | if (r) { |
| 712 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
| 713 | return r; |
| 714 | } |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 715 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 716 | RADEON_GEM_DOMAIN_VRAM, |
| 717 | NULL, &rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 718 | if (r) { |
| 719 | return r; |
| 720 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 721 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
| 722 | if (r) |
| 723 | return r; |
| 724 | r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); |
| 725 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 726 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 727 | radeon_bo_unref(&rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 728 | return r; |
| 729 | } |
| 730 | DRM_INFO("radeon: %uM of VRAM memory ready\n", |
Niels Ole Salscheider | fc98603 | 2013-05-18 21:19:23 +0200 | [diff] [blame] | 731 | (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 732 | r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 733 | rdev->mc.gtt_size >> PAGE_SHIFT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 734 | if (r) { |
| 735 | DRM_ERROR("Failed initializing GTT heap.\n"); |
| 736 | return r; |
| 737 | } |
| 738 | DRM_INFO("radeon: %uM of GTT memory ready.\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 739 | (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); |
Ilija Hadzic | 949c4a3 | 2012-05-15 16:40:10 -0400 | [diff] [blame] | 740 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 741 | |
| 742 | r = radeon_ttm_debugfs_init(rdev); |
| 743 | if (r) { |
| 744 | DRM_ERROR("Failed to init debugfs\n"); |
| 745 | return r; |
| 746 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 747 | return 0; |
| 748 | } |
| 749 | |
| 750 | void radeon_ttm_fini(struct radeon_device *rdev) |
| 751 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 752 | int r; |
| 753 | |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 754 | if (!rdev->mman.initialized) |
| 755 | return; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 756 | if (rdev->stollen_vga_memory) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 757 | r = radeon_bo_reserve(rdev->stollen_vga_memory, false); |
| 758 | if (r == 0) { |
| 759 | radeon_bo_unpin(rdev->stollen_vga_memory); |
| 760 | radeon_bo_unreserve(rdev->stollen_vga_memory); |
| 761 | } |
| 762 | radeon_bo_unref(&rdev->stollen_vga_memory); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 763 | } |
| 764 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 765 | ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); |
| 766 | ttm_bo_device_release(&rdev->mman.bdev); |
| 767 | radeon_gart_fini(rdev); |
| 768 | radeon_ttm_global_fini(rdev); |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 769 | rdev->mman.initialized = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 770 | DRM_INFO("radeon: ttm finalized\n"); |
| 771 | } |
| 772 | |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 773 | /* this should only be called at bootup or when userspace |
| 774 | * isn't running */ |
| 775 | void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) |
| 776 | { |
| 777 | struct ttm_mem_type_manager *man; |
| 778 | |
| 779 | if (!rdev->mman.initialized) |
| 780 | return; |
| 781 | |
| 782 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; |
| 783 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ |
| 784 | man->size = size >> PAGE_SHIFT; |
| 785 | } |
| 786 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 787 | static struct vm_operations_struct radeon_ttm_vm_ops; |
Alexey Dobriyan | f0f37e2 | 2009-09-27 22:29:37 +0400 | [diff] [blame] | 788 | static const struct vm_operations_struct *ttm_vm_ops = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 789 | |
| 790 | static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 791 | { |
| 792 | struct ttm_buffer_object *bo; |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 793 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 794 | int r; |
| 795 | |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 796 | bo = (struct ttm_buffer_object *)vma->vm_private_data; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 797 | if (bo == NULL) { |
| 798 | return VM_FAULT_NOPAGE; |
| 799 | } |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 800 | rdev = radeon_get_rdev(bo->bdev); |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 801 | down_read(&rdev->pm.mclk_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 802 | r = ttm_vm_ops->fault(vma, vmf); |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 803 | up_read(&rdev->pm.mclk_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 804 | return r; |
| 805 | } |
| 806 | |
| 807 | int radeon_mmap(struct file *filp, struct vm_area_struct *vma) |
| 808 | { |
| 809 | struct drm_file *file_priv; |
| 810 | struct radeon_device *rdev; |
| 811 | int r; |
| 812 | |
| 813 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { |
| 814 | return drm_mmap(filp, vma); |
| 815 | } |
| 816 | |
Joe Perches | 40b3be3 | 2010-09-04 18:52:42 -0700 | [diff] [blame] | 817 | file_priv = filp->private_data; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 818 | rdev = file_priv->minor->dev->dev_private; |
| 819 | if (rdev == NULL) { |
| 820 | return -EINVAL; |
| 821 | } |
| 822 | r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); |
| 823 | if (unlikely(r != 0)) { |
| 824 | return r; |
| 825 | } |
| 826 | if (unlikely(ttm_vm_ops == NULL)) { |
| 827 | ttm_vm_ops = vma->vm_ops; |
| 828 | radeon_ttm_vm_ops = *ttm_vm_ops; |
| 829 | radeon_ttm_vm_ops.fault = &radeon_ttm_fault; |
| 830 | } |
| 831 | vma->vm_ops = &radeon_ttm_vm_ops; |
| 832 | return 0; |
| 833 | } |
| 834 | |
| 835 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 836 | #define RADEON_DEBUGFS_MEM_TYPES 2 |
| 837 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 838 | #if defined(CONFIG_DEBUG_FS) |
| 839 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
| 840 | { |
| 841 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 842 | struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; |
| 843 | struct drm_device *dev = node->minor->dev; |
| 844 | struct radeon_device *rdev = dev->dev_private; |
| 845 | int ret; |
| 846 | struct ttm_bo_global *glob = rdev->mman.bdev.glob; |
| 847 | |
| 848 | spin_lock(&glob->lru_lock); |
| 849 | ret = drm_mm_dump_table(m, mm); |
| 850 | spin_unlock(&glob->lru_lock); |
| 851 | return ret; |
| 852 | } |
| 853 | #endif |
| 854 | |
| 855 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) |
| 856 | { |
Mikael Pettersson | f4e45d0 | 2009-09-28 18:27:23 +0200 | [diff] [blame] | 857 | #if defined(CONFIG_DEBUG_FS) |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 858 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; |
| 859 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 860 | unsigned i; |
| 861 | |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 862 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { |
| 863 | if (i == 0) |
| 864 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); |
| 865 | else |
| 866 | sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); |
| 867 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; |
| 868 | radeon_mem_types_list[i].show = &radeon_mm_dump_table; |
| 869 | radeon_mem_types_list[i].driver_features = 0; |
| 870 | if (i == 0) |
Dave Airlie | 16f9fdc | 2011-02-07 12:00:51 +1000 | [diff] [blame] | 871 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 872 | else |
Dave Airlie | 16f9fdc | 2011-02-07 12:00:51 +1000 | [diff] [blame] | 873 | radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 874 | |
| 875 | } |
Pauli Nieminen | 8d7cddc | 2010-04-01 12:44:59 +0000 | [diff] [blame] | 876 | /* Add ttm page pool to debugfs */ |
| 877 | sprintf(radeon_mem_types_names[i], "ttm_page_pool"); |
| 878 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; |
| 879 | radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; |
| 880 | radeon_mem_types_list[i].driver_features = 0; |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 881 | radeon_mem_types_list[i++].data = NULL; |
| 882 | #ifdef CONFIG_SWIOTLB |
| 883 | if (swiotlb_nr_tbl()) { |
| 884 | sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); |
| 885 | radeon_mem_types_list[i].name = radeon_mem_types_names[i]; |
| 886 | radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; |
| 887 | radeon_mem_types_list[i].driver_features = 0; |
| 888 | radeon_mem_types_list[i++].data = NULL; |
| 889 | } |
| 890 | #endif |
| 891 | return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); |
Dave Airlie | fa8a123 | 2009-08-26 13:13:37 +1000 | [diff] [blame] | 892 | |
| 893 | #endif |
| 894 | return 0; |
| 895 | } |