blob: 34cd5d1b586ac854fdcda316e5f5bbcf40d1c953 [file] [log] [blame]
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -07001/*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
Alan Cox64f93032009-06-10 17:30:41 +01005 * Copyright * 2005 Agere Systems Inc.
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -07006 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_phy.c - Routines for configuring and accessing the PHY
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
Alan Cox64f93032009-06-10 17:30:41 +010022 * Copyright * 2005 Agere Systems Inc.
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070023 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
Alan Cox64f93032009-06-10 17:30:41 +010043 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070044 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58#include "et131x_version.h"
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070059#include "et131x_defs.h"
60
61#include <linux/pci.h>
62#include <linux/init.h>
63#include <linux/module.h>
64#include <linux/types.h>
65#include <linux/kernel.h>
66
67#include <linux/sched.h>
68#include <linux/ptrace.h>
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070069#include <linux/ctype.h>
70#include <linux/string.h>
71#include <linux/timer.h>
72#include <linux/interrupt.h>
73#include <linux/in.h>
74#include <linux/delay.h>
Alan Cox64f93032009-06-10 17:30:41 +010075#include <linux/io.h>
76#include <linux/bitops.h>
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070077#include <asm/system.h>
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070078
79#include <linux/netdevice.h>
80#include <linux/etherdevice.h>
81#include <linux/skbuff.h>
82#include <linux/if_arp.h>
83#include <linux/ioport.h>
84#include <linux/random.h>
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070085
86#include "et1310_phy.h"
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070087
88#include "et131x_adapter.h"
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070089
90#include "et1310_address_map.h"
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070091#include "et1310_tx.h"
92#include "et1310_rx.h"
Alan Cox69ea5fc2010-01-18 15:34:24 +000093
94#include "et131x.h"
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070095
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070096/* Prototypes for functions with local scope */
Alan Coxe1bc5842009-10-06 15:51:17 +010097static void et131x_xcvr_init(struct et131x_adapter *etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -070098
99/**
100 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
Alan Coxe1bc5842009-10-06 15:51:17 +0100101 * @etdev: pointer to our private adapter structure
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700102 * @xcvrAddr: the address of the transciever
103 * @xcvrReg: the register to read
104 * @value: pointer to a 16-bit value in which the value will be stored
105 *
106 * Returns 0 on success, errno on failure (as defined in errno.h)
107 */
Alan Coxe1bc5842009-10-06 15:51:17 +0100108int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
Alan Cox1210db92009-10-06 15:51:10 +0100109 u8 xcvrReg, u16 *value)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700110{
Alan Coxe1bc5842009-10-06 15:51:17 +0100111 struct _MAC_t __iomem *mac = &etdev->regs->mac;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700112 int status = 0;
Alan Cox1210db92009-10-06 15:51:10 +0100113 u32 delay;
Alan Cox57aed3b2009-10-06 15:51:04 +0100114 u32 miiAddr;
115 u32 miiCmd;
116 u32 miiIndicator;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700117
118 /* Save a local copy of the registers we are dealing with so we can
119 * set them back
120 */
Alan Cox57aed3b2009-10-06 15:51:04 +0100121 miiAddr = readl(&mac->mii_mgmt_addr);
122 miiCmd = readl(&mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700123
124 /* Stop the current operation */
Alan Cox57aed3b2009-10-06 15:51:04 +0100125 writel(0, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700126
127 /* Set up the register we need to read from on the correct PHY */
Alan Cox57aed3b2009-10-06 15:51:04 +0100128 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700129
130 /* Kick the read cycle off */
131 delay = 0;
132
Alan Cox57aed3b2009-10-06 15:51:04 +0100133 writel(0x1, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700134
135 do {
136 udelay(50);
137 delay++;
Alan Cox57aed3b2009-10-06 15:51:04 +0100138 miiIndicator = readl(&mac->mii_mgmt_indicator);
139 } while ((miiIndicator & MGMT_WAIT) && delay < 50);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700140
141 /* If we hit the max delay, we could not read the register */
Alan Cox57aed3b2009-10-06 15:51:04 +0100142 if (delay == 50) {
Alan Coxe1bc5842009-10-06 15:51:17 +0100143 dev_warn(&etdev->pdev->dev,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700144 "xcvrReg 0x%08x could not be read\n", xcvrReg);
Alan Coxe1bc5842009-10-06 15:51:17 +0100145 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
Alan Cox57aed3b2009-10-06 15:51:04 +0100146 miiIndicator);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700147
148 status = -EIO;
149 }
150
151 /* If we hit here we were able to read the register and we need to
Alan Cox57aed3b2009-10-06 15:51:04 +0100152 * return the value to the caller */
153 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700154
155 /* Stop the read operation */
Alan Cox57aed3b2009-10-06 15:51:04 +0100156 writel(0, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700157
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700158 /* set the registers we touched back to the state at which we entered
159 * this function
160 */
Alan Cox57aed3b2009-10-06 15:51:04 +0100161 writel(miiAddr, &mac->mii_mgmt_addr);
162 writel(miiCmd, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700163
164 return status;
165}
166
167/**
168 * MiWrite - Write to a PHY register through the MII interface of the MAC
Alan Coxe1bc5842009-10-06 15:51:17 +0100169 * @etdev: pointer to our private adapter structure
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700170 * @xcvrReg: the register to read
171 * @value: 16-bit value to write
172 *
Alan Cox1210db92009-10-06 15:51:10 +0100173 * FIXME: one caller in netdev still
174 *
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700175 * Return 0 on success, errno on failure (as defined in errno.h)
176 */
Alan Coxe1bc5842009-10-06 15:51:17 +0100177int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700178{
Alan Coxe1bc5842009-10-06 15:51:17 +0100179 struct _MAC_t __iomem *mac = &etdev->regs->mac;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700180 int status = 0;
Alan Coxe1bc5842009-10-06 15:51:17 +0100181 u8 xcvrAddr = etdev->Stats.xcvr_addr;
Alan Cox1210db92009-10-06 15:51:10 +0100182 u32 delay;
Alan Cox57aed3b2009-10-06 15:51:04 +0100183 u32 miiAddr;
184 u32 miiCmd;
185 u32 miiIndicator;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700186
187 /* Save a local copy of the registers we are dealing with so we can
188 * set them back
189 */
Alan Cox57aed3b2009-10-06 15:51:04 +0100190 miiAddr = readl(&mac->mii_mgmt_addr);
191 miiCmd = readl(&mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700192
193 /* Stop the current operation */
Alan Cox57aed3b2009-10-06 15:51:04 +0100194 writel(0, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700195
196 /* Set up the register we need to write to on the correct PHY */
Alan Cox57aed3b2009-10-06 15:51:04 +0100197 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700198
199 /* Add the value to write to the registers to the mac */
Alan Cox57aed3b2009-10-06 15:51:04 +0100200 writel(value, &mac->mii_mgmt_ctrl);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700201 delay = 0;
202
203 do {
204 udelay(50);
205 delay++;
Alan Cox57aed3b2009-10-06 15:51:04 +0100206 miiIndicator = readl(&mac->mii_mgmt_indicator);
207 } while ((miiIndicator & MGMT_BUSY) && delay < 100);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700208
209 /* If we hit the max delay, we could not write the register */
210 if (delay == 100) {
Alan Cox1210db92009-10-06 15:51:10 +0100211 u16 TempValue;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700212
Alan Coxe1bc5842009-10-06 15:51:17 +0100213 dev_warn(&etdev->pdev->dev,
Alan Cox15700032009-08-27 11:03:09 +0100214 "xcvrReg 0x%08x could not be written", xcvrReg);
Alan Coxe1bc5842009-10-06 15:51:17 +0100215 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
Alan Cox57aed3b2009-10-06 15:51:04 +0100216 miiIndicator);
Alan Coxe1bc5842009-10-06 15:51:17 +0100217 dev_warn(&etdev->pdev->dev, "command is 0x%08x\n",
Alan Cox57aed3b2009-10-06 15:51:04 +0100218 readl(&mac->mii_mgmt_cmd));
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700219
Alan Coxe1bc5842009-10-06 15:51:17 +0100220 MiRead(etdev, xcvrReg, &TempValue);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700221
222 status = -EIO;
223 }
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700224 /* Stop the write operation */
Alan Cox57aed3b2009-10-06 15:51:04 +0100225 writel(0, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700226
227 /* set the registers we touched back to the state at which we entered
Alan Cox64f93032009-06-10 17:30:41 +0100228 * this function
229 */
Alan Cox57aed3b2009-10-06 15:51:04 +0100230 writel(miiAddr, &mac->mii_mgmt_addr);
231 writel(miiCmd, &mac->mii_mgmt_cmd);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700232
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700233 return status;
234}
235
236/**
237 * et131x_xcvr_find - Find the PHY ID
Alan Coxe1bc5842009-10-06 15:51:17 +0100238 * @etdev: pointer to our private adapter structure
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700239 *
240 * Returns 0 on success, errno on failure (as defined in errno.h)
241 */
Alan Coxe1bc5842009-10-06 15:51:17 +0100242int et131x_xcvr_find(struct et131x_adapter *etdev)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700243{
Alan Cox1210db92009-10-06 15:51:10 +0100244 u8 xcvr_addr;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700245 MI_IDR1_t idr1;
246 MI_IDR2_t idr2;
Alan Cox1210db92009-10-06 15:51:10 +0100247 u32 xcvr_id;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700248
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700249 /* We need to get xcvr id and address we just get the first one */
250 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
251 /* Read the ID from the PHY */
Alan Coxe1bc5842009-10-06 15:51:17 +0100252 PhyMiRead(etdev, xcvr_addr,
Alan Cox1210db92009-10-06 15:51:10 +0100253 (u8) offsetof(MI_REGS_t, idr1),
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700254 &idr1.value);
Alan Coxe1bc5842009-10-06 15:51:17 +0100255 PhyMiRead(etdev, xcvr_addr,
Alan Cox1210db92009-10-06 15:51:10 +0100256 (u8) offsetof(MI_REGS_t, idr2),
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700257 &idr2.value);
258
Alan Cox1210db92009-10-06 15:51:10 +0100259 xcvr_id = (u32) ((idr1.value << 16) | idr2.value);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700260
Alan Coxe1bc5842009-10-06 15:51:17 +0100261 if (idr1.value != 0 && idr1.value != 0xffff) {
262 etdev->Stats.xcvr_id = xcvr_id;
263 etdev->Stats.xcvr_addr = xcvr_addr;
264 return 0;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700265 }
266 }
Alan Coxe1bc5842009-10-06 15:51:17 +0100267 return -ENODEV;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700268}
269
Alan Cox1210db92009-10-06 15:51:10 +0100270void ET1310_PhyReset(struct et131x_adapter *etdev)
271{
272 MiWrite(etdev, PHY_CONTROL, 0x8000);
273}
274
Alan Coxe1bc5842009-10-06 15:51:17 +0100275/**
276 * ET1310_PhyPowerDown - PHY power control
277 * @etdev: device to control
278 * @down: true for off/false for back on
279 *
280 * one hundred, ten, one thousand megs
281 * How would you like to have your LAN accessed
282 * Can't you see that this code processed
283 * Phy power, phy power..
284 */
285
Alan Cox1210db92009-10-06 15:51:10 +0100286void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
287{
288 u16 data;
289
290 MiRead(etdev, PHY_CONTROL, &data);
Alan Coxe1bc5842009-10-06 15:51:17 +0100291 data &= ~0x0800; /* Power UP */
292 if (down) /* Power DOWN */
Alan Cox1210db92009-10-06 15:51:10 +0100293 data |= 0x0800;
Alan Coxe1bc5842009-10-06 15:51:17 +0100294 MiWrite(etdev, PHY_CONTROL, data);
Alan Cox1210db92009-10-06 15:51:10 +0100295}
296
Alan Coxe1bc5842009-10-06 15:51:17 +0100297/**
298 * ET130_PhyAutoNEg - autonegotiate control
299 * @etdev: device to control
300 * @enabe: autoneg on/off
301 *
302 * Set up the autonegotiation state according to whether we will be
303 * negotiating the state or forcing a speed.
304 */
305
Alan Cox1210db92009-10-06 15:51:10 +0100306static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
307{
308 u16 data;
309
310 MiRead(etdev, PHY_CONTROL, &data);
Alan Coxe1bc5842009-10-06 15:51:17 +0100311 data &= ~0x1000; /* Autonegotiation OFF */
312 if (enable)
313 data |= 0x1000; /* Autonegotiation ON */
314 MiWrite(etdev, PHY_CONTROL, data);
Alan Cox1210db92009-10-06 15:51:10 +0100315}
316
Alan Coxe1bc5842009-10-06 15:51:17 +0100317/**
318 * ET130_PhyDuplexMode - duplex control
319 * @etdev: device to control
320 * @duplex: duplex on/off
321 *
322 * Set up the duplex state on the PHY
323 */
324
Alan Cox1210db92009-10-06 15:51:10 +0100325static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
326{
327 u16 data;
328
329 MiRead(etdev, PHY_CONTROL, &data);
Alan Coxe1bc5842009-10-06 15:51:17 +0100330 data &= ~0x100; /* Set Half Duplex */
331 if (duplex == TRUEPHY_DUPLEX_FULL)
332 data |= 0x100; /* Set Full Duplex */
333 MiWrite(etdev, PHY_CONTROL, data);
Alan Cox1210db92009-10-06 15:51:10 +0100334}
335
Alan Coxe1bc5842009-10-06 15:51:17 +0100336/**
337 * ET130_PhySpeedSelect - speed control
338 * @etdev: device to control
339 * @duplex: duplex on/off
340 *
341 * Set the speed of our PHY.
342 */
343
Alan Cox1210db92009-10-06 15:51:10 +0100344static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
345{
346 u16 data;
Alan Coxe1bc5842009-10-06 15:51:17 +0100347 static const u16 bits[3]={0x0000, 0x2000, 0x0040};
Alan Cox1210db92009-10-06 15:51:10 +0100348
349 /* Read the PHY control register */
350 MiRead(etdev, PHY_CONTROL, &data);
Alan Cox1210db92009-10-06 15:51:10 +0100351 /* Clear all Speed settings (Bits 6, 13) */
352 data &= ~0x2040;
Alan Cox1210db92009-10-06 15:51:10 +0100353 /* Write back the new speed */
Alan Coxe1bc5842009-10-06 15:51:17 +0100354 MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
Alan Cox1210db92009-10-06 15:51:10 +0100355}
356
Alan Coxe1bc5842009-10-06 15:51:17 +0100357/**
358 * ET1310_PhyLinkStatus - read link state
359 * @etdev: device to read
360 * @link_status: reported link state
361 * @autoneg: reported autonegotiation state (complete/incomplete/disabled)
362 * @linkspeed: returnedlink speed in use
363 * @duplex_mode: reported half/full duplex state
364 * @mdi_mdix: not yet working
365 * @masterslave: report whether we are master or slave
366 * @polarity: link polarity
367 *
368 * I can read your lan like a magazine
369 * I see if your up
370 * I know your link speed
371 * I see all the setting that you'd rather keep
372 */
373
Alan Cox1210db92009-10-06 15:51:10 +0100374static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
375 u8 *link_status,
376 u32 *autoneg,
377 u32 *linkspeed,
378 u32 *duplex_mode,
379 u32 *mdi_mdix,
380 u32 *masterslave, u32 *polarity)
381{
382 u16 mistatus = 0;
383 u16 is1000BaseT = 0;
384 u16 vmi_phystatus = 0;
385 u16 control = 0;
386
387 MiRead(etdev, PHY_STATUS, &mistatus);
388 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
389 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
390 MiRead(etdev, PHY_CONTROL, &control);
391
Alan Coxe1bc5842009-10-06 15:51:17 +0100392 *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
393 *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
Alan Cox1210db92009-10-06 15:51:10 +0100394 TRUEPHY_ANEG_COMPLETE :
395 TRUEPHY_ANEG_NOT_COMPLETE) :
396 TRUEPHY_ANEG_DISABLED;
Alan Coxe1bc5842009-10-06 15:51:17 +0100397 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
398 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
399 /* NOTE: Need to complete this */
400 *mdi_mdix = 0;
Alan Cox1210db92009-10-06 15:51:10 +0100401
Alan Coxe1bc5842009-10-06 15:51:17 +0100402 *masterslave = (is1000BaseT & 0x4000) ?
403 TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
404 *polarity = (vmi_phystatus & 0x0400) ?
405 TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
Alan Cox1210db92009-10-06 15:51:10 +0100406}
407
408static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
409 u16 regnum, u16 andMask, u16 orMask)
410{
411 u16 reg;
412
Alan Cox1210db92009-10-06 15:51:10 +0100413 MiRead(etdev, regnum, &reg);
Alan Cox1210db92009-10-06 15:51:10 +0100414 reg &= andMask;
Alan Cox1210db92009-10-06 15:51:10 +0100415 reg |= orMask;
Alan Cox1210db92009-10-06 15:51:10 +0100416 MiWrite(etdev, regnum, reg);
417}
418
Alan Coxe1bc5842009-10-06 15:51:17 +0100419/* Still used from _mac for BIT_READ */
Alan Cox1210db92009-10-06 15:51:10 +0100420void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
421 u16 regnum, u16 bitnum, u8 *value)
422{
423 u16 reg;
Alan Coxe1bc5842009-10-06 15:51:17 +0100424 u16 mask = 0x0001 << bitnum;
Alan Cox1210db92009-10-06 15:51:10 +0100425
426 /* Read the requested register */
427 MiRead(etdev, regnum, &reg);
428
429 switch (action) {
430 case TRUEPHY_BIT_READ:
Alan Coxe1bc5842009-10-06 15:51:17 +0100431 *value = (reg & mask) >> bitnum;
Alan Cox1210db92009-10-06 15:51:10 +0100432 break;
433
434 case TRUEPHY_BIT_SET:
Alan Coxe1bc5842009-10-06 15:51:17 +0100435 MiWrite(etdev, regnum, reg | mask);
Alan Cox1210db92009-10-06 15:51:10 +0100436 break;
437
438 case TRUEPHY_BIT_CLEAR:
Alan Coxe1bc5842009-10-06 15:51:17 +0100439 MiWrite(etdev, regnum, reg & ~mask);
Alan Cox1210db92009-10-06 15:51:10 +0100440 break;
441
442 default:
443 break;
444 }
445}
446
447void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
448 u16 duplex)
449{
450 u16 data;
451
452 /* Read the PHY 1000 Base-T Control Register */
453 MiRead(etdev, PHY_1000_CONTROL, &data);
454
455 /* Clear Bits 8,9 */
456 data &= ~0x0300;
457
458 switch (duplex) {
459 case TRUEPHY_ADV_DUPLEX_NONE:
460 /* Duplex already cleared, do nothing */
461 break;
462
463 case TRUEPHY_ADV_DUPLEX_FULL:
464 /* Set Bit 9 */
465 data |= 0x0200;
466 break;
467
468 case TRUEPHY_ADV_DUPLEX_HALF:
469 /* Set Bit 8 */
470 data |= 0x0100;
471 break;
472
473 case TRUEPHY_ADV_DUPLEX_BOTH:
474 default:
475 data |= 0x0300;
476 break;
477 }
478
479 /* Write back advertisement */
480 MiWrite(etdev, PHY_1000_CONTROL, data);
481}
482
483static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
484 u16 duplex)
485{
486 u16 data;
487
488 /* Read the Autonegotiation Register (10/100) */
489 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
490
491 /* Clear bits 7,8 */
492 data &= ~0x0180;
493
494 switch (duplex) {
495 case TRUEPHY_ADV_DUPLEX_NONE:
496 /* Duplex already cleared, do nothing */
497 break;
498
499 case TRUEPHY_ADV_DUPLEX_FULL:
500 /* Set Bit 8 */
501 data |= 0x0100;
502 break;
503
504 case TRUEPHY_ADV_DUPLEX_HALF:
505 /* Set Bit 7 */
506 data |= 0x0080;
507 break;
508
509 case TRUEPHY_ADV_DUPLEX_BOTH:
510 default:
511 /* Set Bits 7,8 */
512 data |= 0x0180;
513 break;
514 }
515
516 /* Write back advertisement */
517 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
518}
519
520static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
521 u16 duplex)
522{
523 u16 data;
524
525 /* Read the Autonegotiation Register (10/100) */
526 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
527
528 /* Clear bits 5,6 */
529 data &= ~0x0060;
530
531 switch (duplex) {
532 case TRUEPHY_ADV_DUPLEX_NONE:
533 /* Duplex already cleared, do nothing */
534 break;
535
536 case TRUEPHY_ADV_DUPLEX_FULL:
537 /* Set Bit 6 */
538 data |= 0x0040;
539 break;
540
541 case TRUEPHY_ADV_DUPLEX_HALF:
542 /* Set Bit 5 */
543 data |= 0x0020;
544 break;
545
546 case TRUEPHY_ADV_DUPLEX_BOTH:
547 default:
548 /* Set Bits 5,6 */
549 data |= 0x0060;
550 break;
551 }
552
553 /* Write back advertisement */
554 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
555}
556
Alan Cox1210db92009-10-06 15:51:10 +0100557/**
Alan Coxe1bc5842009-10-06 15:51:17 +0100558 * et131x_setphy_normal - Set PHY for normal operation.
559 * @etdev: pointer to our private adapter structure
Alan Cox1210db92009-10-06 15:51:10 +0100560 *
Alan Coxe1bc5842009-10-06 15:51:17 +0100561 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
562 * when going to D3 in WOL mode. Also used during initialization to set the
563 * PHY for normal operation.
Alan Cox1210db92009-10-06 15:51:10 +0100564 */
Alan Coxe1bc5842009-10-06 15:51:17 +0100565void et131x_setphy_normal(struct et131x_adapter *etdev)
Alan Cox1210db92009-10-06 15:51:10 +0100566{
Alan Coxe1bc5842009-10-06 15:51:17 +0100567 /* Make sure the PHY is powered up */
Alan Cox1210db92009-10-06 15:51:10 +0100568 ET1310_PhyPowerDown(etdev, 0);
Alan Coxe1bc5842009-10-06 15:51:17 +0100569 et131x_xcvr_init(etdev);
Alan Cox1210db92009-10-06 15:51:10 +0100570}
571
Alan Cox1210db92009-10-06 15:51:10 +0100572
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700573/**
574 * et131x_xcvr_init - Init the phy if we are setting it into force mode
Alan Coxe1bc5842009-10-06 15:51:17 +0100575 * @etdev: pointer to our private adapter structure
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700576 *
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700577 */
Alan Coxe1bc5842009-10-06 15:51:17 +0100578static void et131x_xcvr_init(struct et131x_adapter *etdev)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700579{
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700580 MI_IMR_t imr;
581 MI_ISR_t isr;
582 MI_LCR2_t lcr2;
583
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700584 /* Zero out the adapter structure variable representing BMSR */
Alan Coxe1bc5842009-10-06 15:51:17 +0100585 etdev->Bmsr.value = 0;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700586
Alan Coxe1bc5842009-10-06 15:51:17 +0100587 MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value);
588 MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700589
590 /* Set the link status interrupt only. Bad behavior when link status
591 * and auto neg are set, we run into a nested interrupt problem
592 */
593 imr.bits.int_en = 0x1;
594 imr.bits.link_status = 0x1;
595 imr.bits.autoneg_status = 0x1;
596
Alan Coxe1bc5842009-10-06 15:51:17 +0100597 MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700598
599 /* Set the LED behavior such that LED 1 indicates speed (off =
600 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
601 * link and activity (on for link, blink off for activity).
602 *
603 * NOTE: Some customizations have been added here for specific
604 * vendors; The LED behavior is now determined by vendor data in the
605 * EEPROM. However, the above description is the default.
606 */
Alan Coxe1bc5842009-10-06 15:51:17 +0100607 if ((etdev->eepromData[1] & 0x4) == 0) {
608 MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2),
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700609 &lcr2.value);
Alan Coxe1bc5842009-10-06 15:51:17 +0100610 if ((etdev->eepromData[1] & 0x8) == 0)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700611 lcr2.bits.led_tx_rx = 0x3;
612 else
613 lcr2.bits.led_tx_rx = 0x4;
614 lcr2.bits.led_link = 0xa;
Alan Coxe1bc5842009-10-06 15:51:17 +0100615 MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2),
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700616 lcr2.value);
617 }
618
619 /* Determine if we need to go into a force mode and set it */
Alan Coxe1bc5842009-10-06 15:51:17 +0100620 if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
621 if (etdev->RegistryFlowControl == TxOnly ||
622 etdev->RegistryFlowControl == Both)
623 ET1310_PhyAccessMiBit(etdev,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700624 TRUEPHY_BIT_SET, 4, 11, NULL);
Alan Cox1210db92009-10-06 15:51:10 +0100625 else
Alan Coxe1bc5842009-10-06 15:51:17 +0100626 ET1310_PhyAccessMiBit(etdev,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700627 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700628
Alan Coxe1bc5842009-10-06 15:51:17 +0100629 if (etdev->RegistryFlowControl == Both)
630 ET1310_PhyAccessMiBit(etdev,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700631 TRUEPHY_BIT_SET, 4, 10, NULL);
Alan Cox1210db92009-10-06 15:51:10 +0100632 else
Alan Coxe1bc5842009-10-06 15:51:17 +0100633 ET1310_PhyAccessMiBit(etdev,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700634 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700635
636 /* Set the phy to autonegotiation */
Alan Coxe1bc5842009-10-06 15:51:17 +0100637 ET1310_PhyAutoNeg(etdev, true);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700638
639 /* NOTE - Do we need this? */
Alan Coxe1bc5842009-10-06 15:51:17 +0100640 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
641 return;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700642 }
Alan Coxe1bc5842009-10-06 15:51:17 +0100643
644 ET1310_PhyAutoNeg(etdev, false);
645
646 /* Set to the correct force mode. */
647 if (etdev->AiForceDpx != 1) {
648 if (etdev->RegistryFlowControl == TxOnly ||
649 etdev->RegistryFlowControl == Both)
650 ET1310_PhyAccessMiBit(etdev,
651 TRUEPHY_BIT_SET, 4, 11, NULL);
652 else
653 ET1310_PhyAccessMiBit(etdev,
654 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
655
656 if (etdev->RegistryFlowControl == Both)
657 ET1310_PhyAccessMiBit(etdev,
658 TRUEPHY_BIT_SET, 4, 10, NULL);
659 else
660 ET1310_PhyAccessMiBit(etdev,
661 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
662 } else {
663 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
664 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
665 }
666 ET1310_PhyPowerDown(etdev, 1);
667 switch (etdev->AiForceSpeed) {
668 case 10:
669 /* First we need to turn off all other advertisement */
670 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
671 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
672 if (etdev->AiForceDpx == 1) {
673 /* Set our advertise values accordingly */
674 ET1310_PhyAdvertise10BaseT(etdev,
675 TRUEPHY_ADV_DUPLEX_HALF);
676 } else if (etdev->AiForceDpx == 2) {
677 /* Set our advertise values accordingly */
678 ET1310_PhyAdvertise10BaseT(etdev,
679 TRUEPHY_ADV_DUPLEX_FULL);
680 } else {
681 /* Disable autoneg */
682 ET1310_PhyAutoNeg(etdev, false);
683 /* Disable rest of the advertisements */
684 ET1310_PhyAdvertise10BaseT(etdev,
685 TRUEPHY_ADV_DUPLEX_NONE);
686 /* Force 10 Mbps */
687 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
688 /* Force Full duplex */
689 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
690 }
691 break;
692 case 100:
693 /* first we need to turn off all other advertisement */
694 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
695 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
696 if (etdev->AiForceDpx == 1) {
697 /* Set our advertise values accordingly */
698 ET1310_PhyAdvertise100BaseT(etdev,
699 TRUEPHY_ADV_DUPLEX_HALF);
700 /* Set speed */
701 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
702 } else if (etdev->AiForceDpx == 2) {
703 /* Set our advertise values accordingly */
704 ET1310_PhyAdvertise100BaseT(etdev,
705 TRUEPHY_ADV_DUPLEX_FULL);
706 } else {
707 /* Disable autoneg */
708 ET1310_PhyAutoNeg(etdev, false);
709 /* Disable other advertisement */
710 ET1310_PhyAdvertise100BaseT(etdev,
711 TRUEPHY_ADV_DUPLEX_NONE);
712 /* Force 100 Mbps */
713 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
714 /* Force Full duplex */
715 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
716 }
717 break;
718 case 1000:
719 /* first we need to turn off all other advertisement */
720 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
721 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
722 /* set our advertise values accordingly */
723 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
724 break;
725 }
726 ET1310_PhyPowerDown(etdev, 0);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700727}
728
Alan Cox25ad00b2009-08-19 18:21:44 +0100729void et131x_Mii_check(struct et131x_adapter *etdev,
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700730 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
731{
Alan Cox1210db92009-10-06 15:51:10 +0100732 u8 link_status;
733 u32 autoneg_status;
734 u32 speed;
735 u32 duplex;
736 u32 mdi_mdix;
737 u32 masterslave;
738 u32 polarity;
Alan Cox37628602009-08-19 18:21:50 +0100739 unsigned long flags;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700740
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700741 if (bmsr_ints.bits.link_status) {
742 if (bmsr.bits.link_status) {
Alan Cox25ad00b2009-08-19 18:21:44 +0100743 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700744
745 /* Update our state variables and indicate the
746 * connected state
747 */
Alan Cox37628602009-08-19 18:21:50 +0100748 spin_lock_irqsave(&etdev->Lock, flags);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700749
Alan Cox25ad00b2009-08-19 18:21:44 +0100750 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
Alan Coxf6b35d62009-08-27 11:02:05 +0100751 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700752
Alan Cox37628602009-08-19 18:21:50 +0100753 spin_unlock_irqrestore(&etdev->Lock, flags);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700754
Alan Cox5f1377d2009-10-06 15:47:55 +0100755 netif_carrier_on(etdev->netdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700756 } else {
Alan Cox15700032009-08-27 11:03:09 +0100757 dev_warn(&etdev->pdev->dev,
758 "Link down - cable problem ?\n");
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700759
Alan Cox9fa81092009-08-27 11:00:36 +0100760 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
Alan Cox64f93032009-06-10 17:30:41 +0100761 /* NOTE - Is there a way to query this without
762 * TruePHY?
Alan Cox25ad00b2009-08-19 18:21:44 +0100763 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
Alan Cox64f93032009-06-10 17:30:41 +0100764 */
Alan Cox1210db92009-10-06 15:51:10 +0100765 u16 Register18;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700766
Alan Cox25ad00b2009-08-19 18:21:44 +0100767 MiRead(etdev, 0x12, &Register18);
768 MiWrite(etdev, 0x12, Register18 | 0x4);
769 MiWrite(etdev, 0x10, Register18 | 0x8402);
770 MiWrite(etdev, 0x11, Register18 | 511);
771 MiWrite(etdev, 0x12, Register18);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700772 }
773
774 /* For the first N seconds of life, we are in "link
775 * detection" When we are in this state, we should
776 * only report "connected". When the LinkDetection
777 * Timer expires, we can report disconnected (handled
778 * in the LinkDetectionDPC).
779 */
Alan Coxf6b35d62009-08-27 11:02:05 +0100780 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
781 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
Alan Cox37628602009-08-19 18:21:50 +0100782 spin_lock_irqsave(&etdev->Lock, flags);
Alan Cox25ad00b2009-08-19 18:21:44 +0100783 etdev->MediaState =
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700784 NETIF_STATUS_MEDIA_DISCONNECT;
Alan Cox25ad00b2009-08-19 18:21:44 +0100785 spin_unlock_irqrestore(&etdev->Lock,
Alan Cox37628602009-08-19 18:21:50 +0100786 flags);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700787
Alan Cox5f1377d2009-10-06 15:47:55 +0100788 netif_carrier_off(etdev->netdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700789 }
790
Alan Cox9fa81092009-08-27 11:00:36 +0100791 etdev->linkspeed = 0;
Alan Cox576b38e2009-08-27 11:00:47 +0100792 etdev->duplex_mode = 0;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700793
794 /* Free the packets being actively sent & stopped */
Alan Cox25ad00b2009-08-19 18:21:44 +0100795 et131x_free_busy_send_packets(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700796
797 /* Re-initialize the send structures */
Alan Cox25ad00b2009-08-19 18:21:44 +0100798 et131x_init_send(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700799
800 /* Reset the RFD list and re-start RU */
Alan Cox25ad00b2009-08-19 18:21:44 +0100801 et131x_reset_recv(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700802
803 /*
804 * Bring the device back to the state it was during
805 * init prior to autonegotiation being complete. This
806 * way, when we get the auto-neg complete interrupt,
807 * we can complete init by calling ConfigMacREGS2.
808 */
Alan Cox25ad00b2009-08-19 18:21:44 +0100809 et131x_soft_reset(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700810
811 /* Setup ET1310 as per the documentation */
Alan Cox25ad00b2009-08-19 18:21:44 +0100812 et131x_adapter_setup(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700813
814 /* Setup the PHY into coma mode until the cable is
815 * plugged back in
816 */
Alan Cox25ad00b2009-08-19 18:21:44 +0100817 if (etdev->RegistryPhyComa == 1)
818 EnablePhyComa(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700819 }
820 }
821
822 if (bmsr_ints.bits.auto_neg_complete ||
Alan Cox25ad00b2009-08-19 18:21:44 +0100823 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
824 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
825 ET1310_PhyLinkStatus(etdev,
Alan Cox9fa81092009-08-27 11:00:36 +0100826 &link_status, &autoneg_status,
827 &speed, &duplex, &mdi_mdix,
828 &masterslave, &polarity);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700829
Alan Cox9fa81092009-08-27 11:00:36 +0100830 etdev->linkspeed = speed;
831 etdev->duplex_mode = duplex;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700832
Alan Cox25ad00b2009-08-19 18:21:44 +0100833 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700834
Alan Cox9fa81092009-08-27 11:00:36 +0100835 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
Alan Cox64f93032009-06-10 17:30:41 +0100836 /*
837 * NOTE - Is there a way to query this without
838 * TruePHY?
Alan Cox25ad00b2009-08-19 18:21:44 +0100839 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
Alan Cox64f93032009-06-10 17:30:41 +0100840 */
Alan Cox1210db92009-10-06 15:51:10 +0100841 u16 Register18;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700842
Alan Cox25ad00b2009-08-19 18:21:44 +0100843 MiRead(etdev, 0x12, &Register18);
844 MiWrite(etdev, 0x12, Register18 | 0x4);
845 MiWrite(etdev, 0x10, Register18 | 0x8402);
846 MiWrite(etdev, 0x11, Register18 | 511);
847 MiWrite(etdev, 0x12, Register18);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700848 }
849
Alan Cox25ad00b2009-08-19 18:21:44 +0100850 ConfigFlowControl(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700851
Alan Cox9fa81092009-08-27 11:00:36 +0100852 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
Alan Cox25ad00b2009-08-19 18:21:44 +0100853 etdev->RegistryJumboPacket > 2048)
854 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
Alan Cox64f93032009-06-10 17:30:41 +0100855 0x2000);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700856
Alan Cox25ad00b2009-08-19 18:21:44 +0100857 SetRxDmaTimer(etdev);
858 ConfigMACRegs2(etdev);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700859 }
860 }
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700861}
862
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700863/*
864 * The routines which follow provide low-level access to the PHY, and are used
865 * primarily by the routines above (although there are a few places elsewhere
866 * in the driver where this level of access is required).
867 */
868
Alan Cox1210db92009-10-06 15:51:10 +0100869static const u16 ConfigPhy[25][2] = {
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700870 /* Reg Value Register */
871 /* Addr */
872 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
873 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
874 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
875
876 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
877 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
878 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
879
880 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
881 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
882 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
883
884 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
885 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
886 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
887
888 {0x300D, 1}, /* DisableNorm */
889
890 {0x280C, 0x0180}, /* LinkHoldEnd */
891
892 {0x1C21, 0x0002}, /* AlphaM */
893
894 {0x3821, 6}, /* FfeLkgTx0 */
895 {0x381D, 1}, /* FfeLkg1g4 */
896 {0x381E, 1}, /* FfeLkg1g5 */
897 {0x381F, 1}, /* FfeLkg1g6 */
898 {0x3820, 1}, /* FfeLkg1g7 */
899
900 {0x8402, 0x01F0}, /* Btinact */
901 {0x800E, 20}, /* LftrainTime */
902 {0x800F, 24}, /* DvguardTime */
903 {0x8010, 46}, /* IdlguardTime */
904
905 {0, 0}
906
907};
908
909/* condensed version of the phy initialization routine */
Alan Cox25ad00b2009-08-19 18:21:44 +0100910void ET1310_PhyInit(struct et131x_adapter *etdev)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700911{
Alan Cox1210db92009-10-06 15:51:10 +0100912 u16 data, index;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700913
Alan Cox25ad00b2009-08-19 18:21:44 +0100914 if (etdev == NULL)
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700915 return;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700916
Alan Cox64f93032009-06-10 17:30:41 +0100917 /* get the identity (again ?) */
Alan Cox9fa81092009-08-27 11:00:36 +0100918 MiRead(etdev, PHY_ID_1, &data);
919 MiRead(etdev, PHY_ID_2, &data);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700920
Alan Cox64f93032009-06-10 17:30:41 +0100921 /* what does this do/achieve ? */
Alan Cox9fa81092009-08-27 11:00:36 +0100922 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
Alan Cox25ad00b2009-08-19 18:21:44 +0100923 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700924
Alan Cox64f93032009-06-10 17:30:41 +0100925 /* read modem register 0402, should I do something with the return
926 data ? */
Alan Cox25ad00b2009-08-19 18:21:44 +0100927 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
Alan Cox9fa81092009-08-27 11:00:36 +0100928 MiRead(etdev, PHY_DATA_REG, &data);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700929
Alan Cox64f93032009-06-10 17:30:41 +0100930 /* what does this do/achieve ? */
Alan Cox25ad00b2009-08-19 18:21:44 +0100931 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700932
Alan Cox64f93032009-06-10 17:30:41 +0100933 /* get the identity (again ?) */
Alan Cox9fa81092009-08-27 11:00:36 +0100934 MiRead(etdev, PHY_ID_1, &data);
935 MiRead(etdev, PHY_ID_2, &data);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700936
Alan Cox64f93032009-06-10 17:30:41 +0100937 /* what does this achieve ? */
Alan Cox9fa81092009-08-27 11:00:36 +0100938 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
Alan Cox25ad00b2009-08-19 18:21:44 +0100939 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700940
Alan Cox64f93032009-06-10 17:30:41 +0100941 /* read modem register 0402, should I do something with
942 the return data? */
Alan Cox25ad00b2009-08-19 18:21:44 +0100943 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
Alan Cox9fa81092009-08-27 11:00:36 +0100944 MiRead(etdev, PHY_DATA_REG, &data);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700945
Alan Cox25ad00b2009-08-19 18:21:44 +0100946 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700947
Alan Cox64f93032009-06-10 17:30:41 +0100948 /* what does this achieve (should return 0x1040) */
Alan Cox9fa81092009-08-27 11:00:36 +0100949 MiRead(etdev, PHY_CONTROL, &data);
950 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
Alan Cox25ad00b2009-08-19 18:21:44 +0100951 MiWrite(etdev, PHY_CONTROL, 0x1840);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700952
Alan Cox25ad00b2009-08-19 18:21:44 +0100953 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700954
Alan Cox64f93032009-06-10 17:30:41 +0100955 /* here the writing of the array starts.... */
Alan Cox9fa81092009-08-27 11:00:36 +0100956 index = 0;
957 while (ConfigPhy[index][0] != 0x0000) {
Alan Cox64f93032009-06-10 17:30:41 +0100958 /* write value */
Alan Cox9fa81092009-08-27 11:00:36 +0100959 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
960 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700961
Alan Cox64f93032009-06-10 17:30:41 +0100962 /* read it back */
Alan Cox9fa81092009-08-27 11:00:36 +0100963 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
964 MiRead(etdev, PHY_DATA_REG, &data);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700965
Alan Cox64f93032009-06-10 17:30:41 +0100966 /* do a check on the value read back ? */
Alan Cox9fa81092009-08-27 11:00:36 +0100967 index++;
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700968 }
Alan Cox64f93032009-06-10 17:30:41 +0100969 /* here the writing of the array ends... */
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700970
Alan Cox9fa81092009-08-27 11:00:36 +0100971 MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */
972 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
Alan Cox25ad00b2009-08-19 18:21:44 +0100973 MiWrite(etdev, PHY_CONTROL, 0x1040);
974 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
Greg Kroah-Hartmancfb739b2008-04-03 17:30:53 -0700975}
976