blob: 947262fbe031da6837ea20c4759895454d1f1d2d [file] [log] [blame]
Banajit Goswamib016de92017-02-15 21:02:30 -08001/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070014 tlmm: pinctrl@03400000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -080015 compatible = "qcom,sdm845-pinctrl";
Channagoud Kadabieb7f0112017-04-03 20:39:27 -070016 reg = <0x03400000 0xc00000>;
Kyle Yan679cbee2016-07-27 16:55:20 -070017 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Banajit Goswamib016de92017-02-15 21:02:30 -080022
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070023 ufs_dev_reset_assert: ufs_dev_reset_assert {
24 config {
25 pins = "ufs_reset";
26 bias-pull-down; /* default: pull down */
27 /*
28 * UFS_RESET driver strengths are having
29 * different values/steps compared to typical
30 * GPIO drive strengths.
31 *
32 * Following table clarifies:
33 *
34 * HDRV value | UFS_RESET | Typical GPIO
35 * (dec) | (mA) | (mA)
36 * 0 | 0.8 | 2
37 * 1 | 1.55 | 4
38 * 2 | 2.35 | 6
39 * 3 | 3.1 | 8
40 * 4 | 3.9 | 10
41 * 5 | 4.65 | 12
42 * 6 | 5.4 | 14
43 * 7 | 6.15 | 16
44 *
45 * POR value for UFS_RESET HDRV is 3 which means
46 * 3.1mA and we want to use that. Hence just
47 * specify 8mA to "drive-strength" binding and
48 * that should result into writing 3 to HDRV
49 * field.
50 */
51 drive-strength = <8>; /* default: 3.1 mA */
52 output-low; /* active low reset */
53 };
54 };
55
56 ufs_dev_reset_deassert: ufs_dev_reset_deassert {
57 config {
58 pins = "ufs_reset";
59 bias-pull-down; /* default: pull down */
60 /*
61 * default: 3.1 mA
62 * check comments under ufs_dev_reset_assert
63 */
64 drive-strength = <8>;
65 output-high; /* active low reset */
66 };
67 };
68
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070069 flash_led3_front {
70 flash_led3_front_en: flash_led3_front_en {
71 mux {
72 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070073 function = "gpio";
74 };
75
76 config {
77 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070078 drive_strength = <2>;
79 output-high;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070080 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070081 };
82 };
83
84 flash_led3_front_dis: flash_led3_front_dis {
85 mux {
86 pins = "gpio21";
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070087 function = "gpio";
88 };
89
90 config {
91 pins = "gpio21";
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070092 drive_strength = <2>;
93 output-low;
Subbaraman Narayanamurthy58377f02017-03-21 20:38:43 -070094 bias-disable;
Subbaraman Narayanamurthycd21c812017-03-30 18:36:49 -070095 };
96 };
97 };
Subhash Jadavaniafe2a792017-03-31 21:08:29 -070098
Banajit Goswamib016de92017-02-15 21:02:30 -080099 wcd9xxx_intr {
100 wcd_intr_default: wcd_intr_default{
101 mux {
102 pins = "gpio54";
103 function = "gpio";
104 };
105
106 config {
107 pins = "gpio54";
108 drive-strength = <2>; /* 2 mA */
109 bias-pull-down; /* pull down */
110 input-enable;
111 };
112 };
113 };
114
Xiaonian Wang898e0902017-04-08 06:46:29 +0800115 sdc2_clk_on: sdc2_clk_on {
116 config {
117 pins = "sdc2_clk";
118 bias-disable; /* NO pull */
119 drive-strength = <16>; /* 16 MA */
120 };
121 };
122
123 sdc2_clk_off: sdc2_clk_off {
124 config {
125 pins = "sdc2_clk";
126 bias-disable; /* NO pull */
127 drive-strength = <2>; /* 2 MA */
128 };
129 };
130
131 sdc2_cmd_on: sdc2_cmd_on {
132 config {
133 pins = "sdc2_cmd";
134 bias-pull-up; /* pull up */
135 drive-strength = <10>; /* 10 MA */
136 };
137 };
138
139 sdc2_cmd_off: sdc2_cmd_off {
140 config {
141 pins = "sdc2_cmd";
142 bias-pull-up; /* pull up */
143 drive-strength = <2>; /* 2 MA */
144 };
145 };
146
147 sdc2_data_on: sdc2_data_on {
148 config {
149 pins = "sdc2_data";
150 bias-pull-up; /* pull up */
151 drive-strength = <10>; /* 10 MA */
152 };
153 };
154
155 sdc2_data_off: sdc2_data_off {
156 config {
157 pins = "sdc2_data";
158 bias-pull-up; /* pull up */
159 drive-strength = <2>; /* 2 MA */
160 };
161 };
162
Tony Truongc0e0a5f02017-03-15 11:57:40 -0700163 pcie0 {
164 pcie0_clkreq_default: pcie0_clkreq_default {
165 mux {
166 pins = "gpio36";
167 function = "pci_e0";
168 };
169
170 config {
171 pins = "gpio36";
172 drive-strength = <2>;
173 bias-pull-up;
174 };
175 };
176
177 pcie0_perst_default: pcie0_perst_default {
178 mux {
179 pins = "gpio35";
180 function = "gpio";
181 };
182
183 config {
184 pins = "gpio35";
185 drive-strength = <2>;
186 bias-pull-down;
187 };
188 };
189
190 pcie0_wake_default: pcie0_wake_default {
191 mux {
192 pins = "gpio37";
193 function = "gpio";
194 };
195
196 config {
197 pins = "gpio37";
198 drive-strength = <2>;
199 bias-pull-down;
200 };
201 };
202 };
203
Banajit Goswamib016de92017-02-15 21:02:30 -0800204 cdc_reset_ctrl {
205 cdc_reset_sleep: cdc_reset_sleep {
206 mux {
207 pins = "gpio64";
208 function = "gpio";
209 };
210 config {
211 pins = "gpio64";
212 drive-strength = <2>;
213 bias-disable;
214 output-low;
215 };
216 };
217
218 cdc_reset_active:cdc_reset_active {
219 mux {
220 pins = "gpio64";
221 function = "gpio";
222 };
223 config {
224 pins = "gpio64";
225 drive-strength = <8>;
226 bias-pull-down;
227 output-high;
228 };
229 };
230 };
231
232 spkr_i2s_clk_pin {
233 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
234 mux {
235 pins = "gpio69";
236 function = "spkr_i2s";
237 };
238
239 config {
240 pins = "gpio69";
241 drive-strength = <2>; /* 2 mA */
242 bias-pull-down; /* PULL DOWN */
243 };
244 };
245
246 spkr_i2s_clk_active: spkr_i2s_clk_active {
247 mux {
248 pins = "gpio69";
249 function = "spkr_i2s";
250 };
251
252 config {
253 pins = "gpio69";
254 drive-strength = <8>; /* 8 mA */
255 bias-disable; /* NO PULL */
256 };
257 };
258 };
259
260 wcd_gnd_mic_swap {
261 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
262 mux {
263 pins = "gpio51";
264 function = "gpio";
265 };
266 config {
267 pins = "gpio51";
268 drive-strength = <2>;
269 bias-pull-down;
270 output-low;
271 };
272 };
273
274 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
275 mux {
276 pins = "gpio51";
277 function = "gpio";
278 };
279 config {
280 pins = "gpio51";
281 drive-strength = <2>;
282 bias-disable;
283 output-high;
284 };
285 };
286 };
287
288 pri_aux_pcm_clk {
289 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
290 mux {
291 pins = "gpio65";
292 function = "gpio";
293 };
294
295 config {
296 pins = "gpio65";
297 drive-strength = <2>; /* 2 mA */
298 bias-pull-down; /* PULL DOWN */
299 input-enable;
300 };
301 };
302
303 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
304 mux {
305 pins = "gpio65";
306 function = "pri_mi2s";
307 };
308
309 config {
310 pins = "gpio65";
311 drive-strength = <8>; /* 8 mA */
312 bias-disable; /* NO PULL */
313 output-high;
314 };
315 };
316 };
317
318 pri_aux_pcm_sync {
319 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
320 mux {
321 pins = "gpio66";
322 function = "gpio";
323 };
324
325 config {
326 pins = "gpio66";
327 drive-strength = <2>; /* 2 mA */
328 bias-pull-down; /* PULL DOWN */
329 input-enable;
330 };
331 };
332
333 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
334 mux {
335 pins = "gpio66";
336 function = "pri_mi2s_ws";
337 };
338
339 config {
340 pins = "gpio66";
341 drive-strength = <8>; /* 8 mA */
342 bias-disable; /* NO PULL */
343 output-high;
344 };
345 };
346 };
347
348 pri_aux_pcm_din {
349 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
350 mux {
351 pins = "gpio67";
352 function = "gpio";
353 };
354
355 config {
356 pins = "gpio67";
357 drive-strength = <2>; /* 2 mA */
358 bias-pull-down; /* PULL DOWN */
359 input-enable;
360 };
361 };
362
363 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
364 mux {
365 pins = "gpio67";
366 function = "pri_mi2s";
367 };
368
369 config {
370 pins = "gpio67";
371 drive-strength = <8>; /* 8 mA */
372 bias-disable; /* NO PULL */
373 };
374 };
375 };
376
377 pri_aux_pcm_dout {
378 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
379 mux {
380 pins = "gpio68";
381 function = "gpio";
382 };
383
384 config {
385 pins = "gpio68";
386 drive-strength = <2>; /* 2 mA */
387 bias-pull-down; /* PULL DOWN */
388 input-enable;
389 };
390 };
391
392 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
393 mux {
394 pins = "gpio68";
395 function = "pri_mi2s";
396 };
397
398 config {
399 pins = "gpio68";
400 drive-strength = <8>; /* 8 mA */
401 bias-disable; /* NO PULL */
402 };
403 };
404 };
405
Shashank Babu Chinta Venkata2f40bc72017-03-21 15:31:38 -0700406 pmx_sde: pmx_sde {
407 sde_dsi_active: sde_dsi_active {
408 mux {
409 pins = "gpio6", "gpio52";
410 function = "gpio";
411 };
412
413 config {
414 pins = "gpio6", "gpio52";
415 drive-strength = <8>; /* 8 mA */
416 bias-disable = <0>; /* no pull */
417 };
418 };
419 sde_dsi_suspend: sde_dsi_suspend {
420 mux {
421 pins = "gpio6", "gpio52";
422 function = "gpio";
423 };
424
425 config {
426 pins = "gpio6", "gpio52";
427 drive-strength = <2>; /* 2 mA */
428 bias-pull-down; /* PULL DOWN */
429 };
430 };
431 };
432
433 pmx_sde_te {
434 sde_te_active: sde_te_active {
435 mux {
436 pins = "gpio10";
437 function = "mdp_vsync";
438 };
439
440 config {
441 pins = "gpio10";
442 drive-strength = <2>; /* 2 mA */
443 bias-pull-down; /* PULL DOWN */
444 };
445 };
446
447 sde_te_suspend: sde_te_suspend {
448 mux {
449 pins = "gpio10";
450 function = "mdp_vsync";
451 };
452
453 config {
454 pins = "gpio10";
455 drive-strength = <2>; /* 2 mA */
456 bias-pull-down; /* PULL DOWN */
457 };
458 };
459 };
460
Padmanabhan Komanduru887085e2017-05-02 14:57:12 -0700461 sde_dp_aux_active: sde_dp_aux_active {
462 mux {
463 pins = "gpio43", "gpio51";
464 function = "gpio";
465 };
466
467 config {
468 pins = "gpio43", "gpio51";
469 bias-disable = <0>; /* no pull */
470 drive-strength = <8>;
471 };
472 };
473
474 sde_dp_aux_suspend: sde_dp_aux_suspend {
475 mux {
476 pins = "gpio43", "gpio51";
477 function = "gpio";
478 };
479
480 config {
481 pins = "gpio43", "gpio51";
482 bias-pull-down;
483 drive-strength = <2>;
484 };
485 };
486
487 sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
488 mux {
489 pins = "gpio38";
490 function = "gpio";
491 };
492
493 config {
494 pins = "gpio38";
495 bias-disable;
496 drive-strength = <16>;
497 };
498 };
499
500 sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
501 mux {
502 pins = "gpio38";
503 function = "gpio";
504 };
505
506 config {
507 pins = "gpio38";
508 bias-pull-down;
509 drive-strength = <2>;
510 };
511 };
512
Banajit Goswamib016de92017-02-15 21:02:30 -0800513 sec_aux_pcm {
514 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
515 mux {
516 pins = "gpio80", "gpio81";
517 function = "gpio";
518 };
519
520 config {
521 pins = "gpio80", "gpio81";
522 drive-strength = <2>; /* 2 mA */
523 bias-pull-down; /* PULL DOWN */
524 input-enable;
525 };
526 };
527
528 sec_aux_pcm_active: sec_aux_pcm_active {
529 mux {
530 pins = "gpio80", "gpio81";
531 function = "sec_mi2s";
532 };
533
534 config {
535 pins = "gpio80", "gpio81";
536 drive-strength = <8>; /* 8 mA */
537 bias-disable; /* NO PULL */
538 };
539 };
540 };
541
542 sec_aux_pcm_din {
543 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
544 mux {
545 pins = "gpio82";
546 function = "gpio";
547 };
548
549 config {
550 pins = "gpio82";
551 drive-strength = <2>; /* 2 mA */
552 bias-pull-down; /* PULL DOWN */
553 input-enable;
554 };
555 };
556
557 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
558 mux {
559 pins = "gpio82";
560 function = "sec_mi2s";
561 };
562
563 config {
564 pins = "gpio82";
565 drive-strength = <8>; /* 8 mA */
566 bias-disable; /* NO PULL */
567 };
568 };
569 };
570
571 sec_aux_pcm_dout {
572 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
573 mux {
574 pins = "gpio83";
575 function = "gpio";
576 };
577
578 config {
579 pins = "gpio83";
580 drive-strength = <2>; /* 2 mA */
581 bias-pull-down; /* PULL DOWN */
582 input-enable;
583 };
584 };
585
586 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
587 mux {
588 pins = "gpio83";
589 function = "sec_mi2s";
590 };
591
592 config {
593 pins = "gpio83";
594 drive-strength = <8>; /* 8 mA */
595 bias-disable; /* NO PULL */
596 };
597 };
598 };
599
600 tert_aux_pcm {
601 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
602 mux {
603 pins = "gpio75", "gpio76";
604 function = "gpio";
605 };
606
607 config {
608 pins = "gpio75", "gpio76";
609 drive-strength = <2>; /* 2 mA */
610 bias-pull-down; /* PULL DOWN */
611 input-enable;
612 };
613 };
614
615 tert_aux_pcm_active: tert_aux_pcm_active {
616 mux {
617 pins = "gpio75", "gpio76";
618 function = "ter_mi2s";
619 };
620
621 config {
622 pins = "gpio75", "gpio76";
623 drive-strength = <8>; /* 8 mA */
624 bias-disable; /* NO PULL */
625 output-high;
626 };
627 };
628 };
629
630 tert_aux_pcm_din {
631 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
632 mux {
633 pins = "gpio77";
634 function = "gpio";
635 };
636
637 config {
638 pins = "gpio77";
639 drive-strength = <2>; /* 2 mA */
640 bias-pull-down; /* PULL DOWN */
641 input-enable;
642 };
643 };
644
645 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
646 mux {
647 pins = "gpio77";
648 function = "ter_mi2s";
649 };
650
651 config {
652 pins = "gpio77";
653 drive-strength = <8>; /* 8 mA */
654 bias-disable; /* NO PULL */
655 };
656 };
657 };
658
659 tert_aux_pcm_dout {
660 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
661 mux {
662 pins = "gpio78";
663 function = "gpio";
664 };
665
666 config {
667 pins = "gpio78";
668 drive-strength = <2>; /* 2 mA */
669 bias-pull-down; /* PULL DOWN */
670 input-enable;
671 };
672 };
673
674 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
675 mux {
676 pins = "gpio78";
677 function = "ter_mi2s";
678 };
679
680 config {
681 pins = "gpio78";
682 drive-strength = <8>; /* 8 mA */
683 bias-disable; /* NO PULL */
684 };
685 };
686 };
687
688 quat_aux_pcm {
689 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
690 mux {
691 pins = "gpio58", "gpio59";
692 function = "gpio";
693 };
694
695 config {
696 pins = "gpio58", "gpio59";
697 drive-strength = <2>; /* 2 mA */
698 bias-pull-down; /* PULL DOWN */
699 input-enable;
700 };
701 };
702
703 quat_aux_pcm_active: quat_aux_pcm_active {
704 mux {
705 pins = "gpio58", "gpio59";
706 function = "qua_mi2s";
707 };
708
709 config {
710 pins = "gpio58", "gpio59";
711 drive-strength = <8>; /* 8 mA */
712 bias-disable; /* NO PULL */
713 output-high;
714 };
715 };
716 };
717
718 quat_aux_pcm_din {
719 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
720 mux {
721 pins = "gpio60";
722 function = "gpio";
723 };
724
725 config {
726 pins = "gpio60";
727 drive-strength = <2>; /* 2 mA */
728 bias-pull-down; /* PULL DOWN */
729 input-enable;
730 };
731 };
732
733 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
734 mux {
735 pins = "gpio60";
736 function = "qua_mi2s";
737 };
738
739 config {
740 pins = "gpio60";
741 drive-strength = <8>; /* 8 mA */
742 bias-disable; /* NO PULL */
743 };
744 };
745 };
746
747 quat_aux_pcm_dout {
748 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
749 mux {
750 pins = "gpio61";
751 function = "gpio";
752 };
753
754 config {
755 pins = "gpio61";
756 drive-strength = <2>; /* 2 mA */
757 bias-pull-down; /* PULL DOWN */
758 input-enable;
759 };
760 };
761
762 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
763 mux {
764 pins = "gpio61";
765 function = "qua_mi2s";
766 };
767
768 config {
769 pins = "gpio61";
770 drive-strength = <8>; /* 8 mA */
771 bias-disable; /* NO PULL */
772 };
773 };
774 };
775
776 pri_mi2s_mclk {
777 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
778 mux {
779 pins = "gpio64";
780 function = "gpio";
781 };
782
783 config {
784 pins = "gpio64";
785 drive-strength = <2>; /* 2 mA */
786 bias-pull-down; /* PULL DOWN */
787 input-enable;
788 };
789 };
790
791 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
792 mux {
793 pins = "gpio64";
794 function = "pri_mi2s";
795 };
796
797 config {
798 pins = "gpio64";
799 drive-strength = <8>; /* 8 mA */
800 bias-disable; /* NO PULL */
801 output-high;
802 };
803 };
804 };
805
806 pri_mi2s_sck {
807 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
808 mux {
809 pins = "gpio65";
810 function = "gpio";
811 };
812
813 config {
814 pins = "gpio65";
815 drive-strength = <2>; /* 2 mA */
816 bias-pull-down; /* PULL DOWN */
817 input-enable;
818 };
819 };
820
821 pri_mi2s_sck_active: pri_mi2s_sck_active {
822 mux {
823 pins = "gpio65";
824 function = "pri_mi2s";
825 };
826
827 config {
828 pins = "gpio65";
829 drive-strength = <8>; /* 8 mA */
830 bias-disable; /* NO PULL */
831 output-high;
832 };
833 };
834 };
835
836 pri_mi2s_ws {
837 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
838 mux {
839 pins = "gpio66";
840 function = "gpio";
841 };
842
843 config {
844 pins = "gpio66";
845 drive-strength = <2>; /* 2 mA */
846 bias-pull-down; /* PULL DOWN */
847 input-enable;
848 };
849 };
850
851 pri_mi2s_ws_active: pri_mi2s_ws_active {
852 mux {
853 pins = "gpio66";
854 function = "pri_mi2s_ws";
855 };
856
857 config {
858 pins = "gpio66";
859 drive-strength = <8>; /* 8 mA */
860 bias-disable; /* NO PULL */
861 output-high;
862 };
863 };
864 };
865
866 pri_mi2s_sd0 {
867 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
868 mux {
869 pins = "gpio67";
870 function = "gpio";
871 };
872
873 config {
874 pins = "gpio67";
875 drive-strength = <2>; /* 2 mA */
876 bias-pull-down; /* PULL DOWN */
877 input-enable;
878 };
879 };
880
881 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
882 mux {
883 pins = "gpio67";
884 function = "pri_mi2s";
885 };
886
887 config {
888 pins = "gpio67";
889 drive-strength = <8>; /* 8 mA */
890 bias-disable; /* NO PULL */
891 };
892 };
893 };
894
895 pri_mi2s_sd1 {
896 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
897 mux {
898 pins = "gpio68";
899 function = "gpio";
900 };
901
902 config {
903 pins = "gpio68";
904 drive-strength = <2>; /* 2 mA */
905 bias-pull-down; /* PULL DOWN */
906 input-enable;
907 };
908 };
909
910 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
911 mux {
912 pins = "gpio68";
913 function = "pri_mi2s";
914 };
915
916 config {
917 pins = "gpio68";
918 drive-strength = <8>; /* 8 mA */
919 bias-disable; /* NO PULL */
920 };
921 };
922 };
923
924 sec_mi2s_mclk {
925 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
926 mux {
927 pins = "gpio79";
928 function = "gpio";
929 };
930
931 config {
932 pins = "gpio79";
933 drive-strength = <2>; /* 2 mA */
934 bias-pull-down; /* PULL DOWN */
935 input-enable;
936 };
937 };
938
939 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
940 mux {
941 pins = "gpio79";
942 function = "sec_mi2s";
943 };
944
945 config {
946 pins = "gpio79";
947 drive-strength = <8>; /* 8 mA */
948 bias-disable; /* NO PULL */
949 };
950 };
951 };
952
953 sec_mi2s {
954 sec_mi2s_sleep: sec_mi2s_sleep {
955 mux {
956 pins = "gpio80", "gpio81";
957 function = "gpio";
958 };
959
960 config {
961 pins = "gpio80", "gpio81";
962 drive-strength = <2>; /* 2 mA */
963 bias-disable; /* NO PULL */
964 input-enable;
965 };
966 };
967
968 sec_mi2s_active: sec_mi2s_active {
969 mux {
970 pins = "gpio80", "gpio81";
971 function = "sec_mi2s";
972 };
973
974 config {
975 pins = "gpio80", "gpio81";
976 drive-strength = <8>; /* 8 mA */
977 bias-disable; /* NO PULL */
978 };
979 };
980 };
981
982 sec_mi2s_sd0 {
983 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
984 mux {
985 pins = "gpio82";
986 function = "gpio";
987 };
988
989 config {
990 pins = "gpio82";
991 drive-strength = <2>; /* 2 mA */
992 bias-pull-down; /* PULL DOWN */
993 input-enable;
994 };
995 };
996
997 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
998 mux {
999 pins = "gpio82";
1000 function = "sec_mi2s";
1001 };
1002
1003 config {
1004 pins = "gpio82";
1005 drive-strength = <8>; /* 8 mA */
1006 bias-disable; /* NO PULL */
1007 };
1008 };
1009 };
1010
1011 sec_mi2s_sd1 {
1012 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
1013 mux {
1014 pins = "gpio83";
1015 function = "gpio";
1016 };
1017
1018 config {
1019 pins = "gpio83";
1020 drive-strength = <2>; /* 2 mA */
1021 bias-pull-down; /* PULL DOWN */
1022 input-enable;
1023 };
1024 };
1025
1026 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
1027 mux {
1028 pins = "gpio83";
1029 function = "sec_mi2s";
1030 };
1031
1032 config {
1033 pins = "gpio83";
1034 drive-strength = <8>; /* 8 mA */
1035 bias-disable; /* NO PULL */
1036 };
1037 };
1038 };
1039
1040 tert_mi2s_mclk {
1041 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
1042 mux {
1043 pins = "gpio74";
1044 function = "gpio";
1045 };
1046
1047 config {
1048 pins = "gpio74";
1049 drive-strength = <2>; /* 2 mA */
1050 bias-pull-down; /* PULL DOWN */
1051 input-enable;
1052 };
1053 };
1054
1055 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
1056 mux {
1057 pins = "gpio74";
1058 function = "ter_mi2s";
1059 };
1060
1061 config {
1062 pins = "gpio74";
1063 drive-strength = <8>; /* 8 mA */
1064 bias-disable; /* NO PULL */
1065 };
1066 };
1067 };
1068
1069 tert_mi2s {
1070 tert_mi2s_sleep: tert_mi2s_sleep {
1071 mux {
1072 pins = "gpio75", "gpio76";
1073 function = "gpio";
1074 };
1075
1076 config {
1077 pins = "gpio75", "gpio76";
1078 drive-strength = <2>; /* 2 mA */
1079 bias-pull-down; /* PULL DOWN */
1080 input-enable;
1081 };
1082 };
1083
1084 tert_mi2s_active: tert_mi2s_active {
1085 mux {
1086 pins = "gpio75", "gpio76";
1087 function = "ter_mi2s";
1088 };
1089
1090 config {
1091 pins = "gpio75", "gpio76";
1092 drive-strength = <8>; /* 8 mA */
1093 bias-disable; /* NO PULL */
1094 output-high;
1095 };
1096 };
1097 };
1098
1099 tert_mi2s_sd0 {
1100 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
1101 mux {
1102 pins = "gpio77";
1103 function = "gpio";
1104 };
1105
1106 config {
1107 pins = "gpio77";
1108 drive-strength = <2>; /* 2 mA */
1109 bias-pull-down; /* PULL DOWN */
1110 input-enable;
1111 };
1112 };
1113
1114 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
1115 mux {
1116 pins = "gpio77";
1117 function = "ter_mi2s";
1118 };
1119
1120 config {
1121 pins = "gpio77";
1122 drive-strength = <8>; /* 8 mA */
1123 bias-disable; /* NO PULL */
1124 };
1125 };
1126 };
1127
1128 tert_mi2s_sd1 {
1129 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
1130 mux {
1131 pins = "gpio78";
1132 function = "gpio";
1133 };
1134
1135 config {
1136 pins = "gpio78";
1137 drive-strength = <2>; /* 2 mA */
1138 bias-pull-down; /* PULL DOWN */
1139 input-enable;
1140 };
1141 };
1142
1143 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
1144 mux {
1145 pins = "gpio78";
1146 function = "ter_mi2s";
1147 };
1148
1149 config {
1150 pins = "gpio78";
1151 drive-strength = <8>; /* 8 mA */
1152 bias-disable; /* NO PULL */
1153 };
1154 };
1155 };
1156
1157 quat_mi2s_mclk {
1158 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
1159 mux {
1160 pins = "gpio57";
1161 function = "gpio";
1162 };
1163
1164 config {
1165 pins = "gpio57";
1166 drive-strength = <2>; /* 2 mA */
1167 bias-pull-down; /* PULL DOWN */
1168 input-enable;
1169 };
1170 };
1171
1172 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
1173 mux {
1174 pins = "gpio57";
1175 function = "qua_mi2s";
1176 };
1177
1178 config {
1179 pins = "gpio57";
1180 drive-strength = <8>; /* 8 mA */
1181 bias-disable; /* NO PULL */
1182 };
1183 };
1184 };
1185
1186 quat_mi2s {
1187 quat_mi2s_sleep: quat_mi2s_sleep {
1188 mux {
1189 pins = "gpio58", "gpio59";
1190 function = "gpio";
1191 };
1192
1193 config {
1194 pins = "gpio58", "gpio59";
1195 drive-strength = <2>; /* 2 mA */
1196 bias-pull-down; /* PULL DOWN */
1197 input-enable;
1198 };
1199 };
1200
1201 quat_mi2s_active: quat_mi2s_active {
1202 mux {
1203 pins = "gpio58", "gpio59";
1204 function = "qua_mi2s";
1205 };
1206
1207 config {
1208 pins = "gpio58", "gpio59";
1209 drive-strength = <8>; /* 8 mA */
1210 bias-disable; /* NO PULL */
1211 output-high;
1212 };
1213 };
1214 };
1215
1216 quat_mi2s_sd0 {
1217 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
1218 mux {
1219 pins = "gpio60";
1220 function = "gpio";
1221 };
1222
1223 config {
1224 pins = "gpio60";
1225 drive-strength = <2>; /* 2 mA */
1226 bias-pull-down; /* PULL DOWN */
1227 input-enable;
1228 };
1229 };
1230
1231 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
1232 mux {
1233 pins = "gpio60";
1234 function = "qua_mi2s";
1235 };
1236
1237 config {
1238 pins = "gpio60";
1239 drive-strength = <8>; /* 8 mA */
1240 bias-disable; /* NO PULL */
1241 };
1242 };
1243 };
1244
1245 quat_mi2s_sd1 {
1246 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
1247 mux {
1248 pins = "gpio61";
1249 function = "gpio";
1250 };
1251
1252 config {
1253 pins = "gpio61";
1254 drive-strength = <2>; /* 2 mA */
1255 bias-pull-down; /* PULL DOWN */
1256 input-enable;
1257 };
1258 };
1259
1260 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
1261 mux {
1262 pins = "gpio61";
1263 function = "qua_mi2s";
1264 };
1265
1266 config {
1267 pins = "gpio61";
1268 drive-strength = <8>; /* 8 mA */
1269 bias-disable; /* NO PULL */
1270 };
1271 };
1272 };
1273
1274 quat_mi2s_sd2 {
1275 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1276 mux {
1277 pins = "gpio62";
1278 function = "gpio";
1279 };
1280
1281 config {
1282 pins = "gpio62";
1283 drive-strength = <2>; /* 2 mA */
1284 bias-pull-down; /* PULL DOWN */
1285 input-enable;
1286 };
1287 };
1288
1289 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1290 mux {
1291 pins = "gpio62";
1292 function = "qua_mi2s";
1293 };
1294
1295 config {
1296 pins = "gpio62";
1297 drive-strength = <8>; /* 8 mA */
1298 bias-disable; /* NO PULL */
1299 };
1300 };
1301 };
1302
1303 quat_mi2s_sd3 {
1304 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1305 mux {
1306 pins = "gpio63";
1307 function = "gpio";
1308 };
1309
1310 config {
1311 pins = "gpio63";
1312 drive-strength = <2>; /* 2 mA */
1313 bias-pull-down; /* PULL DOWN */
1314 input-enable;
1315 };
1316 };
1317
1318 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1319 mux {
1320 pins = "gpio63";
1321 function = "qua_mi2s";
1322 };
1323
1324 config {
1325 pins = "gpio63";
1326 drive-strength = <8>; /* 8 mA */
1327 bias-disable; /* NO PULL */
1328 };
1329 };
1330 };
Girish Mahadevan2e2fbe72017-03-28 13:28:18 -06001331
1332 /* QUPv3 South SE mappings */
1333 /* SE 0 pin mappings */
1334 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
1335 qupv3_se0_i2c_active: qupv3_se0_i2c_active {
1336 mux {
1337 pins = "gpio0", "gpio1";
1338 function = "qup0";
1339 };
1340
1341 config {
1342 pins = "gpio0", "gpio1";
1343 drive-strength = <2>;
1344 bias-disable;
1345 };
1346 };
1347
1348 qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
1349 mux {
1350 pins = "gpio0", "gpio1";
1351 function = "gpio";
1352 };
1353
1354 config {
1355 pins = "gpio0", "gpio1";
1356 drive-strength = <2>;
1357 bias-pull-up;
1358 };
1359 };
1360 };
1361
1362 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
1363 qupv3_se0_spi_active: qupv3_se0_spi_active {
1364 mux {
1365 pins = "gpio0", "gpio1", "gpio2",
1366 "gpio3";
1367 function = "qup0";
1368 };
1369
1370 config {
1371 pins = "gpio0", "gpio1", "gpio2",
1372 "gpio3";
1373 drive-strength = <6>;
1374 bias-disable;
1375 };
1376 };
1377
1378 qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
1379 mux {
1380 pins = "gpio0", "gpio1", "gpio2",
1381 "gpio3";
1382 function = "gpio";
1383 };
1384
1385 config {
1386 pins = "gpio0", "gpio1", "gpio2",
1387 "gpio3";
1388 drive-strength = <6>;
1389 bias-disable;
1390 };
1391 };
1392 };
1393
1394 /* SE 1 pin mappings */
1395 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
1396 qupv3_se1_i2c_active: qupv3_se1_i2c_active {
1397 mux {
1398 pins = "gpio17", "gpio18";
1399 function = "qup1";
1400 };
1401
1402 config {
1403 pins = "gpio17", "gpio18";
1404 drive-strength = <2>;
1405 bias-disable;
1406 };
1407 };
1408
1409 qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
1410 mux {
1411 pins = "gpio17", "gpio18";
1412 function = "gpio";
1413 };
1414
1415 config {
1416 pins = "gpio17", "gpio18";
1417 drive-strength = <2>;
1418 bias-pull-up;
1419 };
1420 };
1421 };
1422
1423 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
1424 qupv3_se1_spi_active: qupv3_se1_spi_active {
1425 mux {
1426 pins = "gpio17", "gpio18", "gpio19",
1427 "gpio20";
1428 function = "qup1";
1429 };
1430
1431 config {
1432 pins = "gpio17", "gpio18", "gpio19",
1433 "gpio20";
1434 drive-strength = <6>;
1435 bias-disable;
1436 };
1437 };
1438
1439 qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
1440 mux {
1441 pins = "gpio17", "gpio18", "gpio19",
1442 "gpio20";
1443 function = "gpio";
1444 };
1445
1446 config {
1447 pins = "gpio17", "gpio18", "gpio19",
1448 "gpio20";
1449 drive-strength = <6>;
1450 bias-disable;
1451 };
1452 };
1453 };
1454
1455 /* SE 2 pin mappings */
1456 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
1457 qupv3_se2_i2c_active: qupv3_se2_i2c_active {
1458 mux {
1459 pins = "gpio27", "gpio28";
1460 function = "qup2";
1461 };
1462
1463 config {
1464 pins = "gpio27", "gpio28";
1465 drive-strength = <2>;
1466 bias-disable;
1467 };
1468 };
1469
1470 qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
1471 mux {
1472 pins = "gpio27", "gpio28";
1473 function = "gpio";
1474 };
1475
1476 config {
1477 pins = "gpio27", "gpio28";
1478 drive-strength = <2>;
1479 bias-pull-up;
1480 };
1481 };
1482 };
1483
1484 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
1485 qupv3_se2_spi_active: qupv3_se2_spi_active {
1486 mux {
1487 pins = "gpio27", "gpio28", "gpio29",
1488 "gpio30";
1489 function = "qup2";
1490 };
1491
1492 config {
1493 pins = "gpio27", "gpio28", "gpio29",
1494 "gpio30";
1495 drive-strength = <6>;
1496 bias-disable;
1497 };
1498 };
1499
1500 qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
1501 mux {
1502 pins = "gpio27", "gpio28", "gpio29",
1503 "gpio30";
1504 function = "gpio";
1505 };
1506
1507 config {
1508 pins = "gpio27", "gpio28", "gpio29",
1509 "gpio30";
1510 drive-strength = <6>;
1511 bias-disable;
1512 };
1513 };
1514 };
1515
1516 /* SE 3 pin mappings */
1517 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
1518 qupv3_se3_i2c_active: qupv3_se3_i2c_active {
1519 mux {
1520 pins = "gpio41", "gpio42";
1521 function = "qup3";
1522 };
1523
1524 config {
1525 pins = "gpio41", "gpio42";
1526 drive-strength = <2>;
1527 bias-disable;
1528 };
1529 };
1530
1531 qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
1532 mux {
1533 pins = "gpio41", "gpio42";
1534 function = "gpio";
1535 };
1536
1537 config {
1538 pins = "gpio41", "gpio42";
1539 drive-strength = <2>;
1540 bias-pull-up;
1541 };
1542 };
1543 };
1544
1545 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
1546 qupv3_se3_spi_active: qupv3_se3_spi_active {
1547 mux {
1548 pins = "gpio41", "gpio42", "gpio43",
1549 "gpio44";
1550 function = "qup3";
1551 };
1552
1553 config {
1554 pins = "gpio41", "gpio42", "gpio43",
1555 "gpio44";
1556 drive-strength = <6>;
1557 bias-disable;
1558 };
1559 };
1560
1561 qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
1562 mux {
1563 pins = "gpio41", "gpio42", "gpio43",
1564 "gpio44";
1565 function = "gpio";
1566 };
1567
1568 config {
1569 pins = "gpio41", "gpio42", "gpio43",
1570 "gpio44";
1571 drive-strength = <6>;
1572 bias-disable;
1573 };
1574 };
1575 };
1576
1577 /* SE 4 pin mappings */
1578 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
1579 qupv3_se4_i2c_active: qupv3_se4_i2c_active {
1580 mux {
1581 pins = "gpio89", "gpio90";
1582 function = "qup4";
1583 };
1584
1585 config {
1586 pins = "gpio89", "gpio90";
1587 drive-strength = <2>;
1588 bias-disable;
1589 };
1590 };
1591
1592 qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
1593 mux {
1594 pins = "gpio89", "gpio90";
1595 function = "gpio";
1596 };
1597
1598 config {
1599 pins = "gpio89", "gpio90";
1600 drive-strength = <2>;
1601 bias-pull-up;
1602 };
1603 };
1604 };
1605
1606 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
1607 qupv3_se4_spi_active: qupv3_se4_spi_active {
1608 mux {
1609 pins = "gpio89", "gpio90", "gpio91",
1610 "gpio92";
1611 function = "qup4";
1612 };
1613
1614 config {
1615 pins = "gpio89", "gpio90", "gpio91",
1616 "gpio92";
1617 drive-strength = <6>;
1618 bias-disable;
1619 };
1620 };
1621
1622 qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
1623 mux {
1624 pins = "gpio89", "gpio90", "gpio91",
1625 "gpio92";
1626 function = "gpio";
1627 };
1628
1629 config {
1630 pins = "gpio89", "gpio90", "gpio91",
1631 "gpio92";
1632 drive-strength = <6>;
1633 bias-disable;
1634 };
1635 };
1636 };
1637
1638 /* SE 5 pin mappings */
1639 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
1640 qupv3_se5_i2c_active: qupv3_se5_i2c_active {
1641 mux {
1642 pins = "gpio85", "gpio86";
1643 function = "qup5";
1644 };
1645
1646 config {
1647 pins = "gpio85", "gpio86";
1648 drive-strength = <2>;
1649 bias-disable;
1650 };
1651 };
1652
1653 qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
1654 mux {
1655 pins = "gpio85", "gpio86";
1656 function = "gpio";
1657 };
1658
1659 config {
1660 pins = "gpio85", "gpio86";
1661 drive-strength = <2>;
1662 bias-pull-up;
1663 };
1664 };
1665 };
1666
1667 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
1668 qupv3_se5_spi_active: qupv3_se5_spi_active {
1669 mux {
1670 pins = "gpio85", "gpio86", "gpio87",
1671 "gpio88";
1672 function = "qup5";
1673 };
1674
1675 config {
1676 pins = "gpio85", "gpio86", "gpio87",
1677 "gpio88";
1678 drive-strength = <6>;
1679 bias-disable;
1680 };
1681 };
1682
1683 qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
1684 mux {
1685 pins = "gpio85", "gpio86", "gpio87",
1686 "gpio88";
1687 function = "gpio";
1688 };
1689
1690 config {
1691 pins = "gpio85", "gpio86", "gpio87",
1692 "gpio88";
1693 drive-strength = <6>;
1694 bias-disable;
1695 };
1696 };
1697 };
1698
1699 /* SE 6 pin mappings */
1700 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
1701 qupv3_se6_i2c_active: qupv3_se6_i2c_active {
1702 mux {
1703 pins = "gpio45", "gpio46";
1704 function = "qup6";
1705 };
1706
1707 config {
1708 pins = "gpio45", "gpio46";
1709 drive-strength = <2>;
1710 bias-disable;
1711 };
1712 };
1713
1714 qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
1715 mux {
1716 pins = "gpio45", "gpio46";
1717 function = "gpio";
1718 };
1719
1720 config {
1721 pins = "gpio45", "gpio46";
1722 drive-strength = <2>;
1723 bias-pull-up;
1724 };
1725 };
1726 };
1727
1728 qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
1729 qupv3_se6_4uart_active: qupv3_se6_4uart_active {
1730 mux {
1731 pins = "gpio45", "gpio46", "gpio47",
1732 "gpio48";
1733 function = "qup6";
1734 };
1735
1736 config {
1737 pins = "gpio45", "gpio46", "gpio47",
1738 "gpio48";
1739 drive-strength = <2>;
1740 bias-disable;
1741 };
1742 };
1743
1744 qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep {
1745 mux {
1746 pins = "gpio45", "gpio46", "gpio47",
1747 "gpio48";
1748 function = "gpio";
1749 };
1750
1751 config {
1752 pins = "gpio45", "gpio46", "gpio47",
1753 "gpio48";
1754 drive-strength = <2>;
1755 bias-disable;
1756 };
1757 };
1758 };
1759
1760 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
1761 qupv3_se6_spi_active: qupv3_se6_spi_active {
1762 mux {
1763 pins = "gpio45", "gpio46", "gpio47",
1764 "gpio48";
1765 function = "qup6";
1766 };
1767
1768 config {
1769 pins = "gpio45", "gpio46", "gpio47",
1770 "gpio48";
1771 drive-strength = <6>;
1772 bias-disable;
1773 };
1774 };
1775
1776 qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
1777 mux {
1778 pins = "gpio45", "gpio46", "gpio47",
1779 "gpio48";
1780 function = "gpio";
1781 };
1782
1783 config {
1784 pins = "gpio45", "gpio46", "gpio47",
1785 "gpio48";
1786 drive-strength = <6>;
1787 bias-disable;
1788 };
1789 };
1790 };
1791
1792 /* SE 7 pin mappings */
1793 qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
1794 qupv3_se7_i2c_active: qupv3_se7_i2c_active {
1795 mux {
1796 pins = "gpio93", "gpio94";
1797 function = "qup7";
1798 };
1799
1800 config {
1801 pins = "gpio93", "gpio94";
1802 drive-strength = <2>;
1803 bias-disable;
1804 };
1805 };
1806
1807 qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
1808 mux {
1809 pins = "gpio93", "gpio94";
1810 function = "gpio";
1811 };
1812
1813 config {
1814 pins = "gpio93", "gpio94";
1815 drive-strength = <2>;
1816 bias-pull-up;
1817 };
1818 };
1819 };
1820
1821 qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
1822 qupv3_se7_4uart_active: qupv3_se7_4uart_active {
1823 mux {
1824 pins = "gpio93", "gpio94", "gpio95",
1825 "gpio96";
1826 function = "qup7";
1827 };
1828
1829 config {
1830 pins = "gpio93", "gpio94", "gpio95",
1831 "gpio96";
1832 drive-strength = <2>;
1833 bias-disable;
1834 };
1835 };
1836
1837 qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep {
1838 mux {
1839 pins = "gpio93", "gpio94", "gpio95",
1840 "gpio96";
1841 function = "gpio";
1842 };
1843
1844 config {
1845 pins = "gpio93", "gpio94", "gpio95",
1846 "gpio96";
1847 drive-strength = <2>;
1848 bias-disable;
1849 };
1850 };
1851 };
1852
1853 qupv3_se7_spi_pins: qupv3_se7_spi_pins {
1854 qupv3_se7_spi_active: qupv3_se7_spi_active {
1855 mux {
1856 pins = "gpio93", "gpio94", "gpio95",
1857 "gpio96";
1858 function = "qup7";
1859 };
1860
1861 config {
1862 pins = "gpio93", "gpio94", "gpio95",
1863 "gpio96";
1864 drive-strength = <6>;
1865 bias-disable;
1866 };
1867 };
1868
1869 qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
1870 mux {
1871 pins = "gpio93", "gpio94", "gpio95",
1872 "gpio96";
1873 function = "gpio";
1874 };
1875
1876 config {
1877 pins = "gpio93", "gpio94", "gpio95",
1878 "gpio96";
1879 drive-strength = <6>;
1880 bias-disable;
1881 };
1882 };
1883 };
1884
1885 /* QUPv3 North instances */
1886 /* SE 8 pin mappings */
1887 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
1888 qupv3_se8_i2c_active: qupv3_se8_i2c_active {
1889 mux {
1890 pins = "gpio65", "gpio66";
1891 function = "qup8";
1892 };
1893
1894 config {
1895 pins = "gpio65", "gpio66";
1896 drive-strength = <2>;
1897 bias-disable;
1898 };
1899 };
1900
1901 qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
1902 mux {
1903 pins = "gpio65", "gpio66";
1904 function = "gpio";
1905 };
1906
1907 config {
1908 pins = "gpio65", "gpio66";
1909 drive-strength = <2>;
1910 bias-pull-up;
1911 };
1912 };
1913 };
1914
1915 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
1916 qupv3_se8_spi_active: qupv3_se8_spi_active {
1917 mux {
1918 pins = "gpio65", "gpio66", "gpio67",
1919 "gpio68";
1920 function = "qup8";
1921 };
1922
1923 config {
1924 pins = "gpio65", "gpio66", "gpio67",
1925 "gpio68";
1926 drive-strength = <6>;
1927 bias-disable;
1928 };
1929 };
1930
1931 qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
1932 mux {
1933 pins = "gpio65", "gpio66", "gpio67",
1934 "gpio68";
1935 function = "gpio";
1936 };
1937
1938 config {
1939 pins = "gpio65", "gpio66", "gpio67",
1940 "gpio68";
1941 drive-strength = <6>;
1942 bias-disable;
1943 };
1944 };
1945 };
1946
1947 /* SE 9 pin mappings */
1948 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
1949 qupv3_se9_i2c_active: qupv3_se9_i2c_active {
1950 mux {
1951 pins = "gpio6", "gpio7";
1952 function = "qup9";
1953 };
1954
1955 config {
1956 pins = "gpio6", "gpio7";
1957 drive-strength = <2>;
1958 bias-disable;
1959 };
1960 };
1961
1962 qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
1963 mux {
1964 pins = "gpio6", "gpio7";
1965 function = "gpio";
1966 };
1967
1968 config {
1969 pins = "gpio6", "gpio7";
1970 drive-strength = <2>;
1971 bias-pull-up;
1972 };
1973 };
1974 };
1975
1976 qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
1977 qupv3_se9_2uart_active: qupv3_se9_2uart_active {
1978 mux {
1979 pins = "gpio4", "gpio5";
1980 function = "qup9";
1981 };
1982
1983 config {
1984 pins = "gpio4", "gpio5";
1985 drive-strength = <2>;
1986 bias-disable;
1987 };
1988 };
1989
1990 qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
1991 mux {
1992 pins = "gpio4", "gpio5";
1993 function = "gpio";
1994 };
1995
1996 config {
1997 pins = "gpio4", "gpio5";
1998 drive-strength = <2>;
1999 bias-disable;
2000 };
2001 };
2002 };
2003
2004 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
2005 qupv3_se9_spi_active: qupv3_se9_spi_active {
2006 mux {
2007 pins = "gpio4", "gpio5", "gpio6",
2008 "gpio7";
2009 function = "qup9";
2010 };
2011
2012 config {
2013 pins = "gpio4", "gpio5", "gpio6",
2014 "gpio7";
2015 drive-strength = <6>;
2016 bias-disable;
2017 };
2018 };
2019
2020 qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
2021 mux {
2022 pins = "gpio4", "gpio5", "gpio6",
2023 "gpio7";
2024 function = "gpio";
2025 };
2026
2027 config {
2028 pins = "gpio4", "gpio5", "gpio6",
2029 "gpio7";
2030 drive-strength = <6>;
2031 bias-disable;
2032 };
2033 };
2034 };
2035
2036 /* SE 10 pin mappings */
2037 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
2038 qupv3_se10_i2c_active: qupv3_se10_i2c_active {
2039 mux {
2040 pins = "gpio55", "gpio56";
2041 function = "qup10";
2042 };
2043
2044 config {
2045 pins = "gpio55", "gpio56";
2046 drive-strength = <2>;
2047 bias-disable;
2048 };
2049 };
2050
2051 qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
2052 mux {
2053 pins = "gpio55", "gpio56";
2054 function = "gpio";
2055 };
2056
2057 config {
2058 pins = "gpio55", "gpio56";
2059 drive-strength = <2>;
2060 bias-pull-up;
2061 };
2062 };
2063 };
2064
2065 qupv3_se10_2uart_pins: qupv3_se10_2uart_pins {
2066 qupv3_se10_2uart_active: qupv3_se10_2uart_active {
2067 mux {
2068 pins = "gpio53", "gpio54";
2069 function = "qup10";
2070 };
2071
2072 config {
2073 pins = "gpio53", "gpio54";
2074 drive-strength = <2>;
2075 bias-disable;
2076 };
2077 };
2078
2079 qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep {
2080 mux {
2081 pins = "gpio53", "gpio54";
2082 function = "gpio";
2083 };
2084
2085 config {
2086 pins = "gpio53", "gpio54";
2087 drive-strength = <2>;
2088 bias-disable;
2089 };
2090 };
2091 };
2092
2093 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
2094 qupv3_se10_spi_active: qupv3_se10_spi_active {
2095 mux {
2096 pins = "gpio53", "gpio54", "gpio55",
2097 "gpio56";
2098 function = "qup10";
2099 };
2100
2101 config {
2102 pins = "gpio53", "gpio54", "gpio55",
2103 "gpio56";
2104 drive-strength = <6>;
2105 bias-disable;
2106 };
2107 };
2108
2109 qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
2110 mux {
2111 pins = "gpio53", "gpio54", "gpio55",
2112 "gpio56";
2113 function = "gpio";
2114 };
2115
2116 config {
2117 pins = "gpio53", "gpio54", "gpio55",
2118 "gpio56";
2119 drive-strength = <6>;
2120 bias-disable;
2121 };
2122 };
2123 };
2124
2125 /* SE 11 pin mappings */
2126 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
2127 qupv3_se11_i2c_active: qupv3_se11_i2c_active {
2128 mux {
2129 pins = "gpio31", "gpio32";
2130 function = "qup11";
2131 };
2132
2133 config {
2134 pins = "gpio31", "gpio32";
2135 drive-strength = <2>;
2136 bias-disable;
2137 };
2138 };
2139
2140 qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
2141 mux {
2142 pins = "gpio31", "gpio32";
2143 function = "gpio";
2144 };
2145
2146 config {
2147 pins = "gpio31", "gpio32";
2148 drive-strength = <2>;
2149 bias-pull-up;
2150 };
2151 };
2152 };
2153
2154 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
2155 qupv3_se11_spi_active: qupv3_se11_spi_active {
2156 mux {
2157 pins = "gpio31", "gpio32", "gpio33",
2158 "gpio34";
2159 function = "qup11";
2160 };
2161
2162 config {
2163 pins = "gpio31", "gpio32", "gpio33",
2164 "gpio34";
2165 drive-strength = <6>;
2166 bias-disable;
2167 };
2168 };
2169
2170 qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
2171 mux {
2172 pins = "gpio31", "gpio32", "gpio33",
2173 "gpio34";
2174 function = "gpio";
2175 };
2176
2177 config {
2178 pins = "gpio31", "gpio32", "gpio33",
2179 "gpio34";
2180 drive-strength = <6>;
2181 bias-disable;
2182 };
2183 };
2184 };
2185
2186 /* SE 12 pin mappings */
2187 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
2188 qupv3_se12_i2c_active: qupv3_se12_i2c_active {
2189 mux {
2190 pins = "gpio49", "gpio50";
2191 function = "qup12";
2192 };
2193
2194 config {
2195 pins = "gpio49", "gpio50";
2196 drive-strength = <2>;
2197 bias-disable;
2198 };
2199 };
2200
2201 qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
2202 mux {
2203 pins = "gpio49", "gpio50";
2204 function = "gpio";
2205 };
2206
2207 config {
2208 pins = "gpio49", "gpio50";
2209 drive-strength = <2>;
2210 bias-pull-up;
2211 };
2212 };
2213 };
2214
2215 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
2216 qupv3_se12_spi_active: qupv3_se12_spi_active {
2217 mux {
2218 pins = "gpio49", "gpio50", "gpio51",
2219 "gpio52";
2220 function = "qup12";
2221 };
2222
2223 config {
2224 pins = "gpio49", "gpio50", "gpio51",
2225 "gpio52";
2226 drive-strength = <6>;
2227 bias-disable;
2228 };
2229 };
2230
2231 qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
2232 mux {
2233 pins = "gpio49", "gpio50", "gpio51",
2234 "gpio52";
2235 function = "gpio";
2236 };
2237
2238 config {
2239 pins = "gpio49", "gpio50", "gpio51",
2240 "gpio52";
2241 drive-strength = <6>;
2242 bias-disable;
2243 };
2244 };
2245 };
2246
2247 /* SE 13 pin mappings */
2248 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
2249 qupv3_se13_i2c_active: qupv3_se13_i2c_active {
2250 mux {
2251 pins = "gpio105", "gpio106";
2252 function = "qup13";
2253 };
2254
2255 config {
2256 pins = "gpio105", "gpio106";
2257 drive-strength = <2>;
2258 bias-disable;
2259 };
2260 };
2261
2262 qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
2263 mux {
2264 pins = "gpio105", "gpio106";
2265 function = "gpio";
2266 };
2267
2268 config {
2269 pins = "gpio105", "gpio106";
2270 drive-strength = <2>;
2271 bias-pull-up;
2272 };
2273 };
2274 };
2275
2276 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
2277 qupv3_se13_spi_active: qupv3_se13_spi_active {
2278 mux {
2279 pins = "gpio105", "gpio106", "gpio107",
2280 "gpio108";
2281 function = "qup13";
2282 };
2283
2284 config {
2285 pins = "gpio105", "gpio106", "gpio107",
2286 "gpio108";
2287 drive-strength = <6>;
2288 bias-disable;
2289 };
2290 };
2291
2292 qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
2293 mux {
2294 pins = "gpio105", "gpio106", "gpio107",
2295 "gpio108";
2296 function = "gpio";
2297 };
2298
2299 config {
2300 pins = "gpio105", "gpio106", "gpio107",
2301 "gpio108";
2302 drive-strength = <6>;
2303 bias-disable;
2304 };
2305 };
2306 };
2307
2308 /* SE 14 pin mappings */
2309 qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
2310 qupv3_se14_i2c_active: qupv3_se14_i2c_active {
2311 mux {
2312 pins = "gpio33", "gpio34";
2313 function = "qup14";
2314 };
2315
2316 config {
2317 pins = "gpio33", "gpio34";
2318 drive-strength = <2>;
2319 bias-disable;
2320 };
2321 };
2322
2323 qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
2324 mux {
2325 pins = "gpio33", "gpio34";
2326 function = "gpio";
2327 };
2328
2329 config {
2330 pins = "gpio33", "gpio34";
2331 drive-strength = <2>;
2332 bias-pull-up;
2333 };
2334 };
2335 };
2336
2337 qupv3_se14_spi_pins: qupv3_se14_spi_pins {
2338 qupv3_se14_spi_active: qupv3_se14_spi_active {
2339 mux {
2340 pins = "gpio31", "gpio32", "gpio33",
2341 "gpio34";
2342 function = "qup14";
2343 };
2344
2345 config {
2346 pins = "gpio31", "gpio32", "gpio33",
2347 "gpio34";
2348 drive-strength = <6>;
2349 bias-disable;
2350 };
2351 };
2352
2353 qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
2354 mux {
2355 pins = "gpio31", "gpio32", "gpio33",
2356 "gpio34";
2357 function = "gpio";
2358 };
2359
2360 config {
2361 pins = "gpio31", "gpio32", "gpio33",
2362 "gpio34";
2363 drive-strength = <6>;
2364 bias-disable;
2365 };
2366 };
2367 };
2368
2369 /* SE 15 pin mappings */
2370 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
2371 qupv3_se15_i2c_active: qupv3_se15_i2c_active {
2372 mux {
2373 pins = "gpio81", "gpio82";
2374 function = "qup15";
2375 };
2376
2377 config {
2378 pins = "gpio81", "gpio82";
2379 drive-strength = <2>;
2380 bias-disable;
2381 };
2382 };
2383
2384 qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
2385 mux {
2386 pins = "gpio81", "gpio82";
2387 function = "gpio";
2388 };
2389
2390 config {
2391 pins = "gpio81", "gpio82";
2392 drive-strength = <2>;
2393 bias-pull-up;
2394 };
2395 };
2396 };
2397
2398 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
2399 qupv3_se15_spi_active: qupv3_se15_spi_active {
2400 mux {
2401 pins = "gpio81", "gpio82", "gpio83",
2402 "gpio84";
2403 function = "qup15";
2404 };
2405
2406 config {
2407 pins = "gpio81", "gpio82", "gpio83",
2408 "gpio84";
2409 drive-strength = <6>;
2410 bias-disable;
2411 };
2412 };
2413
2414 qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
2415 mux {
2416 pins = "gpio81", "gpio82", "gpio83",
2417 "gpio84";
2418 function = "gpio";
2419 };
2420
2421 config {
2422 pins = "gpio81", "gpio82", "gpio83",
2423 "gpio84";
2424 drive-strength = <6>;
2425 bias-disable;
2426 };
2427 };
2428 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002429
2430 cci0_active: cci0_active {
2431 mux {
2432 /* CLK, DATA */
2433 pins = "gpio17","gpio18"; // Only 2
2434 function = "cci_i2c";
2435 };
2436
2437 config {
2438 pins = "gpio17","gpio18";
2439 bias-pull-up; /* PULL UP*/
2440 drive-strength = <2>; /* 2 MA */
2441 };
2442 };
2443
2444 cci0_suspend: cci0_suspend {
2445 mux {
2446 /* CLK, DATA */
2447 pins = "gpio17","gpio18";
2448 function = "cci_i2c";
2449 };
2450
2451 config {
2452 pins = "gpio17","gpio18";
2453 bias-pull-down; /* PULL DOWN */
2454 drive-strength = <2>; /* 2 MA */
2455 };
2456 };
2457
2458 cci1_active: cci1_active {
2459 mux {
2460 /* CLK, DATA */
2461 pins = "gpio19","gpio20";
2462 function = "cci_i2c";
2463 };
2464
2465 config {
2466 pins = "gpio19","gpio20";
2467 bias-pull-up; /* PULL UP*/
2468 drive-strength = <2>; /* 2 MA */
2469 };
2470 };
2471
2472 cci1_suspend: cci1_suspend {
2473 mux {
2474 /* CLK, DATA */
2475 pins = "gpio19","gpio20";
2476 function = "cci_i2c";
2477 };
2478
2479 config {
2480 pins = "gpio19","gpio20";
2481 bias-pull-down; /* PULL DOWN */
2482 drive-strength = <2>; /* 2 MA */
2483 };
2484 };
2485
2486 cam_sensor_mclk0_active: cam_sensor_mclk0_active {
2487 /* MCLK0 */
2488 mux {
2489 pins = "gpio13";
2490 function = "cam_mclk";
2491 };
2492
2493 config {
2494 pins = "gpio13";
2495 bias-disable; /* No PULL */
2496 drive-strength = <2>; /* 2 MA */
2497 };
2498 };
2499
2500 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
2501 /* MCLK0 */
2502 mux {
2503 pins = "gpio13";
2504 function = "cam_mclk";
2505 };
2506
2507 config {
2508 pins = "gpio13";
2509 bias-pull-down; /* PULL DOWN */
2510 drive-strength = <2>; /* 2 MA */
2511 };
2512 };
2513
2514 cam_sensor_rear_active: cam_sensor_rear_active {
2515 /* RESET, AVDD LDO */
2516 mux {
2517 pins = "gpio80","gpio79";
2518 function = "gpio";
2519 };
2520
2521 config {
2522 pins = "gpio80","gpio79";
2523 bias-disable; /* No PULL */
2524 drive-strength = <2>; /* 2 MA */
2525 };
2526 };
2527
2528 cam_sensor_rear_suspend: cam_sensor_rear_suspend {
2529 /* RESET, AVDD LDO */
2530 mux {
2531 pins = "gpio80","gpio79";
2532 function = "gpio";
2533 };
2534
2535 config {
2536 pins = "gpio80","gpio79";
2537 bias-disable; /* No PULL */
2538 drive-strength = <2>; /* 2 MA */
2539 };
2540 };
2541
2542 cam_sensor_mclk1_active: cam_sensor_mclk1_active {
2543 /* MCLK1 */
2544 mux {
2545 pins = "gpio14";
2546 function = "cam_mclk";
2547 };
2548
2549 config {
2550 pins = "gpio14";
2551 bias-disable; /* No PULL */
2552 drive-strength = <2>; /* 2 MA */
2553 };
2554 };
2555
2556 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
2557 /* MCLK1 */
2558 mux {
2559 pins = "gpio14";
2560 function = "cam_mclk";
2561 };
2562
2563 config {
2564 pins = "gpio14";
2565 bias-pull-down; /* PULL DOWN */
2566 drive-strength = <2>; /* 2 MA */
2567 };
2568 };
2569
2570 cam_sensor_front_active: cam_sensor_front_active {
2571 /* RESET AVDD_LDO*/
2572 mux {
2573 pins = "gpio28", "gpio8";
2574 function = "gpio";
2575 };
2576
2577 config {
2578 pins = "gpio28", "gpio8";
2579 bias-disable; /* No PULL */
2580 drive-strength = <2>; /* 2 MA */
2581 };
2582 };
2583
2584 cam_sensor_front_suspend: cam_sensor_front_suspend {
2585 /* RESET */
2586 mux {
2587 pins = "gpio28";
2588 function = "gpio";
2589 };
2590
2591 config {
2592 pins = "gpio28";
2593 bias-disable; /* No PULL */
2594 drive-strength = <2>; /* 2 MA */
2595 };
2596 };
2597
2598 cam_sensor_mclk2_active: cam_sensor_mclk2_active {
2599 /* MCLK1 */
2600 mux {
2601 /* CLK, DATA */
2602 pins = "gpio15";
2603 function = "cam_mclk";
2604 };
2605
2606 config {
2607 pins = "gpio15";
2608 bias-disable; /* No PULL */
2609 drive-strength = <2>; /* 2 MA */
2610 };
2611 };
2612
2613 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
2614 /* MCLK1 */
2615 mux {
2616 /* CLK, DATA */
2617 pins = "gpio15";
2618 function = "cam_mclk";
2619 };
2620
2621 config {
2622 pins = "gpio15";
2623 bias-pull-down; /* PULL DOWN */
2624 drive-strength = <2>; /* 2 MA */
2625 };
2626 };
2627
2628 cam_sensor_rear2_active: cam_sensor_rear2_active {
2629 /* RESET, STANDBY */
2630 mux {
2631 pins = "gpio9","gpio8";
2632 function = "gpio";
2633 };
2634
2635 config {
2636 pins = "gpio9","gpio8";
2637 bias-disable; /* No PULL */
2638 drive-strength = <2>; /* 2 MA */
2639 };
2640 };
2641
2642 cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
2643 /* RESET, STANDBY */
2644 mux {
2645 pins = "gpio9","gpio8";
2646 function = "gpio";
2647 };
2648 config {
2649 pins = "gpio9","gpio8";
2650 bias-disable; /* No PULL */
2651 drive-strength = <2>; /* 2 MA */
2652 };
2653 };
Satyajit Desaie4508132017-04-05 17:15:22 -07002654
2655 trigout_a: trigout_a {
2656 mux {
2657 pins = "gpio62", "gpio51";
2658 function = "qdss_cti";
2659 };
2660 config {
2661 pins = "gpio62", "gpio51";
2662 drive-strength = <2>;
2663 bias-disable;
2664 };
2665 };
Kyle Yan679cbee2016-07-27 16:55:20 -07002666 };
2667};
David Collinsc6686252017-03-31 14:23:09 -07002668
2669&pm8998_gpios {
2670 key_home {
2671 key_home_default: key_home_default {
2672 pins = "gpio5";
2673 function = "normal";
2674 input-enable;
2675 bias-pull-up;
2676 power-source = <0>;
2677 };
2678 };
2679
2680 key_vol_up {
2681 key_vol_up_default: key_vol_up_default {
2682 pins = "gpio6";
2683 function = "normal";
2684 input-enable;
2685 bias-pull-up;
2686 power-source = <0>;
2687 };
2688 };
2689
2690 key_cam_snapshot {
2691 key_cam_snapshot_default: key_cam_snapshot_default {
2692 pins = "gpio7";
2693 function = "normal";
2694 input-enable;
2695 bias-pull-up;
2696 power-source = <0>;
2697 };
2698 };
2699
2700 key_cam_focus {
2701 key_cam_focus_default: key_cam_focus_default {
2702 pins = "gpio8";
2703 function = "normal";
2704 input-enable;
2705 bias-pull-up;
2706 power-source = <0>;
2707 };
2708 };
Jigarkumar Zala861231152017-02-28 14:05:11 -08002709
2710 camera_dvdd_en {
2711 camera_dvdd_en_default: camera_dvdd_en_default {
2712 pins = "gpio9";
2713 function = "normal";
2714 power-source = <0>;
2715 output-low;
2716 };
2717 };
2718
2719 camera_rear_dvdd_en {
2720 camera_rear_dvdd_en_default: camera_rear_dvdd_en_default {
2721 pins = "gpio12";
2722 function = "normal";
2723 power-source = <0>;
2724 output-low;
2725 };
2726 };
David Collinsc6686252017-03-31 14:23:09 -07002727};
Jack Phamc2160c842017-04-05 09:48:59 -07002728
2729&pmi8998_gpios {
2730 usb2_vbus_boost {
2731 usb2_vbus_boost_default: usb2_vbus_boost_default {
2732 pins = "gpio2";
2733 function = "normal";
2734 output-low;
2735 power-source = <0>;
2736 };
2737 };
2738
2739 usb2_vbus_det {
2740 usb2_vbus_det_default: usb2_vbus_det_default {
2741 pins = "gpio8";
2742 function = "normal";
2743 input-enable;
2744 bias-pull-down;
2745 power-source = <1>; /* VPH input supply */
2746 };
2747 };
2748
2749 usb2_id_det {
2750 usb2_id_det_default: usb2_id_det_default {
2751 pins = "gpio9";
2752 function = "normal";
2753 input-enable;
2754 bias-pull-up;
2755 power-source = <0>;
2756 };
2757 };
2758};