blob: adb0b084eb5a413c601d4a8489e006e061906840 [file] [log] [blame]
Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
26#include <linux/kref.h>
27#include <linux/completion.h>
28#include <linux/rcupdate.h>
Dan Williams7405f742007-01-02 11:10:43 -070029#include <linux/dma-mapping.h>
Chris Leechc13c8262006-05-23 17:18:44 -070030
31/**
Joe Perchesfd3f8982008-02-03 17:45:46 +020032 * enum dma_state - resource PNP/power management state
Chris Leechc13c8262006-05-23 17:18:44 -070033 * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
34 * @DMA_RESOURCE_RESUME: DMA device returning to full power
Dan Williamsd379b012007-07-09 11:56:42 -070035 * @DMA_RESOURCE_AVAILABLE: DMA device available to the system
Chris Leechc13c8262006-05-23 17:18:44 -070036 * @DMA_RESOURCE_REMOVED: DMA device removed from the system
37 */
Dan Williamsd379b012007-07-09 11:56:42 -070038enum dma_state {
Chris Leechc13c8262006-05-23 17:18:44 -070039 DMA_RESOURCE_SUSPEND,
40 DMA_RESOURCE_RESUME,
Dan Williamsd379b012007-07-09 11:56:42 -070041 DMA_RESOURCE_AVAILABLE,
Chris Leechc13c8262006-05-23 17:18:44 -070042 DMA_RESOURCE_REMOVED,
43};
44
45/**
Dan Williamsd379b012007-07-09 11:56:42 -070046 * enum dma_state_client - state of the channel in the client
47 * @DMA_ACK: client would like to use, or was using this channel
48 * @DMA_DUP: client has already seen this channel, or is not using this channel
49 * @DMA_NAK: client does not want to see any more channels
50 */
51enum dma_state_client {
52 DMA_ACK,
53 DMA_DUP,
54 DMA_NAK,
55};
56
57/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070058 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070059 *
60 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
61 */
62typedef s32 dma_cookie_t;
63
64#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
65
66/**
67 * enum dma_status - DMA transaction status
68 * @DMA_SUCCESS: transaction completed successfully
69 * @DMA_IN_PROGRESS: transaction not yet processed
70 * @DMA_ERROR: transaction failed
71 */
72enum dma_status {
73 DMA_SUCCESS,
74 DMA_IN_PROGRESS,
75 DMA_ERROR,
76};
77
78/**
Dan Williams7405f742007-01-02 11:10:43 -070079 * enum dma_transaction_type - DMA transaction types/indexes
80 */
81enum dma_transaction_type {
82 DMA_MEMCPY,
83 DMA_XOR,
84 DMA_PQ_XOR,
85 DMA_DUAL_XOR,
86 DMA_PQ_UPDATE,
87 DMA_ZERO_SUM,
88 DMA_PQ_ZERO_SUM,
89 DMA_MEMSET,
90 DMA_MEMCPY_CRC32C,
91 DMA_INTERRUPT,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070092 DMA_SLAVE,
Dan Williams7405f742007-01-02 11:10:43 -070093};
94
95/* last transaction type for creation of the capabilities mask */
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070096#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
97
98/**
99 * enum dma_slave_width - DMA slave register access width.
100 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
101 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
102 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
103 */
104enum dma_slave_width {
105 DMA_SLAVE_WIDTH_8BIT,
106 DMA_SLAVE_WIDTH_16BIT,
107 DMA_SLAVE_WIDTH_32BIT,
108};
Dan Williams7405f742007-01-02 11:10:43 -0700109
110/**
Dan Williams636bdea2008-04-17 20:17:26 -0700111 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
112 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -0700113 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
114 * this transaction
Dan Williams636bdea2008-04-17 20:17:26 -0700115 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
116 * acknowledges receipt, i.e. has has a chance to establish any
117 * dependency chains
Dan Williamse1d181e2008-07-04 00:13:40 -0700118 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
119 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Dan Williamsd4c56f92008-02-02 19:49:58 -0700120 */
Dan Williams636bdea2008-04-17 20:17:26 -0700121enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -0700122 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700123 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700124 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
125 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700126};
127
128/**
Dan Williams7405f742007-01-02 11:10:43 -0700129 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
130 * See linux/cpumask.h
131 */
132typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
133
134/**
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700135 * struct dma_slave - Information about a DMA slave
136 * @dev: device acting as DMA slave
137 * @dma_dev: required DMA master device. If non-NULL, the client can not be
138 * bound to other masters than this.
139 * @tx_reg: physical address of data register used for
140 * memory-to-peripheral transfers
141 * @rx_reg: physical address of data register used for
142 * peripheral-to-memory transfers
143 * @reg_width: peripheral register width
144 *
145 * If dma_dev is non-NULL, the client can not be bound to other DMA
146 * masters than the one corresponding to this device. The DMA master
147 * driver may use this to determine if there is controller-specific
148 * data wrapped around this struct. Drivers of platform code that sets
149 * the dma_dev field must therefore make sure to use an appropriate
150 * controller-specific dma slave structure wrapping this struct.
151 */
152struct dma_slave {
153 struct device *dev;
154 struct device *dma_dev;
155 dma_addr_t tx_reg;
156 dma_addr_t rx_reg;
157 enum dma_slave_width reg_width;
158};
159
160/**
Chris Leechc13c8262006-05-23 17:18:44 -0700161 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
162 * @refcount: local_t used for open-coded "bigref" counting
163 * @memcpy_count: transaction counter
164 * @bytes_transferred: byte counter
165 */
166
167struct dma_chan_percpu {
168 local_t refcount;
169 /* stats */
170 unsigned long memcpy_count;
171 unsigned long bytes_transferred;
172};
173
174/**
175 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700176 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700177 * @cookie: last cookie value returned to client
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700178 * @chan_id: channel ID for sysfs
179 * @class_dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700180 * @refcount: kref, used in "bigref" slow-mode
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700181 * @slow_ref: indicates that the DMA channel is free
182 * @rcu: the DMA channel's RCU head
Chris Leechc13c8262006-05-23 17:18:44 -0700183 * @device_node: used to add this to the device chan list
184 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700185 * @client-count: how many clients are using this channel
Chris Leechc13c8262006-05-23 17:18:44 -0700186 */
187struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700188 struct dma_device *device;
189 dma_cookie_t cookie;
190
191 /* sysfs */
192 int chan_id;
Tony Jones891f78e2007-09-25 02:03:03 +0200193 struct device dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700194
195 struct kref refcount;
196 int slow_ref;
197 struct rcu_head rcu;
198
Chris Leechc13c8262006-05-23 17:18:44 -0700199 struct list_head device_node;
200 struct dma_chan_percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700201 int client_count;
Chris Leechc13c8262006-05-23 17:18:44 -0700202};
203
Tony Jones891f78e2007-09-25 02:03:03 +0200204#define to_dma_chan(p) container_of(p, struct dma_chan, dev)
Dan Williamsd379b012007-07-09 11:56:42 -0700205
Chris Leechc13c8262006-05-23 17:18:44 -0700206void dma_chan_cleanup(struct kref *kref);
207
208static inline void dma_chan_get(struct dma_chan *chan)
209{
210 if (unlikely(chan->slow_ref))
211 kref_get(&chan->refcount);
212 else {
213 local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
214 put_cpu();
215 }
216}
217
218static inline void dma_chan_put(struct dma_chan *chan)
219{
220 if (unlikely(chan->slow_ref))
221 kref_put(&chan->refcount, dma_chan_cleanup);
222 else {
223 local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
224 put_cpu();
225 }
226}
227
228/*
229 * typedef dma_event_callback - function pointer to a DMA event callback
Dan Williamsd379b012007-07-09 11:56:42 -0700230 * For each channel added to the system this routine is called for each client.
231 * If the client would like to use the channel it returns '1' to signal (ack)
232 * the dmaengine core to take out a reference on the channel and its
233 * corresponding device. A client must not 'ack' an available channel more
234 * than once. When a channel is removed all clients are notified. If a client
235 * is using the channel it must 'ack' the removal. A client must not 'ack' a
236 * removed channel more than once.
237 * @client - 'this' pointer for the client context
238 * @chan - channel to be acted upon
239 * @state - available or removed
Chris Leechc13c8262006-05-23 17:18:44 -0700240 */
Dan Williamsd379b012007-07-09 11:56:42 -0700241struct dma_client;
242typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
243 struct dma_chan *chan, enum dma_state state);
Chris Leechc13c8262006-05-23 17:18:44 -0700244
245/**
246 * struct dma_client - info on the entity making use of DMA services
247 * @event_callback: func ptr to call when something happens
Dan Williamsd379b012007-07-09 11:56:42 -0700248 * @cap_mask: only return channels that satisfy the requested capabilities
249 * a value of zero corresponds to any capability
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700250 * @slave: data for preparing slave transfer. Must be non-NULL iff the
251 * DMA_SLAVE capability is requested.
Chris Leechc13c8262006-05-23 17:18:44 -0700252 * @global_node: list_head for global dma_client_list
253 */
254struct dma_client {
255 dma_event_callback event_callback;
Dan Williamsd379b012007-07-09 11:56:42 -0700256 dma_cap_mask_t cap_mask;
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700257 struct dma_slave *slave;
Chris Leechc13c8262006-05-23 17:18:44 -0700258 struct list_head global_node;
259};
260
Dan Williams7405f742007-01-02 11:10:43 -0700261typedef void (*dma_async_tx_callback)(void *dma_async_param);
262/**
263 * struct dma_async_tx_descriptor - async transaction descriptor
264 * ---dma generic offload fields---
265 * @cookie: tracking cookie for this transaction, set to -EBUSY if
266 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700267 * @flags: flags to augment operation preparation, control completion, and
268 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700269 * @phys: physical address of the descriptor
270 * @tx_list: driver common field for operations that require multiple
271 * descriptors
272 * @chan: target channel for this operation
273 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700274 * @callback: routine to call after this operation is complete
275 * @callback_param: general parameter to pass to the callback routine
276 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700277 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700278 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700279 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700280 */
281struct dma_async_tx_descriptor {
282 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700283 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700284 dma_addr_t phys;
285 struct list_head tx_list;
286 struct dma_chan *chan;
287 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700288 dma_async_tx_callback callback;
289 void *callback_param;
Dan Williams19242d72008-04-17 20:17:25 -0700290 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700291 struct dma_async_tx_descriptor *parent;
292 spinlock_t lock;
293};
294
Chris Leechc13c8262006-05-23 17:18:44 -0700295/**
296 * struct dma_device - info on the entity supplying DMA services
297 * @chancnt: how many DMA channels are supported
298 * @channels: the list of struct dma_chan
299 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700300 * @cap_mask: one or more dma_capability flags
301 * @max_xor: maximum number of xor sources, 0 if no capability
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700302 * @refcount: reference count
303 * @done: IO completion struct
304 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700305 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700306 * @device_alloc_chan_resources: allocate resources and return the
307 * number of allocated descriptors
308 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700309 * @device_prep_dma_memcpy: prepares a memcpy operation
310 * @device_prep_dma_xor: prepares a xor operation
311 * @device_prep_dma_zero_sum: prepares a zero_sum operation
312 * @device_prep_dma_memset: prepares a memset operation
313 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700314 * @device_prep_slave_sg: prepares a slave dma operation
315 * @device_terminate_all: terminate all pending operations
Dan Williams7405f742007-01-02 11:10:43 -0700316 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700317 */
318struct dma_device {
319
320 unsigned int chancnt;
321 struct list_head channels;
322 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700323 dma_cap_mask_t cap_mask;
324 int max_xor;
Chris Leechc13c8262006-05-23 17:18:44 -0700325
326 struct kref refcount;
327 struct completion done;
328
329 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700330 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700331
Haavard Skinnemoen848c5362008-07-08 11:58:58 -0700332 int (*device_alloc_chan_resources)(struct dma_chan *chan,
333 struct dma_client *client);
Chris Leechc13c8262006-05-23 17:18:44 -0700334 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700335
336 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700337 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700338 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700339 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700340 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700341 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700342 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
Dan Williams00367312008-02-02 19:49:57 -0700343 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700344 size_t len, u32 *result, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700345 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700346 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700347 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700348 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700349 struct dma_chan *chan, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700350
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700351 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
352 struct dma_chan *chan, struct scatterlist *sgl,
353 unsigned int sg_len, enum dma_data_direction direction,
354 unsigned long flags);
355 void (*device_terminate_all)(struct dma_chan *chan);
356
Dan Williams7405f742007-01-02 11:10:43 -0700357 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700358 dma_cookie_t cookie, dma_cookie_t *last,
359 dma_cookie_t *used);
Dan Williams7405f742007-01-02 11:10:43 -0700360 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700361};
362
363/* --- public DMA engine API --- */
364
Dan Williamsd379b012007-07-09 11:56:42 -0700365void dma_async_client_register(struct dma_client *client);
Chris Leechc13c8262006-05-23 17:18:44 -0700366void dma_async_client_unregister(struct dma_client *client);
Dan Williamsd379b012007-07-09 11:56:42 -0700367void dma_async_client_chan_request(struct dma_client *client);
Dan Williams7405f742007-01-02 11:10:43 -0700368dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
369 void *dest, void *src, size_t len);
370dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
371 struct page *page, unsigned int offset, void *kdata, size_t len);
372dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700373 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700374 unsigned int src_off, size_t len);
375void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
376 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700377
Dan Williams08398752008-07-17 17:59:56 -0700378static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700379{
Dan Williams636bdea2008-04-17 20:17:26 -0700380 tx->flags |= DMA_CTRL_ACK;
381}
382
Dan Williams08398752008-07-17 17:59:56 -0700383static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700384{
Dan Williams08398752008-07-17 17:59:56 -0700385 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700386}
387
Dan Williams7405f742007-01-02 11:10:43 -0700388#define first_dma_cap(mask) __first_dma_cap(&(mask))
389static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
390{
391 return min_t(int, DMA_TX_TYPE_END,
392 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
393}
394
395#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
396static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
397{
398 return min_t(int, DMA_TX_TYPE_END,
399 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
400}
401
402#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
403static inline void
404__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
405{
406 set_bit(tx_type, dstp->bits);
407}
408
409#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
410static inline int
411__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
412{
413 return test_bit(tx_type, srcp->bits);
414}
415
416#define for_each_dma_cap_mask(cap, mask) \
417 for ((cap) = first_dma_cap(mask); \
418 (cap) < DMA_TX_TYPE_END; \
419 (cap) = next_dma_cap((cap), (mask)))
420
Chris Leechc13c8262006-05-23 17:18:44 -0700421/**
Dan Williams7405f742007-01-02 11:10:43 -0700422 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700423 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700424 *
425 * This allows drivers to push copies to HW in batches,
426 * reducing MMIO writes where possible.
427 */
Dan Williams7405f742007-01-02 11:10:43 -0700428static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700429{
Dan Williamsec8670f2008-03-01 07:51:29 -0700430 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700431}
432
Dan Williams7405f742007-01-02 11:10:43 -0700433#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
434
Chris Leechc13c8262006-05-23 17:18:44 -0700435/**
Dan Williams7405f742007-01-02 11:10:43 -0700436 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700437 * @chan: DMA channel
438 * @cookie: transaction identifier to check status of
439 * @last: returns last completed cookie, can be NULL
440 * @used: returns last issued cookie, can be NULL
441 *
442 * If @last and @used are passed in, upon return they reflect the driver
443 * internal state and can be used with dma_async_is_complete() to check
444 * the status of multiple cookies without re-checking hardware state.
445 */
Dan Williams7405f742007-01-02 11:10:43 -0700446static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700447 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
448{
Dan Williams7405f742007-01-02 11:10:43 -0700449 return chan->device->device_is_tx_complete(chan, cookie, last, used);
Chris Leechc13c8262006-05-23 17:18:44 -0700450}
451
Dan Williams7405f742007-01-02 11:10:43 -0700452#define dma_async_memcpy_complete(chan, cookie, last, used)\
453 dma_async_is_tx_complete(chan, cookie, last, used)
454
Chris Leechc13c8262006-05-23 17:18:44 -0700455/**
456 * dma_async_is_complete - test a cookie against chan state
457 * @cookie: transaction identifier to test status of
458 * @last_complete: last know completed transaction
459 * @last_used: last cookie value handed out
460 *
461 * dma_async_is_complete() is used in dma_async_memcpy_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000462 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700463 */
464static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
465 dma_cookie_t last_complete, dma_cookie_t last_used)
466{
467 if (last_complete <= last_used) {
468 if ((cookie <= last_complete) || (cookie > last_used))
469 return DMA_SUCCESS;
470 } else {
471 if ((cookie <= last_complete) && (cookie > last_used))
472 return DMA_SUCCESS;
473 }
474 return DMA_IN_PROGRESS;
475}
476
Dan Williams7405f742007-01-02 11:10:43 -0700477enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Chris Leechc13c8262006-05-23 17:18:44 -0700478
479/* --- DMA device --- */
480
481int dma_async_device_register(struct dma_device *device);
482void dma_async_device_unregister(struct dma_device *device);
483
Chris Leechde5506e2006-05-23 17:50:37 -0700484/* --- Helper iov-locking functions --- */
485
486struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +0000487 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -0700488 int nr_pages;
489 struct page **pages;
490};
491
492struct dma_pinned_list {
493 int nr_iovecs;
494 struct dma_page_list page_list[0];
495};
496
497struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
498void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
499
500dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
501 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
502dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
503 struct dma_pinned_list *pinned_list, struct page *page,
504 unsigned int offset, size_t len);
505
Chris Leechc13c8262006-05-23 17:18:44 -0700506#endif /* DMAENGINE_H */