Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/common/gic.c |
| 3 | * |
| 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * Interrupt architecture for the GIC: |
| 11 | * |
| 12 | * o There is one Interrupt Distributor, which receives interrupts |
| 13 | * from system devices and sends them to the Interrupt Controllers. |
| 14 | * |
| 15 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 16 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 17 | * associated CPU. The base address of the CPU interface is usually |
| 18 | * aliased so that the same address points to different chips depending |
| 19 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 20 | * |
| 21 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 22 | * As such, the enable set/clear, pending set/clear and active bit |
| 23 | * registers are banked per-cpu for these sources. |
| 24 | */ |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/kernel.h> |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 27 | #include <linux/err.h> |
Arnd Bergmann | 7e1efcf | 2011-11-01 00:28:37 +0100 | [diff] [blame] | 28 | #include <linux/module.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 29 | #include <linux/list.h> |
| 30 | #include <linux/smp.h> |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 31 | #include <linux/cpu_pm.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 32 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 33 | #include <linux/io.h> |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 34 | #include <linux/of.h> |
| 35 | #include <linux/of_address.h> |
| 36 | #include <linux/of_irq.h> |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 37 | #include <linux/irqdomain.h> |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame] | 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/percpu.h> |
| 40 | #include <linux/slab.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 41 | |
| 42 | #include <asm/irq.h> |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 43 | #include <asm/exception.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 44 | #include <asm/mach/irq.h> |
| 45 | #include <asm/hardware/gic.h> |
| 46 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 47 | union gic_base { |
| 48 | void __iomem *common_base; |
| 49 | void __percpu __iomem **percpu_base; |
| 50 | }; |
| 51 | |
| 52 | struct gic_chip_data { |
| 53 | unsigned int irq_offset; |
| 54 | union gic_base dist_base; |
| 55 | union gic_base cpu_base; |
| 56 | #ifdef CONFIG_CPU_PM |
| 57 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; |
| 58 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
| 59 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; |
| 60 | u32 __percpu *saved_ppi_enable; |
| 61 | u32 __percpu *saved_ppi_conf; |
| 62 | #endif |
| 63 | #ifdef CONFIG_IRQ_DOMAIN |
| 64 | struct irq_domain domain; |
| 65 | #endif |
| 66 | unsigned int gic_irqs; |
| 67 | #ifdef CONFIG_GIC_NON_BANKED |
| 68 | void __iomem *(*get_base)(union gic_base *); |
| 69 | #endif |
| 70 | }; |
| 71 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 72 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 73 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 74 | /* |
| 75 | * Supported arch specific GIC irq extension. |
| 76 | * Default make them NULL. |
| 77 | */ |
| 78 | struct irq_chip gic_arch_extn = { |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 79 | .irq_eoi = NULL, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 80 | .irq_mask = NULL, |
| 81 | .irq_unmask = NULL, |
| 82 | .irq_retrigger = NULL, |
| 83 | .irq_set_type = NULL, |
| 84 | .irq_set_wake = NULL, |
| 85 | }; |
| 86 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 87 | #ifndef MAX_GIC_NR |
| 88 | #define MAX_GIC_NR 1 |
| 89 | #endif |
| 90 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 91 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 92 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 93 | #ifdef CONFIG_GIC_NON_BANKED |
| 94 | static void __iomem *gic_get_percpu_base(union gic_base *base) |
| 95 | { |
| 96 | return *__this_cpu_ptr(base->percpu_base); |
| 97 | } |
| 98 | |
| 99 | static void __iomem *gic_get_common_base(union gic_base *base) |
| 100 | { |
| 101 | return base->common_base; |
| 102 | } |
| 103 | |
| 104 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) |
| 105 | { |
| 106 | return data->get_base(&data->dist_base); |
| 107 | } |
| 108 | |
| 109 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) |
| 110 | { |
| 111 | return data->get_base(&data->cpu_base); |
| 112 | } |
| 113 | |
| 114 | static inline void gic_set_base_accessor(struct gic_chip_data *data, |
| 115 | void __iomem *(*f)(union gic_base *)) |
| 116 | { |
| 117 | data->get_base = f; |
| 118 | } |
| 119 | #else |
| 120 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) |
| 121 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) |
| 122 | #define gic_set_base_accessor(d,f) |
| 123 | #endif |
| 124 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 125 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 126 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 127 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 128 | return gic_data_dist_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 129 | } |
| 130 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 131 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 132 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 133 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 134 | return gic_data_cpu_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 135 | } |
| 136 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 137 | static inline unsigned int gic_irq(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 138 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 139 | return d->hwirq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 140 | } |
| 141 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 142 | /* |
| 143 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 144 | */ |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 145 | static void gic_mask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 146 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 147 | u32 mask = 1 << (gic_irq(d) % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 148 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 149 | raw_spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 150 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 151 | if (gic_arch_extn.irq_mask) |
| 152 | gic_arch_extn.irq_mask(d); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 153 | raw_spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 154 | } |
| 155 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 156 | static void gic_unmask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 157 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 158 | u32 mask = 1 << (gic_irq(d) % 32); |
Thomas Gleixner | c4bfa28 | 2006-07-01 22:32:14 +0100 | [diff] [blame] | 159 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 160 | raw_spin_lock(&irq_controller_lock); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 161 | if (gic_arch_extn.irq_unmask) |
| 162 | gic_arch_extn.irq_unmask(d); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 163 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 164 | raw_spin_unlock(&irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 165 | } |
| 166 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 167 | static void gic_eoi_irq(struct irq_data *d) |
| 168 | { |
| 169 | if (gic_arch_extn.irq_eoi) { |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 170 | raw_spin_lock(&irq_controller_lock); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 171 | gic_arch_extn.irq_eoi(d); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 172 | raw_spin_unlock(&irq_controller_lock); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 173 | } |
| 174 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 175 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 176 | } |
| 177 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 178 | static int gic_set_type(struct irq_data *d, unsigned int type) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 179 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 180 | void __iomem *base = gic_dist_base(d); |
| 181 | unsigned int gicirq = gic_irq(d); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 182 | u32 enablemask = 1 << (gicirq % 32); |
| 183 | u32 enableoff = (gicirq / 32) * 4; |
| 184 | u32 confmask = 0x2 << ((gicirq % 16) * 2); |
| 185 | u32 confoff = (gicirq / 16) * 4; |
| 186 | bool enabled = false; |
| 187 | u32 val; |
| 188 | |
| 189 | /* Interrupt configuration for SGIs can't be changed */ |
| 190 | if (gicirq < 16) |
| 191 | return -EINVAL; |
| 192 | |
| 193 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) |
| 194 | return -EINVAL; |
| 195 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 196 | raw_spin_lock(&irq_controller_lock); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 197 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 198 | if (gic_arch_extn.irq_set_type) |
| 199 | gic_arch_extn.irq_set_type(d, type); |
| 200 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 201 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 202 | if (type == IRQ_TYPE_LEVEL_HIGH) |
| 203 | val &= ~confmask; |
| 204 | else if (type == IRQ_TYPE_EDGE_RISING) |
| 205 | val |= confmask; |
| 206 | |
| 207 | /* |
| 208 | * As recommended by the spec, disable the interrupt before changing |
| 209 | * the configuration |
| 210 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 211 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
| 212 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 213 | enabled = true; |
| 214 | } |
| 215 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 216 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 217 | |
| 218 | if (enabled) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 219 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 220 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 221 | raw_spin_unlock(&irq_controller_lock); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 226 | static int gic_retrigger(struct irq_data *d) |
| 227 | { |
| 228 | if (gic_arch_extn.irq_retrigger) |
| 229 | return gic_arch_extn.irq_retrigger(d); |
| 230 | |
| 231 | return -ENXIO; |
| 232 | } |
| 233 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 234 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 235 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 236 | bool force) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 237 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 238 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 239 | unsigned int shift = (gic_irq(d) % 4) * 8; |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 240 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 241 | u32 val, mask, bit; |
| 242 | |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 243 | if (cpu >= 8 || cpu >= nr_cpu_ids) |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 244 | return -EINVAL; |
| 245 | |
| 246 | mask = 0xff << shift; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 247 | bit = 1 << (cpu_logical_map(cpu) + shift); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 248 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 249 | raw_spin_lock(&irq_controller_lock); |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 250 | val = readl_relaxed(reg) & ~mask; |
| 251 | writel_relaxed(val | bit, reg); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 252 | raw_spin_unlock(&irq_controller_lock); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 253 | |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 254 | return IRQ_SET_MASK_OK; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 255 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 256 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 257 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 258 | #ifdef CONFIG_PM |
| 259 | static int gic_set_wake(struct irq_data *d, unsigned int on) |
| 260 | { |
| 261 | int ret = -ENXIO; |
| 262 | |
| 263 | if (gic_arch_extn.irq_set_wake) |
| 264 | ret = gic_arch_extn.irq_set_wake(d, on); |
| 265 | |
| 266 | return ret; |
| 267 | } |
| 268 | |
| 269 | #else |
| 270 | #define gic_set_wake NULL |
| 271 | #endif |
| 272 | |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 273 | asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
| 274 | { |
| 275 | u32 irqstat, irqnr; |
| 276 | struct gic_chip_data *gic = &gic_data[0]; |
| 277 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
| 278 | |
| 279 | do { |
| 280 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); |
| 281 | irqnr = irqstat & ~0x1c00; |
| 282 | |
| 283 | if (likely(irqnr > 15 && irqnr < 1021)) { |
| 284 | irqnr = irq_domain_to_irq(&gic->domain, irqnr); |
| 285 | handle_IRQ(irqnr, regs); |
| 286 | continue; |
| 287 | } |
| 288 | if (irqnr < 16) { |
| 289 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); |
| 290 | #ifdef CONFIG_SMP |
| 291 | handle_IPI(irqnr, regs); |
| 292 | #endif |
| 293 | continue; |
| 294 | } |
| 295 | break; |
| 296 | } while (1); |
| 297 | } |
| 298 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 299 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 300 | { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 301 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
| 302 | struct irq_chip *chip = irq_get_chip(irq); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 303 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 304 | unsigned long status; |
| 305 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 306 | chained_irq_enter(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 307 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 308 | raw_spin_lock(&irq_controller_lock); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 309 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 310 | raw_spin_unlock(&irq_controller_lock); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 311 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 312 | gic_irq = (status & 0x3ff); |
| 313 | if (gic_irq == 1023) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 314 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 315 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 316 | cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 317 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) |
| 318 | do_bad_IRQ(cascade_irq, desc); |
| 319 | else |
| 320 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 321 | |
| 322 | out: |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 323 | chained_irq_exit(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 324 | } |
| 325 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 326 | static struct irq_chip gic_chip = { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 327 | .name = "GIC", |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 328 | .irq_mask = gic_mask_irq, |
| 329 | .irq_unmask = gic_unmask_irq, |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 330 | .irq_eoi = gic_eoi_irq, |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 331 | .irq_set_type = gic_set_type, |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 332 | .irq_retrigger = gic_retrigger, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 333 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 334 | .irq_set_affinity = gic_set_affinity, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 335 | #endif |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 336 | .irq_set_wake = gic_set_wake, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 337 | }; |
| 338 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 339 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 340 | { |
| 341 | if (gic_nr >= MAX_GIC_NR) |
| 342 | BUG(); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 343 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 344 | BUG(); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 345 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 346 | } |
| 347 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 348 | static void __init gic_dist_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 349 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 350 | unsigned int i, irq; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 351 | u32 cpumask; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 352 | unsigned int gic_irqs = gic->gic_irqs; |
| 353 | struct irq_domain *domain = &gic->domain; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 354 | void __iomem *base = gic_data_dist_base(gic); |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 355 | u32 cpu = 0; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 356 | |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 357 | #ifdef CONFIG_SMP |
| 358 | cpu = cpu_logical_map(smp_processor_id()); |
| 359 | #endif |
| 360 | |
| 361 | cpumask = 1 << cpu; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 362 | cpumask |= cpumask << 8; |
| 363 | cpumask |= cpumask << 16; |
| 364 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 365 | writel_relaxed(0, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 366 | |
| 367 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 368 | * Set all global interrupts to be level triggered, active low. |
| 369 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 370 | for (i = 32; i < gic_irqs; i += 16) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 371 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 372 | |
| 373 | /* |
| 374 | * Set all global interrupts to this CPU only. |
| 375 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 376 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 377 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 378 | |
| 379 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 380 | * Set priority on all global interrupts. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 381 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 382 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 383 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 384 | |
| 385 | /* |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 386 | * Disable all interrupts. Leave the PPI and SGIs alone |
| 387 | * as these enables are banked registers. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 388 | */ |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 389 | for (i = 32; i < gic_irqs; i += 32) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 390 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 391 | |
| 392 | /* |
| 393 | * Setup the Linux IRQ subsystem. |
| 394 | */ |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 395 | irq_domain_for_each_irq(domain, i, irq) { |
| 396 | if (i < 32) { |
| 397 | irq_set_percpu_devid(irq); |
| 398 | irq_set_chip_and_handler(irq, &gic_chip, |
| 399 | handle_percpu_devid_irq); |
| 400 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
| 401 | } else { |
| 402 | irq_set_chip_and_handler(irq, &gic_chip, |
| 403 | handle_fasteoi_irq); |
| 404 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 405 | } |
| 406 | irq_set_chip_data(irq, gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 407 | } |
| 408 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 409 | writel_relaxed(1, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 410 | } |
| 411 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 412 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 413 | { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 414 | void __iomem *dist_base = gic_data_dist_base(gic); |
| 415 | void __iomem *base = gic_data_cpu_base(gic); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 416 | int i; |
| 417 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 418 | /* |
| 419 | * Deal with the banked PPI and SGI interrupts - disable all |
| 420 | * PPI interrupts, ensure all SGI interrupts are enabled. |
| 421 | */ |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 422 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
| 423 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * Set priority on PPI and SGI interrupts |
| 427 | */ |
| 428 | for (i = 0; i < 32; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 429 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 430 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 431 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
| 432 | writel_relaxed(1, base + GIC_CPU_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 433 | } |
| 434 | |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 435 | #ifdef CONFIG_CPU_PM |
| 436 | /* |
| 437 | * Saves the GIC distributor registers during suspend or idle. Must be called |
| 438 | * with interrupts disabled but before powering down the GIC. After calling |
| 439 | * this function, no interrupts will be delivered by the GIC, and another |
| 440 | * platform-specific wakeup source must be enabled. |
| 441 | */ |
| 442 | static void gic_dist_save(unsigned int gic_nr) |
| 443 | { |
| 444 | unsigned int gic_irqs; |
| 445 | void __iomem *dist_base; |
| 446 | int i; |
| 447 | |
| 448 | if (gic_nr >= MAX_GIC_NR) |
| 449 | BUG(); |
| 450 | |
| 451 | gic_irqs = gic_data[gic_nr].gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 452 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 453 | |
| 454 | if (!dist_base) |
| 455 | return; |
| 456 | |
| 457 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 458 | gic_data[gic_nr].saved_spi_conf[i] = |
| 459 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 460 | |
| 461 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 462 | gic_data[gic_nr].saved_spi_target[i] = |
| 463 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 464 | |
| 465 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
| 466 | gic_data[gic_nr].saved_spi_enable[i] = |
| 467 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 468 | } |
| 469 | |
| 470 | /* |
| 471 | * Restores the GIC distributor registers during resume or when coming out of |
| 472 | * idle. Must be called before enabling interrupts. If a level interrupt |
| 473 | * that occured while the GIC was suspended is still present, it will be |
| 474 | * handled normally, but any edge interrupts that occured will not be seen by |
| 475 | * the GIC and need to be handled by the platform-specific wakeup source. |
| 476 | */ |
| 477 | static void gic_dist_restore(unsigned int gic_nr) |
| 478 | { |
| 479 | unsigned int gic_irqs; |
| 480 | unsigned int i; |
| 481 | void __iomem *dist_base; |
| 482 | |
| 483 | if (gic_nr >= MAX_GIC_NR) |
| 484 | BUG(); |
| 485 | |
| 486 | gic_irqs = gic_data[gic_nr].gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 487 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 488 | |
| 489 | if (!dist_base) |
| 490 | return; |
| 491 | |
| 492 | writel_relaxed(0, dist_base + GIC_DIST_CTRL); |
| 493 | |
| 494 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 495 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], |
| 496 | dist_base + GIC_DIST_CONFIG + i * 4); |
| 497 | |
| 498 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 499 | writel_relaxed(0xa0a0a0a0, |
| 500 | dist_base + GIC_DIST_PRI + i * 4); |
| 501 | |
| 502 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 503 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], |
| 504 | dist_base + GIC_DIST_TARGET + i * 4); |
| 505 | |
| 506 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
| 507 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], |
| 508 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 509 | |
| 510 | writel_relaxed(1, dist_base + GIC_DIST_CTRL); |
| 511 | } |
| 512 | |
| 513 | static void gic_cpu_save(unsigned int gic_nr) |
| 514 | { |
| 515 | int i; |
| 516 | u32 *ptr; |
| 517 | void __iomem *dist_base; |
| 518 | void __iomem *cpu_base; |
| 519 | |
| 520 | if (gic_nr >= MAX_GIC_NR) |
| 521 | BUG(); |
| 522 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 523 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 524 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 525 | |
| 526 | if (!dist_base || !cpu_base) |
| 527 | return; |
| 528 | |
| 529 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
| 530 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
| 531 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 532 | |
| 533 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
| 534 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
| 535 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 536 | |
| 537 | } |
| 538 | |
| 539 | static void gic_cpu_restore(unsigned int gic_nr) |
| 540 | { |
| 541 | int i; |
| 542 | u32 *ptr; |
| 543 | void __iomem *dist_base; |
| 544 | void __iomem *cpu_base; |
| 545 | |
| 546 | if (gic_nr >= MAX_GIC_NR) |
| 547 | BUG(); |
| 548 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 549 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 550 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 551 | |
| 552 | if (!dist_base || !cpu_base) |
| 553 | return; |
| 554 | |
| 555 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
| 556 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
| 557 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 558 | |
| 559 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
| 560 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
| 561 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); |
| 562 | |
| 563 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) |
| 564 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); |
| 565 | |
| 566 | writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); |
| 567 | writel_relaxed(1, cpu_base + GIC_CPU_CTRL); |
| 568 | } |
| 569 | |
| 570 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
| 571 | { |
| 572 | int i; |
| 573 | |
| 574 | for (i = 0; i < MAX_GIC_NR; i++) { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 575 | #ifdef CONFIG_GIC_NON_BANKED |
| 576 | /* Skip over unused GICs */ |
| 577 | if (!gic_data[i].get_base) |
| 578 | continue; |
| 579 | #endif |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 580 | switch (cmd) { |
| 581 | case CPU_PM_ENTER: |
| 582 | gic_cpu_save(i); |
| 583 | break; |
| 584 | case CPU_PM_ENTER_FAILED: |
| 585 | case CPU_PM_EXIT: |
| 586 | gic_cpu_restore(i); |
| 587 | break; |
| 588 | case CPU_CLUSTER_PM_ENTER: |
| 589 | gic_dist_save(i); |
| 590 | break; |
| 591 | case CPU_CLUSTER_PM_ENTER_FAILED: |
| 592 | case CPU_CLUSTER_PM_EXIT: |
| 593 | gic_dist_restore(i); |
| 594 | break; |
| 595 | } |
| 596 | } |
| 597 | |
| 598 | return NOTIFY_OK; |
| 599 | } |
| 600 | |
| 601 | static struct notifier_block gic_notifier_block = { |
| 602 | .notifier_call = gic_notifier, |
| 603 | }; |
| 604 | |
| 605 | static void __init gic_pm_init(struct gic_chip_data *gic) |
| 606 | { |
| 607 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
| 608 | sizeof(u32)); |
| 609 | BUG_ON(!gic->saved_ppi_enable); |
| 610 | |
| 611 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
| 612 | sizeof(u32)); |
| 613 | BUG_ON(!gic->saved_ppi_conf); |
| 614 | |
Marc Zyngier | abdd7b9 | 2011-11-25 17:58:19 +0100 | [diff] [blame] | 615 | if (gic == &gic_data[0]) |
| 616 | cpu_pm_register_notifier(&gic_notifier_block); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 617 | } |
| 618 | #else |
| 619 | static void __init gic_pm_init(struct gic_chip_data *gic) |
| 620 | { |
| 621 | } |
| 622 | #endif |
| 623 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 624 | #ifdef CONFIG_OF |
| 625 | static int gic_irq_domain_dt_translate(struct irq_domain *d, |
| 626 | struct device_node *controller, |
| 627 | const u32 *intspec, unsigned int intsize, |
| 628 | unsigned long *out_hwirq, unsigned int *out_type) |
| 629 | { |
| 630 | if (d->of_node != controller) |
| 631 | return -EINVAL; |
| 632 | if (intsize < 3) |
| 633 | return -EINVAL; |
| 634 | |
| 635 | /* Get the interrupt number and add 16 to skip over SGIs */ |
| 636 | *out_hwirq = intspec[1] + 16; |
| 637 | |
| 638 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ |
| 639 | if (!intspec[0]) |
| 640 | *out_hwirq += 16; |
| 641 | |
| 642 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
| 643 | return 0; |
| 644 | } |
| 645 | #endif |
| 646 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 647 | const struct irq_domain_ops gic_irq_domain_ops = { |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 648 | #ifdef CONFIG_OF |
| 649 | .dt_translate = gic_irq_domain_dt_translate, |
| 650 | #endif |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 651 | }; |
| 652 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 653 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
| 654 | void __iomem *dist_base, void __iomem *cpu_base, |
| 655 | u32 percpu_offset) |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 656 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 657 | struct gic_chip_data *gic; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 658 | struct irq_domain *domain; |
| 659 | int gic_irqs; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 660 | |
| 661 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 662 | |
| 663 | gic = &gic_data[gic_nr]; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 664 | domain = &gic->domain; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 665 | #ifdef CONFIG_GIC_NON_BANKED |
| 666 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ |
| 667 | unsigned int cpu; |
| 668 | |
| 669 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); |
| 670 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); |
| 671 | if (WARN_ON(!gic->dist_base.percpu_base || |
| 672 | !gic->cpu_base.percpu_base)) { |
| 673 | free_percpu(gic->dist_base.percpu_base); |
| 674 | free_percpu(gic->cpu_base.percpu_base); |
| 675 | return; |
| 676 | } |
| 677 | |
| 678 | for_each_possible_cpu(cpu) { |
| 679 | unsigned long offset = percpu_offset * cpu_logical_map(cpu); |
| 680 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
| 681 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; |
| 682 | } |
| 683 | |
| 684 | gic_set_base_accessor(gic, gic_get_percpu_base); |
| 685 | } else |
| 686 | #endif |
| 687 | { /* Normal, sane GIC... */ |
| 688 | WARN(percpu_offset, |
| 689 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
| 690 | percpu_offset); |
| 691 | gic->dist_base.common_base = dist_base; |
| 692 | gic->cpu_base.common_base = cpu_base; |
| 693 | gic_set_base_accessor(gic, gic_get_common_base); |
| 694 | } |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 695 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 696 | /* |
| 697 | * For primary GICs, skip over SGIs. |
| 698 | * For secondary GICs, skip over PPIs, too. |
| 699 | */ |
Will Deacon | e0b823e | 2012-02-03 14:52:14 +0100 | [diff] [blame^] | 700 | if (gic_nr == 0 && (irq_start & 31) > 0) { |
| 701 | domain->hwirq_base = 16; |
| 702 | if (irq_start != -1) |
| 703 | irq_start = (irq_start & ~31) + 16; |
| 704 | } else { |
| 705 | domain->hwirq_base = 32; |
Will Deacon | fe41db7 | 2011-11-25 19:23:36 +0100 | [diff] [blame] | 706 | } |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 707 | |
| 708 | /* |
| 709 | * Find out how many interrupts are supported. |
| 710 | * The GIC only supports up to 1020 interrupt sources. |
| 711 | */ |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 712 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 713 | gic_irqs = (gic_irqs + 1) * 32; |
| 714 | if (gic_irqs > 1020) |
| 715 | gic_irqs = 1020; |
| 716 | gic->gic_irqs = gic_irqs; |
| 717 | |
| 718 | domain->nr_irq = gic_irqs - domain->hwirq_base; |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 719 | domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq, |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 720 | numa_node_id()); |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 721 | if (IS_ERR_VALUE(domain->irq_base)) { |
| 722 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
| 723 | irq_start); |
| 724 | domain->irq_base = irq_start; |
| 725 | } |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 726 | domain->priv = gic; |
| 727 | domain->ops = &gic_irq_domain_ops; |
| 728 | irq_domain_add(domain); |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 729 | |
Colin Cross | 9c12845 | 2011-06-13 00:45:59 +0000 | [diff] [blame] | 730 | gic_chip.flags |= gic_arch_extn.flags; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 731 | gic_dist_init(gic); |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 732 | gic_cpu_init(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 733 | gic_pm_init(gic); |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 734 | } |
| 735 | |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 736 | void __cpuinit gic_secondary_init(unsigned int gic_nr) |
| 737 | { |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 738 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 739 | |
| 740 | gic_cpu_init(&gic_data[gic_nr]); |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 741 | } |
| 742 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 743 | #ifdef CONFIG_SMP |
Russell King | 8266810 | 2009-05-17 16:20:18 +0100 | [diff] [blame] | 744 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 745 | { |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 746 | int cpu; |
| 747 | unsigned long map = 0; |
| 748 | |
| 749 | /* Convert our logical CPU mask into a physical one. */ |
| 750 | for_each_cpu(cpu, mask) |
| 751 | map |= 1 << cpu_logical_map(cpu); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 752 | |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 753 | /* |
| 754 | * Ensure that stores to Normal memory are visible to the |
| 755 | * other CPUs before issuing the IPI. |
| 756 | */ |
| 757 | dsb(); |
| 758 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 759 | /* this always happens on GIC0 */ |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 760 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 761 | } |
| 762 | #endif |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 763 | |
| 764 | #ifdef CONFIG_OF |
| 765 | static int gic_cnt __initdata = 0; |
| 766 | |
| 767 | int __init gic_of_init(struct device_node *node, struct device_node *parent) |
| 768 | { |
| 769 | void __iomem *cpu_base; |
| 770 | void __iomem *dist_base; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 771 | u32 percpu_offset; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 772 | int irq; |
| 773 | struct irq_domain *domain = &gic_data[gic_cnt].domain; |
| 774 | |
| 775 | if (WARN_ON(!node)) |
| 776 | return -ENODEV; |
| 777 | |
| 778 | dist_base = of_iomap(node, 0); |
| 779 | WARN(!dist_base, "unable to map gic dist registers\n"); |
| 780 | |
| 781 | cpu_base = of_iomap(node, 1); |
| 782 | WARN(!cpu_base, "unable to map gic cpu registers\n"); |
| 783 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 784 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
| 785 | percpu_offset = 0; |
| 786 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 787 | domain->of_node = of_node_get(node); |
| 788 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 789 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset); |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 790 | |
| 791 | if (parent) { |
| 792 | irq = irq_of_parse_and_map(node, 0); |
| 793 | gic_cascade_irq(gic_cnt, irq); |
| 794 | } |
| 795 | gic_cnt++; |
| 796 | return 0; |
| 797 | } |
| 798 | #endif |