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Jason Robertsce082592010-05-13 15:57:33 +01001/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
Jason Robertsce082592010-05-13 15:57:33 +010019#include <linux/interrupt.h>
20#include <linux/delay.h>
Jamie Iles84457942011-05-06 15:28:55 +010021#include <linux/dma-mapping.h>
Jason Robertsce082592010-05-13 15:57:33 +010022#include <linux/wait.h>
23#include <linux/mutex.h>
David Millerb8664b32010-08-04 22:57:51 -070024#include <linux/slab.h>
Jason Robertsce082592010-05-13 15:57:33 +010025#include <linux/mtd/mtd.h>
26#include <linux/module.h>
27
28#include "denali.h"
29
30MODULE_LICENSE("GPL");
31
Masahiro Yamada43914a22014-09-09 11:01:51 +090032/*
33 * We define a module parameter that allows the user to override
Jason Robertsce082592010-05-13 15:57:33 +010034 * the hardware and decide what timing mode should be used.
35 */
36#define NAND_DEFAULT_TIMINGS -1
37
38static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39module_param(onfi_timing_mode, int, S_IRUGO);
Masahiro Yamada81254502014-09-16 20:04:25 +090040MODULE_PARM_DESC(onfi_timing_mode,
41 "Overrides default ONFI setting. -1 indicates use default timings");
Jason Robertsce082592010-05-13 15:57:33 +010042
43#define DENALI_NAND_NAME "denali-nand"
44
Masahiro Yamada43914a22014-09-09 11:01:51 +090045/*
46 * We define a macro here that combines all interrupts this driver uses into
47 * a single constant value, for convenience.
48 */
Jamie Iles9589bf52011-05-06 15:28:56 +010049#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
50 INTR_STATUS__ECC_TRANSACTION_DONE | \
51 INTR_STATUS__ECC_ERR | \
52 INTR_STATUS__PROGRAM_FAIL | \
53 INTR_STATUS__LOAD_COMP | \
54 INTR_STATUS__PROGRAM_COMP | \
55 INTR_STATUS__TIME_OUT | \
56 INTR_STATUS__ERASE_FAIL | \
57 INTR_STATUS__RST_COMP | \
58 INTR_STATUS__ERASE_COMP)
Jason Robertsce082592010-05-13 15:57:33 +010059
Masahiro Yamada43914a22014-09-09 11:01:51 +090060/*
61 * indicates whether or not the internal value for the flash bank is
62 * valid or not
63 */
Chuanxiao5bac3ac2010-08-05 23:06:04 +080064#define CHIP_SELECT_INVALID -1
Jason Robertsce082592010-05-13 15:57:33 +010065
66#define SUPPORT_8BITECC 1
67
Masahiro Yamada43914a22014-09-09 11:01:51 +090068/*
69 * This macro divides two integers and rounds fractional values up
70 * to the nearest integer value.
71 */
Jason Robertsce082592010-05-13 15:57:33 +010072#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
73
Masahiro Yamada43914a22014-09-09 11:01:51 +090074/*
75 * this macro allows us to convert from an MTD structure to our own
Jason Robertsce082592010-05-13 15:57:33 +010076 * device context (denali) structure.
77 */
Boris BREZILLON442f201b2015-12-11 15:06:00 +010078static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
79{
80 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
81}
Jason Robertsce082592010-05-13 15:57:33 +010082
Masahiro Yamada43914a22014-09-09 11:01:51 +090083/*
84 * These constants are defined by the driver to enable common driver
85 * configuration options.
86 */
Jason Robertsce082592010-05-13 15:57:33 +010087#define SPARE_ACCESS 0x41
88#define MAIN_ACCESS 0x42
89#define MAIN_SPARE_ACCESS 0x43
Masahiro Yamada29023302014-07-11 11:14:05 +090090#define PIPELINE_ACCESS 0x2000
Jason Robertsce082592010-05-13 15:57:33 +010091
92#define DENALI_READ 0
93#define DENALI_WRITE 0x100
94
95/* types of device accesses. We can issue commands and get status */
96#define COMMAND_CYCLE 0
97#define ADDR_CYCLE 1
98#define STATUS_CYCLE 2
99
Masahiro Yamada43914a22014-09-09 11:01:51 +0900100/*
101 * this is a helper macro that allows us to
102 * format the bank into the proper bits for the controller
103 */
Jason Robertsce082592010-05-13 15:57:33 +0100104#define BANK(x) ((x) << 24)
105
Jason Robertsce082592010-05-13 15:57:33 +0100106/* forward declarations */
107static void clear_interrupts(struct denali_nand_info *denali);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800108static uint32_t wait_for_irq(struct denali_nand_info *denali,
109 uint32_t irq_mask);
110static void denali_irq_enable(struct denali_nand_info *denali,
111 uint32_t int_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100112static uint32_t read_interrupt_status(struct denali_nand_info *denali);
113
Masahiro Yamada43914a22014-09-09 11:01:51 +0900114/*
115 * Certain operations for the denali NAND controller use an indexed mode to
116 * read/write data. The operation is performed by writing the address value
117 * of the command to the device memory followed by the data. This function
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800118 * abstracts this common operation.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900119 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800120static void index_addr(struct denali_nand_info *denali,
121 uint32_t address, uint32_t data)
Jason Robertsce082592010-05-13 15:57:33 +0100122{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800123 iowrite32(address, denali->flash_mem);
124 iowrite32(data, denali->flash_mem + 0x10);
Jason Robertsce082592010-05-13 15:57:33 +0100125}
126
127/* Perform an indexed read of the device */
128static void index_addr_read_data(struct denali_nand_info *denali,
129 uint32_t address, uint32_t *pdata)
130{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800131 iowrite32(address, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100132 *pdata = ioread32(denali->flash_mem + 0x10);
133}
134
Masahiro Yamada43914a22014-09-09 11:01:51 +0900135/*
136 * We need to buffer some data for some of the NAND core routines.
137 * The operations manage buffering that data.
138 */
Jason Robertsce082592010-05-13 15:57:33 +0100139static void reset_buf(struct denali_nand_info *denali)
140{
141 denali->buf.head = denali->buf.tail = 0;
142}
143
144static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
145{
Jason Robertsce082592010-05-13 15:57:33 +0100146 denali->buf.buf[denali->buf.tail++] = byte;
147}
148
149/* reads the status of the device */
150static void read_status(struct denali_nand_info *denali)
151{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900152 uint32_t cmd;
Jason Robertsce082592010-05-13 15:57:33 +0100153
154 /* initialize the data buffer to store status */
155 reset_buf(denali);
156
Chuanxiao Dongf0bc0c72010-08-11 17:14:59 +0800157 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
158 if (cmd)
159 write_byte_to_buf(denali, NAND_STATUS_WP);
160 else
161 write_byte_to_buf(denali, 0);
Jason Robertsce082592010-05-13 15:57:33 +0100162}
163
164/* resets a specific device connected to the core */
165static void reset_bank(struct denali_nand_info *denali)
166{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900167 uint32_t irq_status;
Masahiro Yamada81254502014-09-16 20:04:25 +0900168 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
Jason Robertsce082592010-05-13 15:57:33 +0100169
170 clear_interrupts(denali);
171
Jamie Iles9589bf52011-05-06 15:28:56 +0100172 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
Jason Robertsce082592010-05-13 15:57:33 +0100173
174 irq_status = wait_for_irq(denali, irq_mask);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800175
Jamie Iles9589bf52011-05-06 15:28:56 +0100176 if (irq_status & INTR_STATUS__TIME_OUT)
Jamie Iles84457942011-05-06 15:28:55 +0100177 dev_err(denali->dev, "reset bank failed.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100178}
179
180/* Reset the flash controller */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800181static uint16_t denali_nand_reset(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100182{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900183 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100184
Jamie Iles84457942011-05-06 15:28:55 +0100185 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900186 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100187
Masahiro Yamada81254502014-09-16 20:04:25 +0900188 for (i = 0; i < denali->max_banks; i++)
Jamie Iles9589bf52011-05-06 15:28:56 +0100189 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
190 denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100191
Masahiro Yamada81254502014-09-16 20:04:25 +0900192 for (i = 0; i < denali->max_banks; i++) {
Jamie Iles9589bf52011-05-06 15:28:56 +0100193 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
Masahiro Yamada81254502014-09-16 20:04:25 +0900194 while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
Jamie Iles9589bf52011-05-06 15:28:56 +0100195 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
Chuanxiao Dong628bfd412010-08-11 17:53:29 +0800196 cpu_relax();
Jamie Iles9589bf52011-05-06 15:28:56 +0100197 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
198 INTR_STATUS__TIME_OUT)
Jamie Iles84457942011-05-06 15:28:55 +0100199 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100200 "NAND Reset operation timed out on bank %d\n", i);
201 }
202
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100203 for (i = 0; i < denali->max_banks; i++)
Jamie Iles9589bf52011-05-06 15:28:56 +0100204 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
Masahiro Yamada81254502014-09-16 20:04:25 +0900205 denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100206
207 return PASS;
208}
209
Masahiro Yamada43914a22014-09-09 11:01:51 +0900210/*
211 * this routine calculates the ONFI timing values for a given mode and
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800212 * programs the clocking register accordingly. The mode is determined by
213 * the get_onfi_nand_para routine.
Jason Robertsce082592010-05-13 15:57:33 +0100214 */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800215static void nand_onfi_timing_set(struct denali_nand_info *denali,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800216 uint16_t mode)
Jason Robertsce082592010-05-13 15:57:33 +0100217{
218 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
219 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
220 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
221 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
222 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
223 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
224 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
225 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
226 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
227 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
228 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
229 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
230
Jason Robertsce082592010-05-13 15:57:33 +0100231 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
232 uint16_t dv_window = 0;
233 uint16_t en_lo, en_hi;
234 uint16_t acc_clks;
235 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
236
Jamie Iles84457942011-05-06 15:28:55 +0100237 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900238 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100239
240 en_lo = CEIL_DIV(Trp[mode], CLK_X);
241 en_hi = CEIL_DIV(Treh[mode], CLK_X);
242#if ONFI_BLOOM_TIME
243 if ((en_hi * CLK_X) < (Treh[mode] + 2))
244 en_hi++;
245#endif
246
247 if ((en_lo + en_hi) * CLK_X < Trc[mode])
248 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
249
250 if ((en_lo + en_hi) < CLK_MULTI)
251 en_lo += CLK_MULTI - en_lo - en_hi;
252
253 while (dv_window < 8) {
254 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
255
256 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
257
Masahiro Yamada81254502014-09-16 20:04:25 +0900258 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
259 data_invalid_rhoh : data_invalid_rloh;
Jason Robertsce082592010-05-13 15:57:33 +0100260
261 dv_window = data_invalid - Trea[mode];
262
263 if (dv_window < 8)
264 en_lo++;
265 }
266
267 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
268
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900269 while (acc_clks * CLK_X - Trea[mode] < 3)
Jason Robertsce082592010-05-13 15:57:33 +0100270 acc_clks++;
271
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900272 if (data_invalid - acc_clks * CLK_X < 2)
Jamie Iles84457942011-05-06 15:28:55 +0100273 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900274 __FILE__, __LINE__);
Jason Robertsce082592010-05-13 15:57:33 +0100275
276 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
277 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
278 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
279 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
280 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
Jason Robertsce082592010-05-13 15:57:33 +0100281 if (cs_cnt == 0)
282 cs_cnt = 1;
283
284 if (Tcea[mode]) {
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900285 while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode])
Jason Robertsce082592010-05-13 15:57:33 +0100286 cs_cnt++;
287 }
288
289#if MODE5_WORKAROUND
290 if (mode == 5)
291 acc_clks = 5;
292#endif
293
294 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900295 if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 &&
296 ioread32(denali->flash_reg + DEVICE_ID) == 0x88)
Jason Robertsce082592010-05-13 15:57:33 +0100297 acc_clks = 6;
298
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800299 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
300 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
301 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
302 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
303 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
304 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
305 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
306 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100307}
308
Jason Robertsce082592010-05-13 15:57:33 +0100309/* queries the NAND device to see what ONFI modes it supports. */
310static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
311{
312 int i;
Masahiro Yamada43914a22014-09-09 11:01:51 +0900313
314 /*
315 * we needn't to do a reset here because driver has already
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800316 * reset all the banks before
Masahiro Yamada43914a22014-09-09 11:01:51 +0900317 */
Jason Robertsce082592010-05-13 15:57:33 +0100318 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
319 ONFI_TIMING_MODE__VALUE))
320 return FAIL;
321
322 for (i = 5; i > 0; i--) {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800323 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
324 (0x01 << i))
Jason Robertsce082592010-05-13 15:57:33 +0100325 break;
326 }
327
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800328 nand_onfi_timing_set(denali, i);
Jason Robertsce082592010-05-13 15:57:33 +0100329
Masahiro Yamada43914a22014-09-09 11:01:51 +0900330 /*
331 * By now, all the ONFI devices we know support the page cache
332 * rw feature. So here we enable the pipeline_rw_ahead feature
333 */
Jason Robertsce082592010-05-13 15:57:33 +0100334 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
335 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
336
337 return PASS;
338}
339
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800340static void get_samsung_nand_para(struct denali_nand_info *denali,
341 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100342{
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800343 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
Jason Robertsce082592010-05-13 15:57:33 +0100344 /* Set timing register values according to datasheet */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800345 iowrite32(5, denali->flash_reg + ACC_CLKS);
346 iowrite32(20, denali->flash_reg + RE_2_WE);
347 iowrite32(12, denali->flash_reg + WE_2_RE);
348 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
349 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
350 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
351 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100352 }
Jason Robertsce082592010-05-13 15:57:33 +0100353}
354
355static void get_toshiba_nand_para(struct denali_nand_info *denali)
356{
Jason Robertsce082592010-05-13 15:57:33 +0100357 uint32_t tmp;
358
Masahiro Yamada43914a22014-09-09 11:01:51 +0900359 /*
360 * Workaround to fix a controller bug which reports a wrong
361 * spare area size for some kind of Toshiba NAND device
362 */
Jason Robertsce082592010-05-13 15:57:33 +0100363 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
364 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800365 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100366 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
367 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800368 iowrite32(tmp,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800369 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100370#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800371 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100372#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800373 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100374#endif
375 }
Jason Robertsce082592010-05-13 15:57:33 +0100376}
377
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800378static void get_hynix_nand_para(struct denali_nand_info *denali,
379 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100380{
Jason Robertsce082592010-05-13 15:57:33 +0100381 uint32_t main_size, spare_size;
382
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800383 switch (device_id) {
Jason Robertsce082592010-05-13 15:57:33 +0100384 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
385 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800386 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
387 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
388 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800389 main_size = 4096 *
390 ioread32(denali->flash_reg + DEVICES_CONNECTED);
391 spare_size = 224 *
392 ioread32(denali->flash_reg + DEVICES_CONNECTED);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800393 iowrite32(main_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800394 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800395 iowrite32(spare_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800396 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800397 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
Jason Robertsce082592010-05-13 15:57:33 +0100398#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800399 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100400#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800401 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100402#endif
Jason Robertsce082592010-05-13 15:57:33 +0100403 break;
404 default:
Jamie Iles84457942011-05-06 15:28:55 +0100405 dev_warn(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900406 "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
407 "Will use default parameter values instead.\n",
408 device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100409 }
410}
411
Masahiro Yamada43914a22014-09-09 11:01:51 +0900412/*
413 * determines how many NAND chips are connected to the controller. Note for
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800414 * Intel CE4100 devices we don't support more than one device.
Jason Robertsce082592010-05-13 15:57:33 +0100415 */
416static void find_valid_banks(struct denali_nand_info *denali)
417{
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100418 uint32_t id[denali->max_banks];
Jason Robertsce082592010-05-13 15:57:33 +0100419 int i;
420
421 denali->total_used_banks = 1;
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100422 for (i = 0; i < denali->max_banks; i++) {
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900423 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
424 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
Masahiro Yamada81254502014-09-16 20:04:25 +0900425 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
Jason Robertsce082592010-05-13 15:57:33 +0100426
Jamie Iles84457942011-05-06 15:28:55 +0100427 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100428 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
429
430 if (i == 0) {
431 if (!(id[i] & 0x0ff))
432 break; /* WTF? */
433 } else {
434 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
435 denali->total_used_banks++;
436 else
437 break;
438 }
439 }
440
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800441 if (denali->platform == INTEL_CE4100) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900442 /*
443 * Platform limitations of the CE4100 device limit
Jason Robertsce082592010-05-13 15:57:33 +0100444 * users to a single chip solution for NAND.
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800445 * Multichip support is not enabled.
446 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800447 if (denali->total_used_banks != 1) {
Jamie Iles84457942011-05-06 15:28:55 +0100448 dev_err(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900449 "Sorry, Intel CE4100 only supports a single NAND device.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100450 BUG();
451 }
452 }
Jamie Iles84457942011-05-06 15:28:55 +0100453 dev_dbg(denali->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100454 "denali->total_used_banks: %d\n", denali->total_used_banks);
455}
456
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100457/*
458 * Use the configuration feature register to determine the maximum number of
459 * banks that the hardware supports.
460 */
461static void detect_max_banks(struct denali_nand_info *denali)
462{
463 uint32_t features = ioread32(denali->flash_reg + FEATURES);
Graham Moore271707b2015-07-21 09:39:31 -0500464 /*
465 * Read the revision register, so we can calculate the max_banks
466 * properly: the encoding changed from rev 5.0 to 5.1
467 */
468 u32 revision = MAKE_COMPARABLE_REVISION(
469 ioread32(denali->flash_reg + REVISION));
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100470
Graham Moore271707b2015-07-21 09:39:31 -0500471 if (revision < REVISION_5_1)
472 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
473 else
474 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100475}
476
Jason Robertsce082592010-05-13 15:57:33 +0100477static void detect_partition_feature(struct denali_nand_info *denali)
478{
Masahiro Yamada43914a22014-09-09 11:01:51 +0900479 /*
480 * For MRST platform, denali->fwblks represent the
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800481 * number of blocks firmware is taken,
482 * FW is in protect partition and MTD driver has no
483 * permission to access it. So let driver know how many
484 * blocks it can't touch.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900485 */
Jason Robertsce082592010-05-13 15:57:33 +0100486 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
Jamie Iles9589bf52011-05-06 15:28:56 +0100487 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
488 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800489 denali->fwblks =
Jamie Iles9589bf52011-05-06 15:28:56 +0100490 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
491 MIN_MAX_BANK__MIN_VALUE) *
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800492 denali->blksperchip)
Jason Robertsce082592010-05-13 15:57:33 +0100493 +
Jamie Iles9589bf52011-05-06 15:28:56 +0100494 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
495 MIN_BLK_ADDR__VALUE);
Masahiro Yamada81254502014-09-16 20:04:25 +0900496 } else {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800497 denali->fwblks = SPECTRA_START_BLOCK;
Masahiro Yamada81254502014-09-16 20:04:25 +0900498 }
499 } else {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800500 denali->fwblks = SPECTRA_START_BLOCK;
Masahiro Yamada81254502014-09-16 20:04:25 +0900501 }
Jason Robertsce082592010-05-13 15:57:33 +0100502}
503
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800504static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100505{
506 uint16_t status = PASS;
grmoore@altera.comd68a5c32014-06-23 14:21:10 -0500507 uint32_t id_bytes[8], addr;
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900508 uint8_t maf_id, device_id;
509 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100510
Masahiro Yamada81254502014-09-16 20:04:25 +0900511 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800512 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100513
Masahiro Yamada43914a22014-09-09 11:01:51 +0900514 /*
515 * Use read id method to get device ID and other params.
516 * For some NAND chips, controller can't report the correct
517 * device ID by reading from DEVICE_ID register
518 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900519 addr = MODE_11 | BANK(denali->flash_bank);
520 index_addr(denali, addr | 0, 0x90);
521 index_addr(denali, addr | 1, 0);
grmoore@altera.comd68a5c32014-06-23 14:21:10 -0500522 for (i = 0; i < 8; i++)
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800523 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
524 maf_id = id_bytes[0];
525 device_id = id_bytes[1];
Jason Robertsce082592010-05-13 15:57:33 +0100526
527 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
528 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
529 if (FAIL == get_onfi_nand_para(denali))
530 return FAIL;
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800531 } else if (maf_id == 0xEC) { /* Samsung NAND */
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800532 get_samsung_nand_para(denali, device_id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800533 } else if (maf_id == 0x98) { /* Toshiba NAND */
Jason Robertsce082592010-05-13 15:57:33 +0100534 get_toshiba_nand_para(denali);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800535 } else if (maf_id == 0xAD) { /* Hynix NAND */
536 get_hynix_nand_para(denali, device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100537 }
538
Jamie Iles84457942011-05-06 15:28:55 +0100539 dev_info(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900540 "Dump timing register values:\n"
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800541 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
542 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
Jason Robertsce082592010-05-13 15:57:33 +0100543 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
544 ioread32(denali->flash_reg + ACC_CLKS),
545 ioread32(denali->flash_reg + RE_2_WE),
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800546 ioread32(denali->flash_reg + RE_2_RE),
Jason Robertsce082592010-05-13 15:57:33 +0100547 ioread32(denali->flash_reg + WE_2_RE),
548 ioread32(denali->flash_reg + ADDR_2_DATA),
549 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
550 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
551 ioread32(denali->flash_reg + CS_SETUP_CNT));
552
Jason Robertsce082592010-05-13 15:57:33 +0100553 find_valid_banks(denali);
554
555 detect_partition_feature(denali);
556
Masahiro Yamada43914a22014-09-09 11:01:51 +0900557 /*
558 * If the user specified to override the default timings
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800559 * with a specific ONFI mode, we apply those changes here.
Jason Robertsce082592010-05-13 15:57:33 +0100560 */
561 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800562 nand_onfi_timing_set(denali, onfi_timing_mode);
Jason Robertsce082592010-05-13 15:57:33 +0100563
564 return status;
565}
566
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800567static void denali_set_intr_modes(struct denali_nand_info *denali,
Jason Robertsce082592010-05-13 15:57:33 +0100568 uint16_t INT_ENABLE)
569{
Jamie Iles84457942011-05-06 15:28:55 +0100570 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
Masahiro Yamada81254502014-09-16 20:04:25 +0900571 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100572
573 if (INT_ENABLE)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800574 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100575 else
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800576 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100577}
578
Masahiro Yamada43914a22014-09-09 11:01:51 +0900579/*
580 * validation function to verify that the controlling software is making
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800581 * a valid request
Jason Robertsce082592010-05-13 15:57:33 +0100582 */
583static inline bool is_flash_bank_valid(int flash_bank)
584{
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +0900585 return flash_bank >= 0 && flash_bank < 4;
Jason Robertsce082592010-05-13 15:57:33 +0100586}
587
588static void denali_irq_init(struct denali_nand_info *denali)
589{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900590 uint32_t int_mask;
Jamie Iles9589bf52011-05-06 15:28:56 +0100591 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100592
593 /* Disable global interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800594 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100595
596 int_mask = DENALI_IRQ_ALL;
597
598 /* Clear all status bits */
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100599 for (i = 0; i < denali->max_banks; ++i)
Jamie Iles9589bf52011-05-06 15:28:56 +0100600 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
Jason Robertsce082592010-05-13 15:57:33 +0100601
602 denali_irq_enable(denali, int_mask);
603}
604
605static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
606{
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800607 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100608 free_irq(irqnum, denali);
609}
610
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800611static void denali_irq_enable(struct denali_nand_info *denali,
612 uint32_t int_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100613{
Jamie Iles9589bf52011-05-06 15:28:56 +0100614 int i;
615
Jamie Ilesc89eeda2011-05-06 15:28:57 +0100616 for (i = 0; i < denali->max_banks; ++i)
Jamie Iles9589bf52011-05-06 15:28:56 +0100617 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
Jason Robertsce082592010-05-13 15:57:33 +0100618}
619
Masahiro Yamada43914a22014-09-09 11:01:51 +0900620/*
621 * This function only returns when an interrupt that this driver cares about
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800622 * occurs. This is to reduce the overhead of servicing interrupts
Jason Robertsce082592010-05-13 15:57:33 +0100623 */
624static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
625{
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800626 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
Jason Robertsce082592010-05-13 15:57:33 +0100627}
628
629/* Interrupts are cleared by writing a 1 to the appropriate status bit */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800630static inline void clear_interrupt(struct denali_nand_info *denali,
631 uint32_t irq_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100632{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900633 uint32_t intr_status_reg;
Jason Robertsce082592010-05-13 15:57:33 +0100634
Jamie Iles9589bf52011-05-06 15:28:56 +0100635 intr_status_reg = INTR_STATUS(denali->flash_bank);
Jason Robertsce082592010-05-13 15:57:33 +0100636
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800637 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
Jason Robertsce082592010-05-13 15:57:33 +0100638}
639
640static void clear_interrupts(struct denali_nand_info *denali)
641{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900642 uint32_t status;
643
Jason Robertsce082592010-05-13 15:57:33 +0100644 spin_lock_irq(&denali->irq_lock);
645
646 status = read_interrupt_status(denali);
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800647 clear_interrupt(denali, status);
Jason Robertsce082592010-05-13 15:57:33 +0100648
Jason Robertsce082592010-05-13 15:57:33 +0100649 denali->irq_status = 0x0;
650 spin_unlock_irq(&denali->irq_lock);
651}
652
653static uint32_t read_interrupt_status(struct denali_nand_info *denali)
654{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900655 uint32_t intr_status_reg;
Jason Robertsce082592010-05-13 15:57:33 +0100656
Jamie Iles9589bf52011-05-06 15:28:56 +0100657 intr_status_reg = INTR_STATUS(denali->flash_bank);
Jason Robertsce082592010-05-13 15:57:33 +0100658
659 return ioread32(denali->flash_reg + intr_status_reg);
660}
661
Masahiro Yamada43914a22014-09-09 11:01:51 +0900662/*
663 * This is the interrupt service routine. It handles all interrupts
664 * sent to this device. Note that on CE4100, this is a shared interrupt.
Jason Robertsce082592010-05-13 15:57:33 +0100665 */
666static irqreturn_t denali_isr(int irq, void *dev_id)
667{
668 struct denali_nand_info *denali = dev_id;
Masahiro Yamada5637b692014-09-09 11:01:52 +0900669 uint32_t irq_status;
Jason Robertsce082592010-05-13 15:57:33 +0100670 irqreturn_t result = IRQ_NONE;
671
672 spin_lock(&denali->irq_lock);
673
Masahiro Yamada43914a22014-09-09 11:01:51 +0900674 /* check to see if a valid NAND chip has been selected. */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800675 if (is_flash_bank_valid(denali->flash_bank)) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900676 /*
677 * check to see if controller generated the interrupt,
678 * since this is a shared interrupt
679 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800680 irq_status = denali_irq_detected(denali);
681 if (irq_status != 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100682 /* handle interrupt */
683 /* first acknowledge it */
684 clear_interrupt(denali, irq_status);
Masahiro Yamada43914a22014-09-09 11:01:51 +0900685 /*
686 * store the status in the device context for someone
687 * to read
688 */
Jason Robertsce082592010-05-13 15:57:33 +0100689 denali->irq_status |= irq_status;
690 /* notify anyone who cares that it happened */
691 complete(&denali->complete);
692 /* tell the OS that we've handled this */
693 result = IRQ_HANDLED;
694 }
695 }
696 spin_unlock(&denali->irq_lock);
697 return result;
698}
699#define BANK(x) ((x) << 24)
700
701static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
702{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900703 unsigned long comp_res;
704 uint32_t intr_status;
Jason Robertsce082592010-05-13 15:57:33 +0100705 unsigned long timeout = msecs_to_jiffies(1000);
706
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800707 do {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800708 comp_res =
709 wait_for_completion_timeout(&denali->complete, timeout);
Jason Robertsce082592010-05-13 15:57:33 +0100710 spin_lock_irq(&denali->irq_lock);
711 intr_status = denali->irq_status;
712
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800713 if (intr_status & irq_mask) {
Jason Robertsce082592010-05-13 15:57:33 +0100714 denali->irq_status &= ~irq_mask;
715 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100716 /* our interrupt was detected */
717 break;
Jason Robertsce082592010-05-13 15:57:33 +0100718 }
Masahiro Yamada81254502014-09-16 20:04:25 +0900719
720 /*
721 * these are not the interrupts you are looking for -
722 * need to wait again
723 */
724 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100725 } while (comp_res != 0);
726
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800727 if (comp_res == 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100728 /* timeout */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -0600729 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800730 intr_status, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100731
732 intr_status = 0;
733 }
734 return intr_status;
735}
736
Masahiro Yamada43914a22014-09-09 11:01:51 +0900737/*
738 * This helper function setups the registers for ECC and whether or not
739 * the spare area will be transferred.
740 */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800741static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
Jason Robertsce082592010-05-13 15:57:33 +0100742 bool transfer_spare)
743{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900744 int ecc_en_flag, transfer_spare_flag;
Jason Robertsce082592010-05-13 15:57:33 +0100745
746 /* set ECC, transfer spare bits if needed */
747 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
748 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
749
750 /* Enable spare area/ECC per user's request. */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800751 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
Masahiro Yamada81254502014-09-16 20:04:25 +0900752 iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
Jason Robertsce082592010-05-13 15:57:33 +0100753}
754
Masahiro Yamada43914a22014-09-09 11:01:51 +0900755/*
756 * sends a pipeline command operation to the controller. See the Denali NAND
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800757 * controller's user guide for more information (section 4.2.3.6).
Jason Robertsce082592010-05-13 15:57:33 +0100758 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800759static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900760 bool ecc_en, bool transfer_spare,
761 int access_type, int op)
Jason Robertsce082592010-05-13 15:57:33 +0100762{
763 int status = PASS;
Masahiro Yamada5637b692014-09-09 11:01:52 +0900764 uint32_t page_count = 1;
765 uint32_t addr, cmd, irq_status, irq_mask;
Jason Robertsce082592010-05-13 15:57:33 +0100766
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800767 if (op == DENALI_READ)
Jamie Iles9589bf52011-05-06 15:28:56 +0100768 irq_mask = INTR_STATUS__LOAD_COMP;
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800769 else if (op == DENALI_WRITE)
770 irq_mask = 0;
771 else
772 BUG();
Jason Robertsce082592010-05-13 15:57:33 +0100773
774 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
775
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800776 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +0100777
778 addr = BANK(denali->flash_bank) | denali->page;
779
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800780 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800781 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800782 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800783 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100784 /* read spare area */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800785 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900786 index_addr(denali, cmd, access_type);
Jason Robertsce082592010-05-13 15:57:33 +0100787
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800788 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800789 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800790 } else if (op == DENALI_READ) {
Jason Robertsce082592010-05-13 15:57:33 +0100791 /* setup page read request for access type */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800792 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900793 index_addr(denali, cmd, access_type);
Jason Robertsce082592010-05-13 15:57:33 +0100794
Masahiro Yamada43914a22014-09-09 11:01:51 +0900795 /*
796 * page 33 of the NAND controller spec indicates we should not
797 * use the pipeline commands in Spare area only mode.
798 * So we don't.
Jason Robertsce082592010-05-13 15:57:33 +0100799 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800800 if (access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100801 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800802 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800803 } else {
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900804 index_addr(denali, cmd,
Masahiro Yamada29023302014-07-11 11:14:05 +0900805 PIPELINE_ACCESS | op | page_count);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800806
Masahiro Yamada43914a22014-09-09 11:01:51 +0900807 /*
808 * wait for command to be accepted
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800809 * can always use status0 bit as the
Masahiro Yamada43914a22014-09-09 11:01:51 +0900810 * mask is identical for each bank.
811 */
Jason Robertsce082592010-05-13 15:57:33 +0100812 irq_status = wait_for_irq(denali, irq_mask);
813
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800814 if (irq_status == 0) {
Jamie Iles84457942011-05-06 15:28:55 +0100815 dev_err(denali->dev,
Masahiro Yamada81254502014-09-16 20:04:25 +0900816 "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n",
817 cmd, denali->page, addr);
Jason Robertsce082592010-05-13 15:57:33 +0100818 status = FAIL;
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800819 } else {
Jason Robertsce082592010-05-13 15:57:33 +0100820 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800821 iowrite32(cmd, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100822 }
823 }
824 }
825 return status;
826}
827
828/* helper function that simply writes a buffer to the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800829static int write_data_to_flash_mem(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900830 const uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100831{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900832 uint32_t *buf32;
833 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100834
Masahiro Yamada43914a22014-09-09 11:01:51 +0900835 /*
836 * verify that the len is a multiple of 4.
837 * see comment in read_data_from_flash_mem()
838 */
Jason Robertsce082592010-05-13 15:57:33 +0100839 BUG_ON((len % 4) != 0);
840
841 /* write the data to the flash memory */
842 buf32 = (uint32_t *)buf;
843 for (i = 0; i < len / 4; i++)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800844 iowrite32(*buf32++, denali->flash_mem + 0x10);
Masahiro Yamada81254502014-09-16 20:04:25 +0900845 return i * 4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100846}
847
848/* helper function that simply reads a buffer from the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800849static int read_data_from_flash_mem(struct denali_nand_info *denali,
Masahiro Yamada81254502014-09-16 20:04:25 +0900850 uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100851{
Masahiro Yamada93e3c8a2014-09-09 11:01:54 +0900852 uint32_t *buf32;
853 int i;
Jason Robertsce082592010-05-13 15:57:33 +0100854
Masahiro Yamada43914a22014-09-09 11:01:51 +0900855 /*
856 * we assume that len will be a multiple of 4, if not it would be nice
857 * to know about it ASAP rather than have random failures...
858 * This assumption is based on the fact that this function is designed
859 * to be used to read flash pages, which are typically multiples of 4.
Jason Robertsce082592010-05-13 15:57:33 +0100860 */
Jason Robertsce082592010-05-13 15:57:33 +0100861 BUG_ON((len % 4) != 0);
862
863 /* transfer the data from the flash */
864 buf32 = (uint32_t *)buf;
865 for (i = 0; i < len / 4; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100866 *buf32++ = ioread32(denali->flash_mem + 0x10);
Masahiro Yamada81254502014-09-16 20:04:25 +0900867 return i * 4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100868}
869
870/* writes OOB data to the device */
871static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
872{
873 struct denali_nand_info *denali = mtd_to_denali(mtd);
Masahiro Yamada5637b692014-09-09 11:01:52 +0900874 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +0100875 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
876 INTR_STATUS__PROGRAM_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +0100877 int status = 0;
878
879 denali->page = page;
880
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800881 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800882 DENALI_WRITE) == PASS) {
Jason Robertsce082592010-05-13 15:57:33 +0100883 write_data_to_flash_mem(denali, buf, mtd->oobsize);
884
Jason Robertsce082592010-05-13 15:57:33 +0100885 /* wait for operation to complete */
886 irq_status = wait_for_irq(denali, irq_mask);
887
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800888 if (irq_status == 0) {
Jamie Iles84457942011-05-06 15:28:55 +0100889 dev_err(denali->dev, "OOB write failed\n");
Jason Robertsce082592010-05-13 15:57:33 +0100890 status = -EIO;
891 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800892 } else {
Jamie Iles84457942011-05-06 15:28:55 +0100893 dev_err(denali->dev, "unable to send pipeline command\n");
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800894 status = -EIO;
Jason Robertsce082592010-05-13 15:57:33 +0100895 }
896 return status;
897}
898
899/* reads OOB data from the device */
900static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
901{
902 struct denali_nand_info *denali = mtd_to_denali(mtd);
Masahiro Yamada5637b692014-09-09 11:01:52 +0900903 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
904 uint32_t irq_status, addr, cmd;
Jason Robertsce082592010-05-13 15:57:33 +0100905
906 denali->page = page;
907
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800908 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800909 DENALI_READ) == PASS) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800910 read_data_from_flash_mem(denali, buf, mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +0100911
Masahiro Yamada43914a22014-09-09 11:01:51 +0900912 /*
913 * wait for command to be accepted
914 * can always use status0 bit as the
915 * mask is identical for each bank.
916 */
Jason Robertsce082592010-05-13 15:57:33 +0100917 irq_status = wait_for_irq(denali, irq_mask);
918
919 if (irq_status == 0)
Jamie Iles84457942011-05-06 15:28:55 +0100920 dev_err(denali->dev, "page on OOB timeout %d\n",
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800921 denali->page);
Jason Robertsce082592010-05-13 15:57:33 +0100922
Masahiro Yamada43914a22014-09-09 11:01:51 +0900923 /*
924 * We set the device back to MAIN_ACCESS here as I observed
Jason Robertsce082592010-05-13 15:57:33 +0100925 * instability with the controller if you do a block erase
926 * and the last transaction was a SPARE_ACCESS. Block erase
927 * is reliable (according to the MTD test infrastructure)
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800928 * if you are in MAIN_ACCESS.
Jason Robertsce082592010-05-13 15:57:33 +0100929 */
930 addr = BANK(denali->flash_bank) | denali->page;
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800931 cmd = MODE_10 | addr;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +0900932 index_addr(denali, cmd, MAIN_ACCESS);
Jason Robertsce082592010-05-13 15:57:33 +0100933 }
934}
935
Masahiro Yamada43914a22014-09-09 11:01:51 +0900936/*
937 * this function examines buffers to see if they contain data that
Jason Robertsce082592010-05-13 15:57:33 +0100938 * indicate that the buffer is part of an erased region of flash.
939 */
Rashika Kheria919193c2013-12-13 12:46:04 +0530940static bool is_erased(uint8_t *buf, int len)
Jason Robertsce082592010-05-13 15:57:33 +0100941{
Masahiro Yamada5637b692014-09-09 11:01:52 +0900942 int i;
Masahiro Yamada81254502014-09-16 20:04:25 +0900943
Jason Robertsce082592010-05-13 15:57:33 +0100944 for (i = 0; i < len; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100945 if (buf[i] != 0xFF)
Jason Robertsce082592010-05-13 15:57:33 +0100946 return false;
Jason Robertsce082592010-05-13 15:57:33 +0100947 return true;
948}
949#define ECC_SECTOR_SIZE 512
950
951#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
952#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
953#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800954#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
955#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
Jason Robertsce082592010-05-13 15:57:33 +0100956#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
957
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800958static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
Mike Dunn3f91e942012-04-25 12:06:09 -0700959 uint32_t irq_status, unsigned int *max_bitflips)
Jason Robertsce082592010-05-13 15:57:33 +0100960{
961 bool check_erased_page = false;
Mike Dunn3f91e942012-04-25 12:06:09 -0700962 unsigned int bitflips = 0;
Jason Robertsce082592010-05-13 15:57:33 +0100963
Jamie Iles9589bf52011-05-06 15:28:56 +0100964 if (irq_status & INTR_STATUS__ECC_ERR) {
Jason Robertsce082592010-05-13 15:57:33 +0100965 /* read the ECC errors. we'll ignore them for now */
Masahiro Yamada5637b692014-09-09 11:01:52 +0900966 uint32_t err_address, err_correction_info, err_byte,
967 err_sector, err_device, err_correction_value;
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800968 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100969
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800970 do {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800971 err_address = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100972 ECC_ERROR_ADDRESS);
973 err_sector = ECC_SECTOR(err_address);
974 err_byte = ECC_BYTE(err_address);
975
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800976 err_correction_info = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100977 ERR_CORRECTION_INFO);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800978 err_correction_value =
Jason Robertsce082592010-05-13 15:57:33 +0100979 ECC_CORRECTION_VALUE(err_correction_info);
980 err_device = ECC_ERR_DEVICE(err_correction_info);
981
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800982 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
Masahiro Yamada43914a22014-09-09 11:01:51 +0900983 /*
984 * If err_byte is larger than ECC_SECTOR_SIZE,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300985 * means error happened in OOB, so we ignore
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800986 * it. It's no need for us to correct it
987 * err_device is represented the NAND error
988 * bits are happened in if there are more
989 * than one NAND connected.
Masahiro Yamada43914a22014-09-09 11:01:51 +0900990 */
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800991 if (err_byte < ECC_SECTOR_SIZE) {
Boris BREZILLON442f201b2015-12-11 15:06:00 +0100992 struct mtd_info *mtd =
993 nand_to_mtd(&denali->nand);
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800994 int offset;
Masahiro Yamada81254502014-09-16 20:04:25 +0900995
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800996 offset = (err_sector *
997 ECC_SECTOR_SIZE +
998 err_byte) *
999 denali->devnum +
1000 err_device;
Jason Robertsce082592010-05-13 15:57:33 +01001001 /* correct the ECC error */
1002 buf[offset] ^= err_correction_value;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001003 mtd->ecc_stats.corrected++;
Mike Dunn3f91e942012-04-25 12:06:09 -07001004 bitflips++;
Jason Robertsce082592010-05-13 15:57:33 +01001005 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001006 } else {
Masahiro Yamada43914a22014-09-09 11:01:51 +09001007 /*
1008 * if the error is not correctable, need to
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001009 * look at the page to see if it is an erased
1010 * page. if so, then it's not a real ECC error
Masahiro Yamada43914a22014-09-09 11:01:51 +09001011 */
Jason Robertsce082592010-05-13 15:57:33 +01001012 check_erased_page = true;
1013 }
Jason Robertsce082592010-05-13 15:57:33 +01001014 } while (!ECC_LAST_ERR(err_correction_info));
Masahiro Yamada43914a22014-09-09 11:01:51 +09001015 /*
1016 * Once handle all ecc errors, controller will triger
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001017 * a ECC_TRANSACTION_DONE interrupt, so here just wait
1018 * for a while for this interrupt
Masahiro Yamada43914a22014-09-09 11:01:51 +09001019 */
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001020 while (!(read_interrupt_status(denali) &
Jamie Iles9589bf52011-05-06 15:28:56 +01001021 INTR_STATUS__ECC_TRANSACTION_DONE))
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001022 cpu_relax();
1023 clear_interrupts(denali);
1024 denali_set_intr_modes(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001025 }
Mike Dunn3f91e942012-04-25 12:06:09 -07001026 *max_bitflips = bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001027 return check_erased_page;
1028}
1029
1030/* programs the controller to either enable/disable DMA transfers */
David Woodhouseaadff492010-05-13 16:12:43 +01001031static void denali_enable_dma(struct denali_nand_info *denali, bool en)
Jason Robertsce082592010-05-13 15:57:33 +01001032{
Masahiro Yamada5637b692014-09-09 11:01:52 +09001033 iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +01001034 ioread32(denali->flash_reg + DMA_ENABLE);
1035}
1036
1037/* setups the HW to perform the data DMA */
David Woodhouseaadff492010-05-13 16:12:43 +01001038static void denali_setup_dma(struct denali_nand_info *denali, int op)
Jason Robertsce082592010-05-13 15:57:33 +01001039{
Masahiro Yamada5637b692014-09-09 11:01:52 +09001040 uint32_t mode;
Jason Robertsce082592010-05-13 15:57:33 +01001041 const int page_count = 1;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001042 uint32_t addr = denali->buf.dma_buf;
Jason Robertsce082592010-05-13 15:57:33 +01001043
1044 mode = MODE_10 | BANK(denali->flash_bank);
1045
1046 /* DMA is a four step process */
1047
1048 /* 1. setup transfer type and # of pages */
1049 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1050
1051 /* 2. set memory high address bits 23:8 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001052 index_addr(denali, mode | ((addr >> 16) << 8), 0x2200);
Jason Robertsce082592010-05-13 15:57:33 +01001053
1054 /* 3. set memory low address bits 23:8 */
Graham Moore7c272ac2015-01-09 09:32:35 -06001055 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
Jason Robertsce082592010-05-13 15:57:33 +01001056
Masahiro Yamada43914a22014-09-09 11:01:51 +09001057 /* 4. interrupt when complete, burst len = 64 bytes */
Jason Robertsce082592010-05-13 15:57:33 +01001058 index_addr(denali, mode | 0x14000, 0x2400);
1059}
1060
Masahiro Yamada43914a22014-09-09 11:01:51 +09001061/*
1062 * writes a page. user specifies type, and this function handles the
1063 * configuration details.
1064 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001065static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001066 const uint8_t *buf, bool raw_xfer)
1067{
1068 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001069 dma_addr_t addr = denali->buf.dma_buf;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001070 size_t size = mtd->writesize + mtd->oobsize;
Masahiro Yamada5637b692014-09-09 11:01:52 +09001071 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +01001072 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1073 INTR_STATUS__PROGRAM_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +01001074
Masahiro Yamada43914a22014-09-09 11:01:51 +09001075 /*
1076 * if it is a raw xfer, we want to disable ecc and send the spare area.
Jason Robertsce082592010-05-13 15:57:33 +01001077 * !raw_xfer - enable ecc
1078 * raw_xfer - transfer spare
1079 */
1080 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1081
1082 /* copy buffer into DMA buffer */
1083 memcpy(denali->buf.buf, buf, mtd->writesize);
1084
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001085 if (raw_xfer) {
Jason Robertsce082592010-05-13 15:57:33 +01001086 /* transfer the data to the spare area */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001087 memcpy(denali->buf.buf + mtd->writesize,
1088 chip->oob_poi,
1089 mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +01001090 }
1091
Jamie Iles84457942011-05-06 15:28:55 +01001092 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001093
1094 clear_interrupts(denali);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001095 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001096
David Woodhouseaadff492010-05-13 16:12:43 +01001097 denali_setup_dma(denali, DENALI_WRITE);
Jason Robertsce082592010-05-13 15:57:33 +01001098
1099 /* wait for operation to complete */
1100 irq_status = wait_for_irq(denali, irq_mask);
1101
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001102 if (irq_status == 0) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001103 dev_err(denali->dev, "timeout on write_page (type = %d)\n",
1104 raw_xfer);
Brian Norrisc115add2014-07-21 19:07:31 -07001105 denali->status = NAND_STATUS_FAIL;
Jason Robertsce082592010-05-13 15:57:33 +01001106 }
1107
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001108 denali_enable_dma(denali, false);
Jamie Iles84457942011-05-06 15:28:55 +01001109 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
Josh Wufdbad98d2012-06-25 18:07:45 +08001110
1111 return 0;
Jason Robertsce082592010-05-13 15:57:33 +01001112}
1113
1114/* NAND core entry points */
1115
Masahiro Yamada43914a22014-09-09 11:01:51 +09001116/*
1117 * this is the callback that the NAND core calls to write a page. Since
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001118 * writing a page with ECC or without is similar, all the work is done
1119 * by write_page above.
Masahiro Yamada43914a22014-09-09 11:01:51 +09001120 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001121static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +02001122 const uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001123{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001124 /*
1125 * for regular page writes, we let HW handle all the ECC
1126 * data written to the device.
1127 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001128 return write_page(mtd, chip, buf, false);
Jason Robertsce082592010-05-13 15:57:33 +01001129}
1130
Masahiro Yamada43914a22014-09-09 11:01:51 +09001131/*
1132 * This is the callback that the NAND core calls to write a page without ECC.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001133 * raw access is similar to ECC page writes, so all the work is done in the
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001134 * write_page() function above.
Jason Robertsce082592010-05-13 15:57:33 +01001135 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001136static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Boris BREZILLON45aaeff2015-10-13 11:22:18 +02001137 const uint8_t *buf, int oob_required,
1138 int page)
Jason Robertsce082592010-05-13 15:57:33 +01001139{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001140 /*
1141 * for raw page writes, we want to disable ECC and simply write
1142 * whatever data is in the buffer.
1143 */
Josh Wufdbad98d2012-06-25 18:07:45 +08001144 return write_page(mtd, chip, buf, true);
Jason Robertsce082592010-05-13 15:57:33 +01001145}
1146
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001147static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001148 int page)
1149{
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001150 return write_oob_data(mtd, chip->oob_poi, page);
Jason Robertsce082592010-05-13 15:57:33 +01001151}
1152
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001153static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +03001154 int page)
Jason Robertsce082592010-05-13 15:57:33 +01001155{
1156 read_oob_data(mtd, chip->oob_poi, page);
1157
Shmulik Ladkani5c2ffb12012-05-09 13:06:35 +03001158 return 0;
Jason Robertsce082592010-05-13 15:57:33 +01001159}
1160
1161static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001162 uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001163{
Mike Dunn3f91e942012-04-25 12:06:09 -07001164 unsigned int max_bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001165 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001166
1167 dma_addr_t addr = denali->buf.dma_buf;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001168 size_t size = mtd->writesize + mtd->oobsize;
Jason Robertsce082592010-05-13 15:57:33 +01001169
Masahiro Yamada5637b692014-09-09 11:01:52 +09001170 uint32_t irq_status;
Jamie Iles9589bf52011-05-06 15:28:56 +01001171 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1172 INTR_STATUS__ECC_ERR;
Jason Robertsce082592010-05-13 15:57:33 +01001173 bool check_erased_page = false;
1174
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001175 if (page != denali->page) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001176 dev_err(denali->dev,
1177 "IN %s: page %d is not equal to denali->page %d",
1178 __func__, page, denali->page);
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001179 BUG();
1180 }
1181
Jason Robertsce082592010-05-13 15:57:33 +01001182 setup_ecc_for_xfer(denali, true, false);
1183
David Woodhouseaadff492010-05-13 16:12:43 +01001184 denali_enable_dma(denali, true);
Jamie Iles84457942011-05-06 15:28:55 +01001185 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001186
1187 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001188 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001189
1190 /* wait for operation to complete */
1191 irq_status = wait_for_irq(denali, irq_mask);
1192
Jamie Iles84457942011-05-06 15:28:55 +01001193 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001194
1195 memcpy(buf, denali->buf.buf, mtd->writesize);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001196
Mike Dunn3f91e942012-04-25 12:06:09 -07001197 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
David Woodhouseaadff492010-05-13 16:12:43 +01001198 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001199
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001200 if (check_erased_page) {
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001201 read_oob_data(mtd, chip->oob_poi, denali->page);
Jason Robertsce082592010-05-13 15:57:33 +01001202
1203 /* check ECC failures that may have occurred on erased pages */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001204 if (check_erased_page) {
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001205 if (!is_erased(buf, mtd->writesize))
1206 mtd->ecc_stats.failed++;
1207 if (!is_erased(buf, mtd->oobsize))
1208 mtd->ecc_stats.failed++;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001209 }
Jason Robertsce082592010-05-13 15:57:33 +01001210 }
Mike Dunn3f91e942012-04-25 12:06:09 -07001211 return max_bitflips;
Jason Robertsce082592010-05-13 15:57:33 +01001212}
1213
1214static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -07001215 uint8_t *buf, int oob_required, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001216{
1217 struct denali_nand_info *denali = mtd_to_denali(mtd);
Jason Robertsce082592010-05-13 15:57:33 +01001218 dma_addr_t addr = denali->buf.dma_buf;
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001219 size_t size = mtd->writesize + mtd->oobsize;
Jamie Iles9589bf52011-05-06 15:28:56 +01001220 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001221
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001222 if (page != denali->page) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001223 dev_err(denali->dev,
1224 "IN %s: page %d is not equal to denali->page %d",
1225 __func__, page, denali->page);
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001226 BUG();
1227 }
1228
Jason Robertsce082592010-05-13 15:57:33 +01001229 setup_ecc_for_xfer(denali, false, true);
David Woodhouseaadff492010-05-13 16:12:43 +01001230 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001231
Jamie Iles84457942011-05-06 15:28:55 +01001232 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001233
1234 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001235 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001236
1237 /* wait for operation to complete */
Brian Norrisba5f2bc2014-09-19 09:37:19 -07001238 wait_for_irq(denali, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +01001239
Jamie Iles84457942011-05-06 15:28:55 +01001240 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
Jason Robertsce082592010-05-13 15:57:33 +01001241
David Woodhouseaadff492010-05-13 16:12:43 +01001242 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001243
1244 memcpy(buf, denali->buf.buf, mtd->writesize);
1245 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1246
1247 return 0;
1248}
1249
1250static uint8_t denali_read_byte(struct mtd_info *mtd)
1251{
1252 struct denali_nand_info *denali = mtd_to_denali(mtd);
1253 uint8_t result = 0xff;
1254
1255 if (denali->buf.head < denali->buf.tail)
Jason Robertsce082592010-05-13 15:57:33 +01001256 result = denali->buf.buf[denali->buf.head++];
Jason Robertsce082592010-05-13 15:57:33 +01001257
Jason Robertsce082592010-05-13 15:57:33 +01001258 return result;
1259}
1260
1261static void denali_select_chip(struct mtd_info *mtd, int chip)
1262{
1263 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001264
Jason Robertsce082592010-05-13 15:57:33 +01001265 spin_lock_irq(&denali->irq_lock);
1266 denali->flash_bank = chip;
1267 spin_unlock_irq(&denali->irq_lock);
1268}
1269
1270static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1271{
1272 struct denali_nand_info *denali = mtd_to_denali(mtd);
1273 int status = denali->status;
Masahiro Yamada81254502014-09-16 20:04:25 +09001274
Jason Robertsce082592010-05-13 15:57:33 +01001275 denali->status = 0;
1276
Jason Robertsce082592010-05-13 15:57:33 +01001277 return status;
1278}
1279
Brian Norris49c50b92014-05-06 16:02:19 -07001280static int denali_erase(struct mtd_info *mtd, int page)
Jason Robertsce082592010-05-13 15:57:33 +01001281{
1282 struct denali_nand_info *denali = mtd_to_denali(mtd);
1283
Masahiro Yamada5637b692014-09-09 11:01:52 +09001284 uint32_t cmd, irq_status;
Jason Robertsce082592010-05-13 15:57:33 +01001285
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001286 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001287
1288 /* setup page read request for access type */
1289 cmd = MODE_10 | BANK(denali->flash_bank) | page;
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001290 index_addr(denali, cmd, 0x1);
Jason Robertsce082592010-05-13 15:57:33 +01001291
1292 /* wait for erase to complete or failure to occur */
Jamie Iles9589bf52011-05-06 15:28:56 +01001293 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1294 INTR_STATUS__ERASE_FAIL);
Jason Robertsce082592010-05-13 15:57:33 +01001295
Masahiro Yamada7d14ecd2014-09-16 20:04:24 +09001296 return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
Jason Robertsce082592010-05-13 15:57:33 +01001297}
1298
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001299static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
Jason Robertsce082592010-05-13 15:57:33 +01001300 int page)
1301{
1302 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001303 uint32_t addr, id;
1304 int i;
Jason Robertsce082592010-05-13 15:57:33 +01001305
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001306 switch (cmd) {
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001307 case NAND_CMD_PAGEPROG:
1308 break;
1309 case NAND_CMD_STATUS:
1310 read_status(denali);
1311 break;
1312 case NAND_CMD_READID:
Florian Fainelli42af8b52010-08-30 18:32:20 +02001313 case NAND_CMD_PARAM:
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001314 reset_buf(denali);
Masahiro Yamada43914a22014-09-09 11:01:51 +09001315 /*
1316 * sometimes ManufactureId read from register is not right
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001317 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1318 * So here we send READID cmd to NAND insteand
Masahiro Yamada43914a22014-09-09 11:01:51 +09001319 */
Masahiro Yamada3157d1e2014-09-09 11:01:53 +09001320 addr = MODE_11 | BANK(denali->flash_bank);
1321 index_addr(denali, addr | 0, 0x90);
Enrico Jorns9c07d092015-09-18 10:02:41 +02001322 index_addr(denali, addr | 1, col);
grmoore@altera.comd68a5c32014-06-23 14:21:10 -05001323 for (i = 0; i < 8; i++) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001324 index_addr_read_data(denali, addr | 2, &id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001325 write_byte_to_buf(denali, id);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001326 }
1327 break;
1328 case NAND_CMD_READ0:
1329 case NAND_CMD_SEQIN:
1330 denali->page = page;
1331 break;
1332 case NAND_CMD_RESET:
1333 reset_bank(denali);
1334 break;
1335 case NAND_CMD_READOOB:
1336 /* TODO: Read OOB data */
1337 break;
1338 default:
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001339 pr_err(": unsupported command received 0x%x\n", cmd);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001340 break;
Jason Robertsce082592010-05-13 15:57:33 +01001341 }
1342}
Jason Robertsce082592010-05-13 15:57:33 +01001343/* end NAND core entry points */
1344
1345/* Initialization code to bring the device up to a known good state */
1346static void denali_hw_init(struct denali_nand_info *denali)
1347{
Masahiro Yamada43914a22014-09-09 11:01:51 +09001348 /*
1349 * tell driver how many bit controller will skip before
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001350 * writing ECC code in OOB, this register may be already
1351 * set by firmware. So we read this value out.
1352 * if this value is 0, just let it be.
Masahiro Yamada43914a22014-09-09 11:01:51 +09001353 */
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001354 denali->bbtskipbytes = ioread32(denali->flash_reg +
1355 SPARE_AREA_SKIP_BYTES);
Jamie Ilesbc27ede2011-06-06 17:11:34 +01001356 detect_max_banks(denali);
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001357 denali_nand_reset(denali);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001358 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1359 iowrite32(CHIP_EN_DONT_CARE__FLAG,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001360 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
Jason Robertsce082592010-05-13 15:57:33 +01001361
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001362 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
Jason Robertsce082592010-05-13 15:57:33 +01001363
1364 /* Should set value for these registers when init */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001365 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1366 iowrite32(1, denali->flash_reg + ECC_ENABLE);
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001367 denali_nand_timing_set(denali);
1368 denali_irq_init(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001369}
1370
Masahiro Yamada43914a22014-09-09 11:01:51 +09001371/*
1372 * Althogh controller spec said SLC ECC is forceb to be 4bit,
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001373 * but denali controller in MRST only support 15bit and 8bit ECC
1374 * correction
Masahiro Yamada43914a22014-09-09 11:01:51 +09001375 */
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001376#define ECC_8BITS 14
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001377#define ECC_15BITS 26
Boris Brezillon14fad622016-02-03 20:00:11 +01001378
1379static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1380 struct mtd_oob_region *oobregion)
1381{
1382 struct denali_nand_info *denali = mtd_to_denali(mtd);
1383 struct nand_chip *chip = mtd_to_nand(mtd);
1384
1385 if (section)
1386 return -ERANGE;
1387
1388 oobregion->offset = denali->bbtskipbytes;
1389 oobregion->length = chip->ecc.total;
1390
1391 return 0;
1392}
1393
1394static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1395 struct mtd_oob_region *oobregion)
1396{
1397 struct denali_nand_info *denali = mtd_to_denali(mtd);
1398 struct nand_chip *chip = mtd_to_nand(mtd);
1399
1400 if (section)
1401 return -ERANGE;
1402
1403 oobregion->offset = chip->ecc.total + denali->bbtskipbytes;
1404 oobregion->length = mtd->oobsize - oobregion->offset;
1405
1406 return 0;
1407}
1408
1409static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1410 .ecc = denali_ooblayout_ecc,
1411 .free = denali_ooblayout_free,
Jason Robertsce082592010-05-13 15:57:33 +01001412};
1413
1414static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1415static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1416
1417static struct nand_bbt_descr bbt_main_descr = {
1418 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1419 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1420 .offs = 8,
1421 .len = 4,
1422 .veroffs = 12,
1423 .maxblocks = 4,
1424 .pattern = bbt_pattern,
1425};
1426
1427static struct nand_bbt_descr bbt_mirror_descr = {
1428 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1429 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1430 .offs = 8,
1431 .len = 4,
1432 .veroffs = 12,
1433 .maxblocks = 4,
1434 .pattern = mirror_pattern,
1435};
1436
Uwe Kleine-König421f91d2010-06-11 12:17:00 +02001437/* initialize driver data structures */
Brian Norris8c519432013-08-10 22:57:30 -07001438static void denali_drv_init(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001439{
1440 denali->idx = 0;
1441
1442 /* setup interrupt handler */
Masahiro Yamada43914a22014-09-09 11:01:51 +09001443 /*
1444 * the completion object will be used to notify
1445 * the callee that the interrupt is done
1446 */
Jason Robertsce082592010-05-13 15:57:33 +01001447 init_completion(&denali->complete);
1448
Masahiro Yamada43914a22014-09-09 11:01:51 +09001449 /*
1450 * the spinlock will be used to synchronize the ISR with any
1451 * element that might be access shared data (interrupt status)
1452 */
Jason Robertsce082592010-05-13 15:57:33 +01001453 spin_lock_init(&denali->irq_lock);
1454
1455 /* indicate that MTD has not selected a valid bank yet */
1456 denali->flash_bank = CHIP_SELECT_INVALID;
1457
1458 /* initialize our irq_status variable to indicate no interrupts */
1459 denali->irq_status = 0;
1460}
1461
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001462int denali_init(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001463{
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001464 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001465 int ret;
Jason Robertsce082592010-05-13 15:57:33 +01001466
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001467 if (denali->platform == INTEL_CE4100) {
Masahiro Yamada43914a22014-09-09 11:01:51 +09001468 /*
1469 * Due to a silicon limitation, we can only support
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001470 * ONFI timing mode 1 and below.
1471 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001472 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001473 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1474 return -EINVAL;
Jason Robertsce082592010-05-13 15:57:33 +01001475 }
1476 }
1477
Huang Shijiee07caa32013-12-21 00:02:28 +08001478 /* allocate a temporary buffer for nand_scan_ident() */
1479 denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
1480 GFP_DMA | GFP_KERNEL);
1481 if (!denali->buf.buf)
1482 return -ENOMEM;
Jason Robertsce082592010-05-13 15:57:33 +01001483
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001484 mtd->dev.parent = denali->dev;
Jason Robertsce082592010-05-13 15:57:33 +01001485 denali_hw_init(denali);
1486 denali_drv_init(denali);
1487
Masahiro Yamada43914a22014-09-09 11:01:51 +09001488 /*
1489 * denali_isr register is done after all the hardware
1490 * initilization is finished
1491 */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001492 if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
Jason Robertsce082592010-05-13 15:57:33 +01001493 DENALI_NAND_NAME, denali)) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001494 pr_err("Spectra: Unable to allocate IRQ\n");
1495 return -ENODEV;
Jason Robertsce082592010-05-13 15:57:33 +01001496 }
1497
1498 /* now that our ISR is registered, we can enable interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001499 denali_set_intr_modes(denali, true);
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001500 mtd->name = "denali-nand";
Jason Robertsce082592010-05-13 15:57:33 +01001501
1502 /* register the driver with the NAND core subsystem */
1503 denali->nand.select_chip = denali_select_chip;
1504 denali->nand.cmdfunc = denali_cmdfunc;
1505 denali->nand.read_byte = denali_read_byte;
1506 denali->nand.waitfunc = denali_waitfunc;
1507
Masahiro Yamada43914a22014-09-09 11:01:51 +09001508 /*
1509 * scan for NAND devices attached to the controller
Jason Robertsce082592010-05-13 15:57:33 +01001510 * this is the first stage in a two step process to register
Masahiro Yamada43914a22014-09-09 11:01:51 +09001511 * with the nand subsystem
1512 */
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001513 if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
Jason Robertsce082592010-05-13 15:57:33 +01001514 ret = -ENXIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001515 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001516 }
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001517
Huang Shijiee07caa32013-12-21 00:02:28 +08001518 /* allocate the right size buffer now */
1519 devm_kfree(denali->dev, denali->buf.buf);
1520 denali->buf.buf = devm_kzalloc(denali->dev,
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001521 mtd->writesize + mtd->oobsize,
Huang Shijiee07caa32013-12-21 00:02:28 +08001522 GFP_KERNEL);
1523 if (!denali->buf.buf) {
1524 ret = -ENOMEM;
1525 goto failed_req_irq;
1526 }
1527
1528 /* Is 32-bit DMA supported? */
1529 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1530 if (ret) {
1531 pr_err("Spectra: no usable DMA configuration\n");
1532 goto failed_req_irq;
1533 }
1534
1535 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001536 mtd->writesize + mtd->oobsize,
Huang Shijiee07caa32013-12-21 00:02:28 +08001537 DMA_BIDIRECTIONAL);
1538 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1539 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1540 ret = -EIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001541 goto failed_req_irq;
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001542 }
1543
Masahiro Yamada43914a22014-09-09 11:01:51 +09001544 /*
1545 * support for multi nand
1546 * MTD known nothing about multi nand, so we should tell it
1547 * the real pagesize and anything necessery
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001548 */
1549 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1550 denali->nand.chipsize <<= (denali->devnum - 1);
1551 denali->nand.page_shift += (denali->devnum - 1);
1552 denali->nand.pagemask = (denali->nand.chipsize >>
1553 denali->nand.page_shift) - 1;
1554 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1555 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1556 denali->nand.chip_shift += (denali->devnum - 1);
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001557 mtd->writesize <<= (denali->devnum - 1);
1558 mtd->oobsize <<= (denali->devnum - 1);
1559 mtd->erasesize <<= (denali->devnum - 1);
1560 mtd->size = denali->nand.numchips * denali->nand.chipsize;
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001561 denali->bbtskipbytes *= denali->devnum;
1562
Masahiro Yamada43914a22014-09-09 11:01:51 +09001563 /*
1564 * second stage of the NAND scan
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001565 * this stage requires information regarding ECC and
Masahiro Yamada43914a22014-09-09 11:01:51 +09001566 * bad block management.
1567 */
Jason Robertsce082592010-05-13 15:57:33 +01001568
1569 /* Bad block management */
1570 denali->nand.bbt_td = &bbt_main_descr;
1571 denali->nand.bbt_md = &bbt_mirror_descr;
1572
1573 /* skip the scan for now until we have OOB read and write support */
Brian Norrisbb9ebd42011-05-31 16:31:23 -07001574 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
Brian Norrisa40f7342011-05-31 16:31:22 -07001575 denali->nand.options |= NAND_SKIP_BBTSCAN;
Jason Robertsce082592010-05-13 15:57:33 +01001576 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1577
Graham Moored99d7282015-01-14 09:38:50 -06001578 /* no subpage writes on denali */
1579 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1580
Masahiro Yamada43914a22014-09-09 11:01:51 +09001581 /*
1582 * Denali Controller only support 15bit and 8bit ECC in MRST,
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001583 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1584 * SLC if possible.
1585 * */
Huang Shijie1d0ed692013-09-25 14:58:10 +08001586 if (!nand_is_slc(&denali->nand) &&
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001587 (mtd->oobsize > (denali->bbtskipbytes +
1588 ECC_15BITS * (mtd->writesize /
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001589 ECC_SECTOR_SIZE)))) {
1590 /* if MLC OOB size is large enough, use 15bit ECC*/
Mike Dunn6a918ba2012-03-11 14:21:11 -07001591 denali->nand.ecc.strength = 15;
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001592 denali->nand.ecc.bytes = ECC_15BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001593 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001594 } else if (mtd->oobsize < (denali->bbtskipbytes +
1595 ECC_8BITS * (mtd->writesize /
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001596 ECC_SECTOR_SIZE))) {
Masahiro Yamada81254502014-09-16 20:04:25 +09001597 pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001598 goto failed_req_irq;
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001599 } else {
Mike Dunn6a918ba2012-03-11 14:21:11 -07001600 denali->nand.ecc.strength = 8;
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001601 denali->nand.ecc.bytes = ECC_8BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001602 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +01001603 }
1604
Boris Brezillon14fad622016-02-03 20:00:11 +01001605 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001606 denali->nand.ecc.bytes *= denali->devnum;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001607 denali->nand.ecc.strength *= denali->devnum;
Chuanxiao Dongdb9a3212010-08-06 18:02:03 +08001608
Masahiro Yamada43914a22014-09-09 11:01:51 +09001609 /*
1610 * Let driver know the total blocks number and how many blocks
1611 * contained by each nand chip. blksperchip will help driver to
1612 * know how many blocks is taken by FW.
1613 */
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001614 denali->totalblks = mtd->size >> denali->nand.phys_erase_shift;
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001615 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1616
Jason Robertsce082592010-05-13 15:57:33 +01001617 /* override the default read operations */
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001618 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
Jason Robertsce082592010-05-13 15:57:33 +01001619 denali->nand.ecc.read_page = denali_read_page;
1620 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1621 denali->nand.ecc.write_page = denali_write_page;
1622 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1623 denali->nand.ecc.read_oob = denali_read_oob;
1624 denali->nand.ecc.write_oob = denali_write_oob;
Brian Norris49c50b92014-05-06 16:02:19 -07001625 denali->nand.erase = denali_erase;
Jason Robertsce082592010-05-13 15:57:33 +01001626
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001627 if (nand_scan_tail(mtd)) {
Jason Robertsce082592010-05-13 15:57:33 +01001628 ret = -ENXIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001629 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001630 }
1631
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001632 ret = mtd_device_register(mtd, NULL, 0);
Jason Robertsce082592010-05-13 15:57:33 +01001633 if (ret) {
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001634 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001635 ret);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001636 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001637 }
1638 return 0;
1639
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001640failed_req_irq:
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001641 denali_irq_cleanup(denali->irq, denali);
1642
Jason Robertsce082592010-05-13 15:57:33 +01001643 return ret;
1644}
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001645EXPORT_SYMBOL(denali_init);
Jason Robertsce082592010-05-13 15:57:33 +01001646
1647/* driver exit point */
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001648void denali_remove(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +01001649{
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001650 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
Boris BREZILLON320092a2015-12-11 15:02:34 +01001651 /*
1652 * Pre-compute DMA buffer size to avoid any problems in case
1653 * nand_release() ever changes in a way that mtd->writesize and
1654 * mtd->oobsize are not reliable after this call.
1655 */
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001656 int bufsize = mtd->writesize + mtd->oobsize;
Boris BREZILLON320092a2015-12-11 15:02:34 +01001657
Boris BREZILLON442f201b2015-12-11 15:06:00 +01001658 nand_release(mtd);
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001659 denali_irq_cleanup(denali->irq, denali);
Boris BREZILLON320092a2015-12-11 15:02:34 +01001660 dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize,
Masahiro Yamada81254502014-09-16 20:04:25 +09001661 DMA_BIDIRECTIONAL);
Jason Robertsce082592010-05-13 15:57:33 +01001662}
Dinh Nguyen2a0a2882012-09-27 10:58:05 -06001663EXPORT_SYMBOL(denali_remove);