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Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
Dan Williams7405f742007-01-02 11:10:43 -070026#include <linux/dma-mapping.h>
Chris Leechc13c8262006-05-23 17:18:44 -070027
28/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070029 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070030 *
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
32 */
33typedef s32 dma_cookie_t;
34
35#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
36
37/**
38 * enum dma_status - DMA transaction status
39 * @DMA_SUCCESS: transaction completed successfully
40 * @DMA_IN_PROGRESS: transaction not yet processed
41 * @DMA_ERROR: transaction failed
42 */
43enum dma_status {
44 DMA_SUCCESS,
45 DMA_IN_PROGRESS,
46 DMA_ERROR,
47};
48
49/**
Dan Williams7405f742007-01-02 11:10:43 -070050 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070051 *
52 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
53 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070054 */
55enum dma_transaction_type {
56 DMA_MEMCPY,
57 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070058 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070059 DMA_XOR_VAL,
60 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070061 DMA_MEMSET,
Dan Williams7405f742007-01-02 11:10:43 -070062 DMA_INTERRUPT,
Dan Williams59b5ec22009-01-06 11:38:15 -070063 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070064 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070065 DMA_SLAVE,
Dan Williams7405f742007-01-02 11:10:43 -070066};
67
68/* last transaction type for creation of the capabilities mask */
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070069#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
70
Dan Williams7405f742007-01-02 11:10:43 -070071
72/**
Dan Williams636bdea2008-04-17 20:17:26 -070073 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070074 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -070075 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -070076 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +010077 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -070078 * acknowledges receipt, i.e. has has a chance to establish any dependency
79 * chains
Dan Williamse1d181e2008-07-04 00:13:40 -070080 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
81 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Maciej Sosnowski4f005db2009-04-23 12:31:51 +020082 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
83 * (if not set, do the source dma-unmapping as page)
84 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
85 * (if not set, do the destination dma-unmapping as page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -070086 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
87 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
88 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
89 * sources that were the result of a previous operation, in the case of a PQ
90 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -070091 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
92 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -070093 */
Dan Williams636bdea2008-04-17 20:17:26 -070094enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -070095 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -070096 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -070097 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
98 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Maciej Sosnowski4f005db2009-04-23 12:31:51 +020099 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
100 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
Dan Williamsf9dd2132009-09-08 17:42:29 -0700101 DMA_PREP_PQ_DISABLE_P = (1 << 6),
102 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
103 DMA_PREP_CONTINUE = (1 << 8),
Dan Williams0403e382009-09-08 17:42:50 -0700104 DMA_PREP_FENCE = (1 << 9),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700105};
106
107/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700108 * enum sum_check_bits - bit position of pq_check_flags
109 */
110enum sum_check_bits {
111 SUM_CHECK_P = 0,
112 SUM_CHECK_Q = 1,
113};
114
115/**
116 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
117 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
118 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
119 */
120enum sum_check_flags {
121 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
122 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
123};
124
125
126/**
Dan Williams7405f742007-01-02 11:10:43 -0700127 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
128 * See linux/cpumask.h
129 */
130typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
131
132/**
Chris Leechc13c8262006-05-23 17:18:44 -0700133 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700134 * @memcpy_count: transaction counter
135 * @bytes_transferred: byte counter
136 */
137
138struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700139 /* stats */
140 unsigned long memcpy_count;
141 unsigned long bytes_transferred;
142};
143
144/**
145 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700146 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700147 * @cookie: last cookie value returned to client
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700148 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700149 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700150 * @device_node: used to add this to the device chan list
151 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700152 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700153 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800154 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700155 */
156struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700157 struct dma_device *device;
158 dma_cookie_t cookie;
159
160 /* sysfs */
161 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700162 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700163
Chris Leechc13c8262006-05-23 17:18:44 -0700164 struct list_head device_node;
165 struct dma_chan_percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700166 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700167 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800168 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700169};
170
Dan Williams41d5e592009-01-06 11:38:21 -0700171/**
172 * struct dma_chan_dev - relate sysfs device node to backing channel device
173 * @chan - driver channel device
174 * @device - sysfs device
Dan Williams864498a2009-01-06 11:38:21 -0700175 * @dev_id - parent dma_device dev_id
176 * @idr_ref - reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700177 */
178struct dma_chan_dev {
179 struct dma_chan *chan;
180 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700181 int dev_id;
182 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700183};
184
185static inline const char *dma_chan_name(struct dma_chan *chan)
186{
187 return dev_name(&chan->dev->device);
188}
Dan Williamsd379b012007-07-09 11:56:42 -0700189
Chris Leechc13c8262006-05-23 17:18:44 -0700190void dma_chan_cleanup(struct kref *kref);
191
Chris Leechc13c8262006-05-23 17:18:44 -0700192/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700193 * typedef dma_filter_fn - callback filter for dma_request_channel
194 * @chan: channel to be reviewed
195 * @filter_param: opaque parameter passed through dma_request_channel
196 *
197 * When this optional parameter is specified in a call to dma_request_channel a
198 * suitable channel is passed to this routine for further dispositioning before
199 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700200 * satisfies the given capability mask. It returns 'true' to indicate that the
201 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700202 */
Dan Williams7dd60252009-01-06 11:38:19 -0700203typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700204
Dan Williams7405f742007-01-02 11:10:43 -0700205typedef void (*dma_async_tx_callback)(void *dma_async_param);
206/**
207 * struct dma_async_tx_descriptor - async transaction descriptor
208 * ---dma generic offload fields---
209 * @cookie: tracking cookie for this transaction, set to -EBUSY if
210 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700211 * @flags: flags to augment operation preparation, control completion, and
212 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700213 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700214 * @chan: target channel for this operation
215 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700216 * @callback: routine to call after this operation is complete
217 * @callback_param: general parameter to pass to the callback routine
218 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700219 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700220 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700221 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700222 */
223struct dma_async_tx_descriptor {
224 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700225 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700226 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700227 struct dma_chan *chan;
228 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700229 dma_async_tx_callback callback;
230 void *callback_param;
Dan Williams19242d72008-04-17 20:17:25 -0700231 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700232 struct dma_async_tx_descriptor *parent;
233 spinlock_t lock;
234};
235
Chris Leechc13c8262006-05-23 17:18:44 -0700236/**
237 * struct dma_device - info on the entity supplying DMA services
238 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900239 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700240 * @channels: the list of struct dma_chan
241 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700242 * @cap_mask: one or more dma_capability flags
243 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700244 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700245 * @copy_align: alignment shift for memcpy operations
246 * @xor_align: alignment shift for xor operations
247 * @pq_align: alignment shift for pq operations
248 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700249 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700250 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700251 * @device_alloc_chan_resources: allocate resources and return the
252 * number of allocated descriptors
253 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700254 * @device_prep_dma_memcpy: prepares a memcpy operation
255 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700256 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700257 * @device_prep_dma_pq: prepares a pq operation
258 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700259 * @device_prep_dma_memset: prepares a memset operation
260 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700261 * @device_prep_slave_sg: prepares a slave dma operation
262 * @device_terminate_all: terminate all pending operations
Johannes Weiner1d93e522009-02-11 08:47:19 -0700263 * @device_is_tx_complete: poll for transaction completion
Dan Williams7405f742007-01-02 11:10:43 -0700264 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700265 */
266struct dma_device {
267
268 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900269 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700270 struct list_head channels;
271 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700272 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700273 unsigned short max_xor;
274 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700275 u8 copy_align;
276 u8 xor_align;
277 u8 pq_align;
278 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700279 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700280
Chris Leechc13c8262006-05-23 17:18:44 -0700281 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700282 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700283
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700284 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700285 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700286
287 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700288 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700289 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700290 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700291 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700292 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700293 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700294 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700295 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700296 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
297 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
298 unsigned int src_cnt, const unsigned char *scf,
299 size_t len, unsigned long flags);
300 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
301 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
302 unsigned int src_cnt, const unsigned char *scf, size_t len,
303 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700304 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700305 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700306 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700307 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700308 struct dma_chan *chan, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700309
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700310 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
311 struct dma_chan *chan, struct scatterlist *sgl,
312 unsigned int sg_len, enum dma_data_direction direction,
313 unsigned long flags);
314 void (*device_terminate_all)(struct dma_chan *chan);
315
Dan Williams7405f742007-01-02 11:10:43 -0700316 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700317 dma_cookie_t cookie, dma_cookie_t *last,
318 dma_cookie_t *used);
Dan Williams7405f742007-01-02 11:10:43 -0700319 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700320};
321
Dan Williams83544ae2009-09-08 17:42:53 -0700322static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
323{
324 size_t mask;
325
326 if (!align)
327 return true;
328 mask = (1 << align) - 1;
329 if (mask & (off1 | off2 | len))
330 return false;
331 return true;
332}
333
334static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
335 size_t off2, size_t len)
336{
337 return dmaengine_check_align(dev->copy_align, off1, off2, len);
338}
339
340static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
341 size_t off2, size_t len)
342{
343 return dmaengine_check_align(dev->xor_align, off1, off2, len);
344}
345
346static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
347 size_t off2, size_t len)
348{
349 return dmaengine_check_align(dev->pq_align, off1, off2, len);
350}
351
352static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
353 size_t off2, size_t len)
354{
355 return dmaengine_check_align(dev->fill_align, off1, off2, len);
356}
357
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700358static inline void
359dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
360{
361 dma->max_pq = maxpq;
362 if (has_pq_continue)
363 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
364}
365
366static inline bool dmaf_continue(enum dma_ctrl_flags flags)
367{
368 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
369}
370
371static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
372{
373 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
374
375 return (flags & mask) == mask;
376}
377
378static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
379{
380 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
381}
382
383static unsigned short dma_dev_to_maxpq(struct dma_device *dma)
384{
385 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
386}
387
388/* dma_maxpq - reduce maxpq in the face of continued operations
389 * @dma - dma device with PQ capability
390 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
391 *
392 * When an engine does not support native continuation we need 3 extra
393 * source slots to reuse P and Q with the following coefficients:
394 * 1/ {00} * P : remove P from Q', but use it as a source for P'
395 * 2/ {01} * Q : use Q to continue Q' calculation
396 * 3/ {00} * Q : subtract Q from P' to cancel (2)
397 *
398 * In the case where P is disabled we only need 1 extra source:
399 * 1/ {01} * Q : use Q to continue Q' calculation
400 */
401static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
402{
403 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
404 return dma_dev_to_maxpq(dma);
405 else if (dmaf_p_disabled_continue(flags))
406 return dma_dev_to_maxpq(dma) - 1;
407 else if (dmaf_continue(flags))
408 return dma_dev_to_maxpq(dma) - 3;
409 BUG();
410}
411
Chris Leechc13c8262006-05-23 17:18:44 -0700412/* --- public DMA engine API --- */
413
Dan Williams649274d2009-01-11 00:20:39 -0800414#ifdef CONFIG_DMA_ENGINE
Dan Williams209b84a2009-01-06 11:38:17 -0700415void dmaengine_get(void);
416void dmaengine_put(void);
Dan Williams649274d2009-01-11 00:20:39 -0800417#else
418static inline void dmaengine_get(void)
419{
420}
421static inline void dmaengine_put(void)
422{
423}
424#endif
425
David S. Millerb4bd07c2009-02-06 22:06:43 -0800426#ifdef CONFIG_NET_DMA
427#define net_dmaengine_get() dmaengine_get()
428#define net_dmaengine_put() dmaengine_put()
429#else
430static inline void net_dmaengine_get(void)
431{
432}
433static inline void net_dmaengine_put(void)
434{
435}
436#endif
437
Dan Williams729b5d12009-03-25 09:13:25 -0700438#ifdef CONFIG_ASYNC_TX_DMA
439#define async_dmaengine_get() dmaengine_get()
440#define async_dmaengine_put() dmaengine_put()
Dan Williams138f4c32009-09-08 17:42:51 -0700441#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
442#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
443#else
Dan Williams729b5d12009-03-25 09:13:25 -0700444#define async_dma_find_channel(type) dma_find_channel(type)
Dan Williams138f4c32009-09-08 17:42:51 -0700445#endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
Dan Williams729b5d12009-03-25 09:13:25 -0700446#else
447static inline void async_dmaengine_get(void)
448{
449}
450static inline void async_dmaengine_put(void)
451{
452}
453static inline struct dma_chan *
454async_dma_find_channel(enum dma_transaction_type type)
455{
456 return NULL;
457}
Dan Williams138f4c32009-09-08 17:42:51 -0700458#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams729b5d12009-03-25 09:13:25 -0700459
Dan Williams7405f742007-01-02 11:10:43 -0700460dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
461 void *dest, void *src, size_t len);
462dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
463 struct page *page, unsigned int offset, void *kdata, size_t len);
464dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700465 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700466 unsigned int src_off, size_t len);
467void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
468 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700469
Dan Williams08398752008-07-17 17:59:56 -0700470static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700471{
Dan Williams636bdea2008-04-17 20:17:26 -0700472 tx->flags |= DMA_CTRL_ACK;
473}
474
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700475static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
476{
477 tx->flags &= ~DMA_CTRL_ACK;
478}
479
Dan Williams08398752008-07-17 17:59:56 -0700480static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700481{
Dan Williams08398752008-07-17 17:59:56 -0700482 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700483}
484
Dan Williams7405f742007-01-02 11:10:43 -0700485#define first_dma_cap(mask) __first_dma_cap(&(mask))
486static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
487{
488 return min_t(int, DMA_TX_TYPE_END,
489 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
490}
491
492#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
493static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
494{
495 return min_t(int, DMA_TX_TYPE_END,
496 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
497}
498
499#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
500static inline void
501__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
502{
503 set_bit(tx_type, dstp->bits);
504}
505
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900506#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
507static inline void
508__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
509{
510 clear_bit(tx_type, dstp->bits);
511}
512
Dan Williams33df8ca2009-01-06 11:38:15 -0700513#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
514static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
515{
516 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
517}
518
Dan Williams7405f742007-01-02 11:10:43 -0700519#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
520static inline int
521__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
522{
523 return test_bit(tx_type, srcp->bits);
524}
525
526#define for_each_dma_cap_mask(cap, mask) \
527 for ((cap) = first_dma_cap(mask); \
528 (cap) < DMA_TX_TYPE_END; \
529 (cap) = next_dma_cap((cap), (mask)))
530
Chris Leechc13c8262006-05-23 17:18:44 -0700531/**
Dan Williams7405f742007-01-02 11:10:43 -0700532 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700533 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700534 *
535 * This allows drivers to push copies to HW in batches,
536 * reducing MMIO writes where possible.
537 */
Dan Williams7405f742007-01-02 11:10:43 -0700538static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700539{
Dan Williamsec8670f2008-03-01 07:51:29 -0700540 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700541}
542
Dan Williams7405f742007-01-02 11:10:43 -0700543#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
544
Chris Leechc13c8262006-05-23 17:18:44 -0700545/**
Dan Williams7405f742007-01-02 11:10:43 -0700546 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700547 * @chan: DMA channel
548 * @cookie: transaction identifier to check status of
549 * @last: returns last completed cookie, can be NULL
550 * @used: returns last issued cookie, can be NULL
551 *
552 * If @last and @used are passed in, upon return they reflect the driver
553 * internal state and can be used with dma_async_is_complete() to check
554 * the status of multiple cookies without re-checking hardware state.
555 */
Dan Williams7405f742007-01-02 11:10:43 -0700556static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700557 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
558{
Dan Williams7405f742007-01-02 11:10:43 -0700559 return chan->device->device_is_tx_complete(chan, cookie, last, used);
Chris Leechc13c8262006-05-23 17:18:44 -0700560}
561
Dan Williams7405f742007-01-02 11:10:43 -0700562#define dma_async_memcpy_complete(chan, cookie, last, used)\
563 dma_async_is_tx_complete(chan, cookie, last, used)
564
Chris Leechc13c8262006-05-23 17:18:44 -0700565/**
566 * dma_async_is_complete - test a cookie against chan state
567 * @cookie: transaction identifier to test status of
568 * @last_complete: last know completed transaction
569 * @last_used: last cookie value handed out
570 *
571 * dma_async_is_complete() is used in dma_async_memcpy_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000572 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700573 */
574static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
575 dma_cookie_t last_complete, dma_cookie_t last_used)
576{
577 if (last_complete <= last_used) {
578 if ((cookie <= last_complete) || (cookie > last_used))
579 return DMA_SUCCESS;
580 } else {
581 if ((cookie <= last_complete) && (cookie > last_used))
582 return DMA_SUCCESS;
583 }
584 return DMA_IN_PROGRESS;
585}
586
Dan Williams7405f742007-01-02 11:10:43 -0700587enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -0700588#ifdef CONFIG_DMA_ENGINE
589enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
Dan Williamsc50331e2009-01-19 15:33:14 -0700590void dma_issue_pending_all(void);
Dan Williams07f22112009-01-05 17:14:31 -0700591#else
592static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
593{
594 return DMA_SUCCESS;
595}
Dan Williamsc50331e2009-01-19 15:33:14 -0700596static inline void dma_issue_pending_all(void)
597{
598 do { } while (0);
599}
Dan Williams07f22112009-01-05 17:14:31 -0700600#endif
Chris Leechc13c8262006-05-23 17:18:44 -0700601
602/* --- DMA device --- */
603
604int dma_async_device_register(struct dma_device *device);
605void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -0700606void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Dan Williamsbec08512009-01-06 11:38:14 -0700607struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dan Williams59b5ec22009-01-06 11:38:15 -0700608#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
609struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
610void dma_release_channel(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700611
Chris Leechde5506e2006-05-23 17:50:37 -0700612/* --- Helper iov-locking functions --- */
613
614struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +0000615 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -0700616 int nr_pages;
617 struct page **pages;
618};
619
620struct dma_pinned_list {
621 int nr_iovecs;
622 struct dma_page_list page_list[0];
623};
624
625struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
626void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
627
628dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
629 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
630dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
631 struct dma_pinned_list *pinned_list, struct page *page,
632 unsigned int offset, size_t len);
633
Chris Leechc13c8262006-05-23 17:18:44 -0700634#endif /* DMAENGINE_H */