Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | * |
| 3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver |
Jesse Brandeburg | af1a2a9 | 2014-02-13 03:48:41 -0800 | [diff] [blame] | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
Jesse Brandeburg | b831607 | 2014-04-05 07:46:11 +0000 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | * |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | * |
| 21 | * Contact Information: |
| 22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 24 | * |
| 25 | ******************************************************************************/ |
| 26 | |
| 27 | #ifndef _I40E_TYPE_H_ |
| 28 | #define _I40E_TYPE_H_ |
| 29 | |
| 30 | #include "i40e_status.h" |
| 31 | #include "i40e_osdep.h" |
| 32 | #include "i40e_register.h" |
| 33 | #include "i40e_adminq.h" |
| 34 | #include "i40e_hmc.h" |
| 35 | #include "i40e_lan_hmc.h" |
| 36 | |
| 37 | /* Device IDs */ |
Jesse Brandeburg | 704599e | 2014-05-10 04:49:14 +0000 | [diff] [blame] | 38 | #define I40E_DEV_ID_SFP_XL710 0x1572 |
Shannon Nelson | ab60085 | 2014-01-17 15:36:39 -0800 | [diff] [blame] | 39 | #define I40E_DEV_ID_QEMU 0x1574 |
| 40 | #define I40E_DEV_ID_KX_A 0x157F |
| 41 | #define I40E_DEV_ID_KX_B 0x1580 |
| 42 | #define I40E_DEV_ID_KX_C 0x1581 |
Shannon Nelson | ab60085 | 2014-01-17 15:36:39 -0800 | [diff] [blame] | 43 | #define I40E_DEV_ID_QSFP_A 0x1583 |
| 44 | #define I40E_DEV_ID_QSFP_B 0x1584 |
| 45 | #define I40E_DEV_ID_QSFP_C 0x1585 |
Paul M Stillwell Jr | 1ac1e76 | 2014-10-17 03:14:44 +0000 | [diff] [blame] | 46 | #define I40E_DEV_ID_10G_BASE_T 0x1586 |
Shannon Nelson | ab60085 | 2014-01-17 15:36:39 -0800 | [diff] [blame] | 47 | #define I40E_DEV_ID_VF 0x154C |
| 48 | #define I40E_DEV_ID_VF_HV 0x1571 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 49 | |
Shannon Nelson | ab60085 | 2014-01-17 15:36:39 -0800 | [diff] [blame] | 50 | #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \ |
| 51 | (d) == I40E_DEV_ID_QSFP_B || \ |
| 52 | (d) == I40E_DEV_ID_QSFP_C) |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 53 | |
Anjali Singhai Jain | 4c33f83 | 2014-06-05 00:18:21 +0000 | [diff] [blame] | 54 | /* I40E_MASK is a macro used on 32 bit registers */ |
| 55 | #define I40E_MASK(mask, shift) (mask << shift) |
| 56 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 57 | #define I40E_MAX_VSI_QP 16 |
| 58 | #define I40E_MAX_VF_VSI 3 |
| 59 | #define I40E_MAX_CHAINED_RX_BUFFERS 5 |
| 60 | #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 |
| 61 | |
| 62 | /* Max default timeout in ms, */ |
| 63 | #define I40E_MAX_NVM_TIMEOUT 18000 |
| 64 | |
Kamil Krawczyk | 4f4e17b | 2014-04-23 04:50:14 +0000 | [diff] [blame] | 65 | /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ |
| 66 | #define I40E_MS_TO_GTIME(time) ((time) * 1000) |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 67 | |
| 68 | /* forward declaration */ |
| 69 | struct i40e_hw; |
| 70 | typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); |
| 71 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 72 | /* Data type manipulation macros. */ |
| 73 | |
| 74 | #define I40E_DESC_UNUSED(R) \ |
| 75 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ |
| 76 | (R)->next_to_clean - (R)->next_to_use - 1) |
| 77 | |
| 78 | /* bitfields for Tx queue mapping in QTX_CTL */ |
| 79 | #define I40E_QTX_CTL_VF_QUEUE 0x0 |
| 80 | #define I40E_QTX_CTL_VM_QUEUE 0x1 |
| 81 | #define I40E_QTX_CTL_PF_QUEUE 0x2 |
| 82 | |
| 83 | /* debug masks - set these bits in hw->debug_mask to control output */ |
| 84 | enum i40e_debug_mask { |
| 85 | I40E_DEBUG_INIT = 0x00000001, |
| 86 | I40E_DEBUG_RELEASE = 0x00000002, |
| 87 | |
| 88 | I40E_DEBUG_LINK = 0x00000010, |
| 89 | I40E_DEBUG_PHY = 0x00000020, |
| 90 | I40E_DEBUG_HMC = 0x00000040, |
| 91 | I40E_DEBUG_NVM = 0x00000080, |
| 92 | I40E_DEBUG_LAN = 0x00000100, |
| 93 | I40E_DEBUG_FLOW = 0x00000200, |
| 94 | I40E_DEBUG_DCB = 0x00000400, |
| 95 | I40E_DEBUG_DIAG = 0x00000800, |
Anjali Singhai Jain | c2e1b59 | 2014-03-06 09:00:03 +0000 | [diff] [blame] | 96 | I40E_DEBUG_FD = 0x00001000, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 97 | |
| 98 | I40E_DEBUG_AQ_MESSAGE = 0x01000000, |
| 99 | I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, |
| 100 | I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, |
| 101 | I40E_DEBUG_AQ_COMMAND = 0x06000000, |
| 102 | I40E_DEBUG_AQ = 0x0F000000, |
| 103 | |
| 104 | I40E_DEBUG_USER = 0xF0000000, |
| 105 | |
| 106 | I40E_DEBUG_ALL = 0xFFFFFFFF |
| 107 | }; |
| 108 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 109 | /* These are structs for managing the hardware information and the operations. |
| 110 | * The structures of function pointers are filled out at init time when we |
| 111 | * know for sure exactly which hardware we're working with. This gives us the |
| 112 | * flexibility of using the same main driver code but adapting to slightly |
| 113 | * different hardware needs as new parts are developed. For this architecture, |
| 114 | * the Firmware and AdminQ are intended to insulate the driver from most of the |
| 115 | * future changes, but these structures will also do part of the job. |
| 116 | */ |
| 117 | enum i40e_mac_type { |
| 118 | I40E_MAC_UNKNOWN = 0, |
| 119 | I40E_MAC_X710, |
| 120 | I40E_MAC_XL710, |
| 121 | I40E_MAC_VF, |
| 122 | I40E_MAC_GENERIC, |
| 123 | }; |
| 124 | |
| 125 | enum i40e_media_type { |
| 126 | I40E_MEDIA_TYPE_UNKNOWN = 0, |
| 127 | I40E_MEDIA_TYPE_FIBER, |
| 128 | I40E_MEDIA_TYPE_BASET, |
| 129 | I40E_MEDIA_TYPE_BACKPLANE, |
| 130 | I40E_MEDIA_TYPE_CX4, |
| 131 | I40E_MEDIA_TYPE_DA, |
| 132 | I40E_MEDIA_TYPE_VIRTUAL |
| 133 | }; |
| 134 | |
| 135 | enum i40e_fc_mode { |
| 136 | I40E_FC_NONE = 0, |
| 137 | I40E_FC_RX_PAUSE, |
| 138 | I40E_FC_TX_PAUSE, |
| 139 | I40E_FC_FULL, |
| 140 | I40E_FC_PFC, |
| 141 | I40E_FC_DEFAULT |
| 142 | }; |
| 143 | |
Catherine Sullivan | c56999f | 2014-06-04 08:45:26 +0000 | [diff] [blame] | 144 | enum i40e_set_fc_aq_failures { |
| 145 | I40E_SET_FC_AQ_FAIL_NONE = 0, |
| 146 | I40E_SET_FC_AQ_FAIL_GET = 1, |
| 147 | I40E_SET_FC_AQ_FAIL_SET = 2, |
| 148 | I40E_SET_FC_AQ_FAIL_UPDATE = 4, |
| 149 | I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 |
| 150 | }; |
| 151 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 152 | enum i40e_vsi_type { |
| 153 | I40E_VSI_MAIN = 0, |
| 154 | I40E_VSI_VMDQ1, |
| 155 | I40E_VSI_VMDQ2, |
| 156 | I40E_VSI_CTRL, |
| 157 | I40E_VSI_FCOE, |
| 158 | I40E_VSI_MIRROR, |
| 159 | I40E_VSI_SRIOV, |
| 160 | I40E_VSI_FDIR, |
| 161 | I40E_VSI_TYPE_UNKNOWN |
| 162 | }; |
| 163 | |
| 164 | enum i40e_queue_type { |
| 165 | I40E_QUEUE_TYPE_RX = 0, |
| 166 | I40E_QUEUE_TYPE_TX, |
| 167 | I40E_QUEUE_TYPE_PE_CEQ, |
| 168 | I40E_QUEUE_TYPE_UNKNOWN |
| 169 | }; |
| 170 | |
| 171 | struct i40e_link_status { |
| 172 | enum i40e_aq_phy_type phy_type; |
| 173 | enum i40e_aq_link_speed link_speed; |
| 174 | u8 link_info; |
| 175 | u8 an_info; |
| 176 | u8 ext_info; |
| 177 | u8 loopback; |
Catherine Sullivan | 8109e12 | 2014-06-04 08:45:24 +0000 | [diff] [blame] | 178 | bool an_enabled; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 179 | /* is Link Status Event notification to SW enabled */ |
| 180 | bool lse_enable; |
Neerav Parikh | 6bb3f23 | 2014-04-01 07:11:56 +0000 | [diff] [blame] | 181 | u16 max_frame_size; |
| 182 | bool crc_enable; |
| 183 | u8 pacing; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 184 | }; |
| 185 | |
| 186 | struct i40e_phy_info { |
| 187 | struct i40e_link_status link_info; |
| 188 | struct i40e_link_status link_info_old; |
| 189 | u32 autoneg_advertised; |
| 190 | u32 phy_id; |
| 191 | u32 module_type; |
| 192 | bool get_link_info; |
| 193 | enum i40e_media_type media_type; |
| 194 | }; |
| 195 | |
| 196 | #define I40E_HW_CAP_MAX_GPIO 30 |
| 197 | /* Capabilities of a PF or a VF or the whole device */ |
| 198 | struct i40e_hw_capabilities { |
| 199 | u32 switch_mode; |
| 200 | #define I40E_NVM_IMAGE_TYPE_EVB 0x0 |
| 201 | #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 |
| 202 | #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 |
| 203 | |
| 204 | u32 management_mode; |
| 205 | u32 npar_enable; |
| 206 | u32 os2bmc; |
| 207 | u32 valid_functions; |
| 208 | bool sr_iov_1_1; |
| 209 | bool vmdq; |
| 210 | bool evb_802_1_qbg; /* Edge Virtual Bridging */ |
| 211 | bool evb_802_1_qbh; /* Bridge Port Extension */ |
| 212 | bool dcb; |
| 213 | bool fcoe; |
| 214 | bool mfp_mode_1; |
| 215 | bool mgmt_cem; |
| 216 | bool ieee_1588; |
| 217 | bool iwarp; |
| 218 | bool fd; |
| 219 | u32 fd_filters_guaranteed; |
| 220 | u32 fd_filters_best_effort; |
| 221 | bool rss; |
| 222 | u32 rss_table_size; |
| 223 | u32 rss_table_entry_width; |
| 224 | bool led[I40E_HW_CAP_MAX_GPIO]; |
| 225 | bool sdp[I40E_HW_CAP_MAX_GPIO]; |
| 226 | u32 nvm_image_type; |
| 227 | u32 num_flow_director_filters; |
| 228 | u32 num_vfs; |
| 229 | u32 vf_base_id; |
| 230 | u32 num_vsis; |
| 231 | u32 num_rx_qp; |
| 232 | u32 num_tx_qp; |
| 233 | u32 base_queue; |
| 234 | u32 num_msix_vectors; |
| 235 | u32 num_msix_vectors_vf; |
| 236 | u32 led_pin_num; |
| 237 | u32 sdp_pin_num; |
| 238 | u32 mdio_port_num; |
| 239 | u32 mdio_port_mode; |
| 240 | u8 rx_buf_chain_len; |
| 241 | u32 enabled_tcmap; |
| 242 | u32 maxtc; |
| 243 | }; |
| 244 | |
| 245 | struct i40e_mac_info { |
| 246 | enum i40e_mac_type type; |
| 247 | u8 addr[ETH_ALEN]; |
| 248 | u8 perm_addr[ETH_ALEN]; |
| 249 | u8 san_addr[ETH_ALEN]; |
| 250 | u16 max_fcoeq; |
| 251 | }; |
| 252 | |
| 253 | enum i40e_aq_resources_ids { |
| 254 | I40E_NVM_RESOURCE_ID = 1 |
| 255 | }; |
| 256 | |
| 257 | enum i40e_aq_resource_access_type { |
| 258 | I40E_RESOURCE_READ = 1, |
| 259 | I40E_RESOURCE_WRITE |
| 260 | }; |
| 261 | |
| 262 | struct i40e_nvm_info { |
| 263 | u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */ |
| 264 | u64 hw_semaphore_wait; /* - || - */ |
| 265 | u32 timeout; /* [ms] */ |
| 266 | u16 sr_size; /* Shadow RAM size in words */ |
| 267 | bool blank_nvm_mode; /* is NVM empty (no FW present)*/ |
| 268 | u16 version; /* NVM package version */ |
| 269 | u32 eetrack; /* NVM data version */ |
| 270 | }; |
| 271 | |
Shannon Nelson | cd552cb | 2014-07-09 07:46:09 +0000 | [diff] [blame] | 272 | /* definitions used in NVM update support */ |
| 273 | |
| 274 | enum i40e_nvmupd_cmd { |
| 275 | I40E_NVMUPD_INVALID, |
| 276 | I40E_NVMUPD_READ_CON, |
| 277 | I40E_NVMUPD_READ_SNT, |
| 278 | I40E_NVMUPD_READ_LCB, |
| 279 | I40E_NVMUPD_READ_SA, |
| 280 | I40E_NVMUPD_WRITE_ERA, |
| 281 | I40E_NVMUPD_WRITE_CON, |
| 282 | I40E_NVMUPD_WRITE_SNT, |
| 283 | I40E_NVMUPD_WRITE_LCB, |
| 284 | I40E_NVMUPD_WRITE_SA, |
| 285 | I40E_NVMUPD_CSUM_CON, |
| 286 | I40E_NVMUPD_CSUM_SA, |
| 287 | I40E_NVMUPD_CSUM_LCB, |
| 288 | }; |
| 289 | |
| 290 | enum i40e_nvmupd_state { |
| 291 | I40E_NVMUPD_STATE_INIT, |
| 292 | I40E_NVMUPD_STATE_READING, |
| 293 | I40E_NVMUPD_STATE_WRITING |
| 294 | }; |
| 295 | |
| 296 | /* nvm_access definition and its masks/shifts need to be accessible to |
| 297 | * application, core driver, and shared code. Where is the right file? |
| 298 | */ |
| 299 | #define I40E_NVM_READ 0xB |
| 300 | #define I40E_NVM_WRITE 0xC |
| 301 | |
| 302 | #define I40E_NVM_MOD_PNT_MASK 0xFF |
| 303 | |
| 304 | #define I40E_NVM_TRANS_SHIFT 8 |
| 305 | #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) |
| 306 | #define I40E_NVM_CON 0x0 |
| 307 | #define I40E_NVM_SNT 0x1 |
| 308 | #define I40E_NVM_LCB 0x2 |
| 309 | #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) |
| 310 | #define I40E_NVM_ERA 0x4 |
| 311 | #define I40E_NVM_CSUM 0x8 |
| 312 | |
| 313 | #define I40E_NVM_ADAPT_SHIFT 16 |
| 314 | #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT) |
| 315 | |
| 316 | #define I40E_NVMUPD_MAX_DATA 4096 |
| 317 | #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ |
| 318 | |
| 319 | struct i40e_nvm_access { |
| 320 | u32 command; |
| 321 | u32 config; |
| 322 | u32 offset; /* in bytes */ |
| 323 | u32 data_size; /* in bytes */ |
| 324 | u8 data[1]; |
| 325 | }; |
| 326 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 327 | /* PCI bus types */ |
| 328 | enum i40e_bus_type { |
| 329 | i40e_bus_type_unknown = 0, |
| 330 | i40e_bus_type_pci, |
| 331 | i40e_bus_type_pcix, |
| 332 | i40e_bus_type_pci_express, |
| 333 | i40e_bus_type_reserved |
| 334 | }; |
| 335 | |
| 336 | /* PCI bus speeds */ |
| 337 | enum i40e_bus_speed { |
| 338 | i40e_bus_speed_unknown = 0, |
| 339 | i40e_bus_speed_33 = 33, |
| 340 | i40e_bus_speed_66 = 66, |
| 341 | i40e_bus_speed_100 = 100, |
| 342 | i40e_bus_speed_120 = 120, |
| 343 | i40e_bus_speed_133 = 133, |
| 344 | i40e_bus_speed_2500 = 2500, |
| 345 | i40e_bus_speed_5000 = 5000, |
| 346 | i40e_bus_speed_8000 = 8000, |
| 347 | i40e_bus_speed_reserved |
| 348 | }; |
| 349 | |
| 350 | /* PCI bus widths */ |
| 351 | enum i40e_bus_width { |
| 352 | i40e_bus_width_unknown = 0, |
| 353 | i40e_bus_width_pcie_x1 = 1, |
| 354 | i40e_bus_width_pcie_x2 = 2, |
| 355 | i40e_bus_width_pcie_x4 = 4, |
| 356 | i40e_bus_width_pcie_x8 = 8, |
| 357 | i40e_bus_width_32 = 32, |
| 358 | i40e_bus_width_64 = 64, |
| 359 | i40e_bus_width_reserved |
| 360 | }; |
| 361 | |
| 362 | /* Bus parameters */ |
| 363 | struct i40e_bus_info { |
| 364 | enum i40e_bus_speed speed; |
| 365 | enum i40e_bus_width width; |
| 366 | enum i40e_bus_type type; |
| 367 | |
| 368 | u16 func; |
| 369 | u16 device; |
| 370 | u16 lan_id; |
| 371 | }; |
| 372 | |
| 373 | /* Flow control (FC) parameters */ |
| 374 | struct i40e_fc_info { |
| 375 | enum i40e_fc_mode current_mode; /* FC mode in effect */ |
| 376 | enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ |
| 377 | }; |
| 378 | |
| 379 | #define I40E_MAX_TRAFFIC_CLASS 8 |
| 380 | #define I40E_MAX_USER_PRIORITY 8 |
| 381 | #define I40E_DCBX_MAX_APPS 32 |
| 382 | #define I40E_LLDPDU_SIZE 1500 |
| 383 | |
| 384 | /* IEEE 802.1Qaz ETS Configuration data */ |
| 385 | struct i40e_ieee_ets_config { |
| 386 | u8 willing; |
| 387 | u8 cbs; |
| 388 | u8 maxtcs; |
| 389 | u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; |
| 390 | u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; |
| 391 | u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; |
| 392 | }; |
| 393 | |
| 394 | /* IEEE 802.1Qaz ETS Recommendation data */ |
| 395 | struct i40e_ieee_ets_recommend { |
| 396 | u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; |
| 397 | u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; |
| 398 | u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; |
| 399 | }; |
| 400 | |
| 401 | /* IEEE 802.1Qaz PFC Configuration data */ |
| 402 | struct i40e_ieee_pfc_config { |
| 403 | u8 willing; |
| 404 | u8 mbc; |
| 405 | u8 pfccap; |
| 406 | u8 pfcenable; |
| 407 | }; |
| 408 | |
| 409 | /* IEEE 802.1Qaz Application Priority data */ |
| 410 | struct i40e_ieee_app_priority_table { |
| 411 | u8 priority; |
| 412 | u8 selector; |
| 413 | u16 protocolid; |
| 414 | }; |
| 415 | |
| 416 | struct i40e_dcbx_config { |
| 417 | u32 numapps; |
| 418 | struct i40e_ieee_ets_config etscfg; |
| 419 | struct i40e_ieee_ets_recommend etsrec; |
| 420 | struct i40e_ieee_pfc_config pfc; |
| 421 | struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS]; |
| 422 | }; |
| 423 | |
| 424 | /* Port hardware description */ |
| 425 | struct i40e_hw { |
| 426 | u8 __iomem *hw_addr; |
| 427 | void *back; |
| 428 | |
| 429 | /* function pointer structs */ |
| 430 | struct i40e_phy_info phy; |
| 431 | struct i40e_mac_info mac; |
| 432 | struct i40e_bus_info bus; |
| 433 | struct i40e_nvm_info nvm; |
| 434 | struct i40e_fc_info fc; |
| 435 | |
| 436 | /* pci info */ |
| 437 | u16 device_id; |
| 438 | u16 vendor_id; |
| 439 | u16 subsystem_device_id; |
| 440 | u16 subsystem_vendor_id; |
| 441 | u8 revision_id; |
| 442 | u8 port; |
| 443 | bool adapter_stopped; |
| 444 | |
| 445 | /* capabilities for entire device and PCI func */ |
| 446 | struct i40e_hw_capabilities dev_caps; |
| 447 | struct i40e_hw_capabilities func_caps; |
| 448 | |
| 449 | /* Flow Director shared filter space */ |
| 450 | u16 fdir_shared_filter_count; |
| 451 | |
| 452 | /* device profile info */ |
| 453 | u8 pf_id; |
| 454 | u16 main_vsi_seid; |
| 455 | |
| 456 | /* Closest numa node to the device */ |
| 457 | u16 numa_node; |
| 458 | |
| 459 | /* Admin Queue info */ |
| 460 | struct i40e_adminq_info aq; |
| 461 | |
Shannon Nelson | cd552cb | 2014-07-09 07:46:09 +0000 | [diff] [blame] | 462 | /* state of nvm update process */ |
| 463 | enum i40e_nvmupd_state nvmupd_state; |
| 464 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 465 | /* HMC info */ |
| 466 | struct i40e_hmc_info hmc; /* HMC info struct */ |
| 467 | |
| 468 | /* LLDP/DCBX Status */ |
| 469 | u16 dcbx_status; |
| 470 | |
| 471 | /* DCBX info */ |
| 472 | struct i40e_dcbx_config local_dcbx_config; |
| 473 | struct i40e_dcbx_config remote_dcbx_config; |
| 474 | |
| 475 | /* debug mask */ |
| 476 | u32 debug_mask; |
| 477 | }; |
| 478 | |
Anjali Singhai Jain | e7f2e4b | 2014-11-11 20:06:58 +0000 | [diff] [blame^] | 479 | #define i40e_is_vf(_hw) ((_hw)->mac.type == I40E_MAC_VF) |
| 480 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 481 | struct i40e_driver_version { |
| 482 | u8 major_version; |
| 483 | u8 minor_version; |
| 484 | u8 build_version; |
| 485 | u8 subbuild_version; |
Shannon Nelson | d246601 | 2014-04-01 07:11:45 +0000 | [diff] [blame] | 486 | u8 driver_string[32]; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | /* RX Descriptors */ |
| 490 | union i40e_16byte_rx_desc { |
| 491 | struct { |
| 492 | __le64 pkt_addr; /* Packet buffer address */ |
| 493 | __le64 hdr_addr; /* Header buffer address */ |
| 494 | } read; |
| 495 | struct { |
| 496 | struct { |
| 497 | struct { |
| 498 | union { |
| 499 | __le16 mirroring_status; |
| 500 | __le16 fcoe_ctx_id; |
| 501 | } mirr_fcoe; |
| 502 | __le16 l2tag1; |
| 503 | } lo_dword; |
| 504 | union { |
| 505 | __le32 rss; /* RSS Hash */ |
| 506 | __le32 fd_id; /* Flow director filter id */ |
| 507 | __le32 fcoe_param; /* FCoE DDP Context id */ |
| 508 | } hi_dword; |
| 509 | } qword0; |
| 510 | struct { |
| 511 | /* ext status/error/pktype/length */ |
| 512 | __le64 status_error_len; |
| 513 | } qword1; |
| 514 | } wb; /* writeback */ |
| 515 | }; |
| 516 | |
| 517 | union i40e_32byte_rx_desc { |
| 518 | struct { |
| 519 | __le64 pkt_addr; /* Packet buffer address */ |
| 520 | __le64 hdr_addr; /* Header buffer address */ |
| 521 | /* bit 0 of hdr_buffer_addr is DD bit */ |
| 522 | __le64 rsvd1; |
| 523 | __le64 rsvd2; |
| 524 | } read; |
| 525 | struct { |
| 526 | struct { |
| 527 | struct { |
| 528 | union { |
| 529 | __le16 mirroring_status; |
| 530 | __le16 fcoe_ctx_id; |
| 531 | } mirr_fcoe; |
| 532 | __le16 l2tag1; |
| 533 | } lo_dword; |
| 534 | union { |
| 535 | __le32 rss; /* RSS Hash */ |
| 536 | __le32 fcoe_param; /* FCoE DDP Context id */ |
Anjali Singhai Jain | 77e29bc | 2014-02-11 08:24:11 +0000 | [diff] [blame] | 537 | /* Flow director filter id in case of |
| 538 | * Programming status desc WB |
| 539 | */ |
| 540 | __le32 fd_id; |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 541 | } hi_dword; |
| 542 | } qword0; |
| 543 | struct { |
| 544 | /* status/error/pktype/length */ |
| 545 | __le64 status_error_len; |
| 546 | } qword1; |
| 547 | struct { |
| 548 | __le16 ext_status; /* extended status */ |
| 549 | __le16 rsvd; |
| 550 | __le16 l2tag2_1; |
| 551 | __le16 l2tag2_2; |
| 552 | } qword2; |
| 553 | struct { |
| 554 | union { |
| 555 | __le32 flex_bytes_lo; |
| 556 | __le32 pe_status; |
| 557 | } lo_dword; |
| 558 | union { |
| 559 | __le32 flex_bytes_hi; |
| 560 | __le32 fd_id; |
| 561 | } hi_dword; |
| 562 | } qword3; |
| 563 | } wb; /* writeback */ |
| 564 | }; |
| 565 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 566 | enum i40e_rx_desc_status_bits { |
| 567 | /* Note: These are predefined bit offsets */ |
| 568 | I40E_RX_DESC_STATUS_DD_SHIFT = 0, |
| 569 | I40E_RX_DESC_STATUS_EOF_SHIFT = 1, |
| 570 | I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, |
| 571 | I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, |
| 572 | I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, |
| 573 | I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ |
| 574 | I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, |
| 575 | I40E_RX_DESC_STATUS_PIF_SHIFT = 8, |
| 576 | I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ |
| 577 | I40E_RX_DESC_STATUS_FLM_SHIFT = 11, |
| 578 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ |
| 579 | I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, |
| 580 | I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, |
| 581 | I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ |
Jesse Brandeburg | c2451d7 | 2014-05-10 04:49:01 +0000 | [diff] [blame] | 582 | I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, |
| 583 | I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 584 | }; |
| 585 | |
Jesse Brandeburg | c2451d7 | 2014-05-10 04:49:01 +0000 | [diff] [blame] | 586 | #define I40E_RXD_QW1_STATUS_SHIFT 0 |
| 587 | #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \ |
| 588 | << I40E_RXD_QW1_STATUS_SHIFT) |
| 589 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 590 | #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT |
| 591 | #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ |
| 592 | I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) |
| 593 | |
| 594 | #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT |
| 595 | #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \ |
| 596 | I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) |
| 597 | |
| 598 | enum i40e_rx_desc_fltstat_values { |
| 599 | I40E_RX_DESC_FLTSTAT_NO_DATA = 0, |
| 600 | I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ |
| 601 | I40E_RX_DESC_FLTSTAT_RSV = 2, |
| 602 | I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, |
| 603 | }; |
| 604 | |
| 605 | #define I40E_RXD_QW1_ERROR_SHIFT 19 |
| 606 | #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) |
| 607 | |
| 608 | enum i40e_rx_desc_error_bits { |
| 609 | /* Note: These are predefined bit offsets */ |
| 610 | I40E_RX_DESC_ERROR_RXE_SHIFT = 0, |
| 611 | I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, |
| 612 | I40E_RX_DESC_ERROR_HBO_SHIFT = 2, |
| 613 | I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ |
| 614 | I40E_RX_DESC_ERROR_IPE_SHIFT = 3, |
| 615 | I40E_RX_DESC_ERROR_L4E_SHIFT = 4, |
| 616 | I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, |
Jesse Brandeburg | 8a3c91c | 2014-05-20 08:01:43 +0000 | [diff] [blame] | 617 | I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, |
| 618 | I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 619 | }; |
| 620 | |
| 621 | enum i40e_rx_desc_error_l3l4e_fcoe_masks { |
| 622 | I40E_RX_DESC_ERROR_L3L4E_NONE = 0, |
| 623 | I40E_RX_DESC_ERROR_L3L4E_PROT = 1, |
| 624 | I40E_RX_DESC_ERROR_L3L4E_FC = 2, |
| 625 | I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, |
| 626 | I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 |
| 627 | }; |
| 628 | |
| 629 | #define I40E_RXD_QW1_PTYPE_SHIFT 30 |
| 630 | #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) |
| 631 | |
| 632 | /* Packet type non-ip values */ |
| 633 | enum i40e_rx_l2_ptype { |
| 634 | I40E_RX_PTYPE_L2_RESERVED = 0, |
| 635 | I40E_RX_PTYPE_L2_MAC_PAY2 = 1, |
| 636 | I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, |
| 637 | I40E_RX_PTYPE_L2_FIP_PAY2 = 3, |
| 638 | I40E_RX_PTYPE_L2_OUI_PAY2 = 4, |
| 639 | I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, |
| 640 | I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, |
| 641 | I40E_RX_PTYPE_L2_ECP_PAY2 = 7, |
| 642 | I40E_RX_PTYPE_L2_EVB_PAY2 = 8, |
| 643 | I40E_RX_PTYPE_L2_QCN_PAY2 = 9, |
| 644 | I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, |
| 645 | I40E_RX_PTYPE_L2_ARP = 11, |
| 646 | I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, |
| 647 | I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, |
| 648 | I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, |
| 649 | I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, |
| 650 | I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, |
| 651 | I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, |
| 652 | I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, |
| 653 | I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, |
| 654 | I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, |
| 655 | I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, |
| 656 | I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, |
| 657 | I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, |
| 658 | I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, |
| 659 | I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 |
| 660 | }; |
| 661 | |
| 662 | struct i40e_rx_ptype_decoded { |
| 663 | u32 ptype:8; |
| 664 | u32 known:1; |
| 665 | u32 outer_ip:1; |
| 666 | u32 outer_ip_ver:1; |
| 667 | u32 outer_frag:1; |
| 668 | u32 tunnel_type:3; |
| 669 | u32 tunnel_end_prot:2; |
| 670 | u32 tunnel_end_frag:1; |
| 671 | u32 inner_prot:4; |
| 672 | u32 payload_layer:3; |
| 673 | }; |
| 674 | |
| 675 | enum i40e_rx_ptype_outer_ip { |
| 676 | I40E_RX_PTYPE_OUTER_L2 = 0, |
| 677 | I40E_RX_PTYPE_OUTER_IP = 1 |
| 678 | }; |
| 679 | |
| 680 | enum i40e_rx_ptype_outer_ip_ver { |
| 681 | I40E_RX_PTYPE_OUTER_NONE = 0, |
| 682 | I40E_RX_PTYPE_OUTER_IPV4 = 0, |
| 683 | I40E_RX_PTYPE_OUTER_IPV6 = 1 |
| 684 | }; |
| 685 | |
| 686 | enum i40e_rx_ptype_outer_fragmented { |
| 687 | I40E_RX_PTYPE_NOT_FRAG = 0, |
| 688 | I40E_RX_PTYPE_FRAG = 1 |
| 689 | }; |
| 690 | |
| 691 | enum i40e_rx_ptype_tunnel_type { |
| 692 | I40E_RX_PTYPE_TUNNEL_NONE = 0, |
| 693 | I40E_RX_PTYPE_TUNNEL_IP_IP = 1, |
| 694 | I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, |
| 695 | I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, |
| 696 | I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, |
| 697 | }; |
| 698 | |
| 699 | enum i40e_rx_ptype_tunnel_end_prot { |
| 700 | I40E_RX_PTYPE_TUNNEL_END_NONE = 0, |
| 701 | I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, |
| 702 | I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, |
| 703 | }; |
| 704 | |
| 705 | enum i40e_rx_ptype_inner_prot { |
| 706 | I40E_RX_PTYPE_INNER_PROT_NONE = 0, |
| 707 | I40E_RX_PTYPE_INNER_PROT_UDP = 1, |
| 708 | I40E_RX_PTYPE_INNER_PROT_TCP = 2, |
| 709 | I40E_RX_PTYPE_INNER_PROT_SCTP = 3, |
| 710 | I40E_RX_PTYPE_INNER_PROT_ICMP = 4, |
| 711 | I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 |
| 712 | }; |
| 713 | |
| 714 | enum i40e_rx_ptype_payload_layer { |
| 715 | I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, |
| 716 | I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, |
| 717 | I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, |
| 718 | I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, |
| 719 | }; |
| 720 | |
| 721 | #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 |
| 722 | #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ |
| 723 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT) |
| 724 | |
| 725 | #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 |
| 726 | #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ |
| 727 | I40E_RXD_QW1_LENGTH_HBUF_SHIFT) |
| 728 | |
| 729 | #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 |
| 730 | #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \ |
| 731 | I40E_RXD_QW1_LENGTH_SPH_SHIFT) |
| 732 | |
| 733 | enum i40e_rx_desc_ext_status_bits { |
| 734 | /* Note: These are predefined bit offsets */ |
| 735 | I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, |
| 736 | I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, |
| 737 | I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ |
| 738 | I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 739 | I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, |
| 740 | I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, |
| 741 | I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, |
| 742 | }; |
| 743 | |
| 744 | enum i40e_rx_desc_pe_status_bits { |
| 745 | /* Note: These are predefined bit offsets */ |
| 746 | I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ |
| 747 | I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ |
| 748 | I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ |
| 749 | I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, |
| 750 | I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, |
| 751 | I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, |
| 752 | I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, |
| 753 | I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, |
| 754 | I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 |
| 755 | }; |
| 756 | |
| 757 | #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 |
| 758 | #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 |
| 759 | |
| 760 | #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 |
| 761 | #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ |
| 762 | I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) |
| 763 | |
| 764 | #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 |
| 765 | #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ |
| 766 | I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) |
| 767 | |
| 768 | enum i40e_rx_prog_status_desc_status_bits { |
| 769 | /* Note: These are predefined bit offsets */ |
| 770 | I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, |
| 771 | I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ |
| 772 | }; |
| 773 | |
| 774 | enum i40e_rx_prog_status_desc_prog_id_masks { |
| 775 | I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, |
| 776 | I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, |
| 777 | I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, |
| 778 | }; |
| 779 | |
| 780 | enum i40e_rx_prog_status_desc_error_bits { |
| 781 | /* Note: These are predefined bit offsets */ |
| 782 | I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, |
Anjali Singhai Jain | 77e29bc | 2014-02-11 08:24:11 +0000 | [diff] [blame] | 783 | I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 784 | I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, |
| 785 | I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 |
| 786 | }; |
| 787 | |
| 788 | /* TX Descriptor */ |
| 789 | struct i40e_tx_desc { |
| 790 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
| 791 | __le64 cmd_type_offset_bsz; |
| 792 | }; |
| 793 | |
| 794 | #define I40E_TXD_QW1_DTYPE_SHIFT 0 |
| 795 | #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) |
| 796 | |
| 797 | enum i40e_tx_desc_dtype_value { |
| 798 | I40E_TX_DESC_DTYPE_DATA = 0x0, |
| 799 | I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ |
| 800 | I40E_TX_DESC_DTYPE_CONTEXT = 0x1, |
| 801 | I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, |
| 802 | I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, |
| 803 | I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, |
| 804 | I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, |
| 805 | I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, |
| 806 | I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, |
| 807 | I40E_TX_DESC_DTYPE_DESC_DONE = 0xF |
| 808 | }; |
| 809 | |
| 810 | #define I40E_TXD_QW1_CMD_SHIFT 4 |
| 811 | #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) |
| 812 | |
| 813 | enum i40e_tx_desc_cmd_bits { |
| 814 | I40E_TX_DESC_CMD_EOP = 0x0001, |
| 815 | I40E_TX_DESC_CMD_RS = 0x0002, |
| 816 | I40E_TX_DESC_CMD_ICRC = 0x0004, |
| 817 | I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, |
| 818 | I40E_TX_DESC_CMD_DUMMY = 0x0010, |
| 819 | I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ |
| 820 | I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ |
| 821 | I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ |
| 822 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ |
| 823 | I40E_TX_DESC_CMD_FCOET = 0x0080, |
| 824 | I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ |
| 825 | I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ |
| 826 | I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ |
| 827 | I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ |
| 828 | I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ |
| 829 | I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ |
| 830 | I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ |
| 831 | I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ |
| 832 | }; |
| 833 | |
| 834 | #define I40E_TXD_QW1_OFFSET_SHIFT 16 |
| 835 | #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ |
| 836 | I40E_TXD_QW1_OFFSET_SHIFT) |
| 837 | |
| 838 | enum i40e_tx_desc_length_fields { |
| 839 | /* Note: These are predefined bit offsets */ |
| 840 | I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ |
| 841 | I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ |
| 842 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ |
| 843 | }; |
| 844 | |
| 845 | #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 |
| 846 | #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ |
| 847 | I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
| 848 | |
| 849 | #define I40E_TXD_QW1_L2TAG1_SHIFT 48 |
| 850 | #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) |
| 851 | |
| 852 | /* Context descriptors */ |
| 853 | struct i40e_tx_context_desc { |
| 854 | __le32 tunneling_params; |
| 855 | __le16 l2tag2; |
| 856 | __le16 rsvd; |
| 857 | __le64 type_cmd_tso_mss; |
| 858 | }; |
| 859 | |
| 860 | #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 |
| 861 | #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) |
| 862 | |
| 863 | #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 |
| 864 | #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) |
| 865 | |
| 866 | enum i40e_tx_ctx_desc_cmd_bits { |
| 867 | I40E_TX_CTX_DESC_TSO = 0x01, |
| 868 | I40E_TX_CTX_DESC_TSYN = 0x02, |
| 869 | I40E_TX_CTX_DESC_IL2TAG2 = 0x04, |
| 870 | I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, |
| 871 | I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, |
| 872 | I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, |
| 873 | I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, |
| 874 | I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, |
| 875 | I40E_TX_CTX_DESC_SWPE = 0x40 |
| 876 | }; |
| 877 | |
| 878 | #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 |
| 879 | #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ |
| 880 | I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
| 881 | |
| 882 | #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 |
| 883 | #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ |
| 884 | I40E_TXD_CTX_QW1_MSS_SHIFT) |
| 885 | |
| 886 | #define I40E_TXD_CTX_QW1_VSI_SHIFT 50 |
| 887 | #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) |
| 888 | |
| 889 | #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 |
| 890 | #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ |
| 891 | I40E_TXD_CTX_QW0_EXT_IP_SHIFT) |
| 892 | |
| 893 | enum i40e_tx_ctx_desc_eipt_offload { |
| 894 | I40E_TX_CTX_EXT_IP_NONE = 0x0, |
| 895 | I40E_TX_CTX_EXT_IP_IPV6 = 0x1, |
| 896 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, |
| 897 | I40E_TX_CTX_EXT_IP_IPV4 = 0x3 |
| 898 | }; |
| 899 | |
| 900 | #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 |
| 901 | #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ |
| 902 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) |
| 903 | |
| 904 | #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 |
| 905 | #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) |
| 906 | |
| 907 | #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) |
| 908 | #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) |
| 909 | |
| 910 | #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 |
| 911 | #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \ |
| 912 | I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) |
| 913 | |
| 914 | #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK |
| 915 | |
| 916 | #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 |
| 917 | #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ |
| 918 | I40E_TXD_CTX_QW0_NATLEN_SHIFT) |
| 919 | |
| 920 | #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 |
| 921 | #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ |
| 922 | I40E_TXD_CTX_QW0_DECTTL_SHIFT) |
| 923 | |
| 924 | struct i40e_filter_program_desc { |
| 925 | __le32 qindex_flex_ptype_vsi; |
| 926 | __le32 rsvd; |
| 927 | __le32 dtype_cmd_cntindex; |
| 928 | __le32 fd_id; |
| 929 | }; |
| 930 | #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 |
| 931 | #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ |
| 932 | I40E_TXD_FLTR_QW0_QINDEX_SHIFT) |
| 933 | #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 |
| 934 | #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ |
| 935 | I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) |
| 936 | #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 |
| 937 | #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ |
| 938 | I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) |
| 939 | |
| 940 | /* Packet Classifier Types for filters */ |
| 941 | enum i40e_filter_pctype { |
Kevin Scott | b2d36c0 | 2014-04-09 05:58:59 +0000 | [diff] [blame] | 942 | /* Note: Values 0-30 are reserved for future use */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 943 | I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, |
Kevin Scott | b2d36c0 | 2014-04-09 05:58:59 +0000 | [diff] [blame] | 944 | /* Note: Value 32 is reserved for future use */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 945 | I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, |
| 946 | I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, |
| 947 | I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, |
| 948 | I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, |
Kevin Scott | b2d36c0 | 2014-04-09 05:58:59 +0000 | [diff] [blame] | 949 | /* Note: Values 37-40 are reserved for future use */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 950 | I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 951 | I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, |
| 952 | I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, |
| 953 | I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, |
| 954 | I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, |
| 955 | /* Note: Value 47 is reserved for future use */ |
| 956 | I40E_FILTER_PCTYPE_FCOE_OX = 48, |
| 957 | I40E_FILTER_PCTYPE_FCOE_RX = 49, |
| 958 | I40E_FILTER_PCTYPE_FCOE_OTHER = 50, |
| 959 | /* Note: Values 51-62 are reserved for future use */ |
| 960 | I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, |
| 961 | }; |
| 962 | |
| 963 | enum i40e_filter_program_desc_dest { |
| 964 | I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, |
| 965 | I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, |
| 966 | I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, |
| 967 | }; |
| 968 | |
| 969 | enum i40e_filter_program_desc_fd_status { |
| 970 | I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, |
| 971 | I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, |
| 972 | I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, |
| 973 | I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, |
| 974 | }; |
| 975 | |
| 976 | #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 |
| 977 | #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ |
| 978 | I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) |
| 979 | |
| 980 | #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 |
| 981 | #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ |
| 982 | I40E_TXD_FLTR_QW1_CMD_SHIFT) |
| 983 | |
| 984 | #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) |
| 985 | #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) |
| 986 | |
| 987 | enum i40e_filter_program_desc_pcmd { |
| 988 | I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, |
| 989 | I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, |
| 990 | }; |
| 991 | |
| 992 | #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) |
| 993 | #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) |
| 994 | |
| 995 | #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) |
| 996 | #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \ |
| 997 | I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) |
| 998 | |
| 999 | #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ |
| 1000 | I40E_TXD_FLTR_QW1_CMD_SHIFT) |
| 1001 | #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ |
| 1002 | I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) |
| 1003 | |
| 1004 | #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 |
| 1005 | #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ |
| 1006 | I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) |
| 1007 | |
| 1008 | enum i40e_filter_type { |
| 1009 | I40E_FLOW_DIRECTOR_FLTR = 0, |
| 1010 | I40E_PE_QUAD_HASH_FLTR = 1, |
| 1011 | I40E_ETHERTYPE_FLTR, |
| 1012 | I40E_FCOE_CTX_FLTR, |
| 1013 | I40E_MAC_VLAN_FLTR, |
| 1014 | I40E_HASH_FLTR |
| 1015 | }; |
| 1016 | |
| 1017 | struct i40e_vsi_context { |
| 1018 | u16 seid; |
| 1019 | u16 uplink_seid; |
| 1020 | u16 vsi_number; |
| 1021 | u16 vsis_allocated; |
| 1022 | u16 vsis_unallocated; |
| 1023 | u16 flags; |
| 1024 | u8 pf_num; |
| 1025 | u8 vf_num; |
| 1026 | u8 connection_type; |
| 1027 | struct i40e_aqc_vsi_properties_data info; |
| 1028 | }; |
| 1029 | |
Kamil Krawczyk | 4f4e17b | 2014-04-23 04:50:14 +0000 | [diff] [blame] | 1030 | struct i40e_veb_context { |
| 1031 | u16 seid; |
| 1032 | u16 uplink_seid; |
| 1033 | u16 veb_number; |
| 1034 | u16 vebs_allocated; |
| 1035 | u16 vebs_unallocated; |
| 1036 | u16 flags; |
| 1037 | struct i40e_aqc_get_veb_parameters_completion info; |
| 1038 | }; |
| 1039 | |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1040 | /* Statistics collected by each port, VSI, VEB, and S-channel */ |
| 1041 | struct i40e_eth_stats { |
| 1042 | u64 rx_bytes; /* gorc */ |
| 1043 | u64 rx_unicast; /* uprc */ |
| 1044 | u64 rx_multicast; /* mprc */ |
| 1045 | u64 rx_broadcast; /* bprc */ |
| 1046 | u64 rx_discards; /* rdpc */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1047 | u64 rx_unknown_protocol; /* rupp */ |
| 1048 | u64 tx_bytes; /* gotc */ |
| 1049 | u64 tx_unicast; /* uptc */ |
| 1050 | u64 tx_multicast; /* mptc */ |
| 1051 | u64 tx_broadcast; /* bptc */ |
| 1052 | u64 tx_discards; /* tdpc */ |
| 1053 | u64 tx_errors; /* tepc */ |
| 1054 | }; |
| 1055 | |
| 1056 | /* Statistics collected by the MAC */ |
| 1057 | struct i40e_hw_port_stats { |
| 1058 | /* eth stats collected by the port */ |
| 1059 | struct i40e_eth_stats eth; |
| 1060 | |
| 1061 | /* additional port specific stats */ |
| 1062 | u64 tx_dropped_link_down; /* tdold */ |
| 1063 | u64 crc_errors; /* crcerrs */ |
| 1064 | u64 illegal_bytes; /* illerrc */ |
| 1065 | u64 error_bytes; /* errbc */ |
| 1066 | u64 mac_local_faults; /* mlfc */ |
| 1067 | u64 mac_remote_faults; /* mrfc */ |
| 1068 | u64 rx_length_errors; /* rlec */ |
| 1069 | u64 link_xon_rx; /* lxonrxc */ |
| 1070 | u64 link_xoff_rx; /* lxoffrxc */ |
| 1071 | u64 priority_xon_rx[8]; /* pxonrxc[8] */ |
| 1072 | u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ |
| 1073 | u64 link_xon_tx; /* lxontxc */ |
| 1074 | u64 link_xoff_tx; /* lxofftxc */ |
| 1075 | u64 priority_xon_tx[8]; /* pxontxc[8] */ |
| 1076 | u64 priority_xoff_tx[8]; /* pxofftxc[8] */ |
| 1077 | u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ |
| 1078 | u64 rx_size_64; /* prc64 */ |
| 1079 | u64 rx_size_127; /* prc127 */ |
| 1080 | u64 rx_size_255; /* prc255 */ |
| 1081 | u64 rx_size_511; /* prc511 */ |
| 1082 | u64 rx_size_1023; /* prc1023 */ |
| 1083 | u64 rx_size_1522; /* prc1522 */ |
| 1084 | u64 rx_size_big; /* prc9522 */ |
| 1085 | u64 rx_undersize; /* ruc */ |
| 1086 | u64 rx_fragments; /* rfc */ |
| 1087 | u64 rx_oversize; /* roc */ |
| 1088 | u64 rx_jabber; /* rjc */ |
| 1089 | u64 tx_size_64; /* ptc64 */ |
| 1090 | u64 tx_size_127; /* ptc127 */ |
| 1091 | u64 tx_size_255; /* ptc255 */ |
| 1092 | u64 tx_size_511; /* ptc511 */ |
| 1093 | u64 tx_size_1023; /* ptc1023 */ |
| 1094 | u64 tx_size_1522; /* ptc1522 */ |
| 1095 | u64 tx_size_big; /* ptc9522 */ |
| 1096 | u64 mac_short_packet_dropped; /* mspdc */ |
| 1097 | u64 checksum_error; /* xec */ |
Anjali Singhai Jain | 433c47d | 2014-05-22 06:32:17 +0000 | [diff] [blame] | 1098 | /* flow director stats */ |
| 1099 | u64 fd_atr_match; |
| 1100 | u64 fd_sb_match; |
Anjali Singhai Jain | bee5af7 | 2014-03-06 08:59:50 +0000 | [diff] [blame] | 1101 | /* EEE LPI */ |
Greg Rose | 10bc478 | 2014-04-09 05:59:03 +0000 | [diff] [blame] | 1102 | u32 tx_lpi_status; |
| 1103 | u32 rx_lpi_status; |
Anjali Singhai Jain | bee5af7 | 2014-03-06 08:59:50 +0000 | [diff] [blame] | 1104 | u64 tx_lpi_count; /* etlpic */ |
| 1105 | u64 rx_lpi_count; /* erlpic */ |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1106 | }; |
| 1107 | |
| 1108 | /* Checksum and Shadow RAM pointers */ |
| 1109 | #define I40E_SR_NVM_CONTROL_WORD 0x00 |
| 1110 | #define I40E_SR_EMP_MODULE_PTR 0x0F |
| 1111 | #define I40E_SR_NVM_IMAGE_VERSION 0x18 |
| 1112 | #define I40E_SR_NVM_WAKE_ON_LAN 0x19 |
| 1113 | #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 |
| 1114 | #define I40E_SR_NVM_EETRACK_LO 0x2D |
| 1115 | #define I40E_SR_NVM_EETRACK_HI 0x2E |
| 1116 | #define I40E_SR_VPD_PTR 0x2F |
| 1117 | #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E |
| 1118 | #define I40E_SR_SW_CHECKSUM_WORD 0x3F |
| 1119 | |
| 1120 | /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ |
| 1121 | #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 |
| 1122 | #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 |
| 1123 | #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 |
| 1124 | #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) |
| 1125 | |
| 1126 | /* Shadow RAM related */ |
| 1127 | #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 |
| 1128 | #define I40E_SR_WORDS_IN_1KB 512 |
| 1129 | /* Checksum should be calculated such that after adding all the words, |
| 1130 | * including the checksum word itself, the sum should be 0xBABA. |
| 1131 | */ |
| 1132 | #define I40E_SR_SW_CHECKSUM_BASE 0xBABA |
| 1133 | |
| 1134 | #define I40E_SRRD_SRCTL_ATTEMPTS 100000 |
| 1135 | |
| 1136 | enum i40e_switch_element_types { |
| 1137 | I40E_SWITCH_ELEMENT_TYPE_MAC = 1, |
| 1138 | I40E_SWITCH_ELEMENT_TYPE_PF = 2, |
| 1139 | I40E_SWITCH_ELEMENT_TYPE_VF = 3, |
| 1140 | I40E_SWITCH_ELEMENT_TYPE_EMP = 4, |
| 1141 | I40E_SWITCH_ELEMENT_TYPE_BMC = 6, |
| 1142 | I40E_SWITCH_ELEMENT_TYPE_PE = 16, |
| 1143 | I40E_SWITCH_ELEMENT_TYPE_VEB = 17, |
| 1144 | I40E_SWITCH_ELEMENT_TYPE_PA = 18, |
| 1145 | I40E_SWITCH_ELEMENT_TYPE_VSI = 19, |
| 1146 | }; |
| 1147 | |
| 1148 | /* Supported EtherType filters */ |
| 1149 | enum i40e_ether_type_index { |
| 1150 | I40E_ETHER_TYPE_1588 = 0, |
| 1151 | I40E_ETHER_TYPE_FIP = 1, |
| 1152 | I40E_ETHER_TYPE_OUI_EXTENDED = 2, |
| 1153 | I40E_ETHER_TYPE_MAC_CONTROL = 3, |
| 1154 | I40E_ETHER_TYPE_LLDP = 4, |
| 1155 | I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, |
| 1156 | I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, |
| 1157 | I40E_ETHER_TYPE_QCN_CNM = 7, |
| 1158 | I40E_ETHER_TYPE_8021X = 8, |
| 1159 | I40E_ETHER_TYPE_ARP = 9, |
| 1160 | I40E_ETHER_TYPE_RSV1 = 10, |
| 1161 | I40E_ETHER_TYPE_RSV2 = 11, |
| 1162 | }; |
| 1163 | |
| 1164 | /* Filter context base size is 1K */ |
| 1165 | #define I40E_HASH_FILTER_BASE_SIZE 1024 |
| 1166 | /* Supported Hash filter values */ |
| 1167 | enum i40e_hash_filter_size { |
| 1168 | I40E_HASH_FILTER_SIZE_1K = 0, |
| 1169 | I40E_HASH_FILTER_SIZE_2K = 1, |
| 1170 | I40E_HASH_FILTER_SIZE_4K = 2, |
| 1171 | I40E_HASH_FILTER_SIZE_8K = 3, |
| 1172 | I40E_HASH_FILTER_SIZE_16K = 4, |
| 1173 | I40E_HASH_FILTER_SIZE_32K = 5, |
| 1174 | I40E_HASH_FILTER_SIZE_64K = 6, |
| 1175 | I40E_HASH_FILTER_SIZE_128K = 7, |
| 1176 | I40E_HASH_FILTER_SIZE_256K = 8, |
| 1177 | I40E_HASH_FILTER_SIZE_512K = 9, |
| 1178 | I40E_HASH_FILTER_SIZE_1M = 10, |
| 1179 | }; |
| 1180 | |
| 1181 | /* DMA context base size is 0.5K */ |
| 1182 | #define I40E_DMA_CNTX_BASE_SIZE 512 |
| 1183 | /* Supported DMA context values */ |
| 1184 | enum i40e_dma_cntx_size { |
| 1185 | I40E_DMA_CNTX_SIZE_512 = 0, |
| 1186 | I40E_DMA_CNTX_SIZE_1K = 1, |
| 1187 | I40E_DMA_CNTX_SIZE_2K = 2, |
| 1188 | I40E_DMA_CNTX_SIZE_4K = 3, |
| 1189 | I40E_DMA_CNTX_SIZE_8K = 4, |
| 1190 | I40E_DMA_CNTX_SIZE_16K = 5, |
| 1191 | I40E_DMA_CNTX_SIZE_32K = 6, |
| 1192 | I40E_DMA_CNTX_SIZE_64K = 7, |
| 1193 | I40E_DMA_CNTX_SIZE_128K = 8, |
| 1194 | I40E_DMA_CNTX_SIZE_256K = 9, |
| 1195 | }; |
| 1196 | |
| 1197 | /* Supported Hash look up table (LUT) sizes */ |
| 1198 | enum i40e_hash_lut_size { |
| 1199 | I40E_HASH_LUT_SIZE_128 = 0, |
| 1200 | I40E_HASH_LUT_SIZE_512 = 1, |
| 1201 | }; |
| 1202 | |
| 1203 | /* Structure to hold a per PF filter control settings */ |
| 1204 | struct i40e_filter_control_settings { |
| 1205 | /* number of PE Quad Hash filter buckets */ |
| 1206 | enum i40e_hash_filter_size pe_filt_num; |
| 1207 | /* number of PE Quad Hash contexts */ |
| 1208 | enum i40e_dma_cntx_size pe_cntx_num; |
| 1209 | /* number of FCoE filter buckets */ |
| 1210 | enum i40e_hash_filter_size fcoe_filt_num; |
| 1211 | /* number of FCoE DDP contexts */ |
| 1212 | enum i40e_dma_cntx_size fcoe_cntx_num; |
| 1213 | /* size of the Hash LUT */ |
| 1214 | enum i40e_hash_lut_size hash_lut_size; |
| 1215 | /* enable FDIR filters for PF and its VFs */ |
| 1216 | bool enable_fdir; |
| 1217 | /* enable Ethertype filters for PF and its VFs */ |
| 1218 | bool enable_ethtype; |
| 1219 | /* enable MAC/VLAN filters for PF and its VFs */ |
| 1220 | bool enable_macvlan; |
| 1221 | }; |
| 1222 | |
| 1223 | /* Structure to hold device level control filter counts */ |
| 1224 | struct i40e_control_filter_stats { |
| 1225 | u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ |
| 1226 | u16 etype_used; /* Used perfect EtherType filters */ |
| 1227 | u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ |
| 1228 | u16 etype_free; /* Un-used perfect EtherType filters */ |
| 1229 | }; |
| 1230 | |
| 1231 | enum i40e_reset_type { |
| 1232 | I40E_RESET_POR = 0, |
| 1233 | I40E_RESET_CORER = 1, |
| 1234 | I40E_RESET_GLOBR = 2, |
| 1235 | I40E_RESET_EMPR = 3, |
| 1236 | }; |
Carolyn Wyborny | e157ea3 | 2014-06-03 23:50:22 +0000 | [diff] [blame] | 1237 | |
| 1238 | /* RSS Hash Table Size */ |
| 1239 | #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 |
Greg Rose | d358aa9 | 2013-12-21 06:13:11 +0000 | [diff] [blame] | 1240 | #endif /* _I40E_TYPE_H_ */ |