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Troy Kiskya177f182013-12-16 18:13:03 -07001/*
2 * Copyright 2013 Boundary Devices, Inc.
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
Troy Kiskyda474d42013-12-18 14:51:44 -070013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
Troy Kiskya177f182013-12-16 18:13:03 -070015
16/ {
Sascha Hauer48f51962014-05-07 15:19:00 +020017 chosen {
18 stdout-path = &uart2;
19 };
20
Troy Kiskya177f182013-12-16 18:13:03 -070021 memory {
22 reg = <0x10000000 0x40000000>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 reg_2p5v: regulator@0 {
31 compatible = "regulator-fixed";
32 reg = <0>;
33 regulator-name = "2P5V";
34 regulator-min-microvolt = <2500000>;
35 regulator-max-microvolt = <2500000>;
36 regulator-always-on;
37 };
38
39 reg_3p3v: regulator@1 {
40 compatible = "regulator-fixed";
41 reg = <1>;
42 regulator-name = "3P3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-always-on;
46 };
47
48 reg_usb_otg_vbus: regulator@2 {
49 compatible = "regulator-fixed";
50 reg = <2>;
51 regulator-name = "usb_otg_vbus";
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
54 gpio = <&gpio3 22 0>;
55 enable-active-high;
56 };
Peter Seiderer3e223392015-06-02 21:07:16 +020057
58 reg_can_xcvr: regulator@3 {
59 compatible = "regulator-fixed";
60 reg = <3>;
61 regulator-name = "CAN XCVR";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_can_xcvr>;
66 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
67 };
Gary Bissonf12fb7a2015-09-30 15:46:39 +020068
69 reg_wlan_vmmc: regulator@4 {
70 compatible = "regulator-fixed";
71 reg = <4>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_wlan_vmmc>;
74 regulator-name = "reg_wlan_vmmc";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
77 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
78 startup-delay-us = <70000>;
79 enable-active-high;
80 };
Troy Kiskya177f182013-12-16 18:13:03 -070081 };
82
Troy Kiskyda474d42013-12-18 14:51:44 -070083 gpio-keys {
84 compatible = "gpio-keys";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_gpio_keys>;
87
88 power {
89 label = "Power Button";
90 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
91 linux,code = <KEY_POWER>;
92 gpio-key,wakeup;
93 };
94
95 menu {
96 label = "Menu";
97 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_MENU>;
99 };
100
101 home {
102 label = "Home";
103 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
104 linux,code = <KEY_HOME>;
105 };
106
107 back {
108 label = "Back";
109 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
110 linux,code = <KEY_BACK>;
111 };
112
113 volume-up {
114 label = "Volume Up";
115 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
116 linux,code = <KEY_VOLUMEUP>;
117 };
118
119 volume-down {
120 label = "Volume Down";
121 gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
122 linux,code = <KEY_VOLUMEDOWN>;
123 };
124 };
125
Troy Kiskya177f182013-12-16 18:13:03 -0700126 sound {
127 compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
128 "fsl,imx-audio-sgtl5000";
129 model = "imx6q-nitrogen6x-sgtl5000";
130 ssi-controller = <&ssi1>;
131 audio-codec = <&codec>;
132 audio-routing =
133 "MIC_IN", "Mic Jack",
134 "Mic Jack", "Mic Bias",
135 "Headphone Jack", "HP_OUT";
136 mux-int-port = <1>;
137 mux-ext-port = <3>;
138 };
139
Gary Bisson9c3d8fa2015-09-30 15:05:19 +0200140 backlight_lcd: backlight_lcd {
Troy Kiskya177f182013-12-16 18:13:03 -0700141 compatible = "pwm-backlight";
142 pwms = <&pwm1 0 5000000>;
143 brightness-levels = <0 4 8 16 32 64 128 255>;
144 default-brightness-level = <7>;
145 power-supply = <&reg_3p3v>;
146 status = "okay";
147 };
148
Eric Nelson5d5c8652015-05-19 08:50:15 -0700149 backlight_lvds: backlight_lvds {
Troy Kiskya177f182013-12-16 18:13:03 -0700150 compatible = "pwm-backlight";
151 pwms = <&pwm4 0 5000000>;
152 brightness-levels = <0 4 8 16 32 64 128 255>;
153 default-brightness-level = <7>;
154 power-supply = <&reg_3p3v>;
155 status = "okay";
156 };
Eric Nelson5d5c8652015-05-19 08:50:15 -0700157
Gary Bisson9c3d8fa2015-09-30 15:05:19 +0200158 lcd_display: display@di0 {
159 compatible = "fsl,imx-parallel-display";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interface-pix-fmt = "bgr666";
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_j15>;
165 status = "okay";
166
167 port@0 {
168 reg = <0>;
169
170 lcd_display_in: endpoint {
171 remote-endpoint = <&ipu1_di0_disp0>;
172 };
173 };
174
175 port@1 {
176 reg = <1>;
177
178 lcd_display_out: endpoint {
179 remote-endpoint = <&lcd_panel_in>;
180 };
181 };
182 };
183
184 lcd_panel {
185 compatible = "okaya,rs800480t-7x0gp";
186 backlight = <&backlight_lcd>;
187
188 port {
189 lcd_panel_in: endpoint {
190 remote-endpoint = <&lcd_display_out>;
191 };
192 };
193 };
194
Eric Nelson5d5c8652015-05-19 08:50:15 -0700195 panel {
196 compatible = "hannstar,hsd100pxn1";
197 backlight = <&backlight_lvds>;
198
199 port {
200 panel_in: endpoint {
201 remote-endpoint = <&lvds0_out>;
202 };
203 };
204 };
Troy Kiskya177f182013-12-16 18:13:03 -0700205};
206
207&audmux {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_audmux>;
210 status = "okay";
211};
212
Peter Seiderer3e223392015-06-02 21:07:16 +0200213&can1 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_can1>;
216 xceiver-supply = <&reg_can_xcvr>;
217 status = "okay";
218};
219
Fabio Estevam7804fbc2015-06-29 13:16:54 -0300220&clks {
221 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
222 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
223 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
224 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
225};
226
Troy Kiskya177f182013-12-16 18:13:03 -0700227&ecspi1 {
228 fsl,spi-num-chipselects = <1>;
229 cs-gpios = <&gpio3 19 0>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_ecspi1>;
232 status = "okay";
233
234 flash: m25p80@0 {
Rafał Miłecki79826ac2015-08-16 08:39:17 +0200235 compatible = "sst,sst25vf016b", "jedec,spi-nor";
Troy Kiskya177f182013-12-16 18:13:03 -0700236 spi-max-frequency = <20000000>;
237 reg = <0>;
238 };
239};
240
241&fec {
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_enet>;
244 phy-mode = "rgmii";
245 phy-reset-gpios = <&gpio1 27 0>;
246 txen-skew-ps = <0>;
247 txc-skew-ps = <3000>;
248 rxdv-skew-ps = <0>;
249 rxc-skew-ps = <3000>;
250 rxd0-skew-ps = <0>;
251 rxd1-skew-ps = <0>;
252 rxd2-skew-ps = <0>;
253 rxd3-skew-ps = <0>;
254 txd0-skew-ps = <0>;
255 txd1-skew-ps = <0>;
256 txd2-skew-ps = <0>;
257 txd3-skew-ps = <0>;
Troy Kisky6261c4c2013-12-20 11:47:11 -0700258 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
259 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
Troy Kiskya177f182013-12-16 18:13:03 -0700260 status = "okay";
261};
262
Michael Olbrichd6536202014-07-25 12:49:52 +0200263&hdmi {
264 ddc-i2c-bus = <&i2c2>;
265 status = "okay";
266};
267
Troy Kiskya177f182013-12-16 18:13:03 -0700268&i2c1 {
269 clock-frequency = <100000>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_i2c1>;
272 status = "okay";
273
274 codec: sgtl5000@0a {
275 compatible = "fsl,sgtl5000";
276 reg = <0x0a>;
277 clocks = <&clks 201>;
278 VDDA-supply = <&reg_2p5v>;
279 VDDIO-supply = <&reg_3p3v>;
280 };
Philipp Zabel7881fb32014-08-22 11:13:02 +0200281
282 rtc: rtc@6f {
283 compatible = "isil,isl1208";
284 reg = <0x6f>;
285 };
Troy Kiskya177f182013-12-16 18:13:03 -0700286};
287
Michael Olbrich43c3c002014-07-25 12:49:51 +0200288&i2c2 {
289 clock-frequency = <100000>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c2>;
292 status = "okay";
293};
294
Philipp Zabel1dffdd62014-07-25 12:49:53 +0200295&i2c3 {
296 clock-frequency = <100000>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c3>;
299 status = "okay";
Gary Bisson140fa362015-09-30 15:46:38 +0200300
301 touchscreen@04 {
302 compatible = "eeti,egalax_ts";
303 reg = <0x04>;
304 interrupt-parent = <&gpio1>;
305 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
306 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
307 };
308
309 touchscreen@38 {
310 compatible = "edt,edt-ft5x06";
311 reg = <0x38>;
312 interrupt-parent = <&gpio1>;
313 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
314 };
Philipp Zabel1dffdd62014-07-25 12:49:53 +0200315};
316
Troy Kiskya177f182013-12-16 18:13:03 -0700317&iomuxc {
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_hog>;
320
321 imx6q-nitrogen6x {
322 pinctrl_hog: hoggrp {
323 fsl,pins = <
324 /* SGTL5000 sys_mclk */
325 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
Gary Bisson140fa362015-09-30 15:46:38 +0200326 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
Troy Kiskya177f182013-12-16 18:13:03 -0700327 >;
328 };
329
330 pinctrl_audmux: audmuxgrp {
331 fsl,pins = <
332 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
333 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
334 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
335 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
336 >;
337 };
338
Peter Seiderer3e223392015-06-02 21:07:16 +0200339 pinctrl_can1: can1grp {
340 fsl,pins = <
341 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
342 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
343 >;
344 };
345
346 pinctrl_can_xcvr: can-xcvrgrp {
347 fsl,pins = <
348 /* Flexcan XCVR enable */
349 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
350 >;
351 };
352
Troy Kiskya177f182013-12-16 18:13:03 -0700353 pinctrl_ecspi1: ecspi1grp {
354 fsl,pins = <
355 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
356 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
357 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
358 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
359 >;
360 };
361
362 pinctrl_enet: enetgrp {
363 fsl,pins = <
364 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
365 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
366 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
367 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
368 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
369 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
370 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
371 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
372 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
373 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
374 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
375 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
376 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
377 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
378 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
379 /* Phy reset */
380 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
Troy Kisky6261c4c2013-12-20 11:47:11 -0700381 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
Troy Kiskya177f182013-12-16 18:13:03 -0700382 >;
383 };
384
Troy Kiskyda474d42013-12-18 14:51:44 -0700385 pinctrl_gpio_keys: gpio_keysgrp {
386 fsl,pins = <
387 /* Power Button */
388 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
389 /* Menu Button */
390 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
391 /* Home Button */
392 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
393 /* Back Button */
394 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
395 /* Volume Up Button */
396 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
397 /* Volume Down Button */
398 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
399 >;
400 };
401
Troy Kiskya177f182013-12-16 18:13:03 -0700402 pinctrl_i2c1: i2c1grp {
403 fsl,pins = <
404 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
405 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
406 >;
407 };
408
Michael Olbrich43c3c002014-07-25 12:49:51 +0200409 pinctrl_i2c2: i2c2grp {
410 fsl,pins = <
411 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
412 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
413 >;
414 };
415
Philipp Zabel1dffdd62014-07-25 12:49:53 +0200416 pinctrl_i2c3: i2c3grp {
417 fsl,pins = <
418 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
419 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
420 >;
421 };
422
Gary Bisson9c3d8fa2015-09-30 15:05:19 +0200423 pinctrl_j15: j15grp {
424 fsl,pins = <
425 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
426 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
427 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
428 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
429 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
430 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
431 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
432 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
433 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
434 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
435 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
436 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
437 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
438 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
439 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
440 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
441 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
442 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
443 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
444 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
445 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
446 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
447 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
448 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
449 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
450 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
451 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
452 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
453 >;
454 };
455
Troy Kiskya177f182013-12-16 18:13:03 -0700456 pinctrl_pwm1: pwm1grp {
457 fsl,pins = <
458 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
459 >;
460 };
461
462 pinctrl_pwm3: pwm3grp {
463 fsl,pins = <
464 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
465 >;
466 };
467
468 pinctrl_pwm4: pwm4grp {
469 fsl,pins = <
470 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
471 >;
472 };
473
474 pinctrl_uart1: uart1grp {
475 fsl,pins = <
476 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
477 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
478 >;
479 };
480
481 pinctrl_uart2: uart2grp {
482 fsl,pins = <
483 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
484 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
485 >;
486 };
487
488 pinctrl_usbotg: usbotggrp {
489 fsl,pins = <
490 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
491 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
492 /* power enable, high active */
493 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
494 >;
495 };
496
Gary Bissonf12fb7a2015-09-30 15:46:39 +0200497 pinctrl_usdhc2: usdhc2grp {
498 fsl,pins = <
499 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
500 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
501 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
502 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
503 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
504 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
505 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
506 >;
507 };
508
Troy Kiskya177f182013-12-16 18:13:03 -0700509 pinctrl_usdhc3: usdhc3grp {
510 fsl,pins = <
511 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
512 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
513 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
514 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
515 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
516 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
517 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
518 >;
519 };
520
521 pinctrl_usdhc4: usdhc4grp {
522 fsl,pins = <
523 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
524 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
525 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
526 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
527 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
528 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
529 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
530 >;
531 };
Gary Bissonf12fb7a2015-09-30 15:46:39 +0200532
533 pinctrl_wlan_vmmc: wlan_vmmcgrp {
534 fsl,pins = <
535 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
536 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
537 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
538 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
539 >;
540 };
Troy Kiskya177f182013-12-16 18:13:03 -0700541 };
542};
543
Gary Bisson9c3d8fa2015-09-30 15:05:19 +0200544&ipu1_di0_disp0 {
545 remote-endpoint = <&lcd_display_in>;
546};
547
Troy Kiskya177f182013-12-16 18:13:03 -0700548&ldb {
549 status = "okay";
550
551 lvds-channel@0 {
552 fsl,data-mapping = "spwg";
553 fsl,data-width = <18>;
554 status = "okay";
555
Eric Nelson5d5c8652015-05-19 08:50:15 -0700556 port@4 {
557 reg = <4>;
558
559 lvds0_out: endpoint {
560 remote-endpoint = <&panel_in>;
Troy Kiskya177f182013-12-16 18:13:03 -0700561 };
562 };
563 };
564};
565
566&pcie {
567 status = "okay";
568};
569
570&pwm1 {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_pwm1>;
573 status = "okay";
574};
575
576&pwm3 {
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_pwm3>;
579 status = "okay";
580};
581
582&pwm4 {
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_pwm4>;
585 status = "okay";
586};
587
588&ssi1 {
Troy Kiskya177f182013-12-16 18:13:03 -0700589 status = "okay";
590};
591
592&uart1 {
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_uart1>;
595 status = "okay";
596};
597
598&uart2 {
599 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_uart2>;
601 status = "okay";
602};
603
604&usbh1 {
605 status = "okay";
606};
607
608&usbotg {
609 vbus-supply = <&reg_usb_otg_vbus>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_usbotg>;
612 disable-over-current;
613 status = "okay";
614};
615
Gary Bissonf12fb7a2015-09-30 15:46:39 +0200616&usdhc2 {
617 pinctrl-names = "default";
618 pinctrl-0 = <&pinctrl_usdhc2>;
619 bus-width = <4>;
620 non-removable;
621 vmmc-supply = <&reg_wlan_vmmc>;
622 cap-power-off-card;
623 keep-power-in-suspend;
624 status = "okay";
625
626 #address-cells = <1>;
627 #size-cells = <0>;
628 wlcore: wlcore@2 {
629 compatible = "ti,wl1271";
630 reg = <2>;
631 interrupt-parent = <&gpio6>;
632 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
633 ref-clock-frequency = <38400000>;
634 };
635};
636
Troy Kiskya177f182013-12-16 18:13:03 -0700637&usdhc3 {
638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_usdhc3>;
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +0800640 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
Troy Kiskya177f182013-12-16 18:13:03 -0700641 vmmc-supply = <&reg_3p3v>;
642 status = "okay";
643};
644
645&usdhc4 {
646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_usdhc4>;
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +0800648 cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
Troy Kiskya177f182013-12-16 18:13:03 -0700649 vmmc-supply = <&reg_3p3v>;
650 status = "okay";
651};