Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 1 | /* |
| 2 | * wm8962.c -- WM8962 ALSA SoC Audio driver |
| 3 | * |
| 4 | * Copyright 2010 Wolfson Microelectronics plc |
| 5 | * |
| 6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
| 7 | * |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/moduleparam.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/pm.h> |
| 19 | #include <linux/gcd.h> |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 20 | #include <linux/gpio.h> |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 21 | #include <linux/i2c.h> |
| 22 | #include <linux/input.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/regulator/consumer.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/workqueue.h> |
| 27 | #include <sound/core.h> |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 28 | #include <sound/jack.h> |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 29 | #include <sound/pcm.h> |
| 30 | #include <sound/pcm_params.h> |
| 31 | #include <sound/soc.h> |
| 32 | #include <sound/soc-dapm.h> |
| 33 | #include <sound/initval.h> |
| 34 | #include <sound/tlv.h> |
| 35 | #include <sound/wm8962.h> |
| 36 | |
| 37 | #include "wm8962.h" |
| 38 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 39 | #define WM8962_NUM_SUPPLIES 8 |
| 40 | static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { |
| 41 | "DCVDD", |
| 42 | "DBVDD", |
| 43 | "AVDD", |
| 44 | "CPVDD", |
| 45 | "MICVDD", |
| 46 | "PLLVDD", |
| 47 | "SPKVDD1", |
| 48 | "SPKVDD2", |
| 49 | }; |
| 50 | |
| 51 | /* codec private data */ |
| 52 | struct wm8962_priv { |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 53 | struct snd_soc_codec *codec; |
| 54 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 55 | u16 reg_cache[WM8962_MAX_REGISTER + 1]; |
| 56 | |
| 57 | int sysclk; |
| 58 | int sysclk_rate; |
| 59 | |
| 60 | int bclk; /* Desired BCLK */ |
| 61 | int lrclk; |
| 62 | |
| 63 | int fll_src; |
| 64 | int fll_fref; |
| 65 | int fll_fout; |
| 66 | |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 67 | struct delayed_work mic_work; |
| 68 | struct snd_soc_jack *jack; |
| 69 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 70 | struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; |
| 71 | struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; |
| 72 | |
| 73 | #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) |
| 74 | struct input_dev *beep; |
| 75 | struct work_struct beep_work; |
| 76 | int beep_rate; |
| 77 | #endif |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 78 | |
| 79 | #ifdef CONFIG_GPIOLIB |
| 80 | struct gpio_chip gpio_chip; |
| 81 | #endif |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | /* We can't use the same notifier block for more than one supply and |
| 85 | * there's no way I can see to get from a callback to the caller |
| 86 | * except container_of(). |
| 87 | */ |
| 88 | #define WM8962_REGULATOR_EVENT(n) \ |
| 89 | static int wm8962_regulator_event_##n(struct notifier_block *nb, \ |
| 90 | unsigned long event, void *data) \ |
| 91 | { \ |
| 92 | struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ |
| 93 | disable_nb[n]); \ |
| 94 | if (event & REGULATOR_EVENT_DISABLE) { \ |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 95 | wm8962->codec->cache_sync = 1; \ |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 96 | } \ |
| 97 | return 0; \ |
| 98 | } |
| 99 | |
| 100 | WM8962_REGULATOR_EVENT(0) |
| 101 | WM8962_REGULATOR_EVENT(1) |
| 102 | WM8962_REGULATOR_EVENT(2) |
| 103 | WM8962_REGULATOR_EVENT(3) |
| 104 | WM8962_REGULATOR_EVENT(4) |
| 105 | WM8962_REGULATOR_EVENT(5) |
| 106 | WM8962_REGULATOR_EVENT(6) |
| 107 | WM8962_REGULATOR_EVENT(7) |
| 108 | |
Mark Brown | f57f6c04 | 2010-10-07 17:41:04 -0700 | [diff] [blame^] | 109 | static const u16 wm8962_reg[WM8962_MAX_REGISTER + 1] = { |
| 110 | [0] = 0x009F, /* R0 - Left Input volume */ |
| 111 | [1] = 0x049F, /* R1 - Right Input volume */ |
| 112 | [2] = 0x0000, /* R2 - HPOUTL volume */ |
| 113 | [3] = 0x0000, /* R3 - HPOUTR volume */ |
| 114 | [4] = 0x0020, /* R4 - Clocking1 */ |
| 115 | [5] = 0x0018, /* R5 - ADC & DAC Control 1 */ |
| 116 | [6] = 0x2008, /* R6 - ADC & DAC Control 2 */ |
| 117 | [7] = 0x000A, /* R7 - Audio Interface 0 */ |
| 118 | [8] = 0x01E4, /* R8 - Clocking2 */ |
| 119 | [9] = 0x0300, /* R9 - Audio Interface 1 */ |
| 120 | [10] = 0x00C0, /* R10 - Left DAC volume */ |
| 121 | [11] = 0x00C0, /* R11 - Right DAC volume */ |
| 122 | |
| 123 | [14] = 0x0040, /* R14 - Audio Interface 2 */ |
| 124 | [15] = 0x6243, /* R15 - Software Reset */ |
| 125 | |
| 126 | [17] = 0x007B, /* R17 - ALC1 */ |
| 127 | [18] = 0x0000, /* R18 - ALC2 */ |
| 128 | [19] = 0x1C32, /* R19 - ALC3 */ |
| 129 | [20] = 0x3200, /* R20 - Noise Gate */ |
| 130 | [21] = 0x00C0, /* R21 - Left ADC volume */ |
| 131 | [22] = 0x00C0, /* R22 - Right ADC volume */ |
| 132 | [23] = 0x0160, /* R23 - Additional control(1) */ |
| 133 | [24] = 0x0000, /* R24 - Additional control(2) */ |
| 134 | [25] = 0x0000, /* R25 - Pwr Mgmt (1) */ |
| 135 | [26] = 0x0000, /* R26 - Pwr Mgmt (2) */ |
| 136 | [27] = 0x0010, /* R27 - Additional Control (3) */ |
| 137 | [28] = 0x0000, /* R28 - Anti-pop */ |
| 138 | |
| 139 | [30] = 0x005E, /* R30 - Clocking 3 */ |
| 140 | [31] = 0x0000, /* R31 - Input mixer control (1) */ |
| 141 | [32] = 0x0145, /* R32 - Left input mixer volume */ |
| 142 | [33] = 0x0145, /* R33 - Right input mixer volume */ |
| 143 | [34] = 0x0009, /* R34 - Input mixer control (2) */ |
| 144 | [35] = 0x0003, /* R35 - Input bias control */ |
| 145 | [37] = 0x0008, /* R37 - Left input PGA control */ |
| 146 | [38] = 0x0008, /* R38 - Right input PGA control */ |
| 147 | |
| 148 | [40] = 0x0000, /* R40 - SPKOUTL volume */ |
| 149 | [41] = 0x0000, /* R41 - SPKOUTR volume */ |
| 150 | |
| 151 | [47] = 0x0000, /* R47 - Thermal Shutdown Status */ |
| 152 | [48] = 0x8027, /* R48 - Additional Control (4) */ |
| 153 | [49] = 0x0010, /* R49 - Class D Control 1 */ |
| 154 | |
| 155 | [51] = 0x0003, /* R51 - Class D Control 2 */ |
| 156 | |
| 157 | [56] = 0x0506, /* R56 - Clocking 4 */ |
| 158 | [57] = 0x0000, /* R57 - DAC DSP Mixing (1) */ |
| 159 | [58] = 0x0000, /* R58 - DAC DSP Mixing (2) */ |
| 160 | |
| 161 | [60] = 0x0300, /* R60 - DC Servo 0 */ |
| 162 | [61] = 0x0300, /* R61 - DC Servo 1 */ |
| 163 | |
| 164 | [64] = 0x0810, /* R64 - DC Servo 4 */ |
| 165 | |
| 166 | [66] = 0x0000, /* R66 - DC Servo 6 */ |
| 167 | |
| 168 | [68] = 0x001B, /* R68 - Analogue PGA Bias */ |
| 169 | [69] = 0x0000, /* R69 - Analogue HP 0 */ |
| 170 | |
| 171 | [71] = 0x01FB, /* R71 - Analogue HP 2 */ |
| 172 | [72] = 0x0000, /* R72 - Charge Pump 1 */ |
| 173 | |
| 174 | [82] = 0x0004, /* R82 - Charge Pump B */ |
| 175 | |
| 176 | [87] = 0x0000, /* R87 - Write Sequencer Control 1 */ |
| 177 | |
| 178 | [90] = 0x0000, /* R90 - Write Sequencer Control 2 */ |
| 179 | |
| 180 | [93] = 0x0000, /* R93 - Write Sequencer Control 3 */ |
| 181 | [94] = 0x0000, /* R94 - Control Interface */ |
| 182 | |
| 183 | [99] = 0x0000, /* R99 - Mixer Enables */ |
| 184 | [100] = 0x0000, /* R100 - Headphone Mixer (1) */ |
| 185 | [101] = 0x0000, /* R101 - Headphone Mixer (2) */ |
| 186 | [102] = 0x013F, /* R102 - Headphone Mixer (3) */ |
| 187 | [103] = 0x013F, /* R103 - Headphone Mixer (4) */ |
| 188 | |
| 189 | [105] = 0x0000, /* R105 - Speaker Mixer (1) */ |
| 190 | [106] = 0x0000, /* R106 - Speaker Mixer (2) */ |
| 191 | [107] = 0x013F, /* R107 - Speaker Mixer (3) */ |
| 192 | [108] = 0x013F, /* R108 - Speaker Mixer (4) */ |
| 193 | [109] = 0x0003, /* R109 - Speaker Mixer (5) */ |
| 194 | [110] = 0x0002, /* R110 - Beep Generator (1) */ |
| 195 | |
| 196 | [115] = 0x0006, /* R115 - Oscillator Trim (3) */ |
| 197 | [116] = 0x0026, /* R116 - Oscillator Trim (4) */ |
| 198 | |
| 199 | [119] = 0x0000, /* R119 - Oscillator Trim (7) */ |
| 200 | |
| 201 | [124] = 0x0011, /* R124 - Analogue Clocking1 */ |
| 202 | [125] = 0x004B, /* R125 - Analogue Clocking2 */ |
| 203 | [126] = 0x000D, /* R126 - Analogue Clocking3 */ |
| 204 | [127] = 0x0000, /* R127 - PLL Software Reset */ |
| 205 | |
| 206 | [129] = 0x0000, /* R129 - PLL2 */ |
| 207 | |
| 208 | [131] = 0x0000, /* R131 - PLL 4 */ |
| 209 | |
| 210 | [136] = 0x0067, /* R136 - PLL 9 */ |
| 211 | [137] = 0x001C, /* R137 - PLL 10 */ |
| 212 | [138] = 0x0071, /* R138 - PLL 11 */ |
| 213 | [139] = 0x00C7, /* R139 - PLL 12 */ |
| 214 | [140] = 0x0067, /* R140 - PLL 13 */ |
| 215 | [141] = 0x0048, /* R141 - PLL 14 */ |
| 216 | [142] = 0x0022, /* R142 - PLL 15 */ |
| 217 | [143] = 0x0097, /* R143 - PLL 16 */ |
| 218 | |
| 219 | [155] = 0x000C, /* R155 - FLL Control (1) */ |
| 220 | [156] = 0x0039, /* R156 - FLL Control (2) */ |
| 221 | [157] = 0x0180, /* R157 - FLL Control (3) */ |
| 222 | |
| 223 | [159] = 0x0032, /* R159 - FLL Control (5) */ |
| 224 | [160] = 0x0018, /* R160 - FLL Control (6) */ |
| 225 | [161] = 0x007D, /* R161 - FLL Control (7) */ |
| 226 | [162] = 0x0008, /* R162 - FLL Control (8) */ |
| 227 | |
| 228 | [252] = 0x0005, /* R252 - General test 1 */ |
| 229 | |
| 230 | [256] = 0x0000, /* R256 - DF1 */ |
| 231 | [257] = 0x0000, /* R257 - DF2 */ |
| 232 | [258] = 0x0000, /* R258 - DF3 */ |
| 233 | [259] = 0x0000, /* R259 - DF4 */ |
| 234 | [260] = 0x0000, /* R260 - DF5 */ |
| 235 | [261] = 0x0000, /* R261 - DF6 */ |
| 236 | [262] = 0x0000, /* R262 - DF7 */ |
| 237 | |
| 238 | [264] = 0x0000, /* R264 - LHPF1 */ |
| 239 | [265] = 0x0000, /* R265 - LHPF2 */ |
| 240 | |
| 241 | [268] = 0x0000, /* R268 - THREED1 */ |
| 242 | [269] = 0x0000, /* R269 - THREED2 */ |
| 243 | [270] = 0x0000, /* R270 - THREED3 */ |
| 244 | [271] = 0x0000, /* R271 - THREED4 */ |
| 245 | |
| 246 | [276] = 0x000C, /* R276 - DRC 1 */ |
| 247 | [277] = 0x0925, /* R277 - DRC 2 */ |
| 248 | [278] = 0x0000, /* R278 - DRC 3 */ |
| 249 | [279] = 0x0000, /* R279 - DRC 4 */ |
| 250 | [280] = 0x0000, /* R280 - DRC 5 */ |
| 251 | |
| 252 | [285] = 0x0000, /* R285 - Tloopback */ |
| 253 | |
| 254 | [335] = 0x0004, /* R335 - EQ1 */ |
| 255 | [336] = 0x6318, /* R336 - EQ2 */ |
| 256 | [337] = 0x6300, /* R337 - EQ3 */ |
| 257 | [338] = 0x0FCA, /* R338 - EQ4 */ |
| 258 | [339] = 0x0400, /* R339 - EQ5 */ |
| 259 | [340] = 0x00D8, /* R340 - EQ6 */ |
| 260 | [341] = 0x1EB5, /* R341 - EQ7 */ |
| 261 | [342] = 0xF145, /* R342 - EQ8 */ |
| 262 | [343] = 0x0B75, /* R343 - EQ9 */ |
| 263 | [344] = 0x01C5, /* R344 - EQ10 */ |
| 264 | [345] = 0x1C58, /* R345 - EQ11 */ |
| 265 | [346] = 0xF373, /* R346 - EQ12 */ |
| 266 | [347] = 0x0A54, /* R347 - EQ13 */ |
| 267 | [348] = 0x0558, /* R348 - EQ14 */ |
| 268 | [349] = 0x168E, /* R349 - EQ15 */ |
| 269 | [350] = 0xF829, /* R350 - EQ16 */ |
| 270 | [351] = 0x07AD, /* R351 - EQ17 */ |
| 271 | [352] = 0x1103, /* R352 - EQ18 */ |
| 272 | [353] = 0x0564, /* R353 - EQ19 */ |
| 273 | [354] = 0x0559, /* R354 - EQ20 */ |
| 274 | [355] = 0x4000, /* R355 - EQ21 */ |
| 275 | [356] = 0x6318, /* R356 - EQ22 */ |
| 276 | [357] = 0x6300, /* R357 - EQ23 */ |
| 277 | [358] = 0x0FCA, /* R358 - EQ24 */ |
| 278 | [359] = 0x0400, /* R359 - EQ25 */ |
| 279 | [360] = 0x00D8, /* R360 - EQ26 */ |
| 280 | [361] = 0x1EB5, /* R361 - EQ27 */ |
| 281 | [362] = 0xF145, /* R362 - EQ28 */ |
| 282 | [363] = 0x0B75, /* R363 - EQ29 */ |
| 283 | [364] = 0x01C5, /* R364 - EQ30 */ |
| 284 | [365] = 0x1C58, /* R365 - EQ31 */ |
| 285 | [366] = 0xF373, /* R366 - EQ32 */ |
| 286 | [367] = 0x0A54, /* R367 - EQ33 */ |
| 287 | [368] = 0x0558, /* R368 - EQ34 */ |
| 288 | [369] = 0x168E, /* R369 - EQ35 */ |
| 289 | [370] = 0xF829, /* R370 - EQ36 */ |
| 290 | [371] = 0x07AD, /* R371 - EQ37 */ |
| 291 | [372] = 0x1103, /* R372 - EQ38 */ |
| 292 | [373] = 0x0564, /* R373 - EQ39 */ |
| 293 | [374] = 0x0559, /* R374 - EQ40 */ |
| 294 | [375] = 0x4000, /* R375 - EQ41 */ |
| 295 | |
| 296 | [513] = 0x0000, /* R513 - GPIO 2 */ |
| 297 | [514] = 0x0000, /* R514 - GPIO 3 */ |
| 298 | |
| 299 | [516] = 0x8100, /* R516 - GPIO 5 */ |
| 300 | [517] = 0x8100, /* R517 - GPIO 6 */ |
| 301 | |
| 302 | [560] = 0x0000, /* R560 - Interrupt Status 1 */ |
| 303 | [561] = 0x0000, /* R561 - Interrupt Status 2 */ |
| 304 | |
| 305 | [568] = 0x0030, /* R568 - Interrupt Status 1 Mask */ |
| 306 | [569] = 0xFFED, /* R569 - Interrupt Status 2 Mask */ |
| 307 | |
| 308 | [576] = 0x0000, /* R576 - Interrupt Control */ |
| 309 | |
| 310 | [584] = 0x002D, /* R584 - IRQ Debounce */ |
| 311 | |
| 312 | [586] = 0x0000, /* R586 - MICINT Source Pol */ |
| 313 | |
| 314 | [768] = 0x1C00, /* R768 - DSP2 Power Management */ |
| 315 | |
| 316 | [1037] = 0x0000, /* R1037 - DSP2_ExecControl */ |
| 317 | |
| 318 | [8192] = 0x0000, /* R8192 - DSP2 Instruction RAM 0 */ |
| 319 | |
| 320 | [9216] = 0x0030, /* R9216 - DSP2 Address RAM 2 */ |
| 321 | [9217] = 0x0000, /* R9217 - DSP2 Address RAM 1 */ |
| 322 | [9218] = 0x0000, /* R9218 - DSP2 Address RAM 0 */ |
| 323 | |
| 324 | [12288] = 0x0000, /* R12288 - DSP2 Data1 RAM 1 */ |
| 325 | [12289] = 0x0000, /* R12289 - DSP2 Data1 RAM 0 */ |
| 326 | |
| 327 | [13312] = 0x0000, /* R13312 - DSP2 Data2 RAM 1 */ |
| 328 | [13313] = 0x0000, /* R13313 - DSP2 Data2 RAM 0 */ |
| 329 | |
| 330 | [14336] = 0x0000, /* R14336 - DSP2 Data3 RAM 1 */ |
| 331 | [14337] = 0x0000, /* R14337 - DSP2 Data3 RAM 0 */ |
| 332 | |
| 333 | [15360] = 0x000A, /* R15360 - DSP2 Coeff RAM 0 */ |
| 334 | |
| 335 | [16384] = 0x0000, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ |
| 336 | [16385] = 0x0000, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ |
| 337 | [16386] = 0x0000, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ |
| 338 | [16387] = 0x0000, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ |
| 339 | [16388] = 0x0000, /* R16388 - SOUNDSTAGE_ENABLES_1 */ |
| 340 | [16389] = 0x0000, /* R16389 - SOUNDSTAGE_ENABLES_0 */ |
| 341 | |
| 342 | [16896] = 0x0002, /* R16896 - HDBASS_AI_1 */ |
| 343 | [16897] = 0xBD12, /* R16897 - HDBASS_AI_0 */ |
| 344 | [16898] = 0x007C, /* R16898 - HDBASS_AR_1 */ |
| 345 | [16899] = 0x586C, /* R16899 - HDBASS_AR_0 */ |
| 346 | [16900] = 0x0053, /* R16900 - HDBASS_B_1 */ |
| 347 | [16901] = 0x8121, /* R16901 - HDBASS_B_0 */ |
| 348 | [16902] = 0x003F, /* R16902 - HDBASS_K_1 */ |
| 349 | [16903] = 0x8BD8, /* R16903 - HDBASS_K_0 */ |
| 350 | [16904] = 0x0032, /* R16904 - HDBASS_N1_1 */ |
| 351 | [16905] = 0xF52D, /* R16905 - HDBASS_N1_0 */ |
| 352 | [16906] = 0x0065, /* R16906 - HDBASS_N2_1 */ |
| 353 | [16907] = 0xAC8C, /* R16907 - HDBASS_N2_0 */ |
| 354 | [16908] = 0x006B, /* R16908 - HDBASS_N3_1 */ |
| 355 | [16909] = 0xE087, /* R16909 - HDBASS_N3_0 */ |
| 356 | [16910] = 0x0072, /* R16910 - HDBASS_N4_1 */ |
| 357 | [16911] = 0x1483, /* R16911 - HDBASS_N4_0 */ |
| 358 | [16912] = 0x0072, /* R16912 - HDBASS_N5_1 */ |
| 359 | [16913] = 0x1483, /* R16913 - HDBASS_N5_0 */ |
| 360 | [16914] = 0x0043, /* R16914 - HDBASS_X1_1 */ |
| 361 | [16915] = 0x3525, /* R16915 - HDBASS_X1_0 */ |
| 362 | [16916] = 0x0006, /* R16916 - HDBASS_X2_1 */ |
| 363 | [16917] = 0x6A4A, /* R16917 - HDBASS_X2_0 */ |
| 364 | [16918] = 0x0043, /* R16918 - HDBASS_X3_1 */ |
| 365 | [16919] = 0x6079, /* R16919 - HDBASS_X3_0 */ |
| 366 | [16920] = 0x0008, /* R16920 - HDBASS_ATK_1 */ |
| 367 | [16921] = 0x0000, /* R16921 - HDBASS_ATK_0 */ |
| 368 | [16922] = 0x0001, /* R16922 - HDBASS_DCY_1 */ |
| 369 | [16923] = 0x0000, /* R16923 - HDBASS_DCY_0 */ |
| 370 | [16924] = 0x0059, /* R16924 - HDBASS_PG_1 */ |
| 371 | [16925] = 0x999A, /* R16925 - HDBASS_PG_0 */ |
| 372 | |
| 373 | [17048] = 0x0083, /* R17408 - HPF_C_1 */ |
| 374 | [17049] = 0x98AD, /* R17409 - HPF_C_0 */ |
| 375 | |
| 376 | [17920] = 0x007F, /* R17920 - ADCL_RETUNE_C1_1 */ |
| 377 | [17921] = 0xFFFF, /* R17921 - ADCL_RETUNE_C1_0 */ |
| 378 | [17922] = 0x0000, /* R17922 - ADCL_RETUNE_C2_1 */ |
| 379 | [17923] = 0x0000, /* R17923 - ADCL_RETUNE_C2_0 */ |
| 380 | [17924] = 0x0000, /* R17924 - ADCL_RETUNE_C3_1 */ |
| 381 | [17925] = 0x0000, /* R17925 - ADCL_RETUNE_C3_0 */ |
| 382 | [17926] = 0x0000, /* R17926 - ADCL_RETUNE_C4_1 */ |
| 383 | [17927] = 0x0000, /* R17927 - ADCL_RETUNE_C4_0 */ |
| 384 | [17928] = 0x0000, /* R17928 - ADCL_RETUNE_C5_1 */ |
| 385 | [17929] = 0x0000, /* R17929 - ADCL_RETUNE_C5_0 */ |
| 386 | [17930] = 0x0000, /* R17930 - ADCL_RETUNE_C6_1 */ |
| 387 | [17931] = 0x0000, /* R17931 - ADCL_RETUNE_C6_0 */ |
| 388 | [17932] = 0x0000, /* R17932 - ADCL_RETUNE_C7_1 */ |
| 389 | [17933] = 0x0000, /* R17933 - ADCL_RETUNE_C7_0 */ |
| 390 | [17934] = 0x0000, /* R17934 - ADCL_RETUNE_C8_1 */ |
| 391 | [17935] = 0x0000, /* R17935 - ADCL_RETUNE_C8_0 */ |
| 392 | [17936] = 0x0000, /* R17936 - ADCL_RETUNE_C9_1 */ |
| 393 | [17937] = 0x0000, /* R17937 - ADCL_RETUNE_C9_0 */ |
| 394 | [17938] = 0x0000, /* R17938 - ADCL_RETUNE_C10_1 */ |
| 395 | [17939] = 0x0000, /* R17939 - ADCL_RETUNE_C10_0 */ |
| 396 | [17940] = 0x0000, /* R17940 - ADCL_RETUNE_C11_1 */ |
| 397 | [17941] = 0x0000, /* R17941 - ADCL_RETUNE_C11_0 */ |
| 398 | [17942] = 0x0000, /* R17942 - ADCL_RETUNE_C12_1 */ |
| 399 | [17943] = 0x0000, /* R17943 - ADCL_RETUNE_C12_0 */ |
| 400 | [17944] = 0x0000, /* R17944 - ADCL_RETUNE_C13_1 */ |
| 401 | [17945] = 0x0000, /* R17945 - ADCL_RETUNE_C13_0 */ |
| 402 | [17946] = 0x0000, /* R17946 - ADCL_RETUNE_C14_1 */ |
| 403 | [17947] = 0x0000, /* R17947 - ADCL_RETUNE_C14_0 */ |
| 404 | [17948] = 0x0000, /* R17948 - ADCL_RETUNE_C15_1 */ |
| 405 | [17949] = 0x0000, /* R17949 - ADCL_RETUNE_C15_0 */ |
| 406 | [17950] = 0x0000, /* R17950 - ADCL_RETUNE_C16_1 */ |
| 407 | [17951] = 0x0000, /* R17951 - ADCL_RETUNE_C16_0 */ |
| 408 | [17952] = 0x0000, /* R17952 - ADCL_RETUNE_C17_1 */ |
| 409 | [17953] = 0x0000, /* R17953 - ADCL_RETUNE_C17_0 */ |
| 410 | [17954] = 0x0000, /* R17954 - ADCL_RETUNE_C18_1 */ |
| 411 | [17955] = 0x0000, /* R17955 - ADCL_RETUNE_C18_0 */ |
| 412 | [17956] = 0x0000, /* R17956 - ADCL_RETUNE_C19_1 */ |
| 413 | [17957] = 0x0000, /* R17957 - ADCL_RETUNE_C19_0 */ |
| 414 | [17958] = 0x0000, /* R17958 - ADCL_RETUNE_C20_1 */ |
| 415 | [17959] = 0x0000, /* R17959 - ADCL_RETUNE_C20_0 */ |
| 416 | [17960] = 0x0000, /* R17960 - ADCL_RETUNE_C21_1 */ |
| 417 | [17961] = 0x0000, /* R17961 - ADCL_RETUNE_C21_0 */ |
| 418 | [17962] = 0x0000, /* R17962 - ADCL_RETUNE_C22_1 */ |
| 419 | [17963] = 0x0000, /* R17963 - ADCL_RETUNE_C22_0 */ |
| 420 | [17964] = 0x0000, /* R17964 - ADCL_RETUNE_C23_1 */ |
| 421 | [17965] = 0x0000, /* R17965 - ADCL_RETUNE_C23_0 */ |
| 422 | [17966] = 0x0000, /* R17966 - ADCL_RETUNE_C24_1 */ |
| 423 | [17967] = 0x0000, /* R17967 - ADCL_RETUNE_C24_0 */ |
| 424 | [17968] = 0x0000, /* R17968 - ADCL_RETUNE_C25_1 */ |
| 425 | [17969] = 0x0000, /* R17969 - ADCL_RETUNE_C25_0 */ |
| 426 | [17970] = 0x0000, /* R17970 - ADCL_RETUNE_C26_1 */ |
| 427 | [17971] = 0x0000, /* R17971 - ADCL_RETUNE_C26_0 */ |
| 428 | [17972] = 0x0000, /* R17972 - ADCL_RETUNE_C27_1 */ |
| 429 | [17973] = 0x0000, /* R17973 - ADCL_RETUNE_C27_0 */ |
| 430 | [17974] = 0x0000, /* R17974 - ADCL_RETUNE_C28_1 */ |
| 431 | [17975] = 0x0000, /* R17975 - ADCL_RETUNE_C28_0 */ |
| 432 | [17976] = 0x0000, /* R17976 - ADCL_RETUNE_C29_1 */ |
| 433 | [17977] = 0x0000, /* R17977 - ADCL_RETUNE_C29_0 */ |
| 434 | [17978] = 0x0000, /* R17978 - ADCL_RETUNE_C30_1 */ |
| 435 | [17979] = 0x0000, /* R17979 - ADCL_RETUNE_C30_0 */ |
| 436 | [17980] = 0x0000, /* R17980 - ADCL_RETUNE_C31_1 */ |
| 437 | [17981] = 0x0000, /* R17981 - ADCL_RETUNE_C31_0 */ |
| 438 | [17982] = 0x0000, /* R17982 - ADCL_RETUNE_C32_1 */ |
| 439 | [17983] = 0x0000, /* R17983 - ADCL_RETUNE_C32_0 */ |
| 440 | |
| 441 | [18432] = 0x0020, /* R18432 - RETUNEADC_PG2_1 */ |
| 442 | [18433] = 0x0000, /* R18433 - RETUNEADC_PG2_0 */ |
| 443 | [18434] = 0x0040, /* R18434 - RETUNEADC_PG_1 */ |
| 444 | [18435] = 0x0000, /* R18435 - RETUNEADC_PG_0 */ |
| 445 | |
| 446 | [18944] = 0x007F, /* R18944 - ADCR_RETUNE_C1_1 */ |
| 447 | [18945] = 0xFFFF, /* R18945 - ADCR_RETUNE_C1_0 */ |
| 448 | [18946] = 0x0000, /* R18946 - ADCR_RETUNE_C2_1 */ |
| 449 | [18947] = 0x0000, /* R18947 - ADCR_RETUNE_C2_0 */ |
| 450 | [18948] = 0x0000, /* R18948 - ADCR_RETUNE_C3_1 */ |
| 451 | [18949] = 0x0000, /* R18949 - ADCR_RETUNE_C3_0 */ |
| 452 | [18950] = 0x0000, /* R18950 - ADCR_RETUNE_C4_1 */ |
| 453 | [18951] = 0x0000, /* R18951 - ADCR_RETUNE_C4_0 */ |
| 454 | [18952] = 0x0000, /* R18952 - ADCR_RETUNE_C5_1 */ |
| 455 | [18953] = 0x0000, /* R18953 - ADCR_RETUNE_C5_0 */ |
| 456 | [18954] = 0x0000, /* R18954 - ADCR_RETUNE_C6_1 */ |
| 457 | [18955] = 0x0000, /* R18955 - ADCR_RETUNE_C6_0 */ |
| 458 | [18956] = 0x0000, /* R18956 - ADCR_RETUNE_C7_1 */ |
| 459 | [18957] = 0x0000, /* R18957 - ADCR_RETUNE_C7_0 */ |
| 460 | [18958] = 0x0000, /* R18958 - ADCR_RETUNE_C8_1 */ |
| 461 | [18959] = 0x0000, /* R18959 - ADCR_RETUNE_C8_0 */ |
| 462 | [18960] = 0x0000, /* R18960 - ADCR_RETUNE_C9_1 */ |
| 463 | [18961] = 0x0000, /* R18961 - ADCR_RETUNE_C9_0 */ |
| 464 | [18962] = 0x0000, /* R18962 - ADCR_RETUNE_C10_1 */ |
| 465 | [18963] = 0x0000, /* R18963 - ADCR_RETUNE_C10_0 */ |
| 466 | [18964] = 0x0000, /* R18964 - ADCR_RETUNE_C11_1 */ |
| 467 | [18965] = 0x0000, /* R18965 - ADCR_RETUNE_C11_0 */ |
| 468 | [18966] = 0x0000, /* R18966 - ADCR_RETUNE_C12_1 */ |
| 469 | [18967] = 0x0000, /* R18967 - ADCR_RETUNE_C12_0 */ |
| 470 | [18968] = 0x0000, /* R18968 - ADCR_RETUNE_C13_1 */ |
| 471 | [18969] = 0x0000, /* R18969 - ADCR_RETUNE_C13_0 */ |
| 472 | [18970] = 0x0000, /* R18970 - ADCR_RETUNE_C14_1 */ |
| 473 | [18971] = 0x0000, /* R18971 - ADCR_RETUNE_C14_0 */ |
| 474 | [18972] = 0x0000, /* R18972 - ADCR_RETUNE_C15_1 */ |
| 475 | [18973] = 0x0000, /* R18973 - ADCR_RETUNE_C15_0 */ |
| 476 | [18974] = 0x0000, /* R18974 - ADCR_RETUNE_C16_1 */ |
| 477 | [18975] = 0x0000, /* R18975 - ADCR_RETUNE_C16_0 */ |
| 478 | [18976] = 0x0000, /* R18976 - ADCR_RETUNE_C17_1 */ |
| 479 | [18977] = 0x0000, /* R18977 - ADCR_RETUNE_C17_0 */ |
| 480 | [18978] = 0x0000, /* R18978 - ADCR_RETUNE_C18_1 */ |
| 481 | [18979] = 0x0000, /* R18979 - ADCR_RETUNE_C18_0 */ |
| 482 | [18980] = 0x0000, /* R18980 - ADCR_RETUNE_C19_1 */ |
| 483 | [18981] = 0x0000, /* R18981 - ADCR_RETUNE_C19_0 */ |
| 484 | [18982] = 0x0000, /* R18982 - ADCR_RETUNE_C20_1 */ |
| 485 | [18983] = 0x0000, /* R18983 - ADCR_RETUNE_C20_0 */ |
| 486 | [18984] = 0x0000, /* R18984 - ADCR_RETUNE_C21_1 */ |
| 487 | [18985] = 0x0000, /* R18985 - ADCR_RETUNE_C21_0 */ |
| 488 | [18986] = 0x0000, /* R18986 - ADCR_RETUNE_C22_1 */ |
| 489 | [18987] = 0x0000, /* R18987 - ADCR_RETUNE_C22_0 */ |
| 490 | [18988] = 0x0000, /* R18988 - ADCR_RETUNE_C23_1 */ |
| 491 | [18989] = 0x0000, /* R18989 - ADCR_RETUNE_C23_0 */ |
| 492 | [18990] = 0x0000, /* R18990 - ADCR_RETUNE_C24_1 */ |
| 493 | [18991] = 0x0000, /* R18991 - ADCR_RETUNE_C24_0 */ |
| 494 | [18992] = 0x0000, /* R18992 - ADCR_RETUNE_C25_1 */ |
| 495 | [18993] = 0x0000, /* R18993 - ADCR_RETUNE_C25_0 */ |
| 496 | [18994] = 0x0000, /* R18994 - ADCR_RETUNE_C26_1 */ |
| 497 | [18995] = 0x0000, /* R18995 - ADCR_RETUNE_C26_0 */ |
| 498 | [18996] = 0x0000, /* R18996 - ADCR_RETUNE_C27_1 */ |
| 499 | [18997] = 0x0000, /* R18997 - ADCR_RETUNE_C27_0 */ |
| 500 | [18998] = 0x0000, /* R18998 - ADCR_RETUNE_C28_1 */ |
| 501 | [18999] = 0x0000, /* R18999 - ADCR_RETUNE_C28_0 */ |
| 502 | [19000] = 0x0000, /* R19000 - ADCR_RETUNE_C29_1 */ |
| 503 | [19001] = 0x0000, /* R19001 - ADCR_RETUNE_C29_0 */ |
| 504 | [19002] = 0x0000, /* R19002 - ADCR_RETUNE_C30_1 */ |
| 505 | [19003] = 0x0000, /* R19003 - ADCR_RETUNE_C30_0 */ |
| 506 | [19004] = 0x0000, /* R19004 - ADCR_RETUNE_C31_1 */ |
| 507 | [19005] = 0x0000, /* R19005 - ADCR_RETUNE_C31_0 */ |
| 508 | [19006] = 0x0000, /* R19006 - ADCR_RETUNE_C32_1 */ |
| 509 | [19007] = 0x0000, /* R19007 - ADCR_RETUNE_C32_0 */ |
| 510 | |
| 511 | [19456] = 0x007F, /* R19456 - DACL_RETUNE_C1_1 */ |
| 512 | [19457] = 0xFFFF, /* R19457 - DACL_RETUNE_C1_0 */ |
| 513 | [19458] = 0x0000, /* R19458 - DACL_RETUNE_C2_1 */ |
| 514 | [19459] = 0x0000, /* R19459 - DACL_RETUNE_C2_0 */ |
| 515 | [19460] = 0x0000, /* R19460 - DACL_RETUNE_C3_1 */ |
| 516 | [19461] = 0x0000, /* R19461 - DACL_RETUNE_C3_0 */ |
| 517 | [19462] = 0x0000, /* R19462 - DACL_RETUNE_C4_1 */ |
| 518 | [19463] = 0x0000, /* R19463 - DACL_RETUNE_C4_0 */ |
| 519 | [19464] = 0x0000, /* R19464 - DACL_RETUNE_C5_1 */ |
| 520 | [19465] = 0x0000, /* R19465 - DACL_RETUNE_C5_0 */ |
| 521 | [19466] = 0x0000, /* R19466 - DACL_RETUNE_C6_1 */ |
| 522 | [19467] = 0x0000, /* R19467 - DACL_RETUNE_C6_0 */ |
| 523 | [19468] = 0x0000, /* R19468 - DACL_RETUNE_C7_1 */ |
| 524 | [19469] = 0x0000, /* R19469 - DACL_RETUNE_C7_0 */ |
| 525 | [19470] = 0x0000, /* R19470 - DACL_RETUNE_C8_1 */ |
| 526 | [19471] = 0x0000, /* R19471 - DACL_RETUNE_C8_0 */ |
| 527 | [19472] = 0x0000, /* R19472 - DACL_RETUNE_C9_1 */ |
| 528 | [19473] = 0x0000, /* R19473 - DACL_RETUNE_C9_0 */ |
| 529 | [19474] = 0x0000, /* R19474 - DACL_RETUNE_C10_1 */ |
| 530 | [19475] = 0x0000, /* R19475 - DACL_RETUNE_C10_0 */ |
| 531 | [19476] = 0x0000, /* R19476 - DACL_RETUNE_C11_1 */ |
| 532 | [19477] = 0x0000, /* R19477 - DACL_RETUNE_C11_0 */ |
| 533 | [19478] = 0x0000, /* R19478 - DACL_RETUNE_C12_1 */ |
| 534 | [19479] = 0x0000, /* R19479 - DACL_RETUNE_C12_0 */ |
| 535 | [19480] = 0x0000, /* R19480 - DACL_RETUNE_C13_1 */ |
| 536 | [19481] = 0x0000, /* R19481 - DACL_RETUNE_C13_0 */ |
| 537 | [19482] = 0x0000, /* R19482 - DACL_RETUNE_C14_1 */ |
| 538 | [19483] = 0x0000, /* R19483 - DACL_RETUNE_C14_0 */ |
| 539 | [19484] = 0x0000, /* R19484 - DACL_RETUNE_C15_1 */ |
| 540 | [19485] = 0x0000, /* R19485 - DACL_RETUNE_C15_0 */ |
| 541 | [19486] = 0x0000, /* R19486 - DACL_RETUNE_C16_1 */ |
| 542 | [19487] = 0x0000, /* R19487 - DACL_RETUNE_C16_0 */ |
| 543 | [19488] = 0x0000, /* R19488 - DACL_RETUNE_C17_1 */ |
| 544 | [19489] = 0x0000, /* R19489 - DACL_RETUNE_C17_0 */ |
| 545 | [19490] = 0x0000, /* R19490 - DACL_RETUNE_C18_1 */ |
| 546 | [19491] = 0x0000, /* R19491 - DACL_RETUNE_C18_0 */ |
| 547 | [19492] = 0x0000, /* R19492 - DACL_RETUNE_C19_1 */ |
| 548 | [19493] = 0x0000, /* R19493 - DACL_RETUNE_C19_0 */ |
| 549 | [19494] = 0x0000, /* R19494 - DACL_RETUNE_C20_1 */ |
| 550 | [19495] = 0x0000, /* R19495 - DACL_RETUNE_C20_0 */ |
| 551 | [19496] = 0x0000, /* R19496 - DACL_RETUNE_C21_1 */ |
| 552 | [19497] = 0x0000, /* R19497 - DACL_RETUNE_C21_0 */ |
| 553 | [19498] = 0x0000, /* R19498 - DACL_RETUNE_C22_1 */ |
| 554 | [19499] = 0x0000, /* R19499 - DACL_RETUNE_C22_0 */ |
| 555 | [19500] = 0x0000, /* R19500 - DACL_RETUNE_C23_1 */ |
| 556 | [19501] = 0x0000, /* R19501 - DACL_RETUNE_C23_0 */ |
| 557 | [19502] = 0x0000, /* R19502 - DACL_RETUNE_C24_1 */ |
| 558 | [19503] = 0x0000, /* R19503 - DACL_RETUNE_C24_0 */ |
| 559 | [19504] = 0x0000, /* R19504 - DACL_RETUNE_C25_1 */ |
| 560 | [19505] = 0x0000, /* R19505 - DACL_RETUNE_C25_0 */ |
| 561 | [19506] = 0x0000, /* R19506 - DACL_RETUNE_C26_1 */ |
| 562 | [19507] = 0x0000, /* R19507 - DACL_RETUNE_C26_0 */ |
| 563 | [19508] = 0x0000, /* R19508 - DACL_RETUNE_C27_1 */ |
| 564 | [19509] = 0x0000, /* R19509 - DACL_RETUNE_C27_0 */ |
| 565 | [19510] = 0x0000, /* R19510 - DACL_RETUNE_C28_1 */ |
| 566 | [19511] = 0x0000, /* R19511 - DACL_RETUNE_C28_0 */ |
| 567 | [19512] = 0x0000, /* R19512 - DACL_RETUNE_C29_1 */ |
| 568 | [19513] = 0x0000, /* R19513 - DACL_RETUNE_C29_0 */ |
| 569 | [19514] = 0x0000, /* R19514 - DACL_RETUNE_C30_1 */ |
| 570 | [19515] = 0x0000, /* R19515 - DACL_RETUNE_C30_0 */ |
| 571 | [19516] = 0x0000, /* R19516 - DACL_RETUNE_C31_1 */ |
| 572 | [19517] = 0x0000, /* R19517 - DACL_RETUNE_C31_0 */ |
| 573 | [19518] = 0x0000, /* R19518 - DACL_RETUNE_C32_1 */ |
| 574 | [19519] = 0x0000, /* R19519 - DACL_RETUNE_C32_0 */ |
| 575 | |
| 576 | [19968] = 0x0020, /* R19968 - RETUNEDAC_PG2_1 */ |
| 577 | [19969] = 0x0000, /* R19969 - RETUNEDAC_PG2_0 */ |
| 578 | [19970] = 0x0040, /* R19970 - RETUNEDAC_PG_1 */ |
| 579 | [19971] = 0x0000, /* R19971 - RETUNEDAC_PG_0 */ |
| 580 | |
| 581 | [20480] = 0x007F, /* R20480 - DACR_RETUNE_C1_1 */ |
| 582 | [20481] = 0xFFFF, /* R20481 - DACR_RETUNE_C1_0 */ |
| 583 | [20482] = 0x0000, /* R20482 - DACR_RETUNE_C2_1 */ |
| 584 | [20483] = 0x0000, /* R20483 - DACR_RETUNE_C2_0 */ |
| 585 | [20484] = 0x0000, /* R20484 - DACR_RETUNE_C3_1 */ |
| 586 | [20485] = 0x0000, /* R20485 - DACR_RETUNE_C3_0 */ |
| 587 | [20486] = 0x0000, /* R20486 - DACR_RETUNE_C4_1 */ |
| 588 | [20487] = 0x0000, /* R20487 - DACR_RETUNE_C4_0 */ |
| 589 | [20488] = 0x0000, /* R20488 - DACR_RETUNE_C5_1 */ |
| 590 | [20489] = 0x0000, /* R20489 - DACR_RETUNE_C5_0 */ |
| 591 | [20490] = 0x0000, /* R20490 - DACR_RETUNE_C6_1 */ |
| 592 | [20491] = 0x0000, /* R20491 - DACR_RETUNE_C6_0 */ |
| 593 | [20492] = 0x0000, /* R20492 - DACR_RETUNE_C7_1 */ |
| 594 | [20493] = 0x0000, /* R20493 - DACR_RETUNE_C7_0 */ |
| 595 | [20494] = 0x0000, /* R20494 - DACR_RETUNE_C8_1 */ |
| 596 | [20495] = 0x0000, /* R20495 - DACR_RETUNE_C8_0 */ |
| 597 | [20496] = 0x0000, /* R20496 - DACR_RETUNE_C9_1 */ |
| 598 | [20497] = 0x0000, /* R20497 - DACR_RETUNE_C9_0 */ |
| 599 | [20498] = 0x0000, /* R20498 - DACR_RETUNE_C10_1 */ |
| 600 | [20499] = 0x0000, /* R20499 - DACR_RETUNE_C10_0 */ |
| 601 | [20500] = 0x0000, /* R20500 - DACR_RETUNE_C11_1 */ |
| 602 | [20501] = 0x0000, /* R20501 - DACR_RETUNE_C11_0 */ |
| 603 | [20502] = 0x0000, /* R20502 - DACR_RETUNE_C12_1 */ |
| 604 | [20503] = 0x0000, /* R20503 - DACR_RETUNE_C12_0 */ |
| 605 | [20504] = 0x0000, /* R20504 - DACR_RETUNE_C13_1 */ |
| 606 | [20505] = 0x0000, /* R20505 - DACR_RETUNE_C13_0 */ |
| 607 | [20506] = 0x0000, /* R20506 - DACR_RETUNE_C14_1 */ |
| 608 | [20507] = 0x0000, /* R20507 - DACR_RETUNE_C14_0 */ |
| 609 | [20508] = 0x0000, /* R20508 - DACR_RETUNE_C15_1 */ |
| 610 | [20509] = 0x0000, /* R20509 - DACR_RETUNE_C15_0 */ |
| 611 | [20510] = 0x0000, /* R20510 - DACR_RETUNE_C16_1 */ |
| 612 | [20511] = 0x0000, /* R20511 - DACR_RETUNE_C16_0 */ |
| 613 | [20512] = 0x0000, /* R20512 - DACR_RETUNE_C17_1 */ |
| 614 | [20513] = 0x0000, /* R20513 - DACR_RETUNE_C17_0 */ |
| 615 | [20514] = 0x0000, /* R20514 - DACR_RETUNE_C18_1 */ |
| 616 | [20515] = 0x0000, /* R20515 - DACR_RETUNE_C18_0 */ |
| 617 | [20516] = 0x0000, /* R20516 - DACR_RETUNE_C19_1 */ |
| 618 | [20517] = 0x0000, /* R20517 - DACR_RETUNE_C19_0 */ |
| 619 | [20518] = 0x0000, /* R20518 - DACR_RETUNE_C20_1 */ |
| 620 | [20519] = 0x0000, /* R20519 - DACR_RETUNE_C20_0 */ |
| 621 | [20520] = 0x0000, /* R20520 - DACR_RETUNE_C21_1 */ |
| 622 | [20521] = 0x0000, /* R20521 - DACR_RETUNE_C21_0 */ |
| 623 | [20522] = 0x0000, /* R20522 - DACR_RETUNE_C22_1 */ |
| 624 | [20523] = 0x0000, /* R20523 - DACR_RETUNE_C22_0 */ |
| 625 | [20524] = 0x0000, /* R20524 - DACR_RETUNE_C23_1 */ |
| 626 | [20525] = 0x0000, /* R20525 - DACR_RETUNE_C23_0 */ |
| 627 | [20526] = 0x0000, /* R20526 - DACR_RETUNE_C24_1 */ |
| 628 | [20527] = 0x0000, /* R20527 - DACR_RETUNE_C24_0 */ |
| 629 | [20528] = 0x0000, /* R20528 - DACR_RETUNE_C25_1 */ |
| 630 | [20529] = 0x0000, /* R20529 - DACR_RETUNE_C25_0 */ |
| 631 | [20530] = 0x0000, /* R20530 - DACR_RETUNE_C26_1 */ |
| 632 | [20531] = 0x0000, /* R20531 - DACR_RETUNE_C26_0 */ |
| 633 | [20532] = 0x0000, /* R20532 - DACR_RETUNE_C27_1 */ |
| 634 | [20533] = 0x0000, /* R20533 - DACR_RETUNE_C27_0 */ |
| 635 | [20534] = 0x0000, /* R20534 - DACR_RETUNE_C28_1 */ |
| 636 | [20535] = 0x0000, /* R20535 - DACR_RETUNE_C28_0 */ |
| 637 | [20536] = 0x0000, /* R20536 - DACR_RETUNE_C29_1 */ |
| 638 | [20537] = 0x0000, /* R20537 - DACR_RETUNE_C29_0 */ |
| 639 | [20538] = 0x0000, /* R20538 - DACR_RETUNE_C30_1 */ |
| 640 | [20539] = 0x0000, /* R20539 - DACR_RETUNE_C30_0 */ |
| 641 | [20540] = 0x0000, /* R20540 - DACR_RETUNE_C31_1 */ |
| 642 | [20541] = 0x0000, /* R20541 - DACR_RETUNE_C31_0 */ |
| 643 | [20542] = 0x0000, /* R20542 - DACR_RETUNE_C32_1 */ |
| 644 | [20543] = 0x0000, /* R20543 - DACR_RETUNE_C32_0 */ |
| 645 | |
| 646 | [20992] = 0x008C, /* R20992 - VSS_XHD2_1 */ |
| 647 | [20993] = 0x0200, /* R20993 - VSS_XHD2_0 */ |
| 648 | [20994] = 0x0035, /* R20994 - VSS_XHD3_1 */ |
| 649 | [20995] = 0x0700, /* R20995 - VSS_XHD3_0 */ |
| 650 | [20996] = 0x003A, /* R20996 - VSS_XHN1_1 */ |
| 651 | [20997] = 0x4100, /* R20997 - VSS_XHN1_0 */ |
| 652 | [20998] = 0x008B, /* R20998 - VSS_XHN2_1 */ |
| 653 | [20999] = 0x7D00, /* R20999 - VSS_XHN2_0 */ |
| 654 | [21000] = 0x003A, /* R21000 - VSS_XHN3_1 */ |
| 655 | [21001] = 0x4100, /* R21001 - VSS_XHN3_0 */ |
| 656 | [21002] = 0x008C, /* R21002 - VSS_XLA_1 */ |
| 657 | [21003] = 0xFEE8, /* R21003 - VSS_XLA_0 */ |
| 658 | [21004] = 0x0078, /* R21004 - VSS_XLB_1 */ |
| 659 | [21005] = 0x0000, /* R21005 - VSS_XLB_0 */ |
| 660 | [21006] = 0x003F, /* R21006 - VSS_XLG_1 */ |
| 661 | [21007] = 0xB260, /* R21007 - VSS_XLG_0 */ |
| 662 | [21008] = 0x002D, /* R21008 - VSS_PG2_1 */ |
| 663 | [21009] = 0x1818, /* R21009 - VSS_PG2_0 */ |
| 664 | [21010] = 0x0020, /* R21010 - VSS_PG_1 */ |
| 665 | [21011] = 0x0000, /* R21011 - VSS_PG_0 */ |
| 666 | [21012] = 0x00F1, /* R21012 - VSS_XTD1_1 */ |
| 667 | [21013] = 0x8340, /* R21013 - VSS_XTD1_0 */ |
| 668 | [21014] = 0x00FB, /* R21014 - VSS_XTD2_1 */ |
| 669 | [21015] = 0x8300, /* R21015 - VSS_XTD2_0 */ |
| 670 | [21016] = 0x00EE, /* R21016 - VSS_XTD3_1 */ |
| 671 | [21017] = 0xAEC0, /* R21017 - VSS_XTD3_0 */ |
| 672 | [21018] = 0x00FB, /* R21018 - VSS_XTD4_1 */ |
| 673 | [21019] = 0xAC40, /* R21019 - VSS_XTD4_0 */ |
| 674 | [21020] = 0x00F1, /* R21020 - VSS_XTD5_1 */ |
| 675 | [21021] = 0x7F80, /* R21021 - VSS_XTD5_0 */ |
| 676 | [21022] = 0x00F4, /* R21022 - VSS_XTD6_1 */ |
| 677 | [21023] = 0x3B40, /* R21023 - VSS_XTD6_0 */ |
| 678 | [21024] = 0x00F5, /* R21024 - VSS_XTD7_1 */ |
| 679 | [21025] = 0xFB00, /* R21025 - VSS_XTD7_0 */ |
| 680 | [21026] = 0x00EA, /* R21026 - VSS_XTD8_1 */ |
| 681 | [21027] = 0x10C0, /* R21027 - VSS_XTD8_0 */ |
| 682 | [21028] = 0x00FC, /* R21028 - VSS_XTD9_1 */ |
| 683 | [21029] = 0xC580, /* R21029 - VSS_XTD9_0 */ |
| 684 | [21030] = 0x00E2, /* R21030 - VSS_XTD10_1 */ |
| 685 | [21031] = 0x75C0, /* R21031 - VSS_XTD10_0 */ |
| 686 | [21032] = 0x0004, /* R21032 - VSS_XTD11_1 */ |
| 687 | [21033] = 0xB480, /* R21033 - VSS_XTD11_0 */ |
| 688 | [21034] = 0x00D4, /* R21034 - VSS_XTD12_1 */ |
| 689 | [21035] = 0xF980, /* R21035 - VSS_XTD12_0 */ |
| 690 | [21036] = 0x0004, /* R21036 - VSS_XTD13_1 */ |
| 691 | [21037] = 0x9140, /* R21037 - VSS_XTD13_0 */ |
| 692 | [21038] = 0x00D8, /* R21038 - VSS_XTD14_1 */ |
| 693 | [21039] = 0xA480, /* R21039 - VSS_XTD14_0 */ |
| 694 | [21040] = 0x0002, /* R21040 - VSS_XTD15_1 */ |
| 695 | [21041] = 0x3DC0, /* R21041 - VSS_XTD15_0 */ |
| 696 | [21042] = 0x00CF, /* R21042 - VSS_XTD16_1 */ |
| 697 | [21043] = 0x7A80, /* R21043 - VSS_XTD16_0 */ |
| 698 | [21044] = 0x00DC, /* R21044 - VSS_XTD17_1 */ |
| 699 | [21045] = 0x0600, /* R21045 - VSS_XTD17_0 */ |
| 700 | [21046] = 0x00F2, /* R21046 - VSS_XTD18_1 */ |
| 701 | [21047] = 0xDAC0, /* R21047 - VSS_XTD18_0 */ |
| 702 | [21048] = 0x00BA, /* R21048 - VSS_XTD19_1 */ |
| 703 | [21049] = 0xF340, /* R21049 - VSS_XTD19_0 */ |
| 704 | [21050] = 0x000A, /* R21050 - VSS_XTD20_1 */ |
| 705 | [21051] = 0x7940, /* R21051 - VSS_XTD20_0 */ |
| 706 | [21052] = 0x001C, /* R21052 - VSS_XTD21_1 */ |
| 707 | [21053] = 0x0680, /* R21053 - VSS_XTD21_0 */ |
| 708 | [21054] = 0x00FD, /* R21054 - VSS_XTD22_1 */ |
| 709 | [21055] = 0x2D00, /* R21055 - VSS_XTD22_0 */ |
| 710 | [21056] = 0x001C, /* R21056 - VSS_XTD23_1 */ |
| 711 | [21057] = 0xE840, /* R21057 - VSS_XTD23_0 */ |
| 712 | [21058] = 0x000D, /* R21058 - VSS_XTD24_1 */ |
| 713 | [21059] = 0xDC40, /* R21059 - VSS_XTD24_0 */ |
| 714 | [21060] = 0x00FC, /* R21060 - VSS_XTD25_1 */ |
| 715 | [21061] = 0x9D00, /* R21061 - VSS_XTD25_0 */ |
| 716 | [21062] = 0x0009, /* R21062 - VSS_XTD26_1 */ |
| 717 | [21063] = 0x5580, /* R21063 - VSS_XTD26_0 */ |
| 718 | [21064] = 0x00FE, /* R21064 - VSS_XTD27_1 */ |
| 719 | [21065] = 0x7E80, /* R21065 - VSS_XTD27_0 */ |
| 720 | [21066] = 0x000E, /* R21066 - VSS_XTD28_1 */ |
| 721 | [21067] = 0xAB40, /* R21067 - VSS_XTD28_0 */ |
| 722 | [21068] = 0x00F9, /* R21068 - VSS_XTD29_1 */ |
| 723 | [21069] = 0x9880, /* R21069 - VSS_XTD29_0 */ |
| 724 | [21070] = 0x0009, /* R21070 - VSS_XTD30_1 */ |
| 725 | [21071] = 0x87C0, /* R21071 - VSS_XTD30_0 */ |
| 726 | [21072] = 0x00FD, /* R21072 - VSS_XTD31_1 */ |
| 727 | [21073] = 0x2C40, /* R21073 - VSS_XTD31_0 */ |
| 728 | [21074] = 0x0009, /* R21074 - VSS_XTD32_1 */ |
| 729 | [21075] = 0x4800, /* R21075 - VSS_XTD32_0 */ |
| 730 | [21076] = 0x0003, /* R21076 - VSS_XTS1_1 */ |
| 731 | [21077] = 0x5F40, /* R21077 - VSS_XTS1_0 */ |
| 732 | [21078] = 0x0000, /* R21078 - VSS_XTS2_1 */ |
| 733 | [21079] = 0x8700, /* R21079 - VSS_XTS2_0 */ |
| 734 | [21080] = 0x00FA, /* R21080 - VSS_XTS3_1 */ |
| 735 | [21081] = 0xE4C0, /* R21081 - VSS_XTS3_0 */ |
| 736 | [21082] = 0x0000, /* R21082 - VSS_XTS4_1 */ |
| 737 | [21083] = 0x0B40, /* R21083 - VSS_XTS4_0 */ |
| 738 | [21084] = 0x0004, /* R21084 - VSS_XTS5_1 */ |
| 739 | [21085] = 0xE180, /* R21085 - VSS_XTS5_0 */ |
| 740 | [21086] = 0x0001, /* R21086 - VSS_XTS6_1 */ |
| 741 | [21087] = 0x1F40, /* R21087 - VSS_XTS6_0 */ |
| 742 | [21088] = 0x00F8, /* R21088 - VSS_XTS7_1 */ |
| 743 | [21089] = 0xB000, /* R21089 - VSS_XTS7_0 */ |
| 744 | [21090] = 0x00FB, /* R21090 - VSS_XTS8_1 */ |
| 745 | [21091] = 0xCBC0, /* R21091 - VSS_XTS8_0 */ |
| 746 | [21092] = 0x0004, /* R21092 - VSS_XTS9_1 */ |
| 747 | [21093] = 0xF380, /* R21093 - VSS_XTS9_0 */ |
| 748 | [21094] = 0x0007, /* R21094 - VSS_XTS10_1 */ |
| 749 | [21095] = 0xDF40, /* R21095 - VSS_XTS10_0 */ |
| 750 | [21096] = 0x00FF, /* R21096 - VSS_XTS11_1 */ |
| 751 | [21097] = 0x0700, /* R21097 - VSS_XTS11_0 */ |
| 752 | [21098] = 0x00EF, /* R21098 - VSS_XTS12_1 */ |
| 753 | [21099] = 0xD700, /* R21099 - VSS_XTS12_0 */ |
| 754 | [21100] = 0x00FB, /* R21100 - VSS_XTS13_1 */ |
| 755 | [21101] = 0xAF40, /* R21101 - VSS_XTS13_0 */ |
| 756 | [21102] = 0x0010, /* R21102 - VSS_XTS14_1 */ |
| 757 | [21103] = 0x8A80, /* R21103 - VSS_XTS14_0 */ |
| 758 | [21104] = 0x0011, /* R21104 - VSS_XTS15_1 */ |
| 759 | [21105] = 0x07C0, /* R21105 - VSS_XTS15_0 */ |
| 760 | [21106] = 0x00E0, /* R21106 - VSS_XTS16_1 */ |
| 761 | [21107] = 0x0800, /* R21107 - VSS_XTS16_0 */ |
| 762 | [21108] = 0x00D2, /* R21108 - VSS_XTS17_1 */ |
| 763 | [21109] = 0x7600, /* R21109 - VSS_XTS17_0 */ |
| 764 | [21110] = 0x0020, /* R21110 - VSS_XTS18_1 */ |
| 765 | [21111] = 0xCF40, /* R21111 - VSS_XTS18_0 */ |
| 766 | [21112] = 0x0030, /* R21112 - VSS_XTS19_1 */ |
| 767 | [21113] = 0x2340, /* R21113 - VSS_XTS19_0 */ |
| 768 | [21114] = 0x00FD, /* R21114 - VSS_XTS20_1 */ |
| 769 | [21115] = 0x69C0, /* R21115 - VSS_XTS20_0 */ |
| 770 | [21116] = 0x0028, /* R21116 - VSS_XTS21_1 */ |
| 771 | [21117] = 0x3500, /* R21117 - VSS_XTS21_0 */ |
| 772 | [21118] = 0x0006, /* R21118 - VSS_XTS22_1 */ |
| 773 | [21119] = 0x3300, /* R21119 - VSS_XTS22_0 */ |
| 774 | [21120] = 0x00D9, /* R21120 - VSS_XTS23_1 */ |
| 775 | [21121] = 0xF6C0, /* R21121 - VSS_XTS23_0 */ |
| 776 | [21122] = 0x00F3, /* R21122 - VSS_XTS24_1 */ |
| 777 | [21123] = 0x3340, /* R21123 - VSS_XTS24_0 */ |
| 778 | [21124] = 0x000F, /* R21124 - VSS_XTS25_1 */ |
| 779 | [21125] = 0x4200, /* R21125 - VSS_XTS25_0 */ |
| 780 | [21126] = 0x0004, /* R21126 - VSS_XTS26_1 */ |
| 781 | [21127] = 0x0C80, /* R21127 - VSS_XTS26_0 */ |
| 782 | [21128] = 0x00FB, /* R21128 - VSS_XTS27_1 */ |
| 783 | [21129] = 0x3F80, /* R21129 - VSS_XTS27_0 */ |
| 784 | [21130] = 0x00F7, /* R21130 - VSS_XTS28_1 */ |
| 785 | [21131] = 0x57C0, /* R21131 - VSS_XTS28_0 */ |
| 786 | [21132] = 0x0003, /* R21132 - VSS_XTS29_1 */ |
| 787 | [21133] = 0x5400, /* R21133 - VSS_XTS29_0 */ |
| 788 | [21134] = 0x0000, /* R21134 - VSS_XTS30_1 */ |
| 789 | [21135] = 0xC6C0, /* R21135 - VSS_XTS30_0 */ |
| 790 | [21136] = 0x0003, /* R21136 - VSS_XTS31_1 */ |
| 791 | [21137] = 0x12C0, /* R21137 - VSS_XTS31_0 */ |
| 792 | [21138] = 0x00FD, /* R21138 - VSS_XTS32_1 */ |
| 793 | [21139] = 0x8580, /* R21139 - VSS_XTS32_0 */ |
| 794 | }; |
| 795 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 796 | static int wm8962_volatile_register(unsigned int reg) |
| 797 | { |
| 798 | if (wm8962_reg_access[reg].vol) |
| 799 | return 1; |
| 800 | else |
| 801 | return 0; |
| 802 | } |
| 803 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 804 | static int wm8962_readable_register(unsigned int reg) |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 805 | { |
| 806 | if (wm8962_reg_access[reg].read) |
| 807 | return 1; |
| 808 | else |
| 809 | return 0; |
| 810 | } |
| 811 | |
| 812 | static int wm8962_reset(struct snd_soc_codec *codec) |
| 813 | { |
| 814 | return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0); |
| 815 | } |
| 816 | |
| 817 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); |
| 818 | static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); |
| 819 | static const unsigned int mixinpga_tlv[] = { |
| 820 | TLV_DB_RANGE_HEAD(7), |
| 821 | 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), |
| 822 | 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), |
| 823 | 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), |
| 824 | 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), |
| 825 | 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0), |
| 826 | }; |
| 827 | static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); |
| 828 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); |
| 829 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); |
| 830 | static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); |
| 831 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); |
| 832 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); |
| 833 | static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); |
| 834 | static const unsigned int classd_tlv[] = { |
| 835 | TLV_DB_RANGE_HEAD(7), |
| 836 | 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), |
| 837 | 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0), |
| 838 | }; |
| 839 | |
| 840 | /* The VU bits for the headphones are in a different register to the mute |
| 841 | * bits and only take effect on the PGA if it is actually powered. |
| 842 | */ |
| 843 | static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, |
| 844 | struct snd_ctl_elem_value *ucontrol) |
| 845 | { |
| 846 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 847 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 848 | u16 *reg_cache = wm8962->reg_cache; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 849 | int ret; |
| 850 | |
| 851 | /* Apply the update (if any) */ |
| 852 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
| 853 | if (ret == 0) |
| 854 | return 0; |
| 855 | |
| 856 | /* If the left PGA is enabled hit that VU bit... */ |
| 857 | if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA) |
| 858 | return snd_soc_write(codec, WM8962_HPOUTL_VOLUME, |
| 859 | reg_cache[WM8962_HPOUTL_VOLUME]); |
| 860 | |
| 861 | /* ...otherwise the right. The VU is stereo. */ |
| 862 | if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA) |
| 863 | return snd_soc_write(codec, WM8962_HPOUTR_VOLUME, |
| 864 | reg_cache[WM8962_HPOUTR_VOLUME]); |
| 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
| 869 | /* The VU bits for the speakers are in a different register to the mute |
| 870 | * bits and only take effect on the PGA if it is actually powered. |
| 871 | */ |
| 872 | static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, |
| 873 | struct snd_ctl_elem_value *ucontrol) |
| 874 | { |
| 875 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 876 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 877 | u16 *reg_cache = wm8962->reg_cache; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 878 | int ret; |
| 879 | |
| 880 | /* Apply the update (if any) */ |
| 881 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
| 882 | if (ret == 0) |
| 883 | return 0; |
| 884 | |
| 885 | /* If the left PGA is enabled hit that VU bit... */ |
| 886 | if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA) |
| 887 | return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME, |
| 888 | reg_cache[WM8962_SPKOUTL_VOLUME]); |
| 889 | |
| 890 | /* ...otherwise the right. The VU is stereo. */ |
| 891 | if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA) |
| 892 | return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME, |
| 893 | reg_cache[WM8962_SPKOUTR_VOLUME]); |
| 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | static const struct snd_kcontrol_new wm8962_snd_controls[] = { |
| 899 | SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), |
| 900 | |
| 901 | SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, |
| 902 | mixin_tlv), |
| 903 | SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, |
| 904 | mixinpga_tlv), |
| 905 | SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, |
| 906 | mixin_tlv), |
| 907 | |
| 908 | SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, |
| 909 | mixin_tlv), |
| 910 | SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, |
| 911 | mixinpga_tlv), |
| 912 | SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, |
| 913 | mixin_tlv), |
| 914 | |
| 915 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, |
| 916 | WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), |
| 917 | SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, |
| 918 | WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), |
| 919 | SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, |
| 920 | WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), |
| 921 | SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, |
| 922 | WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), |
| 923 | |
| 924 | SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, |
| 925 | WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), |
| 926 | |
| 927 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, |
| 928 | WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), |
| 929 | SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), |
| 930 | |
| 931 | SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, |
| 932 | 5, 1, 0), |
| 933 | |
| 934 | SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), |
| 935 | |
| 936 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, |
| 937 | WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), |
| 938 | SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, |
| 939 | snd_soc_get_volsw, wm8962_put_hp_sw), |
| 940 | SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, |
| 941 | 7, 1, 0), |
| 942 | SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, |
| 943 | hp_tlv), |
| 944 | |
| 945 | SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, |
| 946 | WM8962_HEADPHONE_MIXER_4, 8, 1, 1), |
| 947 | |
| 948 | SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, |
| 949 | 3, 7, 0, bypass_tlv), |
| 950 | SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, |
| 951 | 0, 7, 0, bypass_tlv), |
| 952 | SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, |
| 953 | 7, 1, 1, inmix_tlv), |
| 954 | SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, |
| 955 | 6, 1, 1, inmix_tlv), |
| 956 | |
| 957 | SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, |
| 958 | 3, 7, 0, bypass_tlv), |
| 959 | SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, |
| 960 | 0, 7, 0, bypass_tlv), |
| 961 | SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, |
| 962 | 7, 1, 1, inmix_tlv), |
| 963 | SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, |
| 964 | 6, 1, 1, inmix_tlv), |
| 965 | |
| 966 | SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, |
| 967 | classd_tlv), |
| 968 | }; |
| 969 | |
| 970 | static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { |
| 971 | SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), |
| 972 | SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, |
| 973 | snd_soc_get_volsw, wm8962_put_spk_sw), |
| 974 | SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), |
| 975 | |
| 976 | SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), |
| 977 | SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, |
| 978 | 3, 7, 0, bypass_tlv), |
| 979 | SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, |
| 980 | 0, 7, 0, bypass_tlv), |
| 981 | SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, |
| 982 | 7, 1, 1, inmix_tlv), |
| 983 | SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, |
| 984 | 6, 1, 1, inmix_tlv), |
| 985 | SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, |
| 986 | 7, 1, 0, inmix_tlv), |
| 987 | SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, |
| 988 | 6, 1, 0, inmix_tlv), |
| 989 | }; |
| 990 | |
| 991 | static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { |
| 992 | SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, |
| 993 | WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), |
| 994 | SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, |
| 995 | snd_soc_get_volsw, wm8962_put_spk_sw), |
| 996 | SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, |
| 997 | 7, 1, 0), |
| 998 | |
| 999 | SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, |
| 1000 | WM8962_SPEAKER_MIXER_4, 8, 1, 1), |
| 1001 | |
| 1002 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, |
| 1003 | 3, 7, 0, bypass_tlv), |
| 1004 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, |
| 1005 | 0, 7, 0, bypass_tlv), |
| 1006 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, |
| 1007 | 7, 1, 1, inmix_tlv), |
| 1008 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, |
| 1009 | 6, 1, 1, inmix_tlv), |
| 1010 | SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, |
| 1011 | 7, 1, 0, inmix_tlv), |
| 1012 | SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, |
| 1013 | 6, 1, 0, inmix_tlv), |
| 1014 | |
| 1015 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, |
| 1016 | 3, 7, 0, bypass_tlv), |
| 1017 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, |
| 1018 | 0, 7, 0, bypass_tlv), |
| 1019 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, |
| 1020 | 7, 1, 1, inmix_tlv), |
| 1021 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, |
| 1022 | 6, 1, 1, inmix_tlv), |
| 1023 | SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, |
| 1024 | 5, 1, 0, inmix_tlv), |
| 1025 | SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, |
| 1026 | 4, 1, 0, inmix_tlv), |
| 1027 | }; |
| 1028 | |
| 1029 | static int sysclk_event(struct snd_soc_dapm_widget *w, |
| 1030 | struct snd_kcontrol *kcontrol, int event) |
| 1031 | { |
| 1032 | struct snd_soc_codec *codec = w->codec; |
| 1033 | int src; |
| 1034 | int fll; |
| 1035 | |
| 1036 | src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK; |
| 1037 | |
| 1038 | switch (src) { |
| 1039 | case 0: /* MCLK */ |
| 1040 | fll = 0; |
| 1041 | break; |
| 1042 | case 0x200: /* FLL */ |
| 1043 | fll = 1; |
| 1044 | break; |
| 1045 | default: |
| 1046 | dev_err(codec->dev, "Unknown SYSCLK source %x\n", src); |
| 1047 | return -EINVAL; |
| 1048 | } |
| 1049 | |
| 1050 | switch (event) { |
| 1051 | case SND_SOC_DAPM_PRE_PMU: |
| 1052 | if (fll) |
| 1053 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
| 1054 | WM8962_FLL_ENA, WM8962_FLL_ENA); |
| 1055 | break; |
| 1056 | |
| 1057 | case SND_SOC_DAPM_POST_PMD: |
| 1058 | if (fll) |
| 1059 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
| 1060 | WM8962_FLL_ENA, 0); |
| 1061 | break; |
| 1062 | |
| 1063 | default: |
| 1064 | BUG(); |
| 1065 | return -EINVAL; |
| 1066 | } |
| 1067 | |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
| 1071 | static int cp_event(struct snd_soc_dapm_widget *w, |
| 1072 | struct snd_kcontrol *kcontrol, int event) |
| 1073 | { |
| 1074 | switch (event) { |
| 1075 | case SND_SOC_DAPM_POST_PMU: |
| 1076 | msleep(5); |
| 1077 | break; |
| 1078 | |
| 1079 | default: |
| 1080 | BUG(); |
| 1081 | return -EINVAL; |
| 1082 | } |
| 1083 | |
| 1084 | return 0; |
| 1085 | } |
| 1086 | |
| 1087 | static int hp_event(struct snd_soc_dapm_widget *w, |
| 1088 | struct snd_kcontrol *kcontrol, int event) |
| 1089 | { |
| 1090 | struct snd_soc_codec *codec = w->codec; |
| 1091 | int timeout; |
| 1092 | int reg; |
| 1093 | int expected = (WM8962_DCS_STARTUP_DONE_HP1L | |
| 1094 | WM8962_DCS_STARTUP_DONE_HP1R); |
| 1095 | |
| 1096 | switch (event) { |
| 1097 | case SND_SOC_DAPM_POST_PMU: |
| 1098 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, |
| 1099 | WM8962_HP1L_ENA | WM8962_HP1R_ENA, |
| 1100 | WM8962_HP1L_ENA | WM8962_HP1R_ENA); |
| 1101 | udelay(20); |
| 1102 | |
| 1103 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, |
| 1104 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, |
| 1105 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); |
| 1106 | |
| 1107 | /* Start the DC servo */ |
| 1108 | snd_soc_update_bits(codec, WM8962_DC_SERVO_1, |
| 1109 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | |
| 1110 | WM8962_HP1L_DCS_STARTUP | |
| 1111 | WM8962_HP1R_DCS_STARTUP, |
| 1112 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | |
| 1113 | WM8962_HP1L_DCS_STARTUP | |
| 1114 | WM8962_HP1R_DCS_STARTUP); |
| 1115 | |
| 1116 | /* Wait for it to complete, should be well under 100ms */ |
| 1117 | timeout = 0; |
| 1118 | do { |
| 1119 | msleep(1); |
| 1120 | reg = snd_soc_read(codec, WM8962_DC_SERVO_6); |
| 1121 | if (reg < 0) { |
| 1122 | dev_err(codec->dev, |
| 1123 | "Failed to read DCS status: %d\n", |
| 1124 | reg); |
| 1125 | continue; |
| 1126 | } |
| 1127 | dev_dbg(codec->dev, "DCS status: %x\n", reg); |
| 1128 | } while (++timeout < 200 && (reg & expected) != expected); |
| 1129 | |
| 1130 | if ((reg & expected) != expected) |
| 1131 | dev_err(codec->dev, "DC servo timed out\n"); |
| 1132 | else |
| 1133 | dev_dbg(codec->dev, "DC servo complete after %dms\n", |
| 1134 | timeout); |
| 1135 | |
| 1136 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, |
| 1137 | WM8962_HP1L_ENA_OUTP | |
| 1138 | WM8962_HP1R_ENA_OUTP, |
| 1139 | WM8962_HP1L_ENA_OUTP | |
| 1140 | WM8962_HP1R_ENA_OUTP); |
| 1141 | udelay(20); |
| 1142 | |
| 1143 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, |
| 1144 | WM8962_HP1L_RMV_SHORT | |
| 1145 | WM8962_HP1R_RMV_SHORT, |
| 1146 | WM8962_HP1L_RMV_SHORT | |
| 1147 | WM8962_HP1R_RMV_SHORT); |
| 1148 | break; |
| 1149 | |
| 1150 | case SND_SOC_DAPM_PRE_PMD: |
| 1151 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, |
| 1152 | WM8962_HP1L_RMV_SHORT | |
| 1153 | WM8962_HP1R_RMV_SHORT, 0); |
| 1154 | |
| 1155 | udelay(20); |
| 1156 | |
| 1157 | snd_soc_update_bits(codec, WM8962_DC_SERVO_1, |
| 1158 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | |
| 1159 | WM8962_HP1L_DCS_STARTUP | |
| 1160 | WM8962_HP1R_DCS_STARTUP, |
| 1161 | 0); |
| 1162 | |
| 1163 | snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, |
| 1164 | WM8962_HP1L_ENA | WM8962_HP1R_ENA | |
| 1165 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | |
| 1166 | WM8962_HP1L_ENA_OUTP | |
| 1167 | WM8962_HP1R_ENA_OUTP, 0); |
| 1168 | |
| 1169 | break; |
| 1170 | |
| 1171 | default: |
| 1172 | BUG(); |
| 1173 | return -EINVAL; |
| 1174 | |
| 1175 | } |
| 1176 | |
| 1177 | return 0; |
| 1178 | } |
| 1179 | |
| 1180 | /* VU bits for the output PGAs only take effect while the PGA is powered */ |
| 1181 | static int out_pga_event(struct snd_soc_dapm_widget *w, |
| 1182 | struct snd_kcontrol *kcontrol, int event) |
| 1183 | { |
| 1184 | struct snd_soc_codec *codec = w->codec; |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 1185 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 1186 | u16 *reg_cache = wm8962->reg_cache; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 1187 | int reg; |
| 1188 | |
| 1189 | switch (w->shift) { |
| 1190 | case WM8962_HPOUTR_PGA_ENA_SHIFT: |
| 1191 | reg = WM8962_HPOUTR_VOLUME; |
| 1192 | break; |
| 1193 | case WM8962_HPOUTL_PGA_ENA_SHIFT: |
| 1194 | reg = WM8962_HPOUTL_VOLUME; |
| 1195 | break; |
| 1196 | case WM8962_SPKOUTR_PGA_ENA_SHIFT: |
| 1197 | reg = WM8962_SPKOUTR_VOLUME; |
| 1198 | break; |
| 1199 | case WM8962_SPKOUTL_PGA_ENA_SHIFT: |
| 1200 | reg = WM8962_SPKOUTL_VOLUME; |
| 1201 | break; |
| 1202 | default: |
| 1203 | BUG(); |
| 1204 | return -EINVAL; |
| 1205 | } |
| 1206 | |
| 1207 | switch (event) { |
| 1208 | case SND_SOC_DAPM_POST_PMU: |
| 1209 | return snd_soc_write(codec, reg, reg_cache[reg]); |
| 1210 | default: |
| 1211 | BUG(); |
| 1212 | return -EINVAL; |
| 1213 | } |
| 1214 | } |
| 1215 | |
| 1216 | static const char *st_text[] = { "None", "Right", "Left" }; |
| 1217 | |
| 1218 | static const struct soc_enum str_enum = |
| 1219 | SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text); |
| 1220 | |
| 1221 | static const struct snd_kcontrol_new str_mux = |
| 1222 | SOC_DAPM_ENUM("Right Sidetone", str_enum); |
| 1223 | |
| 1224 | static const struct soc_enum stl_enum = |
| 1225 | SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text); |
| 1226 | |
| 1227 | static const struct snd_kcontrol_new stl_mux = |
| 1228 | SOC_DAPM_ENUM("Left Sidetone", stl_enum); |
| 1229 | |
| 1230 | static const char *outmux_text[] = { "DAC", "Mixer" }; |
| 1231 | |
| 1232 | static const struct soc_enum spkoutr_enum = |
| 1233 | SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text); |
| 1234 | |
| 1235 | static const struct snd_kcontrol_new spkoutr_mux = |
| 1236 | SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); |
| 1237 | |
| 1238 | static const struct soc_enum spkoutl_enum = |
| 1239 | SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text); |
| 1240 | |
| 1241 | static const struct snd_kcontrol_new spkoutl_mux = |
| 1242 | SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); |
| 1243 | |
| 1244 | static const struct soc_enum hpoutr_enum = |
| 1245 | SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text); |
| 1246 | |
| 1247 | static const struct snd_kcontrol_new hpoutr_mux = |
| 1248 | SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); |
| 1249 | |
| 1250 | static const struct soc_enum hpoutl_enum = |
| 1251 | SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text); |
| 1252 | |
| 1253 | static const struct snd_kcontrol_new hpoutl_mux = |
| 1254 | SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); |
| 1255 | |
| 1256 | static const struct snd_kcontrol_new inpgal[] = { |
| 1257 | SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), |
| 1258 | SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), |
| 1259 | SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), |
| 1260 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), |
| 1261 | }; |
| 1262 | |
| 1263 | static const struct snd_kcontrol_new inpgar[] = { |
| 1264 | SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), |
| 1265 | SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), |
| 1266 | SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), |
| 1267 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), |
| 1268 | }; |
| 1269 | |
| 1270 | static const struct snd_kcontrol_new mixinl[] = { |
| 1271 | SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), |
| 1272 | SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), |
| 1273 | SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), |
| 1274 | }; |
| 1275 | |
| 1276 | static const struct snd_kcontrol_new mixinr[] = { |
| 1277 | SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), |
| 1278 | SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), |
| 1279 | SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), |
| 1280 | }; |
| 1281 | |
| 1282 | static const struct snd_kcontrol_new hpmixl[] = { |
| 1283 | SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), |
| 1284 | SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), |
| 1285 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), |
| 1286 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), |
| 1287 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), |
| 1288 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), |
| 1289 | }; |
| 1290 | |
| 1291 | static const struct snd_kcontrol_new hpmixr[] = { |
| 1292 | SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), |
| 1293 | SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), |
| 1294 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), |
| 1295 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), |
| 1296 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), |
| 1297 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), |
| 1298 | }; |
| 1299 | |
| 1300 | static const struct snd_kcontrol_new spkmixl[] = { |
| 1301 | SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), |
| 1302 | SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), |
| 1303 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), |
| 1304 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), |
| 1305 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), |
| 1306 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), |
| 1307 | }; |
| 1308 | |
| 1309 | static const struct snd_kcontrol_new spkmixr[] = { |
| 1310 | SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), |
| 1311 | SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), |
| 1312 | SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), |
| 1313 | SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), |
| 1314 | SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), |
| 1315 | SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), |
| 1316 | }; |
| 1317 | |
| 1318 | static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { |
| 1319 | SND_SOC_DAPM_INPUT("IN1L"), |
| 1320 | SND_SOC_DAPM_INPUT("IN1R"), |
| 1321 | SND_SOC_DAPM_INPUT("IN2L"), |
| 1322 | SND_SOC_DAPM_INPUT("IN2R"), |
| 1323 | SND_SOC_DAPM_INPUT("IN3L"), |
| 1324 | SND_SOC_DAPM_INPUT("IN3R"), |
| 1325 | SND_SOC_DAPM_INPUT("IN4L"), |
| 1326 | SND_SOC_DAPM_INPUT("IN4R"), |
| 1327 | SND_SOC_DAPM_INPUT("Beep"), |
| 1328 | |
Mark Brown | a4f28c0 | 2010-09-29 13:24:35 -0700 | [diff] [blame] | 1329 | SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0), |
| 1330 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 1331 | SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), |
| 1332 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event, |
| 1333 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1334 | SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, |
| 1335 | SND_SOC_DAPM_POST_PMU), |
| 1336 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), |
| 1337 | |
| 1338 | SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, |
| 1339 | inpgal, ARRAY_SIZE(inpgal)), |
| 1340 | SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, |
| 1341 | inpgar, ARRAY_SIZE(inpgar)), |
| 1342 | SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, |
| 1343 | mixinl, ARRAY_SIZE(mixinl)), |
| 1344 | SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, |
| 1345 | mixinr, ARRAY_SIZE(mixinr)), |
| 1346 | |
| 1347 | SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), |
| 1348 | SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), |
| 1349 | |
| 1350 | SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), |
| 1351 | SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), |
| 1352 | |
| 1353 | SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), |
| 1354 | SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), |
| 1355 | |
| 1356 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1357 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1358 | |
| 1359 | SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, |
| 1360 | hpmixl, ARRAY_SIZE(hpmixl)), |
| 1361 | SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, |
| 1362 | hpmixr, ARRAY_SIZE(hpmixr)), |
| 1363 | |
| 1364 | SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, |
| 1365 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
| 1366 | SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, |
| 1367 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
| 1368 | |
| 1369 | SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, |
| 1370 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 1371 | |
| 1372 | SND_SOC_DAPM_OUTPUT("HPOUTL"), |
| 1373 | SND_SOC_DAPM_OUTPUT("HPOUTR"), |
| 1374 | }; |
| 1375 | |
| 1376 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { |
| 1377 | SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, |
| 1378 | spkmixl, ARRAY_SIZE(spkmixl)), |
| 1379 | SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, |
| 1380 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
| 1381 | SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), |
| 1382 | SND_SOC_DAPM_OUTPUT("SPKOUT"), |
| 1383 | }; |
| 1384 | |
| 1385 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { |
| 1386 | SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, |
| 1387 | spkmixl, ARRAY_SIZE(spkmixl)), |
| 1388 | SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, |
| 1389 | spkmixr, ARRAY_SIZE(spkmixr)), |
| 1390 | |
| 1391 | SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, |
| 1392 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
| 1393 | SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, |
| 1394 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
| 1395 | |
| 1396 | SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), |
| 1397 | SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), |
| 1398 | |
| 1399 | SND_SOC_DAPM_OUTPUT("SPKOUTL"), |
| 1400 | SND_SOC_DAPM_OUTPUT("SPKOUTR"), |
| 1401 | }; |
| 1402 | |
| 1403 | static const struct snd_soc_dapm_route wm8962_intercon[] = { |
| 1404 | { "INPGAL", "IN1L Switch", "IN1L" }, |
| 1405 | { "INPGAL", "IN2L Switch", "IN2L" }, |
| 1406 | { "INPGAL", "IN3L Switch", "IN3L" }, |
| 1407 | { "INPGAL", "IN4L Switch", "IN4L" }, |
| 1408 | |
| 1409 | { "INPGAR", "IN1R Switch", "IN1R" }, |
| 1410 | { "INPGAR", "IN2R Switch", "IN2R" }, |
| 1411 | { "INPGAR", "IN3R Switch", "IN3R" }, |
| 1412 | { "INPGAR", "IN4R Switch", "IN4R" }, |
| 1413 | |
| 1414 | { "MIXINL", "IN2L Switch", "IN2L" }, |
| 1415 | { "MIXINL", "IN3L Switch", "IN3L" }, |
| 1416 | { "MIXINL", "PGA Switch", "INPGAL" }, |
| 1417 | |
| 1418 | { "MIXINR", "IN2R Switch", "IN2R" }, |
| 1419 | { "MIXINR", "IN3R Switch", "IN3R" }, |
| 1420 | { "MIXINR", "PGA Switch", "INPGAR" }, |
| 1421 | |
| 1422 | { "ADCL", NULL, "SYSCLK" }, |
| 1423 | { "ADCL", NULL, "TOCLK" }, |
| 1424 | { "ADCL", NULL, "MIXINL" }, |
| 1425 | |
| 1426 | { "ADCR", NULL, "SYSCLK" }, |
| 1427 | { "ADCR", NULL, "TOCLK" }, |
| 1428 | { "ADCR", NULL, "MIXINR" }, |
| 1429 | |
| 1430 | { "STL", "Left", "ADCL" }, |
| 1431 | { "STL", "Right", "ADCR" }, |
| 1432 | |
| 1433 | { "STR", "Left", "ADCL" }, |
| 1434 | { "STR", "Right", "ADCR" }, |
| 1435 | |
| 1436 | { "DACL", NULL, "SYSCLK" }, |
| 1437 | { "DACL", NULL, "TOCLK" }, |
| 1438 | { "DACL", NULL, "Beep" }, |
| 1439 | { "DACL", NULL, "STL" }, |
| 1440 | |
| 1441 | { "DACR", NULL, "SYSCLK" }, |
| 1442 | { "DACR", NULL, "TOCLK" }, |
| 1443 | { "DACR", NULL, "Beep" }, |
| 1444 | { "DACR", NULL, "STR" }, |
| 1445 | |
| 1446 | { "HPMIXL", "IN4L Switch", "IN4L" }, |
| 1447 | { "HPMIXL", "IN4R Switch", "IN4R" }, |
| 1448 | { "HPMIXL", "DACL Switch", "DACL" }, |
| 1449 | { "HPMIXL", "DACR Switch", "DACR" }, |
| 1450 | { "HPMIXL", "MIXINL Switch", "MIXINL" }, |
| 1451 | { "HPMIXL", "MIXINR Switch", "MIXINR" }, |
| 1452 | |
| 1453 | { "HPMIXR", "IN4L Switch", "IN4L" }, |
| 1454 | { "HPMIXR", "IN4R Switch", "IN4R" }, |
| 1455 | { "HPMIXR", "DACL Switch", "DACL" }, |
| 1456 | { "HPMIXR", "DACR Switch", "DACR" }, |
| 1457 | { "HPMIXR", "MIXINL Switch", "MIXINL" }, |
| 1458 | { "HPMIXR", "MIXINR Switch", "MIXINR" }, |
| 1459 | |
| 1460 | { "Left Bypass", NULL, "HPMIXL" }, |
| 1461 | { "Left Bypass", NULL, "Class G" }, |
| 1462 | |
| 1463 | { "Right Bypass", NULL, "HPMIXR" }, |
| 1464 | { "Right Bypass", NULL, "Class G" }, |
| 1465 | |
| 1466 | { "HPOUTL PGA", "Mixer", "Left Bypass" }, |
| 1467 | { "HPOUTL PGA", "DAC", "DACL" }, |
| 1468 | |
| 1469 | { "HPOUTR PGA", "Mixer", "Right Bypass" }, |
| 1470 | { "HPOUTR PGA", "DAC", "DACR" }, |
| 1471 | |
| 1472 | { "HPOUT", NULL, "HPOUTL PGA" }, |
| 1473 | { "HPOUT", NULL, "HPOUTR PGA" }, |
| 1474 | { "HPOUT", NULL, "Charge Pump" }, |
| 1475 | { "HPOUT", NULL, "SYSCLK" }, |
| 1476 | { "HPOUT", NULL, "TOCLK" }, |
| 1477 | |
| 1478 | { "HPOUTL", NULL, "HPOUT" }, |
| 1479 | { "HPOUTR", NULL, "HPOUT" }, |
| 1480 | }; |
| 1481 | |
| 1482 | static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { |
| 1483 | { "Speaker Mixer", "IN4L Switch", "IN4L" }, |
| 1484 | { "Speaker Mixer", "IN4R Switch", "IN4R" }, |
| 1485 | { "Speaker Mixer", "DACL Switch", "DACL" }, |
| 1486 | { "Speaker Mixer", "DACR Switch", "DACR" }, |
| 1487 | { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, |
| 1488 | { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, |
| 1489 | |
| 1490 | { "Speaker PGA", "Mixer", "Speaker Mixer" }, |
| 1491 | { "Speaker PGA", "DAC", "DACL" }, |
| 1492 | |
| 1493 | { "Speaker Output", NULL, "Speaker PGA" }, |
| 1494 | { "Speaker Output", NULL, "SYSCLK" }, |
| 1495 | { "Speaker Output", NULL, "TOCLK" }, |
| 1496 | |
| 1497 | { "SPKOUT", NULL, "Speaker Output" }, |
| 1498 | }; |
| 1499 | |
| 1500 | static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { |
| 1501 | { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, |
| 1502 | { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, |
| 1503 | { "SPKOUTL Mixer", "DACL Switch", "DACL" }, |
| 1504 | { "SPKOUTL Mixer", "DACR Switch", "DACR" }, |
| 1505 | { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, |
| 1506 | { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, |
| 1507 | |
| 1508 | { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, |
| 1509 | { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, |
| 1510 | { "SPKOUTR Mixer", "DACL Switch", "DACL" }, |
| 1511 | { "SPKOUTR Mixer", "DACR Switch", "DACR" }, |
| 1512 | { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, |
| 1513 | { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, |
| 1514 | |
| 1515 | { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, |
| 1516 | { "SPKOUTL PGA", "DAC", "DACL" }, |
| 1517 | |
| 1518 | { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, |
| 1519 | { "SPKOUTR PGA", "DAC", "DACR" }, |
| 1520 | |
| 1521 | { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, |
| 1522 | { "SPKOUTL Output", NULL, "SYSCLK" }, |
| 1523 | { "SPKOUTL Output", NULL, "TOCLK" }, |
| 1524 | |
| 1525 | { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, |
| 1526 | { "SPKOUTR Output", NULL, "SYSCLK" }, |
| 1527 | { "SPKOUTR Output", NULL, "TOCLK" }, |
| 1528 | |
| 1529 | { "SPKOUTL", NULL, "SPKOUTL Output" }, |
| 1530 | { "SPKOUTR", NULL, "SPKOUTR Output" }, |
| 1531 | }; |
| 1532 | |
| 1533 | static int wm8962_add_widgets(struct snd_soc_codec *codec) |
| 1534 | { |
| 1535 | struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); |
| 1536 | |
| 1537 | snd_soc_add_controls(codec, wm8962_snd_controls, |
| 1538 | ARRAY_SIZE(wm8962_snd_controls)); |
| 1539 | if (pdata && pdata->spk_mono) |
| 1540 | snd_soc_add_controls(codec, wm8962_spk_mono_controls, |
| 1541 | ARRAY_SIZE(wm8962_spk_mono_controls)); |
| 1542 | else |
| 1543 | snd_soc_add_controls(codec, wm8962_spk_stereo_controls, |
| 1544 | ARRAY_SIZE(wm8962_spk_stereo_controls)); |
| 1545 | |
| 1546 | |
| 1547 | snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets, |
| 1548 | ARRAY_SIZE(wm8962_dapm_widgets)); |
| 1549 | if (pdata && pdata->spk_mono) |
| 1550 | snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets, |
| 1551 | ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); |
| 1552 | else |
| 1553 | snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets, |
| 1554 | ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); |
| 1555 | |
| 1556 | snd_soc_dapm_add_routes(codec, wm8962_intercon, |
| 1557 | ARRAY_SIZE(wm8962_intercon)); |
| 1558 | if (pdata && pdata->spk_mono) |
| 1559 | snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon, |
| 1560 | ARRAY_SIZE(wm8962_spk_mono_intercon)); |
| 1561 | else |
| 1562 | snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon, |
| 1563 | ARRAY_SIZE(wm8962_spk_stereo_intercon)); |
| 1564 | |
| 1565 | |
| 1566 | snd_soc_dapm_disable_pin(codec, "Beep"); |
| 1567 | |
| 1568 | return 0; |
| 1569 | } |
| 1570 | |
| 1571 | static void wm8962_sync_cache(struct snd_soc_codec *codec) |
| 1572 | { |
| 1573 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 1574 | int i; |
| 1575 | |
| 1576 | if (!codec->cache_sync) |
| 1577 | return; |
| 1578 | |
| 1579 | dev_dbg(codec->dev, "Syncing cache\n"); |
| 1580 | |
| 1581 | codec->cache_only = 0; |
| 1582 | |
| 1583 | /* Sync back cached values if they're different from the |
| 1584 | * hardware default. |
| 1585 | */ |
| 1586 | for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) { |
| 1587 | if (i == WM8962_SOFTWARE_RESET) |
| 1588 | continue; |
| 1589 | if (wm8962->reg_cache[i] == wm8962_reg[i]) |
| 1590 | continue; |
| 1591 | |
| 1592 | snd_soc_write(codec, i, wm8962->reg_cache[i]); |
| 1593 | } |
| 1594 | |
| 1595 | codec->cache_sync = 0; |
| 1596 | } |
| 1597 | |
| 1598 | /* -1 for reserved values */ |
| 1599 | static const int bclk_divs[] = { |
| 1600 | 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 |
| 1601 | }; |
| 1602 | |
| 1603 | static void wm8962_configure_bclk(struct snd_soc_codec *codec) |
| 1604 | { |
| 1605 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 1606 | int dspclk, i; |
| 1607 | int clocking2 = 0; |
| 1608 | int aif2 = 0; |
| 1609 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 1610 | if (!wm8962->bclk) { |
| 1611 | dev_dbg(codec->dev, "No BCLK rate configured\n"); |
| 1612 | return; |
| 1613 | } |
| 1614 | |
| 1615 | dspclk = snd_soc_read(codec, WM8962_CLOCKING1); |
| 1616 | if (dspclk < 0) { |
| 1617 | dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk); |
| 1618 | return; |
| 1619 | } |
| 1620 | |
| 1621 | dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; |
| 1622 | switch (dspclk) { |
| 1623 | case 0: |
| 1624 | dspclk = wm8962->sysclk_rate; |
| 1625 | break; |
| 1626 | case 1: |
| 1627 | dspclk = wm8962->sysclk_rate / 2; |
| 1628 | break; |
| 1629 | case 2: |
| 1630 | dspclk = wm8962->sysclk_rate / 4; |
| 1631 | break; |
| 1632 | default: |
| 1633 | dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n"); |
| 1634 | dspclk = wm8962->sysclk; |
| 1635 | } |
| 1636 | |
| 1637 | dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); |
| 1638 | |
| 1639 | /* We're expecting an exact match */ |
| 1640 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { |
| 1641 | if (bclk_divs[i] < 0) |
| 1642 | continue; |
| 1643 | |
| 1644 | if (dspclk / bclk_divs[i] == wm8962->bclk) { |
| 1645 | dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n", |
| 1646 | bclk_divs[i], wm8962->bclk); |
| 1647 | clocking2 |= i; |
| 1648 | break; |
| 1649 | } |
| 1650 | } |
| 1651 | if (i == ARRAY_SIZE(bclk_divs)) { |
| 1652 | dev_err(codec->dev, "Unsupported BCLK ratio %d\n", |
| 1653 | dspclk / wm8962->bclk); |
| 1654 | return; |
| 1655 | } |
| 1656 | |
| 1657 | aif2 |= wm8962->bclk / wm8962->lrclk; |
| 1658 | dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n", |
| 1659 | wm8962->bclk / wm8962->lrclk, wm8962->lrclk); |
| 1660 | |
| 1661 | snd_soc_update_bits(codec, WM8962_CLOCKING2, |
| 1662 | WM8962_BCLK_DIV_MASK, clocking2); |
| 1663 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2, |
| 1664 | WM8962_AIF_RATE_MASK, aif2); |
| 1665 | } |
| 1666 | |
| 1667 | static int wm8962_set_bias_level(struct snd_soc_codec *codec, |
| 1668 | enum snd_soc_bias_level level) |
| 1669 | { |
| 1670 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 1671 | int ret; |
| 1672 | |
| 1673 | if (level == codec->bias_level) |
| 1674 | return 0; |
| 1675 | |
| 1676 | switch (level) { |
| 1677 | case SND_SOC_BIAS_ON: |
| 1678 | break; |
| 1679 | |
| 1680 | case SND_SOC_BIAS_PREPARE: |
| 1681 | /* VMID 2*50k */ |
| 1682 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, |
| 1683 | WM8962_VMID_SEL_MASK, 0x80); |
| 1684 | break; |
| 1685 | |
| 1686 | case SND_SOC_BIAS_STANDBY: |
| 1687 | if (codec->bias_level == SND_SOC_BIAS_OFF) { |
| 1688 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), |
| 1689 | wm8962->supplies); |
| 1690 | if (ret != 0) { |
| 1691 | dev_err(codec->dev, |
| 1692 | "Failed to enable supplies: %d\n", |
| 1693 | ret); |
| 1694 | return ret; |
| 1695 | } |
| 1696 | |
| 1697 | wm8962_sync_cache(codec); |
| 1698 | |
| 1699 | snd_soc_update_bits(codec, WM8962_ANTI_POP, |
| 1700 | WM8962_STARTUP_BIAS_ENA | |
| 1701 | WM8962_VMID_BUF_ENA, |
| 1702 | WM8962_STARTUP_BIAS_ENA | |
| 1703 | WM8962_VMID_BUF_ENA); |
| 1704 | |
| 1705 | /* Bias enable at 2*50k for ramp */ |
| 1706 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, |
| 1707 | WM8962_VMID_SEL_MASK | |
| 1708 | WM8962_BIAS_ENA, |
| 1709 | WM8962_BIAS_ENA | 0x180); |
| 1710 | |
| 1711 | msleep(5); |
| 1712 | |
| 1713 | snd_soc_update_bits(codec, WM8962_CLOCKING2, |
| 1714 | WM8962_CLKREG_OVD, |
| 1715 | WM8962_CLKREG_OVD); |
| 1716 | |
| 1717 | wm8962_configure_bclk(codec); |
| 1718 | } |
| 1719 | |
| 1720 | /* VMID 2*250k */ |
| 1721 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, |
| 1722 | WM8962_VMID_SEL_MASK, 0x100); |
| 1723 | break; |
| 1724 | |
| 1725 | case SND_SOC_BIAS_OFF: |
| 1726 | snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, |
| 1727 | WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); |
| 1728 | |
| 1729 | snd_soc_update_bits(codec, WM8962_ANTI_POP, |
| 1730 | WM8962_STARTUP_BIAS_ENA | |
| 1731 | WM8962_VMID_BUF_ENA, 0); |
| 1732 | |
| 1733 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), |
| 1734 | wm8962->supplies); |
| 1735 | break; |
| 1736 | } |
| 1737 | codec->bias_level = level; |
| 1738 | return 0; |
| 1739 | } |
| 1740 | |
| 1741 | static const struct { |
| 1742 | int rate; |
| 1743 | int reg; |
| 1744 | } sr_vals[] = { |
| 1745 | { 48000, 0 }, |
| 1746 | { 44100, 0 }, |
| 1747 | { 32000, 1 }, |
| 1748 | { 22050, 2 }, |
| 1749 | { 24000, 2 }, |
| 1750 | { 16000, 3 }, |
| 1751 | { 11025, 4 }, |
| 1752 | { 12000, 4 }, |
| 1753 | { 8000, 5 }, |
| 1754 | { 88200, 6 }, |
| 1755 | { 96000, 6 }, |
| 1756 | }; |
| 1757 | |
| 1758 | static const int sysclk_rates[] = { |
| 1759 | 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, |
| 1760 | }; |
| 1761 | |
| 1762 | static int wm8962_hw_params(struct snd_pcm_substream *substream, |
| 1763 | struct snd_pcm_hw_params *params, |
| 1764 | struct snd_soc_dai *dai) |
| 1765 | { |
| 1766 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 1767 | struct snd_soc_codec *codec = rtd->codec; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 1768 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 1769 | int rate = params_rate(params); |
| 1770 | int i; |
| 1771 | int aif0 = 0; |
| 1772 | int adctl3 = 0; |
| 1773 | int clocking4 = 0; |
| 1774 | |
| 1775 | wm8962->bclk = snd_soc_params_to_bclk(params); |
| 1776 | wm8962->lrclk = params_rate(params); |
| 1777 | |
| 1778 | for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { |
| 1779 | if (sr_vals[i].rate == rate) { |
| 1780 | adctl3 |= sr_vals[i].reg; |
| 1781 | break; |
| 1782 | } |
| 1783 | } |
| 1784 | if (i == ARRAY_SIZE(sr_vals)) { |
| 1785 | dev_err(codec->dev, "Unsupported rate %dHz\n", rate); |
| 1786 | return -EINVAL; |
| 1787 | } |
| 1788 | |
| 1789 | if (rate % 8000 == 0) |
| 1790 | adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; |
| 1791 | |
| 1792 | for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { |
| 1793 | if (sysclk_rates[i] == wm8962->sysclk_rate / rate) { |
| 1794 | clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; |
| 1795 | break; |
| 1796 | } |
| 1797 | } |
| 1798 | if (i == ARRAY_SIZE(sysclk_rates)) { |
| 1799 | dev_err(codec->dev, "Unsupported sysclk ratio %d\n", |
| 1800 | wm8962->sysclk_rate / rate); |
| 1801 | return -EINVAL; |
| 1802 | } |
| 1803 | |
| 1804 | switch (params_format(params)) { |
| 1805 | case SNDRV_PCM_FORMAT_S16_LE: |
| 1806 | break; |
| 1807 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 1808 | aif0 |= 0x40; |
| 1809 | break; |
| 1810 | case SNDRV_PCM_FORMAT_S24_LE: |
| 1811 | aif0 |= 0x80; |
| 1812 | break; |
| 1813 | case SNDRV_PCM_FORMAT_S32_LE: |
| 1814 | aif0 |= 0xc0; |
| 1815 | break; |
| 1816 | default: |
| 1817 | return -EINVAL; |
| 1818 | } |
| 1819 | |
| 1820 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, |
| 1821 | WM8962_WL_MASK, aif0); |
| 1822 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3, |
| 1823 | WM8962_SAMPLE_RATE_INT_MODE | |
| 1824 | WM8962_SAMPLE_RATE_MASK, adctl3); |
| 1825 | snd_soc_update_bits(codec, WM8962_CLOCKING_4, |
| 1826 | WM8962_SYSCLK_RATE_MASK, clocking4); |
| 1827 | |
| 1828 | wm8962_configure_bclk(codec); |
| 1829 | |
| 1830 | return 0; |
| 1831 | } |
| 1832 | |
| 1833 | static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
| 1834 | unsigned int freq, int dir) |
| 1835 | { |
| 1836 | struct snd_soc_codec *codec = dai->codec; |
| 1837 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 1838 | int src; |
| 1839 | |
| 1840 | switch (clk_id) { |
| 1841 | case WM8962_SYSCLK_MCLK: |
| 1842 | wm8962->sysclk = WM8962_SYSCLK_MCLK; |
| 1843 | src = 0; |
| 1844 | break; |
| 1845 | case WM8962_SYSCLK_FLL: |
| 1846 | wm8962->sysclk = WM8962_SYSCLK_FLL; |
| 1847 | src = 1 << WM8962_SYSCLK_SRC_SHIFT; |
| 1848 | WARN_ON(freq != wm8962->fll_fout); |
| 1849 | break; |
| 1850 | default: |
| 1851 | return -EINVAL; |
| 1852 | } |
| 1853 | |
| 1854 | snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, |
| 1855 | src); |
| 1856 | |
| 1857 | wm8962->sysclk_rate = freq; |
| 1858 | |
| 1859 | return 0; |
| 1860 | } |
| 1861 | |
| 1862 | static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 1863 | { |
| 1864 | struct snd_soc_codec *codec = dai->codec; |
| 1865 | int aif0 = 0; |
| 1866 | |
| 1867 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 1868 | case SND_SOC_DAIFMT_DSP_A: |
| 1869 | aif0 |= WM8962_LRCLK_INV; |
| 1870 | case SND_SOC_DAIFMT_DSP_B: |
| 1871 | aif0 |= 3; |
| 1872 | |
| 1873 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1874 | case SND_SOC_DAIFMT_NB_NF: |
| 1875 | case SND_SOC_DAIFMT_IB_NF: |
| 1876 | break; |
| 1877 | default: |
| 1878 | return -EINVAL; |
| 1879 | } |
| 1880 | break; |
| 1881 | |
| 1882 | case SND_SOC_DAIFMT_RIGHT_J: |
| 1883 | break; |
| 1884 | case SND_SOC_DAIFMT_LEFT_J: |
| 1885 | aif0 |= 1; |
| 1886 | break; |
| 1887 | case SND_SOC_DAIFMT_I2S: |
| 1888 | aif0 |= 2; |
| 1889 | break; |
| 1890 | default: |
| 1891 | return -EINVAL; |
| 1892 | } |
| 1893 | |
| 1894 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 1895 | case SND_SOC_DAIFMT_NB_NF: |
| 1896 | break; |
| 1897 | case SND_SOC_DAIFMT_IB_NF: |
| 1898 | aif0 |= WM8962_BCLK_INV; |
| 1899 | break; |
| 1900 | case SND_SOC_DAIFMT_NB_IF: |
| 1901 | aif0 |= WM8962_LRCLK_INV; |
| 1902 | break; |
| 1903 | case SND_SOC_DAIFMT_IB_IF: |
| 1904 | aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; |
| 1905 | break; |
| 1906 | default: |
| 1907 | return -EINVAL; |
| 1908 | } |
| 1909 | |
| 1910 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 1911 | case SND_SOC_DAIFMT_CBM_CFM: |
| 1912 | aif0 |= WM8962_MSTR; |
| 1913 | break; |
| 1914 | case SND_SOC_DAIFMT_CBS_CFS: |
| 1915 | break; |
| 1916 | default: |
| 1917 | return -EINVAL; |
| 1918 | } |
| 1919 | |
| 1920 | snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, |
| 1921 | WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | |
| 1922 | WM8962_LRCLK_INV, aif0); |
| 1923 | |
| 1924 | return 0; |
| 1925 | } |
| 1926 | |
| 1927 | struct _fll_div { |
| 1928 | u16 fll_fratio; |
| 1929 | u16 fll_outdiv; |
| 1930 | u16 fll_refclk_div; |
| 1931 | u16 n; |
| 1932 | u16 theta; |
| 1933 | u16 lambda; |
| 1934 | }; |
| 1935 | |
| 1936 | /* The size in bits of the FLL divide multiplied by 10 |
| 1937 | * to allow rounding later */ |
| 1938 | #define FIXED_FLL_SIZE ((1 << 16) * 10) |
| 1939 | |
| 1940 | static struct { |
| 1941 | unsigned int min; |
| 1942 | unsigned int max; |
| 1943 | u16 fll_fratio; |
| 1944 | int ratio; |
| 1945 | } fll_fratios[] = { |
| 1946 | { 0, 64000, 4, 16 }, |
| 1947 | { 64000, 128000, 3, 8 }, |
| 1948 | { 128000, 256000, 2, 4 }, |
| 1949 | { 256000, 1000000, 1, 2 }, |
| 1950 | { 1000000, 13500000, 0, 1 }, |
| 1951 | }; |
| 1952 | |
| 1953 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, |
| 1954 | unsigned int Fout) |
| 1955 | { |
| 1956 | unsigned int target; |
| 1957 | unsigned int div; |
| 1958 | unsigned int fratio, gcd_fll; |
| 1959 | int i; |
| 1960 | |
| 1961 | /* Fref must be <=13.5MHz */ |
| 1962 | div = 1; |
| 1963 | fll_div->fll_refclk_div = 0; |
| 1964 | while ((Fref / div) > 13500000) { |
| 1965 | div *= 2; |
| 1966 | fll_div->fll_refclk_div++; |
| 1967 | |
| 1968 | if (div > 4) { |
| 1969 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", |
| 1970 | Fref); |
| 1971 | return -EINVAL; |
| 1972 | } |
| 1973 | } |
| 1974 | |
| 1975 | pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); |
| 1976 | |
| 1977 | /* Apply the division for our remaining calculations */ |
| 1978 | Fref /= div; |
| 1979 | |
| 1980 | /* Fvco should be 90-100MHz; don't check the upper bound */ |
| 1981 | div = 2; |
| 1982 | while (Fout * div < 90000000) { |
| 1983 | div++; |
| 1984 | if (div > 64) { |
| 1985 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", |
| 1986 | Fout); |
| 1987 | return -EINVAL; |
| 1988 | } |
| 1989 | } |
| 1990 | target = Fout * div; |
| 1991 | fll_div->fll_outdiv = div - 1; |
| 1992 | |
| 1993 | pr_debug("FLL Fvco=%dHz\n", target); |
| 1994 | |
| 1995 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ |
| 1996 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
| 1997 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { |
| 1998 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; |
| 1999 | fratio = fll_fratios[i].ratio; |
| 2000 | break; |
| 2001 | } |
| 2002 | } |
| 2003 | if (i == ARRAY_SIZE(fll_fratios)) { |
| 2004 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); |
| 2005 | return -EINVAL; |
| 2006 | } |
| 2007 | |
| 2008 | fll_div->n = target / (fratio * Fref); |
| 2009 | |
| 2010 | if (target % Fref == 0) { |
| 2011 | fll_div->theta = 0; |
| 2012 | fll_div->lambda = 0; |
| 2013 | } else { |
| 2014 | gcd_fll = gcd(target, fratio * Fref); |
| 2015 | |
| 2016 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) |
| 2017 | / gcd_fll; |
| 2018 | fll_div->lambda = (fratio * Fref) / gcd_fll; |
| 2019 | } |
| 2020 | |
| 2021 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", |
| 2022 | fll_div->n, fll_div->theta, fll_div->lambda); |
| 2023 | pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", |
| 2024 | fll_div->fll_fratio, fll_div->fll_outdiv, |
| 2025 | fll_div->fll_refclk_div); |
| 2026 | |
| 2027 | return 0; |
| 2028 | } |
| 2029 | |
| 2030 | static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source, |
| 2031 | unsigned int Fref, unsigned int Fout) |
| 2032 | { |
| 2033 | struct snd_soc_codec *codec = dai->codec; |
| 2034 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2035 | struct _fll_div fll_div; |
| 2036 | int ret; |
Mark Brown | 6137112 | 2010-09-27 17:20:11 -0700 | [diff] [blame] | 2037 | int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2038 | |
| 2039 | /* Any change? */ |
| 2040 | if (source == wm8962->fll_src && Fref == wm8962->fll_fref && |
| 2041 | Fout == wm8962->fll_fout) |
| 2042 | return 0; |
| 2043 | |
| 2044 | if (Fout == 0) { |
| 2045 | dev_dbg(codec->dev, "FLL disabled\n"); |
| 2046 | |
| 2047 | wm8962->fll_fref = 0; |
| 2048 | wm8962->fll_fout = 0; |
| 2049 | |
| 2050 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
| 2051 | WM8962_FLL_ENA, 0); |
| 2052 | |
| 2053 | return 0; |
| 2054 | } |
| 2055 | |
| 2056 | ret = fll_factors(&fll_div, Fref, Fout); |
| 2057 | if (ret != 0) |
| 2058 | return ret; |
| 2059 | |
| 2060 | switch (fll_id) { |
| 2061 | case WM8962_FLL_MCLK: |
| 2062 | case WM8962_FLL_BCLK: |
| 2063 | case WM8962_FLL_OSC: |
| 2064 | fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; |
| 2065 | break; |
| 2066 | case WM8962_FLL_INT: |
| 2067 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
| 2068 | WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); |
| 2069 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5, |
| 2070 | WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); |
| 2071 | break; |
| 2072 | default: |
| 2073 | dev_err(codec->dev, "Unknown FLL source %d\n", ret); |
| 2074 | return -EINVAL; |
| 2075 | } |
| 2076 | |
| 2077 | if (fll_div.theta || fll_div.lambda) |
| 2078 | fll1 |= WM8962_FLL_FRAC; |
| 2079 | |
| 2080 | /* Stop the FLL while we reconfigure */ |
| 2081 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); |
| 2082 | |
| 2083 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2, |
| 2084 | WM8962_FLL_OUTDIV_MASK | |
| 2085 | WM8962_FLL_REFCLK_DIV_MASK, |
| 2086 | (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | |
| 2087 | (fll_div.fll_refclk_div)); |
| 2088 | |
| 2089 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3, |
| 2090 | WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); |
| 2091 | |
| 2092 | snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta); |
| 2093 | snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda); |
| 2094 | snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n); |
| 2095 | |
| 2096 | snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, |
| 2097 | WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | |
| 2098 | WM8962_FLL_ENA, fll1); |
| 2099 | |
| 2100 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); |
| 2101 | |
| 2102 | wm8962->fll_fref = Fref; |
| 2103 | wm8962->fll_fout = Fout; |
| 2104 | wm8962->fll_src = source; |
| 2105 | |
| 2106 | return 0; |
| 2107 | } |
| 2108 | |
| 2109 | static int wm8962_mute(struct snd_soc_dai *dai, int mute) |
| 2110 | { |
| 2111 | struct snd_soc_codec *codec = dai->codec; |
| 2112 | int val; |
| 2113 | |
| 2114 | if (mute) |
| 2115 | val = WM8962_DAC_MUTE; |
| 2116 | else |
| 2117 | val = 0; |
| 2118 | |
| 2119 | return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, |
| 2120 | WM8962_DAC_MUTE, val); |
| 2121 | } |
| 2122 | |
| 2123 | #define WM8962_RATES SNDRV_PCM_RATE_8000_96000 |
| 2124 | |
| 2125 | #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
| 2126 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 2127 | |
| 2128 | static struct snd_soc_dai_ops wm8962_dai_ops = { |
| 2129 | .hw_params = wm8962_hw_params, |
| 2130 | .set_sysclk = wm8962_set_dai_sysclk, |
| 2131 | .set_fmt = wm8962_set_dai_fmt, |
| 2132 | .set_pll = wm8962_set_fll, |
| 2133 | .digital_mute = wm8962_mute, |
| 2134 | }; |
| 2135 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2136 | static struct snd_soc_dai_driver wm8962_dai = { |
| 2137 | .name = "wm8962", |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2138 | .playback = { |
| 2139 | .stream_name = "Playback", |
| 2140 | .channels_min = 2, |
| 2141 | .channels_max = 2, |
| 2142 | .rates = WM8962_RATES, |
| 2143 | .formats = WM8962_FORMATS, |
| 2144 | }, |
| 2145 | .capture = { |
| 2146 | .stream_name = "Capture", |
| 2147 | .channels_min = 2, |
| 2148 | .channels_max = 2, |
| 2149 | .rates = WM8962_RATES, |
| 2150 | .formats = WM8962_FORMATS, |
| 2151 | }, |
| 2152 | .ops = &wm8962_dai_ops, |
| 2153 | .symmetric_rates = 1, |
| 2154 | }; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2155 | |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 2156 | static void wm8962_mic_work(struct work_struct *work) |
| 2157 | { |
| 2158 | struct wm8962_priv *wm8962 = container_of(work, |
| 2159 | struct wm8962_priv, |
| 2160 | mic_work.work); |
| 2161 | struct snd_soc_codec *codec = wm8962->codec; |
| 2162 | int status = 0; |
| 2163 | int irq_pol = 0; |
| 2164 | int reg; |
| 2165 | |
| 2166 | reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4); |
| 2167 | |
| 2168 | if (reg & WM8962_MICDET_STS) { |
| 2169 | status |= SND_JACK_MICROPHONE; |
| 2170 | irq_pol |= WM8962_MICD_IRQ_POL; |
| 2171 | } |
| 2172 | |
| 2173 | if (reg & WM8962_MICSHORT_STS) { |
| 2174 | status |= SND_JACK_BTN_0; |
| 2175 | irq_pol |= WM8962_MICSCD_IRQ_POL; |
| 2176 | } |
| 2177 | |
| 2178 | snd_soc_jack_report(wm8962->jack, status, |
| 2179 | SND_JACK_MICROPHONE | SND_JACK_BTN_0); |
| 2180 | |
| 2181 | snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL, |
| 2182 | WM8962_MICSCD_IRQ_POL | |
| 2183 | WM8962_MICD_IRQ_POL, irq_pol); |
| 2184 | } |
| 2185 | |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2186 | static irqreturn_t wm8962_irq(int irq, void *data) |
| 2187 | { |
| 2188 | struct snd_soc_codec *codec = data; |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 2189 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2190 | int mask; |
| 2191 | int active; |
| 2192 | |
| 2193 | mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2); |
| 2194 | |
| 2195 | active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2); |
| 2196 | active &= ~mask; |
| 2197 | |
| 2198 | if (active & WM8962_FIFOS_ERR_EINT) |
| 2199 | dev_err(codec->dev, "FIFO error\n"); |
| 2200 | |
| 2201 | if (active & WM8962_TEMP_SHUT_EINT) |
| 2202 | dev_crit(codec->dev, "Thermal shutdown\n"); |
| 2203 | |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 2204 | if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { |
| 2205 | dev_dbg(codec->dev, "Microphone event detected\n"); |
| 2206 | |
| 2207 | schedule_delayed_work(&wm8962->mic_work, |
| 2208 | msecs_to_jiffies(250)); |
| 2209 | } |
| 2210 | |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2211 | /* Acknowledge the interrupts */ |
| 2212 | snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active); |
| 2213 | |
| 2214 | return IRQ_HANDLED; |
| 2215 | } |
| 2216 | |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 2217 | /** |
| 2218 | * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ |
| 2219 | * |
| 2220 | * @codec: WM8962 codec |
| 2221 | * @jack: jack to report detection events on |
| 2222 | * |
| 2223 | * Enable microphone detection via IRQ on the WM8962. If GPIOs are |
| 2224 | * being used to bring out signals to the processor then only platform |
| 2225 | * data configuration is needed for WM8962 and processor GPIOs should |
| 2226 | * be configured using snd_soc_jack_add_gpios() instead. |
| 2227 | * |
| 2228 | * If no jack is supplied detection will be disabled. |
| 2229 | */ |
| 2230 | int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) |
| 2231 | { |
| 2232 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2233 | int irq_mask, enable; |
| 2234 | |
| 2235 | wm8962->jack = jack; |
| 2236 | if (jack) { |
| 2237 | irq_mask = 0; |
| 2238 | enable = WM8962_MICDET_ENA; |
| 2239 | } else { |
| 2240 | irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; |
| 2241 | enable = 0; |
| 2242 | } |
| 2243 | |
| 2244 | snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK, |
| 2245 | WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); |
| 2246 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, |
| 2247 | WM8962_MICDET_ENA, enable); |
| 2248 | |
| 2249 | /* Send an initial empty report */ |
| 2250 | snd_soc_jack_report(wm8962->jack, 0, |
| 2251 | SND_JACK_MICROPHONE | SND_JACK_BTN_0); |
| 2252 | |
| 2253 | return 0; |
| 2254 | } |
| 2255 | EXPORT_SYMBOL_GPL(wm8962_mic_detect); |
| 2256 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2257 | #ifdef CONFIG_PM |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2258 | static int wm8962_resume(struct snd_soc_codec *codec) |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2259 | { |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2260 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2261 | u16 *reg_cache = codec->reg_cache; |
| 2262 | int i; |
| 2263 | |
| 2264 | /* Restore the registers */ |
| 2265 | for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) { |
| 2266 | switch (i) { |
| 2267 | case WM8962_SOFTWARE_RESET: |
| 2268 | continue; |
| 2269 | default: |
| 2270 | break; |
| 2271 | } |
| 2272 | |
| 2273 | if (reg_cache[i] != wm8962_reg[i]) |
| 2274 | snd_soc_write(codec, i, reg_cache[i]); |
| 2275 | } |
| 2276 | |
| 2277 | return 0; |
| 2278 | } |
| 2279 | #else |
| 2280 | #define wm8962_resume NULL |
| 2281 | #endif |
| 2282 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2283 | #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) |
| 2284 | static int beep_rates[] = { |
| 2285 | 500, 1000, 2000, 4000, |
| 2286 | }; |
| 2287 | |
| 2288 | static void wm8962_beep_work(struct work_struct *work) |
| 2289 | { |
| 2290 | struct wm8962_priv *wm8962 = |
| 2291 | container_of(work, struct wm8962_priv, beep_work); |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2292 | struct snd_soc_codec *codec = wm8962->codec; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2293 | int i; |
| 2294 | int reg = 0; |
| 2295 | int best = 0; |
| 2296 | |
| 2297 | if (wm8962->beep_rate) { |
| 2298 | for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { |
| 2299 | if (abs(wm8962->beep_rate - beep_rates[i]) < |
| 2300 | abs(wm8962->beep_rate - beep_rates[best])) |
| 2301 | best = i; |
| 2302 | } |
| 2303 | |
| 2304 | dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n", |
| 2305 | beep_rates[best], wm8962->beep_rate); |
| 2306 | |
| 2307 | reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); |
| 2308 | |
| 2309 | snd_soc_dapm_enable_pin(codec, "Beep"); |
| 2310 | } else { |
| 2311 | dev_dbg(codec->dev, "Disabling beep\n"); |
| 2312 | snd_soc_dapm_disable_pin(codec, "Beep"); |
| 2313 | } |
| 2314 | |
| 2315 | snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, |
| 2316 | WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); |
| 2317 | |
| 2318 | snd_soc_dapm_sync(codec); |
| 2319 | } |
| 2320 | |
| 2321 | /* For usability define a way of injecting beep events for the device - |
| 2322 | * many systems will not have a keyboard. |
| 2323 | */ |
| 2324 | static int wm8962_beep_event(struct input_dev *dev, unsigned int type, |
| 2325 | unsigned int code, int hz) |
| 2326 | { |
| 2327 | struct snd_soc_codec *codec = input_get_drvdata(dev); |
| 2328 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2329 | |
| 2330 | dev_dbg(codec->dev, "Beep event %x %x\n", code, hz); |
| 2331 | |
| 2332 | switch (code) { |
| 2333 | case SND_BELL: |
| 2334 | if (hz) |
| 2335 | hz = 1000; |
| 2336 | case SND_TONE: |
| 2337 | break; |
| 2338 | default: |
| 2339 | return -1; |
| 2340 | } |
| 2341 | |
| 2342 | /* Kick the beep from a workqueue */ |
| 2343 | wm8962->beep_rate = hz; |
| 2344 | schedule_work(&wm8962->beep_work); |
| 2345 | return 0; |
| 2346 | } |
| 2347 | |
| 2348 | static ssize_t wm8962_beep_set(struct device *dev, |
| 2349 | struct device_attribute *attr, |
| 2350 | const char *buf, size_t count) |
| 2351 | { |
| 2352 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); |
| 2353 | long int time; |
| 2354 | |
| 2355 | strict_strtol(buf, 10, &time); |
| 2356 | |
| 2357 | input_event(wm8962->beep, EV_SND, SND_TONE, time); |
| 2358 | |
| 2359 | return count; |
| 2360 | } |
| 2361 | |
| 2362 | static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set); |
| 2363 | |
| 2364 | static void wm8962_init_beep(struct snd_soc_codec *codec) |
| 2365 | { |
| 2366 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2367 | int ret; |
| 2368 | |
| 2369 | wm8962->beep = input_allocate_device(); |
| 2370 | if (!wm8962->beep) { |
| 2371 | dev_err(codec->dev, "Failed to allocate beep device\n"); |
| 2372 | return; |
| 2373 | } |
| 2374 | |
| 2375 | INIT_WORK(&wm8962->beep_work, wm8962_beep_work); |
| 2376 | wm8962->beep_rate = 0; |
| 2377 | |
| 2378 | wm8962->beep->name = "WM8962 Beep Generator"; |
| 2379 | wm8962->beep->phys = dev_name(codec->dev); |
| 2380 | wm8962->beep->id.bustype = BUS_I2C; |
| 2381 | |
| 2382 | wm8962->beep->evbit[0] = BIT_MASK(EV_SND); |
| 2383 | wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); |
| 2384 | wm8962->beep->event = wm8962_beep_event; |
| 2385 | wm8962->beep->dev.parent = codec->dev; |
| 2386 | input_set_drvdata(wm8962->beep, codec); |
| 2387 | |
| 2388 | ret = input_register_device(wm8962->beep); |
| 2389 | if (ret != 0) { |
| 2390 | input_free_device(wm8962->beep); |
| 2391 | wm8962->beep = NULL; |
| 2392 | dev_err(codec->dev, "Failed to register beep device\n"); |
| 2393 | } |
| 2394 | |
| 2395 | ret = device_create_file(codec->dev, &dev_attr_beep); |
| 2396 | if (ret != 0) { |
| 2397 | dev_err(codec->dev, "Failed to create keyclick file: %d\n", |
| 2398 | ret); |
| 2399 | } |
| 2400 | } |
| 2401 | |
| 2402 | static void wm8962_free_beep(struct snd_soc_codec *codec) |
| 2403 | { |
| 2404 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2405 | |
| 2406 | device_remove_file(codec->dev, &dev_attr_beep); |
| 2407 | input_unregister_device(wm8962->beep); |
| 2408 | cancel_work_sync(&wm8962->beep_work); |
| 2409 | wm8962->beep = NULL; |
| 2410 | |
| 2411 | snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); |
| 2412 | } |
| 2413 | #else |
| 2414 | static void wm8962_init_beep(struct snd_soc_codec *codec) |
| 2415 | { |
| 2416 | } |
| 2417 | |
| 2418 | static void wm8962_free_beep(struct snd_soc_codec *codec) |
| 2419 | { |
| 2420 | } |
| 2421 | #endif |
| 2422 | |
Mark Brown | 8ca2aa9 | 2010-10-01 17:46:37 -0700 | [diff] [blame] | 2423 | static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio) |
| 2424 | { |
| 2425 | int mask = 0; |
| 2426 | int val = 0; |
| 2427 | |
| 2428 | /* Some of the GPIOs are behind MFP configuration and need to |
| 2429 | * be put into GPIO mode. */ |
| 2430 | switch (gpio) { |
| 2431 | case 2: |
| 2432 | mask = WM8962_CLKOUT2_SEL_MASK; |
| 2433 | val = 1 << WM8962_CLKOUT2_SEL_SHIFT; |
| 2434 | break; |
| 2435 | case 3: |
| 2436 | mask = WM8962_CLKOUT3_SEL_MASK; |
| 2437 | val = 1 << WM8962_CLKOUT3_SEL_SHIFT; |
| 2438 | break; |
| 2439 | default: |
| 2440 | break; |
| 2441 | } |
| 2442 | |
| 2443 | if (mask) |
| 2444 | snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1, |
| 2445 | mask, val); |
| 2446 | } |
| 2447 | |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2448 | #ifdef CONFIG_GPIOLIB |
| 2449 | static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip) |
| 2450 | { |
| 2451 | return container_of(chip, struct wm8962_priv, gpio_chip); |
| 2452 | } |
| 2453 | |
| 2454 | static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 2455 | { |
| 2456 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); |
| 2457 | struct snd_soc_codec *codec = wm8962->codec; |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2458 | |
| 2459 | /* The WM8962 GPIOs aren't linearly numbered. For simplicity |
| 2460 | * we export linear numbers and error out if the unsupported |
| 2461 | * ones are requsted. |
| 2462 | */ |
| 2463 | switch (offset + 1) { |
| 2464 | case 2: |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2465 | case 3: |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2466 | case 5: |
| 2467 | case 6: |
| 2468 | break; |
| 2469 | default: |
| 2470 | return -EINVAL; |
| 2471 | } |
| 2472 | |
Mark Brown | 8ca2aa9 | 2010-10-01 17:46:37 -0700 | [diff] [blame] | 2473 | wm8962_set_gpio_mode(codec, offset + 1); |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2474 | |
| 2475 | return 0; |
| 2476 | } |
| 2477 | |
| 2478 | static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 2479 | { |
| 2480 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); |
| 2481 | struct snd_soc_codec *codec = wm8962->codec; |
| 2482 | |
| 2483 | snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, |
| 2484 | WM8962_GP2_LVL, value << WM8962_GP2_LVL_SHIFT); |
| 2485 | } |
| 2486 | |
| 2487 | static int wm8962_gpio_direction_out(struct gpio_chip *chip, |
| 2488 | unsigned offset, int value) |
| 2489 | { |
| 2490 | struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); |
| 2491 | struct snd_soc_codec *codec = wm8962->codec; |
| 2492 | int val; |
| 2493 | |
| 2494 | /* Force function 1 (logic output) */ |
| 2495 | val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); |
| 2496 | |
| 2497 | return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, |
| 2498 | WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); |
| 2499 | } |
| 2500 | |
| 2501 | static struct gpio_chip wm8962_template_chip = { |
| 2502 | .label = "wm8962", |
| 2503 | .owner = THIS_MODULE, |
| 2504 | .request = wm8962_gpio_request, |
| 2505 | .direction_output = wm8962_gpio_direction_out, |
| 2506 | .set = wm8962_gpio_set, |
| 2507 | .can_sleep = 1, |
| 2508 | }; |
| 2509 | |
| 2510 | static void wm8962_init_gpio(struct snd_soc_codec *codec) |
| 2511 | { |
| 2512 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2513 | struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); |
| 2514 | int ret; |
| 2515 | |
| 2516 | wm8962->gpio_chip = wm8962_template_chip; |
| 2517 | wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; |
| 2518 | wm8962->gpio_chip.dev = codec->dev; |
| 2519 | |
| 2520 | if (pdata && pdata->gpio_base) |
| 2521 | wm8962->gpio_chip.base = pdata->gpio_base; |
| 2522 | else |
| 2523 | wm8962->gpio_chip.base = -1; |
| 2524 | |
| 2525 | ret = gpiochip_add(&wm8962->gpio_chip); |
| 2526 | if (ret != 0) |
| 2527 | dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); |
| 2528 | } |
| 2529 | |
| 2530 | static void wm8962_free_gpio(struct snd_soc_codec *codec) |
| 2531 | { |
| 2532 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
| 2533 | int ret; |
| 2534 | |
| 2535 | ret = gpiochip_remove(&wm8962->gpio_chip); |
| 2536 | if (ret != 0) |
| 2537 | dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); |
| 2538 | } |
| 2539 | #else |
| 2540 | static void wm8962_init_gpio(struct snd_soc_codec *codec) |
| 2541 | { |
| 2542 | } |
| 2543 | |
| 2544 | static void wm8962_free_gpio(struct snd_soc_codec *codec) |
| 2545 | { |
| 2546 | } |
| 2547 | #endif |
| 2548 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2549 | static int wm8962_probe(struct snd_soc_codec *codec) |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2550 | { |
| 2551 | int ret; |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2552 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2553 | struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2554 | struct i2c_client *i2c = container_of(codec->dev, struct i2c_client, |
| 2555 | dev); |
| 2556 | int i, trigger, irq_pol; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2557 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2558 | wm8962->codec = codec; |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 2559 | INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2560 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2561 | codec->cache_sync = 1; |
| 2562 | codec->idle_bias_off = 1; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2563 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2564 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2565 | if (ret != 0) { |
| 2566 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
| 2567 | goto err; |
| 2568 | } |
| 2569 | |
| 2570 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) |
| 2571 | wm8962->supplies[i].supply = wm8962_supply_names[i]; |
| 2572 | |
| 2573 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies), |
| 2574 | wm8962->supplies); |
| 2575 | if (ret != 0) { |
| 2576 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); |
| 2577 | goto err; |
| 2578 | } |
| 2579 | |
| 2580 | wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; |
| 2581 | wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; |
| 2582 | wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; |
| 2583 | wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; |
| 2584 | wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; |
| 2585 | wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; |
| 2586 | wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; |
| 2587 | wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; |
| 2588 | |
| 2589 | /* This should really be moved into the regulator core */ |
| 2590 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { |
| 2591 | ret = regulator_register_notifier(wm8962->supplies[i].consumer, |
| 2592 | &wm8962->disable_nb[i]); |
| 2593 | if (ret != 0) { |
| 2594 | dev_err(codec->dev, |
| 2595 | "Failed to register regulator notifier: %d\n", |
| 2596 | ret); |
| 2597 | } |
| 2598 | } |
| 2599 | |
| 2600 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), |
| 2601 | wm8962->supplies); |
| 2602 | if (ret != 0) { |
| 2603 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); |
| 2604 | goto err_get; |
| 2605 | } |
| 2606 | |
| 2607 | ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET); |
| 2608 | if (ret < 0) { |
| 2609 | dev_err(codec->dev, "Failed to read ID register\n"); |
| 2610 | goto err_enable; |
| 2611 | } |
| 2612 | if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) { |
| 2613 | dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n", |
| 2614 | ret, wm8962_reg[WM8962_SOFTWARE_RESET]); |
| 2615 | ret = -EINVAL; |
| 2616 | goto err_enable; |
| 2617 | } |
| 2618 | |
| 2619 | ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME); |
| 2620 | if (ret < 0) { |
| 2621 | dev_err(codec->dev, "Failed to read device revision: %d\n", |
| 2622 | ret); |
| 2623 | goto err_enable; |
| 2624 | } |
| 2625 | |
| 2626 | dev_info(codec->dev, "customer id %x revision %c\n", |
| 2627 | (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, |
| 2628 | ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) |
| 2629 | + 'A'); |
| 2630 | |
| 2631 | ret = wm8962_reset(codec); |
| 2632 | if (ret < 0) { |
| 2633 | dev_err(codec->dev, "Failed to issue reset\n"); |
| 2634 | goto err_enable; |
| 2635 | } |
| 2636 | |
| 2637 | /* SYSCLK defaults to on; make sure it is off so we can safely |
| 2638 | * write to registers if the device is declocked. |
| 2639 | */ |
| 2640 | snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0); |
| 2641 | |
| 2642 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); |
| 2643 | |
| 2644 | if (pdata) { |
| 2645 | /* Apply static configuration for GPIOs */ |
| 2646 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) |
Mark Brown | 8ca2aa9 | 2010-10-01 17:46:37 -0700 | [diff] [blame] | 2647 | if (pdata->gpio_init[i]) { |
| 2648 | wm8962_set_gpio_mode(codec, i + 1); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2649 | snd_soc_write(codec, 0x200 + i, |
| 2650 | pdata->gpio_init[i] & 0xffff); |
Mark Brown | 8ca2aa9 | 2010-10-01 17:46:37 -0700 | [diff] [blame] | 2651 | } |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2652 | |
| 2653 | /* Put the speakers into mono mode? */ |
| 2654 | if (pdata->spk_mono) |
| 2655 | wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2] |
| 2656 | |= WM8962_SPK_MONO; |
Mark Brown | a4f28c0 | 2010-09-29 13:24:35 -0700 | [diff] [blame] | 2657 | |
| 2658 | /* Micbias setup, detection enable and detection |
| 2659 | * threasholds. */ |
| 2660 | if (pdata->mic_cfg) |
| 2661 | snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, |
| 2662 | WM8962_MICDET_ENA | |
| 2663 | WM8962_MICDET_THR_MASK | |
| 2664 | WM8962_MICSHORT_THR_MASK | |
| 2665 | WM8962_MICBIAS_LVL, |
| 2666 | pdata->mic_cfg); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2667 | } |
| 2668 | |
| 2669 | /* Latch volume update bits */ |
| 2670 | wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU; |
| 2671 | wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU; |
| 2672 | wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU; |
| 2673 | wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU; |
| 2674 | wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU; |
| 2675 | wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU; |
| 2676 | wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU; |
| 2677 | wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU; |
| 2678 | wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU; |
| 2679 | wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU; |
| 2680 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2681 | wm8962_add_widgets(codec); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2682 | |
| 2683 | wm8962_init_beep(codec); |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2684 | wm8962_init_gpio(codec); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2685 | |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2686 | if (i2c->irq) { |
| 2687 | if (pdata && pdata->irq_active_low) { |
| 2688 | trigger = IRQF_TRIGGER_LOW; |
| 2689 | irq_pol = WM8962_IRQ_POL; |
| 2690 | } else { |
| 2691 | trigger = IRQF_TRIGGER_HIGH; |
| 2692 | irq_pol = 0; |
| 2693 | } |
| 2694 | |
| 2695 | snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL, |
| 2696 | WM8962_IRQ_POL, irq_pol); |
| 2697 | |
| 2698 | ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq, |
| 2699 | trigger | IRQF_ONESHOT, |
| 2700 | "wm8962", codec); |
| 2701 | if (ret != 0) { |
| 2702 | dev_err(codec->dev, "Failed to request IRQ %d: %d\n", |
| 2703 | i2c->irq, ret); |
| 2704 | /* Non-fatal */ |
| 2705 | } else { |
| 2706 | /* Enable error reporting IRQs by default */ |
| 2707 | snd_soc_update_bits(codec, |
| 2708 | WM8962_INTERRUPT_STATUS_2_MASK, |
| 2709 | WM8962_TEMP_SHUT_EINT | |
| 2710 | WM8962_FIFOS_ERR_EINT, 0); |
| 2711 | } |
| 2712 | } |
| 2713 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2714 | return 0; |
| 2715 | |
| 2716 | err_enable: |
| 2717 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); |
| 2718 | err_get: |
| 2719 | regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); |
| 2720 | err: |
| 2721 | kfree(wm8962); |
| 2722 | return ret; |
| 2723 | } |
| 2724 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2725 | static int wm8962_remove(struct snd_soc_codec *codec) |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2726 | { |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2727 | struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2728 | struct i2c_client *i2c = container_of(codec->dev, struct i2c_client, |
| 2729 | dev); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2730 | int i; |
| 2731 | |
Mark Brown | 45e6550 | 2010-09-28 16:01:20 -0700 | [diff] [blame] | 2732 | if (i2c->irq) |
| 2733 | free_irq(i2c->irq, codec); |
| 2734 | |
Mark Brown | 7711308 | 2010-09-30 15:37:53 -0700 | [diff] [blame] | 2735 | cancel_delayed_work_sync(&wm8962->mic_work); |
| 2736 | |
Mark Brown | 3367b8d | 2010-09-20 17:34:58 +0100 | [diff] [blame] | 2737 | wm8962_free_gpio(codec); |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2738 | wm8962_free_beep(codec); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2739 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) |
| 2740 | regulator_unregister_notifier(wm8962->supplies[i].consumer, |
| 2741 | &wm8962->disable_nb[i]); |
| 2742 | regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2743 | |
| 2744 | return 0; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2745 | } |
| 2746 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2747 | static struct snd_soc_codec_driver soc_codec_dev_wm8962 = { |
| 2748 | .probe = wm8962_probe, |
| 2749 | .remove = wm8962_remove, |
| 2750 | .resume = wm8962_resume, |
| 2751 | .set_bias_level = wm8962_set_bias_level, |
Dimitris Papastamos | 6946e03 | 2010-09-10 18:24:08 +0100 | [diff] [blame] | 2752 | .reg_cache_size = WM8962_MAX_REGISTER + 1, |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2753 | .reg_word_size = sizeof(u16), |
| 2754 | .reg_cache_default = wm8962_reg, |
| 2755 | .volatile_register = wm8962_volatile_register, |
| 2756 | .readable_register = wm8962_readable_register, |
| 2757 | }; |
| 2758 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2759 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 2760 | static __devinit int wm8962_i2c_probe(struct i2c_client *i2c, |
| 2761 | const struct i2c_device_id *id) |
| 2762 | { |
| 2763 | struct wm8962_priv *wm8962; |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2764 | int ret; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2765 | |
| 2766 | wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL); |
| 2767 | if (wm8962 == NULL) |
| 2768 | return -ENOMEM; |
| 2769 | |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2770 | i2c_set_clientdata(i2c, wm8962); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2771 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2772 | ret = snd_soc_register_codec(&i2c->dev, |
| 2773 | &soc_codec_dev_wm8962, &wm8962_dai, 1); |
| 2774 | if (ret < 0) |
| 2775 | kfree(wm8962); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2776 | |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2777 | return ret; |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2778 | } |
| 2779 | |
| 2780 | static __devexit int wm8962_i2c_remove(struct i2c_client *client) |
| 2781 | { |
Mark Brown | 54d8d0a | 2010-08-12 15:02:11 +0100 | [diff] [blame] | 2782 | snd_soc_unregister_codec(&client->dev); |
| 2783 | kfree(i2c_get_clientdata(client)); |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2784 | return 0; |
| 2785 | } |
| 2786 | |
| 2787 | static const struct i2c_device_id wm8962_i2c_id[] = { |
| 2788 | { "wm8962", 0 }, |
| 2789 | { } |
| 2790 | }; |
| 2791 | MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); |
| 2792 | |
| 2793 | static struct i2c_driver wm8962_i2c_driver = { |
| 2794 | .driver = { |
Mark Brown | ea738ba | 2010-09-20 20:36:19 +0100 | [diff] [blame] | 2795 | .name = "wm8962", |
Mark Brown | 9a76f1f | 2010-08-05 13:20:59 +0100 | [diff] [blame] | 2796 | .owner = THIS_MODULE, |
| 2797 | }, |
| 2798 | .probe = wm8962_i2c_probe, |
| 2799 | .remove = __devexit_p(wm8962_i2c_remove), |
| 2800 | .id_table = wm8962_i2c_id, |
| 2801 | }; |
| 2802 | #endif |
| 2803 | |
| 2804 | static int __init wm8962_modinit(void) |
| 2805 | { |
| 2806 | int ret; |
| 2807 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 2808 | ret = i2c_add_driver(&wm8962_i2c_driver); |
| 2809 | if (ret != 0) { |
| 2810 | printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n", |
| 2811 | ret); |
| 2812 | } |
| 2813 | #endif |
| 2814 | return 0; |
| 2815 | } |
| 2816 | module_init(wm8962_modinit); |
| 2817 | |
| 2818 | static void __exit wm8962_exit(void) |
| 2819 | { |
| 2820 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
| 2821 | i2c_del_driver(&wm8962_i2c_driver); |
| 2822 | #endif |
| 2823 | } |
| 2824 | module_exit(wm8962_exit); |
| 2825 | |
| 2826 | MODULE_DESCRIPTION("ASoC WM8962 driver"); |
| 2827 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); |
| 2828 | MODULE_LICENSE("GPL"); |