blob: 5327decde5a04e58a2d6a7a0be6589d279fbeb49 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/arm/mach-ixp4xx/common.c
3 *
4 * Generic code shared across all IXP4XX platforms
5 *
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/serial.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/tty.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010021#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/serial_core.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/time.h>
26#include <linux/timex.h>
Kevin Hilman84904d02006-09-22 00:58:57 +010027#include <linux/clocksource.h>
Kevin Hilmane32f1502007-03-08 20:23:59 +010028#include <linux/clockchips.h>
Russell Kingfced80c2008-09-06 12:10:45 +010029#include <linux/io.h>
Paul Gortmakerdc280942011-07-31 16:17:29 -040030#include <linux/export.h>
Richard Cochran9dde0ae2012-05-23 18:19:51 +020031#include <linux/gpio.h>
Thomas Gleixnerf7b861b2013-03-21 22:49:38 +010032#include <linux/cpu.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070033#include <linux/sched_clock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
Russell Kinga09e64f2008-08-05 16:14:15 +010035#include <mach/udc.h>
36#include <mach/hardware.h>
Rob Herringf4495882012-03-06 15:01:53 -060037#include <mach/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <asm/uaccess.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <asm/pgtable.h>
40#include <asm/page.h>
41#include <asm/irq.h>
Olof Johansson86dfe442012-03-29 23:22:44 -070042#include <asm/system_misc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46#include <asm/mach/time.h>
47
Mikael Petterssonceb69a82009-09-11 00:59:07 +020048static void __init ixp4xx_clocksource_init(void);
49static void __init ixp4xx_clockevent_init(void);
Kevin Hilmane32f1502007-03-08 20:23:59 +010050static struct clock_event_device clockevent_ixp4xx;
Kevin Hilmanf9a8ca12006-12-06 00:45:07 +010051
Linus Torvalds1da177e2005-04-16 15:20:36 -070052/*************************************************************************
53 * IXP4xx chipset I/O mapping
54 *************************************************************************/
55static struct map_desc ixp4xx_io_desc[] __initdata = {
56 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
Arnd Bergmann13ec32f2012-09-14 20:19:40 +000057 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
Deepak Saxena87fe04b2005-10-28 15:18:59 +010058 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
60 .type = MT_DEVICE
61 }, { /* Expansion Bus Config Registers */
Arnd Bergmann13ec32f2012-09-14 20:19:40 +000062 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
Deepak Saxena87fe04b2005-10-28 15:18:59 +010063 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 .length = IXP4XX_EXP_CFG_REGION_SIZE,
65 .type = MT_DEVICE
66 }, { /* PCI Registers */
Arnd Bergmann13ec32f2012-09-14 20:19:40 +000067 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
Deepak Saxena87fe04b2005-10-28 15:18:59 +010068 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 .length = IXP4XX_PCI_CFG_REGION_SIZE,
70 .type = MT_DEVICE
Krzysztof HaƂasaf0cdb152010-03-26 16:38:52 +010071 }, { /* Queue Manager */
72 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
73 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
74 .length = IXP4XX_QMGR_REGION_SIZE,
75 .type = MT_DEVICE
Deepak Saxena5932ae32005-06-24 20:54:35 +010076 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070077};
78
79void __init ixp4xx_map_io(void)
80{
81 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
82}
83
84
85/*************************************************************************
86 * IXP4xx chipset IRQ handling
87 *
88 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
89 * (be it PCI or something else) configures that GPIO line
90 * as an IRQ.
91 **************************************************************************/
Deepak Saxenabdf82b52005-08-29 22:46:30 +010092enum ixp4xx_irq_type {
93 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
94};
95
Kevin Hilman984d1152006-11-03 01:47:20 +010096/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
97static unsigned long long ixp4xx_irq_edge = 0;
Deepak Saxenabdf82b52005-08-29 22:46:30 +010098
99/*
100 * IRQ -> GPIO mapping table
101 */
Lennert Buytenhek6cc1b652006-04-20 21:24:38 +0100102static signed char irq2gpio[32] = {
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100103 -1, -1, -1, -1, -1, -1, 0, 1,
104 -1, -1, -1, -1, -1, -1, -1, -1,
105 -1, -1, -1, 2, 3, 4, 5, 6,
106 7, 8, 9, 10, 11, 12, -1, -1,
107};
108
Richard Cochran9dde0ae2012-05-23 18:19:51 +0200109static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
Milan Svoboda25735d12007-03-21 14:04:08 +0100110{
111 int irq;
112
113 for (irq = 0; irq < 32; irq++) {
114 if (irq2gpio[irq] == gpio)
115 return irq;
116 }
117 return -EINVAL;
118}
Milan Svoboda25735d12007-03-21 14:04:08 +0100119
Roel Kluinefec1942009-11-03 23:05:32 +0100120int irq_to_gpio(unsigned int irq)
Milan Svoboda25735d12007-03-21 14:04:08 +0100121{
122 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
123
124 if (gpio == -1)
125 return -EINVAL;
126
127 return gpio;
128}
129EXPORT_SYMBOL(irq_to_gpio);
130
Lennert Buytenhekee040872010-11-29 10:33:49 +0100131static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100132{
Lennert Buytenhekee040872010-11-29 10:33:49 +0100133 int line = irq2gpio[d->irq];
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100134 u32 int_style;
135 enum ixp4xx_irq_type irq_type;
136 volatile u32 *int_reg;
137
138 /*
139 * Only for GPIO IRQs
140 */
141 if (line < 0)
142 return -EINVAL;
143
MÄrten Wikström06e44792006-02-22 22:27:23 +0000144 switch (type){
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100145 case IRQ_TYPE_EDGE_BOTH:
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100146 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
147 irq_type = IXP4XX_IRQ_EDGE;
MÄrten Wikström06e44792006-02-22 22:27:23 +0000148 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100149 case IRQ_TYPE_EDGE_RISING:
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100150 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
151 irq_type = IXP4XX_IRQ_EDGE;
MÄrten Wikström06e44792006-02-22 22:27:23 +0000152 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100153 case IRQ_TYPE_EDGE_FALLING:
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100154 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
155 irq_type = IXP4XX_IRQ_EDGE;
MÄrten Wikström06e44792006-02-22 22:27:23 +0000156 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100157 case IRQ_TYPE_LEVEL_HIGH:
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100158 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
159 irq_type = IXP4XX_IRQ_LEVEL;
MÄrten Wikström06e44792006-02-22 22:27:23 +0000160 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100161 case IRQ_TYPE_LEVEL_LOW:
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100162 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
163 irq_type = IXP4XX_IRQ_LEVEL;
MÄrten Wikström06e44792006-02-22 22:27:23 +0000164 break;
165 default:
David Vrabel6132f9e2005-09-26 19:52:56 +0100166 return -EINVAL;
MÄrten Wikström06e44792006-02-22 22:27:23 +0000167 }
Kevin Hilman984d1152006-11-03 01:47:20 +0100168
169 if (irq_type == IXP4XX_IRQ_EDGE)
Lennert Buytenhekee040872010-11-29 10:33:49 +0100170 ixp4xx_irq_edge |= (1 << d->irq);
Kevin Hilman984d1152006-11-03 01:47:20 +0100171 else
Lennert Buytenhekee040872010-11-29 10:33:49 +0100172 ixp4xx_irq_edge &= ~(1 << d->irq);
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100173
174 if (line >= 8) { /* pins 8-15 */
175 line -= 8;
176 int_reg = IXP4XX_GPIO_GPIT2R;
177 } else { /* pins 0-7 */
178 int_reg = IXP4XX_GPIO_GPIT1R;
179 }
180
181 /* Clear the style for the appropriate pin */
182 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
183 (line * IXP4XX_GPIO_STYLE_SIZE));
184
Deepak Saxenaf7e8bbb82006-01-04 17:17:10 +0000185 *IXP4XX_GPIO_GPISR = (1 << line);
186
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100187 /* Set the new style */
188 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
David Vrabel6132f9e2005-09-26 19:52:56 +0100189
Alessandro Zummo73deb7d2006-03-20 17:10:12 +0000190 /* Configure the line as an input */
Lennert Buytenhekee040872010-11-29 10:33:49 +0100191 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
Alessandro Zummo73deb7d2006-03-20 17:10:12 +0000192
David Vrabel6132f9e2005-09-26 19:52:56 +0100193 return 0;
Deepak Saxenabdf82b52005-08-29 22:46:30 +0100194}
195
Lennert Buytenhekee040872010-11-29 10:33:49 +0100196static void ixp4xx_irq_mask(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197{
Lennert Buytenhekee040872010-11-29 10:33:49 +0100198 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
199 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 else
Lennert Buytenhekee040872010-11-29 10:33:49 +0100201 *IXP4XX_ICMR &= ~(1 << d->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202}
203
Lennert Buytenhekee040872010-11-29 10:33:49 +0100204static void ixp4xx_irq_ack(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205{
Lennert Buytenhekee040872010-11-29 10:33:49 +0100206 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207
208 if (line >= 0)
Deepak Saxenaf7e8bbb82006-01-04 17:17:10 +0000209 *IXP4XX_GPIO_GPISR = (1 << line);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210}
211
212/*
213 * Level triggered interrupts on GPIO lines can only be cleared when the
214 * interrupt condition disappears.
215 */
Lennert Buytenhekee040872010-11-29 10:33:49 +0100216static void ixp4xx_irq_unmask(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217{
Lennert Buytenhekee040872010-11-29 10:33:49 +0100218 if (!(ixp4xx_irq_edge & (1 << d->irq)))
219 ixp4xx_irq_ack(d);
Kevin Hilman984d1152006-11-03 01:47:20 +0100220
Lennert Buytenhekee040872010-11-29 10:33:49 +0100221 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
222 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
Kevin Hilman984d1152006-11-03 01:47:20 +0100223 else
Lennert Buytenhekee040872010-11-29 10:33:49 +0100224 *IXP4XX_ICMR |= (1 << d->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225}
226
Russell King10dd5ce2006-11-23 11:41:32 +0000227static struct irq_chip ixp4xx_irq_chip = {
Kevin Hilman984d1152006-11-03 01:47:20 +0100228 .name = "IXP4xx",
Lennert Buytenhekee040872010-11-29 10:33:49 +0100229 .irq_ack = ixp4xx_irq_ack,
230 .irq_mask = ixp4xx_irq_mask,
231 .irq_unmask = ixp4xx_irq_unmask,
232 .irq_set_type = ixp4xx_set_irq_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233};
234
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235void __init ixp4xx_init_irq(void)
236{
237 int i = 0;
238
Nicolas Pitre12d2b4e2011-08-03 07:25:39 -0400239 /*
240 * ixp4xx does not implement the XScale PWRMODE register
241 * so it must not call cpu_do_idle().
242 */
Thomas Gleixnerf7b861b2013-03-21 22:49:38 +0100243 cpu_idle_poll_ctrl(true);
Nicolas Pitre12d2b4e2011-08-03 07:25:39 -0400244
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 /* Route all sources to IRQ instead of FIQ */
246 *IXP4XX_ICLR = 0x0;
247
248 /* Disable all interrupt */
249 *IXP4XX_ICMR = 0x0;
250
Ruslan V. Sushko45fba082007-04-06 15:00:31 +0100251 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252 /* Route upper 32 sources to IRQ instead of FIQ */
253 *IXP4XX_ICLR2 = 0x00;
254
255 /* Disable upper 32 interrupts */
256 *IXP4XX_ICMR2 = 0x00;
257 }
258
259 /* Default to all level triggered */
Kevin Hilman984d1152006-11-03 01:47:20 +0100260 for(i = 0; i < NR_IRQS; i++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100261 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
262 handle_level_irq);
Kevin Hilman984d1152006-11-03 01:47:20 +0100263 set_irq_flags(i, IRQF_VALID);
264 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265}
266
267
268/*************************************************************************
269 * IXP4xx timer tick
270 * We use OS timer1 on the CPU for the timer tick and the timestamp
271 * counter as a source of real clock ticks to account for missed jiffies.
272 *************************************************************************/
273
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700274static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275{
Mikael Petterssonceb69a82009-09-11 00:59:07 +0200276 struct clock_event_device *evt = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277
278 /* Clear Pending Interrupt by writing '1' to it */
279 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
280
Kevin Hilmane32f1502007-03-08 20:23:59 +0100281 evt->event_handler(evt);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282
283 return IRQ_HANDLED;
284}
285
286static struct irqaction ixp4xx_timer_irq = {
Kevin Hilmane32f1502007-03-08 20:23:59 +0100287 .name = "timer1",
Bernhard Walleb30faba2007-05-08 00:35:39 -0700288 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Russell King09b8b5f2005-06-26 17:06:36 +0100289 .handler = ixp4xx_timer_interrupt,
Mikael Petterssonceb69a82009-09-11 00:59:07 +0200290 .dev_id = &clockevent_ixp4xx,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291};
292
Michael-Luke Jones435c5da2007-05-23 22:38:45 +0100293void __init ixp4xx_timer_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294{
Kevin Hilmane32f1502007-03-08 20:23:59 +0100295 /* Reset/disable counter */
296 *IXP4XX_OSRT1 = 0;
297
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 /* Clear Pending Interrupt by writing '1' to it */
299 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
300
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 /* Reset time-stamp counter */
302 *IXP4XX_OSTS = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304 /* Connect the interrupt handler and enable the interrupt */
305 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
Kevin Hilmanf9a8ca12006-12-06 00:45:07 +0100306
307 ixp4xx_clocksource_init();
Kevin Hilmane32f1502007-03-08 20:23:59 +0100308 ixp4xx_clockevent_init();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309}
310
Milan Svobodae520a362006-12-01 11:36:41 +0100311static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
312
313void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
314{
315 memcpy(&ixp4xx_udc_info, info, sizeof *info);
316}
317
318static struct resource ixp4xx_udc_resources[] = {
319 [0] = {
320 .start = 0xc800b000,
321 .end = 0xc800bfff,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
325 .start = IRQ_IXP4XX_USB,
326 .end = IRQ_IXP4XX_USB,
327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331/*
Philipp Zabel7a857622008-06-22 23:36:39 +0100332 * USB device controller. The IXP4xx uses the same controller as PXA25X,
Milan Svobodae520a362006-12-01 11:36:41 +0100333 * so we just use the same device.
334 */
335static struct platform_device ixp4xx_udc_device = {
Philipp Zabel7a857622008-06-22 23:36:39 +0100336 .name = "pxa25x-udc",
Milan Svobodae520a362006-12-01 11:36:41 +0100337 .id = -1,
338 .num_resources = 2,
339 .resource = ixp4xx_udc_resources,
340 .dev = {
341 .platform_data = &ixp4xx_udc_info,
342 },
343};
344
345static struct platform_device *ixp4xx_devices[] __initdata = {
346 &ixp4xx_udc_device,
347};
348
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349static struct resource ixp46x_i2c_resources[] = {
350 [0] = {
351 .start = 0xc8011000,
352 .end = 0xc801101c,
353 .flags = IORESOURCE_MEM,
354 },
355 [1] = {
356 .start = IRQ_IXP4XX_I2C,
357 .end = IRQ_IXP4XX_I2C,
358 .flags = IORESOURCE_IRQ
359 }
360};
361
362/*
363 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
364 * we just use the same device name.
365 */
366static struct platform_device ixp46x_i2c_controller = {
367 .name = "IOP3xx-I2C",
368 .id = 0,
369 .num_resources = 2,
370 .resource = ixp46x_i2c_resources
371};
372
373static struct platform_device *ixp46x_devices[] __initdata = {
374 &ixp46x_i2c_controller
375};
376
Deepak Saxena54e269e2006-01-05 20:59:29 +0000377unsigned long ixp4xx_exp_bus_size;
David Vrabel1e74c892006-01-18 22:46:43 +0000378EXPORT_SYMBOL(ixp4xx_exp_bus_size);
Deepak Saxena54e269e2006-01-05 20:59:29 +0000379
Richard Cochran9dde0ae2012-05-23 18:19:51 +0200380static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
381{
382 gpio_line_config(gpio, IXP4XX_GPIO_IN);
383
384 return 0;
385}
386
387static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
388 int level)
389{
390 gpio_line_set(gpio, level);
391 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
392
393 return 0;
394}
395
396static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
397{
398 int value;
399
400 gpio_line_get(gpio, &value);
401
402 return value;
403}
404
405static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
406 int value)
407{
408 gpio_line_set(gpio, value);
409}
410
411static struct gpio_chip ixp4xx_gpio_chip = {
412 .label = "IXP4XX_GPIO_CHIP",
413 .direction_input = ixp4xx_gpio_direction_input,
414 .direction_output = ixp4xx_gpio_direction_output,
415 .get = ixp4xx_gpio_get_value,
416 .set = ixp4xx_gpio_set_value,
417 .to_irq = ixp4xx_gpio_to_irq,
418 .base = 0,
419 .ngpio = 16,
420};
421
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422void __init ixp4xx_sys_init(void)
423{
Deepak Saxena54e269e2006-01-05 20:59:29 +0000424 ixp4xx_exp_bus_size = SZ_16M;
425
Milan Svobodae520a362006-12-01 11:36:41 +0100426 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
427
Richard Cochran9dde0ae2012-05-23 18:19:51 +0200428 gpiochip_add(&ixp4xx_gpio_chip);
429
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 if (cpu_is_ixp46x()) {
Deepak Saxena54e269e2006-01-05 20:59:29 +0000431 int region;
432
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 platform_add_devices(ixp46x_devices,
434 ARRAY_SIZE(ixp46x_devices));
Deepak Saxena54e269e2006-01-05 20:59:29 +0000435
436 for (region = 0; region < 7; region++) {
437 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
438 ixp4xx_exp_bus_size = SZ_32M;
439 break;
440 }
441 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 }
Deepak Saxena54e269e2006-01-05 20:59:29 +0000443
David Vrabel1e74c892006-01-18 22:46:43 +0000444 printk("IXP4xx: Using %luMiB expansion bus window size\n",
Deepak Saxena54e269e2006-01-05 20:59:29 +0000445 ixp4xx_exp_bus_size >> 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446}
447
Kevin Hilmane32f1502007-03-08 20:23:59 +0100448/*
Russell King5b0d4952010-12-15 21:23:13 +0000449 * sched_clock()
450 */
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100451static u32 notrace ixp4xx_read_sched_clock(void)
Russell King5b0d4952010-12-15 21:23:13 +0000452{
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100453 return *IXP4XX_OSTS;
Russell King5b0d4952010-12-15 21:23:13 +0000454}
455
456/*
Kevin Hilmane32f1502007-03-08 20:23:59 +0100457 * clocksource
458 */
Richard Cochran900b1702011-07-15 21:33:12 +0200459
460static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
461{
462 return *IXP4XX_OSTS;
463}
464
Ben Hutchingse66a0222010-12-11 20:17:54 +0000465unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
Krzysztof Halasa5dbc4652009-09-05 03:59:49 +0000466EXPORT_SYMBOL(ixp4xx_timer_freq);
Mikael Petterssonceb69a82009-09-11 00:59:07 +0200467static void __init ixp4xx_clocksource_init(void)
Kevin Hilman84904d02006-09-22 00:58:57 +0100468{
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100469 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
Russell King5b0d4952010-12-15 21:23:13 +0000470
Richard Cochran900b1702011-07-15 21:33:12 +0200471 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
472 ixp4xx_clocksource_read);
Kevin Hilman84904d02006-09-22 00:58:57 +0100473}
Kevin Hilmane32f1502007-03-08 20:23:59 +0100474
475/*
476 * clockevents
477 */
478static int ixp4xx_set_next_event(unsigned long evt,
479 struct clock_event_device *unused)
480{
481 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
482
483 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
484
485 return 0;
486}
487
488static void ixp4xx_set_mode(enum clock_event_mode mode,
489 struct clock_event_device *evt)
490{
Kevin Hilman553876c2007-12-12 00:32:58 +0100491 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
492 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
Kevin Hilmane32f1502007-03-08 20:23:59 +0100493
494 switch (mode) {
495 case CLOCK_EVT_MODE_PERIODIC:
496 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
497 opts = IXP4XX_OST_ENABLE;
498 break;
499 case CLOCK_EVT_MODE_ONESHOT:
500 /* period set by 'set next_event' */
501 osrt = 0;
502 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
503 break;
504 case CLOCK_EVT_MODE_SHUTDOWN:
Kevin Hilman553876c2007-12-12 00:32:58 +0100505 opts &= ~IXP4XX_OST_ENABLE;
506 break;
507 case CLOCK_EVT_MODE_RESUME:
508 opts |= IXP4XX_OST_ENABLE;
509 break;
Kevin Hilmane32f1502007-03-08 20:23:59 +0100510 case CLOCK_EVT_MODE_UNUSED:
511 default:
512 osrt = opts = 0;
513 break;
514 }
515
516 *IXP4XX_OSRT1 = osrt | opts;
517}
518
519static struct clock_event_device clockevent_ixp4xx = {
520 .name = "ixp4xx timer1",
521 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
522 .rating = 200,
Kevin Hilmane32f1502007-03-08 20:23:59 +0100523 .set_mode = ixp4xx_set_mode,
524 .set_next_event = ixp4xx_set_next_event,
525};
526
Mikael Petterssonceb69a82009-09-11 00:59:07 +0200527static void __init ixp4xx_clockevent_init(void)
Kevin Hilmane32f1502007-03-08 20:23:59 +0100528{
Rusty Russell320ab2b2008-12-13 21:20:26 +1030529 clockevent_ixp4xx.cpumask = cpumask_of(0);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000530 clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
531 0xf, 0xfffffffe);
Kevin Hilmane32f1502007-03-08 20:23:59 +0100532}
Russell Kingd1b860f2011-11-05 12:10:55 +0000533
Robin Holt7b6d8642013-07-08 16:01:40 -0700534void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
Russell Kingd1b860f2011-11-05 12:10:55 +0000535{
Robin Holt7b6d8642013-07-08 16:01:40 -0700536 if ( 1 && mode == REBOOT_SOFT) {
Russell Kingd1b860f2011-11-05 12:10:55 +0000537 /* Jump into ROM at address 0 */
538 soft_restart(0);
539 } else {
540 /* Use on-chip reset capability */
541
542 /* set the "key" register to enable access to
543 * "timer" and "enable" registers
544 */
545 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
546
547 /* write 0 to the timer register for an immediate reset */
548 *IXP4XX_OSWT = 0;
549
550 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
551 }
552}
Rob Herringf4495882012-03-06 15:01:53 -0600553
554#ifdef CONFIG_IXP4XX_INDIRECT_PCI
555/*
556 * In the case of using indirect PCI, we simply return the actual PCI
557 * address and our read/write implementation use that to drive the
558 * access registers. If something outside of PCI is ioremap'd, we
559 * fallback to the default.
560 */
561
Laura Abbott9b971732013-05-16 19:40:22 +0100562static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
Rob Herringf4495882012-03-06 15:01:53 -0600563 unsigned int mtype, void *caller)
564{
565 if (!is_pci_memory(addr))
566 return __arm_ioremap_caller(addr, size, mtype, caller);
567
568 return (void __iomem *)addr;
569}
570
571static void ixp4xx_iounmap(void __iomem *addr)
572{
573 if (!is_pci_memory((__force u32)addr))
574 __iounmap(addr);
575}
576
577void __init ixp4xx_init_early(void)
578{
579 arch_ioremap_caller = ixp4xx_ioremap_caller;
580 arch_iounmap = ixp4xx_iounmap;
581}
582#else
583void __init ixp4xx_init_early(void) {}
584#endif