Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 25 | #include <core/client.h> |
| 26 | #include <core/handle.h> |
| 27 | #include <core/namedb.h> |
| 28 | #include <core/gpuobj.h> |
| 29 | #include <core/engctx.h> |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 30 | #include <core/event.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 31 | #include <core/class.h> |
| 32 | #include <core/math.h> |
| 33 | #include <core/enum.h> |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 34 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 35 | #include <subdev/timer.h> |
| 36 | #include <subdev/bar.h> |
| 37 | #include <subdev/vm.h> |
| 38 | |
| 39 | #include <engine/dmaobj.h> |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame] | 40 | #include <engine/fifo.h> |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 41 | |
| 42 | struct nvc0_fifo_priv { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 43 | struct nouveau_fifo base; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 44 | struct nouveau_gpuobj *playlist[2]; |
| 45 | int cur_playlist; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 46 | struct { |
| 47 | struct nouveau_gpuobj *mem; |
| 48 | struct nouveau_vma bar; |
| 49 | } user; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 50 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 51 | }; |
| 52 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 53 | struct nvc0_fifo_base { |
| 54 | struct nouveau_fifo_base base; |
| 55 | struct nouveau_gpuobj *pgd; |
| 56 | struct nouveau_vm *vm; |
| 57 | }; |
| 58 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 59 | struct nvc0_fifo_chan { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 60 | struct nouveau_fifo_chan base; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 61 | }; |
| 62 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 63 | /******************************************************************************* |
| 64 | * FIFO channel objects |
| 65 | ******************************************************************************/ |
| 66 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 67 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 68 | nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 69 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 70 | struct nouveau_bar *bar = nouveau_bar(priv); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 71 | struct nouveau_gpuobj *cur; |
| 72 | int i, p; |
| 73 | |
Ben Skeggs | fadb171 | 2013-05-13 10:02:11 +1000 | [diff] [blame^] | 74 | mutex_lock(&nv_subdev(priv)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 75 | cur = priv->playlist[priv->cur_playlist]; |
| 76 | priv->cur_playlist = !priv->cur_playlist; |
| 77 | |
| 78 | for (i = 0, p = 0; i < 128; i++) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 79 | if (!(nv_rd32(priv, 0x003004 + (i * 8)) & 1)) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 80 | continue; |
| 81 | nv_wo32(cur, p + 0, i); |
| 82 | nv_wo32(cur, p + 4, 0x00000004); |
| 83 | p += 8; |
| 84 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 85 | bar->flush(bar); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 86 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 87 | nv_wr32(priv, 0x002270, cur->addr >> 12); |
| 88 | nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); |
| 89 | if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000)) |
| 90 | nv_error(priv, "playlist update failed\n"); |
Ben Skeggs | fadb171 | 2013-05-13 10:02:11 +1000 | [diff] [blame^] | 91 | mutex_unlock(&nv_subdev(priv)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 92 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 93 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 94 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 95 | nvc0_fifo_context_attach(struct nouveau_object *parent, |
| 96 | struct nouveau_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 97 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 98 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 99 | struct nvc0_fifo_base *base = (void *)parent->parent; |
| 100 | struct nouveau_engctx *ectx = (void *)object; |
| 101 | u32 addr; |
| 102 | int ret; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 103 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 104 | switch (nv_engidx(object->engine)) { |
| 105 | case NVDEV_ENGINE_SW : return 0; |
| 106 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 107 | case NVDEV_ENGINE_COPY0: addr = 0x0230; break; |
| 108 | case NVDEV_ENGINE_COPY1: addr = 0x0240; break; |
Maarten Lankhorst | 23c14ed | 2012-11-23 11:08:23 +1000 | [diff] [blame] | 109 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
| 110 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
| 111 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 112 | default: |
| 113 | return -EINVAL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 114 | } |
| 115 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 116 | if (!ectx->vma.node) { |
| 117 | ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 118 | NV_MEM_ACCESS_RW, &ectx->vma); |
| 119 | if (ret) |
| 120 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 121 | |
| 122 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 123 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 124 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 125 | nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 126 | nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
| 127 | bar->flush(bar); |
| 128 | return 0; |
| 129 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 130 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 131 | static int |
| 132 | nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, |
| 133 | struct nouveau_object *object) |
| 134 | { |
| 135 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 136 | struct nvc0_fifo_priv *priv = (void *)parent->engine; |
| 137 | struct nvc0_fifo_base *base = (void *)parent->parent; |
| 138 | struct nvc0_fifo_chan *chan = (void *)parent; |
| 139 | u32 addr; |
| 140 | |
| 141 | switch (nv_engidx(object->engine)) { |
| 142 | case NVDEV_ENGINE_SW : return 0; |
| 143 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 144 | case NVDEV_ENGINE_COPY0: addr = 0x0230; break; |
| 145 | case NVDEV_ENGINE_COPY1: addr = 0x0240; break; |
Maarten Lankhorst | 23c14ed | 2012-11-23 11:08:23 +1000 | [diff] [blame] | 146 | case NVDEV_ENGINE_BSP : addr = 0x0270; break; |
| 147 | case NVDEV_ENGINE_VP : addr = 0x0250; break; |
| 148 | case NVDEV_ENGINE_PPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 149 | default: |
| 150 | return -EINVAL; |
| 151 | } |
| 152 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 153 | nv_wr32(priv, 0x002634, chan->base.chid); |
| 154 | if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 155 | nv_error(priv, "channel %d [%s] kick timeout\n", |
| 156 | chan->base.chid, nouveau_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 157 | if (suspend) |
| 158 | return -EBUSY; |
| 159 | } |
| 160 | |
Ben Skeggs | edc260d | 2012-11-27 11:05:36 +1000 | [diff] [blame] | 161 | nv_wo32(base, addr + 0x00, 0x00000000); |
| 162 | nv_wo32(base, addr + 0x04, 0x00000000); |
| 163 | bar->flush(bar); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | static int |
| 168 | nvc0_fifo_chan_ctor(struct nouveau_object *parent, |
| 169 | struct nouveau_object *engine, |
| 170 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 171 | struct nouveau_object **pobject) |
| 172 | { |
| 173 | struct nouveau_bar *bar = nouveau_bar(parent); |
| 174 | struct nvc0_fifo_priv *priv = (void *)engine; |
| 175 | struct nvc0_fifo_base *base = (void *)parent; |
| 176 | struct nvc0_fifo_chan *chan; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 177 | struct nv50_channel_ind_class *args = data; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 178 | u64 usermem, ioffset, ilength; |
| 179 | int ret, i; |
| 180 | |
| 181 | if (size < sizeof(*args)) |
| 182 | return -EINVAL; |
| 183 | |
| 184 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, |
| 185 | priv->user.bar.offset, 0x1000, |
| 186 | args->pushbuf, |
Martin Peres | 507ceb1 | 2012-11-27 00:30:32 +0100 | [diff] [blame] | 187 | (1ULL << NVDEV_ENGINE_SW) | |
| 188 | (1ULL << NVDEV_ENGINE_GR) | |
| 189 | (1ULL << NVDEV_ENGINE_COPY0) | |
| 190 | (1ULL << NVDEV_ENGINE_COPY1) | |
| 191 | (1ULL << NVDEV_ENGINE_BSP) | |
| 192 | (1ULL << NVDEV_ENGINE_VP) | |
| 193 | (1ULL << NVDEV_ENGINE_PPP), &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 194 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 195 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 196 | return ret; |
| 197 | |
| 198 | nv_parent(chan)->context_attach = nvc0_fifo_context_attach; |
| 199 | nv_parent(chan)->context_detach = nvc0_fifo_context_detach; |
| 200 | |
| 201 | usermem = chan->base.chid * 0x1000; |
| 202 | ioffset = args->ioffset; |
| 203 | ilength = log2i(args->ilength / 8); |
| 204 | |
| 205 | for (i = 0; i < 0x1000; i += 4) |
| 206 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); |
| 207 | |
| 208 | nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); |
| 209 | nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); |
| 210 | nv_wo32(base, 0x10, 0x0000face); |
| 211 | nv_wo32(base, 0x30, 0xfffff902); |
| 212 | nv_wo32(base, 0x48, lower_32_bits(ioffset)); |
| 213 | nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 214 | nv_wo32(base, 0x54, 0x00000002); |
| 215 | nv_wo32(base, 0x84, 0x20400000); |
| 216 | nv_wo32(base, 0x94, 0x30000001); |
| 217 | nv_wo32(base, 0x9c, 0x00000100); |
| 218 | nv_wo32(base, 0xa4, 0x1f1f1f1f); |
| 219 | nv_wo32(base, 0xa8, 0x1f1f1f1f); |
| 220 | nv_wo32(base, 0xac, 0x0000001f); |
| 221 | nv_wo32(base, 0xb8, 0xf8000000); |
| 222 | nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ |
| 223 | nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ |
| 224 | bar->flush(bar); |
| 225 | return 0; |
| 226 | } |
| 227 | |
| 228 | static int |
| 229 | nvc0_fifo_chan_init(struct nouveau_object *object) |
| 230 | { |
| 231 | struct nouveau_gpuobj *base = nv_gpuobj(object->parent); |
| 232 | struct nvc0_fifo_priv *priv = (void *)object->engine; |
| 233 | struct nvc0_fifo_chan *chan = (void *)object; |
| 234 | u32 chid = chan->base.chid; |
| 235 | int ret; |
| 236 | |
| 237 | ret = nouveau_fifo_channel_init(&chan->base); |
| 238 | if (ret) |
| 239 | return ret; |
| 240 | |
| 241 | nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); |
| 242 | nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); |
| 243 | nvc0_fifo_playlist_update(priv); |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | static int |
| 248 | nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend) |
| 249 | { |
| 250 | struct nvc0_fifo_priv *priv = (void *)object->engine; |
| 251 | struct nvc0_fifo_chan *chan = (void *)object; |
| 252 | u32 chid = chan->base.chid; |
| 253 | |
| 254 | nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); |
| 255 | nvc0_fifo_playlist_update(priv); |
| 256 | nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); |
| 257 | |
| 258 | return nouveau_fifo_channel_fini(&chan->base, suspend); |
| 259 | } |
| 260 | |
| 261 | static struct nouveau_ofuncs |
| 262 | nvc0_fifo_ofuncs = { |
| 263 | .ctor = nvc0_fifo_chan_ctor, |
| 264 | .dtor = _nouveau_fifo_channel_dtor, |
| 265 | .init = nvc0_fifo_chan_init, |
| 266 | .fini = nvc0_fifo_chan_fini, |
| 267 | .rd32 = _nouveau_fifo_channel_rd32, |
| 268 | .wr32 = _nouveau_fifo_channel_wr32, |
| 269 | }; |
| 270 | |
| 271 | static struct nouveau_oclass |
| 272 | nvc0_fifo_sclass[] = { |
Ben Skeggs | c97f8c9 | 2012-08-19 16:03:00 +1000 | [diff] [blame] | 273 | { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 274 | {} |
| 275 | }; |
| 276 | |
| 277 | /******************************************************************************* |
| 278 | * FIFO context - instmem heap and vm setup |
| 279 | ******************************************************************************/ |
| 280 | |
| 281 | static int |
| 282 | nvc0_fifo_context_ctor(struct nouveau_object *parent, |
| 283 | struct nouveau_object *engine, |
| 284 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 285 | struct nouveau_object **pobject) |
| 286 | { |
| 287 | struct nvc0_fifo_base *base; |
| 288 | int ret; |
| 289 | |
| 290 | ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 291 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | |
| 292 | NVOBJ_FLAG_HEAP, &base); |
| 293 | *pobject = nv_object(base); |
| 294 | if (ret) |
| 295 | return ret; |
| 296 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 297 | ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 298 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 299 | if (ret) |
| 300 | return ret; |
| 301 | |
| 302 | nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); |
| 303 | nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); |
| 304 | nv_wo32(base, 0x0208, 0xffffffff); |
| 305 | nv_wo32(base, 0x020c, 0x000000ff); |
| 306 | |
| 307 | ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); |
| 308 | if (ret) |
| 309 | return ret; |
| 310 | |
| 311 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 312 | } |
| 313 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 314 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 315 | nvc0_fifo_context_dtor(struct nouveau_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 316 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 317 | struct nvc0_fifo_base *base = (void *)object; |
| 318 | nouveau_vm_ref(NULL, &base->vm, base->pgd); |
| 319 | nouveau_gpuobj_ref(NULL, &base->pgd); |
| 320 | nouveau_fifo_context_destroy(&base->base); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 321 | } |
| 322 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 323 | static struct nouveau_oclass |
| 324 | nvc0_fifo_cclass = { |
| 325 | .handle = NV_ENGCTX(FIFO, 0xc0), |
| 326 | .ofuncs = &(struct nouveau_ofuncs) { |
| 327 | .ctor = nvc0_fifo_context_ctor, |
| 328 | .dtor = nvc0_fifo_context_dtor, |
| 329 | .init = _nouveau_fifo_context_init, |
| 330 | .fini = _nouveau_fifo_context_fini, |
| 331 | .rd32 = _nouveau_fifo_context_rd32, |
| 332 | .wr32 = _nouveau_fifo_context_wr32, |
| 333 | }, |
| 334 | }; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 335 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 336 | /******************************************************************************* |
| 337 | * PFIFO engine |
| 338 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 339 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 340 | static const struct nouveau_enum nvc0_fifo_fault_unit[] = { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 341 | { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 342 | { 0x03, "PEEPHOLE" }, |
| 343 | { 0x04, "BAR1" }, |
| 344 | { 0x05, "BAR3" }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 345 | { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, |
| 346 | { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP }, |
| 347 | { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 348 | { 0x13, "PCOUNTER" }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 349 | { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, |
| 350 | { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 }, |
| 351 | { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 352 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 353 | {} |
| 354 | }; |
| 355 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 356 | static const struct nouveau_enum nvc0_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 357 | { 0x00, "PT_NOT_PRESENT" }, |
| 358 | { 0x01, "PT_TOO_SHORT" }, |
| 359 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 360 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 361 | { 0x04, "NO_CHANNEL" }, |
| 362 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 363 | { 0x06, "PAGE_READ_ONLY" }, |
| 364 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 365 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 366 | {} |
| 367 | }; |
| 368 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 369 | static const struct nouveau_enum nvc0_fifo_fault_hubclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 370 | { 0x01, "PCOPY0" }, |
| 371 | { 0x02, "PCOPY1" }, |
| 372 | { 0x04, "DISPATCH" }, |
| 373 | { 0x05, "CTXCTL" }, |
| 374 | { 0x06, "PFIFO" }, |
| 375 | { 0x07, "BAR_READ" }, |
| 376 | { 0x08, "BAR_WRITE" }, |
| 377 | { 0x0b, "PVP" }, |
| 378 | { 0x0c, "PPPP" }, |
| 379 | { 0x0d, "PBSP" }, |
| 380 | { 0x11, "PCOUNTER" }, |
| 381 | { 0x12, "PDAEMON" }, |
| 382 | { 0x14, "CCACHE" }, |
| 383 | { 0x15, "CCACHE_POST" }, |
| 384 | {} |
| 385 | }; |
| 386 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 387 | static const struct nouveau_enum nvc0_fifo_fault_gpcclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 388 | { 0x01, "TEX" }, |
| 389 | { 0x0c, "ESETUP" }, |
| 390 | { 0x0e, "CTXCTL" }, |
| 391 | { 0x0f, "PROP" }, |
| 392 | {} |
| 393 | }; |
| 394 | |
Marcin Slusarz | e662625 | 2012-08-19 22:59:59 +0200 | [diff] [blame] | 395 | static const struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = { |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 396 | /* { 0x00008000, "" } seen with null ib push */ |
| 397 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 398 | { 0x00800000, "EMPTY_SUBC" }, |
| 399 | {} |
| 400 | }; |
| 401 | |
| 402 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 403 | nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 404 | { |
Ben Skeggs | b3ccd34 | 2012-09-06 20:26:38 -0400 | [diff] [blame] | 405 | u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); |
| 406 | u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); |
| 407 | u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); |
| 408 | u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 409 | u32 client = (stat & 0x00001f00) >> 8; |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 410 | const struct nouveau_enum *en; |
| 411 | struct nouveau_engine *engine; |
| 412 | struct nouveau_object *engctx = NULL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 413 | |
Ben Skeggs | b3ccd34 | 2012-09-06 20:26:38 -0400 | [diff] [blame] | 414 | switch (unit) { |
| 415 | case 3: /* PEEPHOLE */ |
| 416 | nv_mask(priv, 0x001718, 0x00000000, 0x00000000); |
| 417 | break; |
| 418 | case 4: /* BAR1 */ |
| 419 | nv_mask(priv, 0x001704, 0x00000000, 0x00000000); |
| 420 | break; |
| 421 | case 5: /* BAR3 */ |
| 422 | nv_mask(priv, 0x001714, 0x00000000, 0x00000000); |
| 423 | break; |
| 424 | default: |
| 425 | break; |
| 426 | } |
| 427 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 428 | nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ? |
| 429 | "write" : "read", (u64)vahi << 32 | valo); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 430 | nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 431 | pr_cont("] from "); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 432 | en = nouveau_enum_print(nvc0_fifo_fault_unit, unit); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 433 | if (stat & 0x00000040) { |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 434 | pr_cont("/"); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 435 | nouveau_enum_print(nvc0_fifo_fault_hubclient, client); |
| 436 | } else { |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 437 | pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24); |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 438 | nouveau_enum_print(nvc0_fifo_fault_gpcclient, client); |
| 439 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 440 | |
| 441 | if (en && en->data2) { |
| 442 | engine = nouveau_engine(priv, en->data2); |
| 443 | if (engine) |
| 444 | engctx = nouveau_engctx_get(engine, inst); |
| 445 | |
| 446 | } |
| 447 | pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, |
| 448 | nouveau_client_name(engctx)); |
| 449 | |
| 450 | nouveau_engctx_put(engctx); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 451 | } |
| 452 | |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 453 | static int |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 454 | nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 455 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 456 | struct nvc0_fifo_chan *chan = NULL; |
| 457 | struct nouveau_handle *bind; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 458 | unsigned long flags; |
| 459 | int ret = -EINVAL; |
| 460 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 461 | spin_lock_irqsave(&priv->base.lock, flags); |
| 462 | if (likely(chid >= priv->base.min && chid <= priv->base.max)) |
| 463 | chan = (void *)priv->base.channel[chid]; |
| 464 | if (unlikely(!chan)) |
| 465 | goto out; |
| 466 | |
| 467 | bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); |
| 468 | if (likely(bind)) { |
| 469 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 470 | ret = 0; |
| 471 | nouveau_namedb_put(bind); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 472 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 473 | |
| 474 | out: |
| 475 | spin_unlock_irqrestore(&priv->base.lock, flags); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 476 | return ret; |
| 477 | } |
| 478 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 479 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 480 | nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 481 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 482 | u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); |
| 483 | u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); |
| 484 | u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); |
| 485 | u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; |
| 486 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 487 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 488 | u32 show = stat; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 489 | |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 490 | if (stat & 0x00200000) { |
| 491 | if (mthd == 0x0054) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 492 | if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000)) |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 493 | show &= ~0x00200000; |
| 494 | } |
| 495 | } |
| 496 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 497 | if (stat & 0x00800000) { |
| 498 | if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) |
| 499 | show &= ~0x00800000; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 500 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 501 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 502 | if (show) { |
| 503 | nv_error(priv, "SUBFIFO%d:", unit); |
| 504 | nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show); |
Marcin Slusarz | f533da1 | 2012-12-09 15:45:20 +0100 | [diff] [blame] | 505 | pr_cont("\n"); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 506 | nv_error(priv, |
| 507 | "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
| 508 | unit, chid, |
| 509 | nouveau_client_name_for_fifo_chid(&priv->base, chid), |
| 510 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 514 | nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 515 | } |
| 516 | |
| 517 | static void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 518 | nvc0_fifo_intr(struct nouveau_subdev *subdev) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 519 | { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 520 | struct nvc0_fifo_priv *priv = (void *)subdev; |
| 521 | u32 mask = nv_rd32(priv, 0x002140); |
| 522 | u32 stat = nv_rd32(priv, 0x002100) & mask; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 523 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 524 | if (stat & 0x00000001) { |
| 525 | u32 intr = nv_rd32(priv, 0x00252c); |
| 526 | nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); |
| 527 | nv_wr32(priv, 0x002100, 0x00000001); |
| 528 | stat &= ~0x00000001; |
| 529 | } |
| 530 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 531 | if (stat & 0x00000100) { |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 532 | u32 intr = nv_rd32(priv, 0x00254c); |
| 533 | nv_warn(priv, "INTR 0x00000100: 0x%08x\n", intr); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 534 | nv_wr32(priv, 0x002100, 0x00000100); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 535 | stat &= ~0x00000100; |
| 536 | } |
| 537 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 538 | if (stat & 0x00010000) { |
| 539 | u32 intr = nv_rd32(priv, 0x00256c); |
| 540 | nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); |
| 541 | nv_wr32(priv, 0x002100, 0x00010000); |
| 542 | stat &= ~0x00010000; |
| 543 | } |
| 544 | |
| 545 | if (stat & 0x01000000) { |
| 546 | u32 intr = nv_rd32(priv, 0x00258c); |
| 547 | nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); |
| 548 | nv_wr32(priv, 0x002100, 0x01000000); |
| 549 | stat &= ~0x01000000; |
| 550 | } |
| 551 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 552 | if (stat & 0x10000000) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 553 | u32 units = nv_rd32(priv, 0x00259c); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 554 | u32 u = units; |
| 555 | |
| 556 | while (u) { |
| 557 | int i = ffs(u) - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 558 | nvc0_fifo_isr_vm_fault(priv, i); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 559 | u &= ~(1 << i); |
| 560 | } |
| 561 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 562 | nv_wr32(priv, 0x00259c, units); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 563 | stat &= ~0x10000000; |
| 564 | } |
| 565 | |
| 566 | if (stat & 0x20000000) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 567 | u32 units = nv_rd32(priv, 0x0025a0); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 568 | u32 u = units; |
| 569 | |
| 570 | while (u) { |
| 571 | int i = ffs(u) - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 572 | nvc0_fifo_isr_subfifo_intr(priv, i); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 573 | u &= ~(1 << i); |
| 574 | } |
| 575 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 576 | nv_wr32(priv, 0x0025a0, units); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 577 | stat &= ~0x20000000; |
| 578 | } |
| 579 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 580 | if (stat & 0x40000000) { |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 581 | u32 intr0 = nv_rd32(priv, 0x0025a4); |
| 582 | u32 intr1 = nv_mask(priv, 0x002a00, 0x00000000, 0x00000); |
| 583 | nv_debug(priv, "INTR 0x40000000: 0x%08x 0x%08x\n", |
| 584 | intr0, intr1); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 585 | stat &= ~0x40000000; |
| 586 | } |
| 587 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 588 | if (stat & 0x80000000) { |
| 589 | u32 intr = nv_mask(priv, 0x0025a8, 0x00000000, 0x00000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 590 | nouveau_event_trigger(priv->base.uevent, 0); |
| 591 | nv_debug(priv, "INTR 0x80000000: 0x%08x\n", intr); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 592 | stat &= ~0x80000000; |
| 593 | } |
| 594 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 595 | if (stat) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 596 | nv_fatal(priv, "unhandled status 0x%08x\n", stat); |
| 597 | nv_wr32(priv, 0x002100, stat); |
| 598 | nv_wr32(priv, 0x002140, 0); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 599 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 600 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 601 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 602 | static void |
| 603 | nvc0_fifo_uevent_enable(struct nouveau_event *event, int index) |
| 604 | { |
| 605 | struct nvc0_fifo_priv *priv = event->priv; |
| 606 | nv_mask(priv, 0x002140, 0x80000000, 0x80000000); |
| 607 | } |
| 608 | |
| 609 | static void |
| 610 | nvc0_fifo_uevent_disable(struct nouveau_event *event, int index) |
| 611 | { |
| 612 | struct nvc0_fifo_priv *priv = event->priv; |
| 613 | nv_mask(priv, 0x002140, 0x80000000, 0x00000000); |
| 614 | } |
| 615 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 616 | static int |
| 617 | nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 618 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 619 | struct nouveau_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 620 | { |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 621 | struct nvc0_fifo_priv *priv; |
| 622 | int ret; |
| 623 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 624 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv); |
| 625 | *pobject = nv_object(priv); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 626 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 627 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 628 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 629 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 630 | &priv->playlist[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 631 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 632 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 633 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 634 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 635 | &priv->playlist[1]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 636 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 637 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 638 | |
Ben Skeggs | f50c805 | 2013-04-24 18:02:35 +1000 | [diff] [blame] | 639 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 640 | &priv->user.mem); |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 641 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 642 | return ret; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 643 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 644 | ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, |
| 645 | &priv->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 646 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 647 | return ret; |
| 648 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 649 | priv->base.uevent->enable = nvc0_fifo_uevent_enable; |
| 650 | priv->base.uevent->disable = nvc0_fifo_uevent_disable; |
| 651 | priv->base.uevent->priv = priv; |
| 652 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 653 | nv_subdev(priv)->unit = 0x00000100; |
| 654 | nv_subdev(priv)->intr = nvc0_fifo_intr; |
| 655 | nv_engine(priv)->cclass = &nvc0_fifo_cclass; |
| 656 | nv_engine(priv)->sclass = nvc0_fifo_sclass; |
| 657 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 658 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 659 | |
| 660 | static void |
| 661 | nvc0_fifo_dtor(struct nouveau_object *object) |
| 662 | { |
| 663 | struct nvc0_fifo_priv *priv = (void *)object; |
| 664 | |
| 665 | nouveau_gpuobj_unmap(&priv->user.bar); |
| 666 | nouveau_gpuobj_ref(NULL, &priv->user.mem); |
| 667 | nouveau_gpuobj_ref(NULL, &priv->playlist[1]); |
| 668 | nouveau_gpuobj_ref(NULL, &priv->playlist[0]); |
| 669 | |
| 670 | nouveau_fifo_destroy(&priv->base); |
| 671 | } |
| 672 | |
| 673 | static int |
| 674 | nvc0_fifo_init(struct nouveau_object *object) |
| 675 | { |
| 676 | struct nvc0_fifo_priv *priv = (void *)object; |
| 677 | int ret, i; |
| 678 | |
| 679 | ret = nouveau_fifo_init(&priv->base); |
| 680 | if (ret) |
| 681 | return ret; |
| 682 | |
| 683 | nv_wr32(priv, 0x000204, 0xffffffff); |
| 684 | nv_wr32(priv, 0x002204, 0xffffffff); |
| 685 | |
| 686 | priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204)); |
| 687 | nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr); |
| 688 | |
| 689 | /* assign engines to subfifos */ |
| 690 | if (priv->spoon_nr >= 3) { |
| 691 | nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 692 | nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ |
| 693 | nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */ |
| 694 | nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */ |
| 695 | nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 696 | nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ |
| 697 | } |
| 698 | |
| 699 | /* PSUBFIFO[n] */ |
| 700 | for (i = 0; i < priv->spoon_nr; i++) { |
| 701 | nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 702 | nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 703 | nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
| 704 | } |
| 705 | |
| 706 | nv_mask(priv, 0x002200, 0x00000001, 0x00000001); |
| 707 | nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); |
| 708 | |
| 709 | nv_wr32(priv, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */ |
| 710 | nv_wr32(priv, 0x002100, 0xffffffff); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 711 | nv_wr32(priv, 0x002140, 0x3fffffff); |
Ben Skeggs | a2fa2973 | 2013-01-31 17:43:55 -0500 | [diff] [blame] | 712 | nv_wr32(priv, 0x002628, 0x00000001); /* makes mthd 0x20 work */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 713 | return 0; |
| 714 | } |
| 715 | |
| 716 | struct nouveau_oclass |
| 717 | nvc0_fifo_oclass = { |
| 718 | .handle = NV_ENGINE(FIFO, 0xc0), |
| 719 | .ofuncs = &(struct nouveau_ofuncs) { |
| 720 | .ctor = nvc0_fifo_ctor, |
| 721 | .dtor = nvc0_fifo_dtor, |
| 722 | .init = nvc0_fifo_init, |
| 723 | .fini = _nouveau_fifo_fini, |
| 724 | }, |
| 725 | }; |