blob: f544e58e1536047a30dbe91414e055f4008a6e7e [file] [log] [blame]
eric miao2c8086a2007-09-11 19:13:17 -07001/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
eric miaoe9bba8e2007-10-30 08:01:38 +01008 * 2007-09-02: eric miao <eric.miao@marvell.com>
eric miao2c8086a2007-09-11 19:13:17 -07009 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
Russell King7b5dea12008-01-07 22:18:30 +000022#include <linux/io.h>
eric miaoc01655042008-01-28 23:00:02 +000023#include <linux/sysdev.h>
eric miao2c8086a2007-09-11 19:13:17 -070024
Russell Kinga09e64f2008-08-05 16:14:15 +010025#include <mach/hardware.h>
Eric Miaoa58fbcd2009-01-06 17:37:37 +080026#include <mach/gpio.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010027#include <mach/pxa3xx-regs.h>
Russell Kingafd2fc02008-08-07 11:05:25 +010028#include <mach/reset.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010029#include <mach/ohci.h>
30#include <mach/pm.h>
31#include <mach/dma.h>
Mike Rapoportbf293ae2009-11-11 11:36:59 +020032#include <mach/regs-intc.h>
Eric Miaof0a83702009-04-13 15:03:11 +080033#include <plat/i2c.h>
eric miao2c8086a2007-09-11 19:13:17 -070034
35#include "generic.h"
36#include "devices.h"
37#include "clock.h"
38
39/* Crystal clock: 13MHz */
40#define BASE_CLK 13000000
41
42/* Ring Oscillator Clock: 60MHz */
43#define RO_CLK 60000000
44
45#define ACCR_D0CS (1 << 26)
eric miaoc4d1fb62008-01-28 23:00:02 +000046#define ACCR_PCCE (1 << 11)
eric miao2c8086a2007-09-11 19:13:17 -070047
Mike Rapoportbf293ae2009-11-11 11:36:59 +020048#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
49#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
50
eric miao2c8086a2007-09-11 19:13:17 -070051/* crystal frequency to static memory controller multiplier (SMCFS) */
52static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
53
54/* crystal frequency to HSIO bus frequency multiplier (HSS) */
55static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
56
57/*
58 * Get the clock frequency as reflected by CCSR and the turbo flag.
59 * We assume these values have been applied via a fcs.
60 * If info is not 0 we also display the current settings.
61 */
62unsigned int pxa3xx_get_clk_frequency_khz(int info)
63{
64 unsigned long acsr, xclkcfg;
65 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
66
67 /* Read XCLKCFG register turbo bit */
68 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
69 t = xclkcfg & 0x1;
70
71 acsr = ACSR;
72
73 xl = acsr & 0x1f;
74 xn = (acsr >> 8) & 0x7;
75 hss = (acsr >> 14) & 0x3;
76
77 XL = xl * BASE_CLK;
78 XN = xn * XL;
79
80 ro = acsr & ACCR_D0CS;
81
82 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
83 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
84
85 if (info) {
86 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
87 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
88 (ro) ? "" : "in");
89 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
90 XL / 1000000, (XL % 1000000) / 10000, xl);
91 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
92 XN / 1000000, (XN % 1000000) / 10000, xn,
93 (t) ? "" : "in");
94 pr_info("HSIO bus clock: %d.%02dMHz\n",
95 HSS / 1000000, (HSS % 1000000) / 10000);
96 }
97
eric miao6232be32008-01-24 02:27:30 +010098 return CLK / 1000;
eric miao2c8086a2007-09-11 19:13:17 -070099}
100
101/*
102 * Return the current static memory controller clock frequency
103 * in units of 10kHz
104 */
105unsigned int pxa3xx_get_memclk_frequency_10khz(void)
106{
107 unsigned long acsr;
108 unsigned int smcfs, clk = 0;
109
110 acsr = ACSR;
111
112 smcfs = (acsr >> 23) & 0x7;
113 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
114
115 return (clk / 10000);
116}
117
Eric Miao04fef222008-07-29 14:26:00 +0800118void pxa3xx_clear_reset_status(unsigned int mask)
119{
120 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
121 ARSR = mask;
122}
123
eric miao2c8086a2007-09-11 19:13:17 -0700124/*
Mark Brown60bfe7f2008-03-04 11:14:23 +0100125 * Return the current AC97 clock frequency.
126 */
127static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
128{
129 unsigned long rate = 312000000;
130 unsigned long ac97_div;
131
132 ac97_div = AC97_DIV;
133
134 /* This may loose precision for some rates but won't for the
135 * standard 24.576MHz.
136 */
137 rate /= (ac97_div >> 12) & 0x7fff;
138 rate *= (ac97_div & 0xfff);
139
140 return rate;
141}
142
143/*
eric miao2c8086a2007-09-11 19:13:17 -0700144 * Return the current HSIO bus clock frequency
145 */
146static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
147{
148 unsigned long acsr;
149 unsigned int hss, hsio_clk;
150
151 acsr = ACSR;
152
153 hss = (acsr >> 14) & 0x3;
154 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
155
156 return hsio_clk;
157}
158
eric miao7a2c5cb2008-02-19 11:13:31 +0800159void clk_pxa3xx_cken_enable(struct clk *clk)
eric miao2c8086a2007-09-11 19:13:17 -0700160{
161 unsigned long mask = 1ul << (clk->cken & 0x1f);
162
eric miao2c8086a2007-09-11 19:13:17 -0700163 if (clk->cken < 32)
164 CKENA |= mask;
165 else
166 CKENB |= mask;
eric miao2c8086a2007-09-11 19:13:17 -0700167}
168
eric miao7a2c5cb2008-02-19 11:13:31 +0800169void clk_pxa3xx_cken_disable(struct clk *clk)
eric miao2c8086a2007-09-11 19:13:17 -0700170{
171 unsigned long mask = 1ul << (clk->cken & 0x1f);
172
eric miao2c8086a2007-09-11 19:13:17 -0700173 if (clk->cken < 32)
174 CKENA &= ~mask;
175 else
176 CKENB &= ~mask;
eric miao2c8086a2007-09-11 19:13:17 -0700177}
178
eric miao7a2c5cb2008-02-19 11:13:31 +0800179const struct clkops clk_pxa3xx_cken_ops = {
eric miao2a0d7182007-10-30 08:10:18 +0100180 .enable = clk_pxa3xx_cken_enable,
181 .disable = clk_pxa3xx_cken_disable,
182};
183
eric miao2c8086a2007-09-11 19:13:17 -0700184static const struct clkops clk_pxa3xx_hsio_ops = {
185 .enable = clk_pxa3xx_cken_enable,
186 .disable = clk_pxa3xx_cken_disable,
187 .getrate = clk_pxa3xx_hsio_getrate,
188};
189
Mark Brown60bfe7f2008-03-04 11:14:23 +0100190static const struct clkops clk_pxa3xx_ac97_ops = {
191 .enable = clk_pxa3xx_cken_enable,
192 .disable = clk_pxa3xx_cken_disable,
193 .getrate = clk_pxa3xx_ac97_getrate,
194};
195
Mark Browndcc88a12008-02-13 16:39:21 +0100196static void clk_pout_enable(struct clk *clk)
197{
198 OSCC |= OSCC_PEN;
199}
200
201static void clk_pout_disable(struct clk *clk)
202{
203 OSCC &= ~OSCC_PEN;
204}
205
206static const struct clkops clk_pout_ops = {
207 .enable = clk_pout_enable,
208 .disable = clk_pout_disable,
209};
210
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100211static void clk_dummy_enable(struct clk *clk)
212{
213}
214
215static void clk_dummy_disable(struct clk *clk)
216{
217}
218
219static const struct clkops clk_dummy_ops = {
220 .enable = clk_dummy_enable,
221 .disable = clk_dummy_disable,
222};
223
Russell King8c3abc72008-11-08 20:25:21 +0000224static struct clk clk_pxa3xx_pout = {
225 .ops = &clk_pout_ops,
226 .rate = 13000000,
227 .delay = 70,
228};
Mark Browndcc88a12008-02-13 16:39:21 +0100229
Russell King8c3abc72008-11-08 20:25:21 +0000230static struct clk clk_dummy = {
231 .ops = &clk_dummy_ops,
232};
233
234static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
235static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
236static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
237static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
238static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
239static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
240static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
241static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
242static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
Igor Grinberge68750a2009-11-04 14:14:39 +0200243static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
Russell King8c3abc72008-11-08 20:25:21 +0000244static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
245static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
246static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
247static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
248static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
249static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
250static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
251static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
252static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
253
254static struct clk_lookup pxa3xx_clkregs[] = {
255 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100256 /* Power I2C clock is always on */
Daniel Mack5c68b092009-06-22 21:01:58 +0200257 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
Russell King8c3abc72008-11-08 20:25:21 +0000258 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
259 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
260 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
261 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
262 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
263 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
264 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
265 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
266 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
267 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
Igor Grinberge68750a2009-11-04 14:14:39 +0200268 INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
Russell King8c3abc72008-11-08 20:25:21 +0000269 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
270 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
271 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
272 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
273 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
274 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
275 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
276 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
277 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
eric miao2c8086a2007-09-11 19:13:17 -0700278};
279
Russell King7b5dea12008-01-07 22:18:30 +0000280#ifdef CONFIG_PM
Russell King7b5dea12008-01-07 22:18:30 +0000281
282#define ISRAM_START 0x5c000000
283#define ISRAM_SIZE SZ_256K
284
285static void __iomem *sram;
286static unsigned long wakeup_src;
287
eric miaoc4d1fb62008-01-28 23:00:02 +0000288#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
289#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
290
Robert Jarzmik649de512008-05-02 21:17:06 +0100291enum { SLEEP_SAVE_CKENA,
eric miaoc4d1fb62008-01-28 23:00:02 +0000292 SLEEP_SAVE_CKENB,
293 SLEEP_SAVE_ACCR,
294
Robert Jarzmik649de512008-05-02 21:17:06 +0100295 SLEEP_SAVE_COUNT,
eric miaoc4d1fb62008-01-28 23:00:02 +0000296};
297
Russell King7b5dea12008-01-07 22:18:30 +0000298static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
299{
eric miaoc4d1fb62008-01-28 23:00:02 +0000300 SAVE(CKENA);
301 SAVE(CKENB);
302 SAVE(ACCR);
Russell King7b5dea12008-01-07 22:18:30 +0000303}
304
305static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
306{
eric miaoc4d1fb62008-01-28 23:00:02 +0000307 RESTORE(ACCR);
308 RESTORE(CKENA);
309 RESTORE(CKENB);
Russell King7b5dea12008-01-07 22:18:30 +0000310}
311
312/*
313 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
314 * memory controller has to be reinitialised, so we place some code
315 * in the SRAM to perform this function.
316 *
317 * We disable FIQs across the standby - otherwise, we might receive a
318 * FIQ while the SDRAM is unavailable.
319 */
320static void pxa3xx_cpu_standby(unsigned int pwrmode)
321{
322 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
323 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
324
325 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
326 pm_enter_standby_end - pm_enter_standby_start);
327
328 AD2D0SR = ~0;
329 AD2D1SR = ~0;
330 AD2D0ER = wakeup_src;
331 AD2D1ER = 0;
332 ASCR = ASCR;
333 ARSR = ARSR;
334
335 local_fiq_disable();
336 fn(pwrmode);
337 local_fiq_enable();
338
339 AD2D0ER = 0;
340 AD2D1ER = 0;
Russell King7b5dea12008-01-07 22:18:30 +0000341}
342
eric miaoc4d1fb62008-01-28 23:00:02 +0000343/*
344 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
345 * PXA3xx development kits assumes that the resuming process continues
346 * with the address stored within the first 4 bytes of SDRAM. The PSPR
347 * register is used privately by BootROM and OBM, and _must_ be set to
348 * 0x5c014000 for the moment.
349 */
350static void pxa3xx_cpu_pm_suspend(void)
351{
352 volatile unsigned long *p = (volatile void *)0xc0000000;
353 unsigned long saved_data = *p;
354
355 extern void pxa3xx_cpu_suspend(void);
356 extern void pxa3xx_cpu_resume(void);
357
358 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
359 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
360 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
361
362 /* clear and setup wakeup source */
363 AD3SR = ~0;
364 AD3ER = wakeup_src;
365 ASCR = ASCR;
366 ARSR = ARSR;
367
368 PCFR |= (1u << 13); /* L1_DIS */
369 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
370
371 PSPR = 0x5c014000;
372
373 /* overwrite with the resume address */
374 *p = virt_to_phys(pxa3xx_cpu_resume);
375
376 pxa3xx_cpu_suspend();
377
378 *p = saved_data;
379
380 AD3ER = 0;
381}
382
Russell King7b5dea12008-01-07 22:18:30 +0000383static void pxa3xx_cpu_pm_enter(suspend_state_t state)
384{
385 /*
386 * Don't sleep if no wakeup sources are defined
387 */
Mark Brownb86a5da2008-04-09 11:32:21 +0100388 if (wakeup_src == 0) {
389 printk(KERN_ERR "Not suspending: no wakeup sources\n");
Russell King7b5dea12008-01-07 22:18:30 +0000390 return;
Mark Brownb86a5da2008-04-09 11:32:21 +0100391 }
Russell King7b5dea12008-01-07 22:18:30 +0000392
393 switch (state) {
394 case PM_SUSPEND_STANDBY:
395 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
396 break;
397
398 case PM_SUSPEND_MEM:
eric miaoc4d1fb62008-01-28 23:00:02 +0000399 pxa3xx_cpu_pm_suspend();
Russell King7b5dea12008-01-07 22:18:30 +0000400 break;
401 }
402}
403
404static int pxa3xx_cpu_pm_valid(suspend_state_t state)
405{
406 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
407}
408
409static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
Robert Jarzmik649de512008-05-02 21:17:06 +0100410 .save_count = SLEEP_SAVE_COUNT,
Russell King7b5dea12008-01-07 22:18:30 +0000411 .save = pxa3xx_cpu_pm_save,
412 .restore = pxa3xx_cpu_pm_restore,
413 .valid = pxa3xx_cpu_pm_valid,
414 .enter = pxa3xx_cpu_pm_enter,
415};
416
417static void __init pxa3xx_init_pm(void)
418{
419 sram = ioremap(ISRAM_START, ISRAM_SIZE);
420 if (!sram) {
421 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
422 return;
423 }
424
425 /*
426 * Since we copy wakeup code into the SRAM, we need to ensure
427 * that it is preserved over the low power modes. Note: bit 8
428 * is undocumented in the developer manual, but must be set.
429 */
430 AD1R |= ADXR_L2 | ADXR_R0;
431 AD2R |= ADXR_L2 | ADXR_R0;
432 AD3R |= ADXR_L2 | ADXR_R0;
433
434 /*
435 * Clear the resume enable registers.
436 */
437 AD1D0ER = 0;
438 AD2D0ER = 0;
439 AD2D1ER = 0;
440 AD3ER = 0;
441
442 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
443}
444
445static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
446{
447 unsigned long flags, mask = 0;
448
449 switch (irq) {
450 case IRQ_SSP3:
451 mask = ADXER_MFP_WSSP3;
452 break;
453 case IRQ_MSL:
454 mask = ADXER_WMSL0;
455 break;
456 case IRQ_USBH2:
457 case IRQ_USBH1:
458 mask = ADXER_WUSBH;
459 break;
460 case IRQ_KEYPAD:
461 mask = ADXER_WKP;
462 break;
463 case IRQ_AC97:
464 mask = ADXER_MFP_WAC97;
465 break;
466 case IRQ_USIM:
467 mask = ADXER_WUSIM0;
468 break;
469 case IRQ_SSP2:
470 mask = ADXER_MFP_WSSP2;
471 break;
472 case IRQ_I2C:
473 mask = ADXER_MFP_WI2C;
474 break;
475 case IRQ_STUART:
476 mask = ADXER_MFP_WUART3;
477 break;
478 case IRQ_BTUART:
479 mask = ADXER_MFP_WUART2;
480 break;
481 case IRQ_FFUART:
482 mask = ADXER_MFP_WUART1;
483 break;
484 case IRQ_MMC:
485 mask = ADXER_MFP_WMMC1;
486 break;
487 case IRQ_SSP:
488 mask = ADXER_MFP_WSSP1;
489 break;
490 case IRQ_RTCAlrm:
491 mask = ADXER_WRTC;
492 break;
493 case IRQ_SSP4:
494 mask = ADXER_MFP_WSSP4;
495 break;
496 case IRQ_TSI:
497 mask = ADXER_WTSI;
498 break;
499 case IRQ_USIM2:
500 mask = ADXER_WUSIM1;
501 break;
502 case IRQ_MMC2:
503 mask = ADXER_MFP_WMMC2;
504 break;
505 case IRQ_NAND:
506 mask = ADXER_MFP_WFLASH;
507 break;
508 case IRQ_USB2:
509 mask = ADXER_WUSB2;
510 break;
511 case IRQ_WAKEUP0:
512 mask = ADXER_WEXTWAKE0;
513 break;
514 case IRQ_WAKEUP1:
515 mask = ADXER_WEXTWAKE1;
516 break;
517 case IRQ_MMC3:
518 mask = ADXER_MFP_GEN12;
519 break;
Mark Browne1217702008-04-23 10:28:18 +0100520 default:
521 return -EINVAL;
Russell King7b5dea12008-01-07 22:18:30 +0000522 }
523
524 local_irq_save(flags);
525 if (on)
526 wakeup_src |= mask;
527 else
528 wakeup_src &= ~mask;
529 local_irq_restore(flags);
530
531 return 0;
532}
Russell King7b5dea12008-01-07 22:18:30 +0000533#else
534static inline void pxa3xx_init_pm(void) {}
eric miaob9e25ac2008-03-04 14:19:58 +0800535#define pxa3xx_set_wake NULL
Russell King7b5dea12008-01-07 22:18:30 +0000536#endif
537
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200538static void pxa_ack_ext_wakeup(unsigned int irq)
539{
540 PECR |= PECR_IS(irq - IRQ_WAKEUP0);
541}
542
543static void pxa_mask_ext_wakeup(unsigned int irq)
544{
545 ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
546 PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
547}
548
549static void pxa_unmask_ext_wakeup(unsigned int irq)
550{
551 ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
552 PECR |= PECR_IE(irq - IRQ_WAKEUP0);
553}
554
555static struct irq_chip pxa_ext_wakeup_chip = {
556 .name = "WAKEUP",
557 .ack = pxa_ack_ext_wakeup,
558 .mask = pxa_mask_ext_wakeup,
559 .unmask = pxa_unmask_ext_wakeup,
560};
561
562static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
563{
564 int irq;
565
566 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
567 set_irq_chip(irq, &pxa_ext_wakeup_chip);
568 set_irq_handler(irq, handle_edge_irq);
569 set_irq_flags(irq, IRQF_VALID);
570 }
571
572 pxa_ext_wakeup_chip.set_wake = fn;
573}
574
eric miao2c8086a2007-09-11 19:13:17 -0700575void __init pxa3xx_init_irq(void)
576{
577 /* enable CP6 access */
578 u32 value;
579 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
580 value |= (1 << 6);
581 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
582
eric miaob9e25ac2008-03-04 14:19:58 +0800583 pxa_init_irq(56, pxa3xx_set_wake);
Mike Rapoportbf293ae2009-11-11 11:36:59 +0200584 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800585 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
eric miao2c8086a2007-09-11 19:13:17 -0700586}
587
588/*
589 * device registration specific to PXA3xx.
590 */
591
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100592void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
593{
Eric Miao14758222008-11-28 15:24:12 +0800594 pxa_register_device(&pxa3xx_device_i2c_power, info);
Mike Rapoport9ba63c42008-08-17 06:23:05 +0100595}
596
eric miao2c8086a2007-09-11 19:13:17 -0700597static struct platform_device *devices[] __initdata = {
Robert Jarzmik94c35a62009-04-21 19:19:36 +0200598 &pxa27x_device_udc,
eric miao2c8086a2007-09-11 19:13:17 -0700599 &pxa_device_i2s,
Robert Jarzmik72493142008-11-13 23:50:56 +0100600 &sa1100_device_rtc,
eric miao2c8086a2007-09-11 19:13:17 -0700601 &pxa_device_rtc,
eric miaod8e0db12007-12-10 17:54:36 +0800602 &pxa27x_device_ssp1,
603 &pxa27x_device_ssp2,
604 &pxa27x_device_ssp3,
605 &pxa3xx_device_ssp4,
eric miao75540c12008-04-13 21:44:04 +0100606 &pxa27x_device_pwm0,
607 &pxa27x_device_pwm1,
eric miao2c8086a2007-09-11 19:13:17 -0700608};
609
eric miaoc01655042008-01-28 23:00:02 +0000610static struct sys_device pxa3xx_sysdev[] = {
611 {
eric miaoc01655042008-01-28 23:00:02 +0000612 .cls = &pxa_irq_sysclass,
eric miao16dfdbf2008-01-28 23:00:02 +0000613 }, {
eric miao4be35e22008-02-04 10:07:09 +0800614 .cls = &pxa3xx_mfp_sysclass,
615 }, {
eric miao16dfdbf2008-01-28 23:00:02 +0000616 .cls = &pxa_gpio_sysclass,
eric miaoc01655042008-01-28 23:00:02 +0000617 },
618};
619
eric miao2c8086a2007-09-11 19:13:17 -0700620static int __init pxa3xx_init(void)
621{
eric miaoc01655042008-01-28 23:00:02 +0000622 int i, ret = 0;
eric miao2c8086a2007-09-11 19:13:17 -0700623
624 if (cpu_is_pxa3xx()) {
Eric Miao04fef222008-07-29 14:26:00 +0800625
626 reset_status = ARSR;
627
Dmitry Krivoschekov86260f92008-02-08 15:02:03 +0100628 /*
629 * clear RDH bit every time after reset
630 *
631 * Note: the last 3 bits DxS are write-1-to-clear so carefully
632 * preserve them here in case they will be referenced later
633 */
634 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
635
Russell King0a0300d2010-01-12 12:28:00 +0000636 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
eric miao2c8086a2007-09-11 19:13:17 -0700637
Eric Miaofef1f992009-01-02 16:26:33 +0800638 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
eric miao2c8086a2007-09-11 19:13:17 -0700639 return ret;
640
Russell King7b5dea12008-01-07 22:18:30 +0000641 pxa3xx_init_pm();
642
eric miaoc01655042008-01-28 23:00:02 +0000643 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
644 ret = sysdev_register(&pxa3xx_sysdev[i]);
645 if (ret)
646 pr_err("failed to register sysdev[%d]\n", i);
647 }
648
649 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
eric miao2c8086a2007-09-11 19:13:17 -0700650 }
eric miaoc01655042008-01-28 23:00:02 +0000651
652 return ret;
eric miao2c8086a2007-09-11 19:13:17 -0700653}
654
Russell King1c104e02008-04-19 10:59:24 +0100655postcore_initcall(pxa3xx_init);