arch/arm64/boot/dts/qcom/msm-gdsc-skunk.dtsi

/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	/* GDSCs in Global CC */
	pcie_0_gdsc: qcom,gdsc@0x16b004 {
		compatible = "qcom,gdsc";
		regulator-name = "pcie_0_gdsc";
		reg = <0x16b004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	pcie_1_gdsc: qcom,gdsc@0x18d004 {
		compatible = "qcom,gdsc";
		regulator-name = "pcie_1_gdsc";
		reg = <0x18d004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	ufs_card_gdsc: qcom,gdsc@0x175004 {
		compatible = "qcom,gdsc";
		regulator-name = "ufs_card_gdsc";
		reg = <0x175004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	ufs_phy_gdsc: qcom,gdsc@0x177004 {
		compatible = "qcom,gdsc";
		regulator-name = "ufs_phy_gdsc";
		reg = <0x177004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	usb30_prim_gdsc: qcom,gdsc@0x10f004 {
		compatible = "qcom,gdsc";
		regulator-name = "usb30_prim_gdsc";
		reg = <0x10f004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	usb30_sec_gdsc: qcom,gdsc@0x110004 {
		compatible = "qcom,gdsc";
		regulator-name = "usb30_sec_gdsc";
		reg = <0x110004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@0x17d030 {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc";
		reg = <0x17d030 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@0x17d03c {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc";
		reg = <0x17d03c 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@0x17d034 {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc";
		reg = <0x17d034 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@0x17d038 {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc";
		reg = <0x17d038 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@0x17d040 {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
		reg = <0x17d040 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@0x17d048 {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
		reg = <0x17d048 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@0x17d044 {
		compatible = "qcom,gdsc";
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
		reg = <0x17d044 0x4>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	/* GDSCs in Camera CC */
	bps_gdsc: qcom,gdsc@0xad06004 {
		compatible = "qcom,gdsc";
		regulator-name = "bps_gdsc";
		reg = <0xad06004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	ife_0_gdsc: qcom,gdsc@0xad09004 {
		compatible = "qcom,gdsc";
		regulator-name = "ife_0_gdsc";
		reg = <0xad09004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	ife_1_gdsc: qcom,gdsc@0xad0a004 {
		compatible = "qcom,gdsc";
		regulator-name = "ife_1_gdsc";
		reg = <0xad0a004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	ipe_0_gdsc: qcom,gdsc@0xad07004 {
		compatible = "qcom,gdsc";
		regulator-name = "ipe_0_gdsc";
		reg = <0xad07004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	ipe_1_gdsc: qcom,gdsc@0xad08004 {
		compatible = "qcom,gdsc";
		regulator-name = "ipe_1_gdsc";
		reg = <0xad08004 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	titan_top_gdsc: qcom,gdsc@0xad0b134 {
		compatible = "qcom,gdsc";
		regulator-name = "titan_top_gdsc";
		reg = <0xad0b134 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	/* GDSCs in Display CC */
	mdss_core_gdsc: qcom,gdsc@0xaf03000 {
		compatible = "qcom,gdsc";
		regulator-name = "mdss_core_gdsc";
		reg = <0xaf03000 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	/* GDSCs in Graphics CC */
	gpu_cx_hw_ctrl: syscon@0x5091540 {
		compatible = "syscon";
		reg = <0x5091540 0x4>;
	};

	gpu_cx_gdsc: qcom,gdsc@0x509106c {
		compatible = "qcom,gdsc";
		regulator-name = "gpu_cx_gdsc";
		reg = <0x509106c 0x4>;
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
		status = "disabled";
	};

	gpu_gx_domain_addr: syscon@0x5091508 {
		compatible = "syscon";
		reg = <0x5091508 0x4>;
	};

	gpu_gx_sw_reset: syscon@0x5091008 {
		compatible = "syscon";
		reg = <0x5091008 0x4>;
	};

	gpu_gx_gdsc: qcom,gdsc@0x509100c {
		compatible = "qcom,gdsc";
		regulator-name = "gpu_gx_gdsc";
		reg = <0x509100c 0x4>;
		domain-addr = <&gpu_gx_domain_addr>;
		sw-reset = <&gpu_gx_sw_reset>;
		qcom,reset-aon-logic;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	/* GDSCs in Video CC */
	vcodec0_gdsc: qcom,gdsc@0xab00874 {
		compatible = "qcom,gdsc";
		regulator-name = "vcodec0_gdsc";
		reg = <0xab00874 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	vcodec1_gdsc: qcom,gdsc@0xab008b4 {
		compatible = "qcom,gdsc";
		regulator-name = "vcodec1_gdsc";
		reg = <0xab008b4 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};

	venus_gdsc: qcom,gdsc@0xab00814 {
		compatible = "qcom,gdsc";
		regulator-name = "venus_gdsc";
		reg = <0xab00814 0x4>;
		qcom,poll-cfg-gdscr;
		status = "disabled";
	};
};