R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
| 15 | / { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | compatible = "ti,dra7xx"; |
| 20 | interrupt-parent = <&gic>; |
| 21 | |
| 22 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 23 | i2c0 = &i2c1; |
| 24 | i2c1 = &i2c2; |
| 25 | i2c2 = &i2c3; |
| 26 | i2c3 = &i2c4; |
| 27 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 28 | serial0 = &uart1; |
| 29 | serial1 = &uart2; |
| 30 | serial2 = &uart3; |
| 31 | serial3 = &uart4; |
| 32 | serial4 = &uart5; |
| 33 | serial5 = &uart6; |
| 34 | }; |
| 35 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 36 | timer { |
| 37 | compatible = "arm,armv7-timer"; |
| 38 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 39 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 40 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 41 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 42 | }; |
| 43 | |
| 44 | gic: interrupt-controller@48211000 { |
| 45 | compatible = "arm,cortex-a15-gic"; |
| 46 | interrupt-controller; |
| 47 | #interrupt-cells = <3>; |
| 48 | reg = <0x48211000 0x1000>, |
| 49 | <0x48212000 0x1000>, |
| 50 | <0x48214000 0x2000>, |
| 51 | <0x48216000 0x2000>; |
| 52 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 53 | }; |
| 54 | |
| 55 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 56 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 57 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 58 | */ |
| 59 | soc { |
| 60 | compatible = "ti,omap-infra"; |
| 61 | mpu { |
| 62 | compatible = "ti,omap5-mpu"; |
| 63 | ti,hwmods = "mpu"; |
| 64 | }; |
| 65 | }; |
| 66 | |
| 67 | /* |
| 68 | * XXX: Use a flat representation of the SOC interconnect. |
| 69 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 70 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 71 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 72 | * hierarchy. |
| 73 | */ |
| 74 | ocp { |
| 75 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
| 76 | #address-cells = <1>; |
| 77 | #size-cells = <1>; |
| 78 | ranges; |
| 79 | ti,hwmods = "l3_main_1", "l3_main_2"; |
| 80 | reg = <0x44000000 0x2000>, |
| 81 | <0x44800000 0x3000>; |
| 82 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 84 | |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 85 | prm: prm@4ae06000 { |
| 86 | compatible = "ti,dra7-prm"; |
| 87 | reg = <0x4ae06000 0x3000>; |
| 88 | |
| 89 | prm_clocks: clocks { |
| 90 | #address-cells = <1>; |
| 91 | #size-cells = <0>; |
| 92 | }; |
| 93 | |
| 94 | prm_clockdomains: clockdomains { |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | cm_core_aon: cm_core_aon@4a005000 { |
| 99 | compatible = "ti,dra7-cm-core-aon"; |
| 100 | reg = <0x4a005000 0x2000>; |
| 101 | |
| 102 | cm_core_aon_clocks: clocks { |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <0>; |
| 105 | }; |
| 106 | |
| 107 | cm_core_aon_clockdomains: clockdomains { |
| 108 | }; |
| 109 | }; |
| 110 | |
| 111 | cm_core: cm_core@4a008000 { |
| 112 | compatible = "ti,dra7-cm-core"; |
| 113 | reg = <0x4a008000 0x3000>; |
| 114 | |
| 115 | cm_core_clocks: clocks { |
| 116 | #address-cells = <1>; |
| 117 | #size-cells = <0>; |
| 118 | }; |
| 119 | |
| 120 | cm_core_clockdomains: clockdomains { |
| 121 | }; |
| 122 | }; |
| 123 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 124 | counter32k: counter@4ae04000 { |
| 125 | compatible = "ti,omap-counter32k"; |
| 126 | reg = <0x4ae04000 0x40>; |
| 127 | ti,hwmods = "counter_32k"; |
| 128 | }; |
| 129 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 130 | dra7_ctrl_general: tisyscon@4a002e00 { |
| 131 | compatible = "syscon"; |
| 132 | reg = <0x4a002e00 0x7c>; |
| 133 | }; |
| 134 | |
| 135 | pbias_regulator: pbias_regulator { |
| 136 | compatible = "ti,pbias-omap"; |
| 137 | reg = <0 0x4>; |
| 138 | syscon = <&dra7_ctrl_general>; |
| 139 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 140 | regulator-name = "pbias_mmc_omap5"; |
| 141 | regulator-min-microvolt = <1800000>; |
| 142 | regulator-max-microvolt = <3000000>; |
| 143 | }; |
| 144 | }; |
| 145 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 146 | dra7_pmx_core: pinmux@4a003400 { |
| 147 | compatible = "pinctrl-single"; |
| 148 | reg = <0x4a003400 0x0464>; |
| 149 | #address-cells = <1>; |
| 150 | #size-cells = <0>; |
| 151 | pinctrl-single,register-width = <32>; |
| 152 | pinctrl-single,function-mask = <0x3fffffff>; |
| 153 | }; |
| 154 | |
| 155 | sdma: dma-controller@4a056000 { |
| 156 | compatible = "ti,omap4430-sdma"; |
| 157 | reg = <0x4a056000 0x1000>; |
| 158 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 159 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 160 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 161 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 162 | #dma-cells = <1>; |
| 163 | #dma-channels = <32>; |
| 164 | #dma-requests = <127>; |
| 165 | }; |
| 166 | |
| 167 | gpio1: gpio@4ae10000 { |
| 168 | compatible = "ti,omap4-gpio"; |
| 169 | reg = <0x4ae10000 0x200>; |
| 170 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 171 | ti,hwmods = "gpio1"; |
| 172 | gpio-controller; |
| 173 | #gpio-cells = <2>; |
| 174 | interrupt-controller; |
| 175 | #interrupt-cells = <1>; |
| 176 | }; |
| 177 | |
| 178 | gpio2: gpio@48055000 { |
| 179 | compatible = "ti,omap4-gpio"; |
| 180 | reg = <0x48055000 0x200>; |
| 181 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 182 | ti,hwmods = "gpio2"; |
| 183 | gpio-controller; |
| 184 | #gpio-cells = <2>; |
| 185 | interrupt-controller; |
| 186 | #interrupt-cells = <1>; |
| 187 | }; |
| 188 | |
| 189 | gpio3: gpio@48057000 { |
| 190 | compatible = "ti,omap4-gpio"; |
| 191 | reg = <0x48057000 0x200>; |
| 192 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 193 | ti,hwmods = "gpio3"; |
| 194 | gpio-controller; |
| 195 | #gpio-cells = <2>; |
| 196 | interrupt-controller; |
| 197 | #interrupt-cells = <1>; |
| 198 | }; |
| 199 | |
| 200 | gpio4: gpio@48059000 { |
| 201 | compatible = "ti,omap4-gpio"; |
| 202 | reg = <0x48059000 0x200>; |
| 203 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 204 | ti,hwmods = "gpio4"; |
| 205 | gpio-controller; |
| 206 | #gpio-cells = <2>; |
| 207 | interrupt-controller; |
| 208 | #interrupt-cells = <1>; |
| 209 | }; |
| 210 | |
| 211 | gpio5: gpio@4805b000 { |
| 212 | compatible = "ti,omap4-gpio"; |
| 213 | reg = <0x4805b000 0x200>; |
| 214 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | ti,hwmods = "gpio5"; |
| 216 | gpio-controller; |
| 217 | #gpio-cells = <2>; |
| 218 | interrupt-controller; |
| 219 | #interrupt-cells = <1>; |
| 220 | }; |
| 221 | |
| 222 | gpio6: gpio@4805d000 { |
| 223 | compatible = "ti,omap4-gpio"; |
| 224 | reg = <0x4805d000 0x200>; |
| 225 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | ti,hwmods = "gpio6"; |
| 227 | gpio-controller; |
| 228 | #gpio-cells = <2>; |
| 229 | interrupt-controller; |
| 230 | #interrupt-cells = <1>; |
| 231 | }; |
| 232 | |
| 233 | gpio7: gpio@48051000 { |
| 234 | compatible = "ti,omap4-gpio"; |
| 235 | reg = <0x48051000 0x200>; |
| 236 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 237 | ti,hwmods = "gpio7"; |
| 238 | gpio-controller; |
| 239 | #gpio-cells = <2>; |
| 240 | interrupt-controller; |
| 241 | #interrupt-cells = <1>; |
| 242 | }; |
| 243 | |
| 244 | gpio8: gpio@48053000 { |
| 245 | compatible = "ti,omap4-gpio"; |
| 246 | reg = <0x48053000 0x200>; |
| 247 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 248 | ti,hwmods = "gpio8"; |
| 249 | gpio-controller; |
| 250 | #gpio-cells = <2>; |
| 251 | interrupt-controller; |
| 252 | #interrupt-cells = <1>; |
| 253 | }; |
| 254 | |
| 255 | uart1: serial@4806a000 { |
| 256 | compatible = "ti,omap4-uart"; |
| 257 | reg = <0x4806a000 0x100>; |
| 258 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 259 | ti,hwmods = "uart1"; |
| 260 | clock-frequency = <48000000>; |
| 261 | status = "disabled"; |
| 262 | }; |
| 263 | |
| 264 | uart2: serial@4806c000 { |
| 265 | compatible = "ti,omap4-uart"; |
| 266 | reg = <0x4806c000 0x100>; |
| 267 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 268 | ti,hwmods = "uart2"; |
| 269 | clock-frequency = <48000000>; |
| 270 | status = "disabled"; |
| 271 | }; |
| 272 | |
| 273 | uart3: serial@48020000 { |
| 274 | compatible = "ti,omap4-uart"; |
| 275 | reg = <0x48020000 0x100>; |
| 276 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 277 | ti,hwmods = "uart3"; |
| 278 | clock-frequency = <48000000>; |
| 279 | status = "disabled"; |
| 280 | }; |
| 281 | |
| 282 | uart4: serial@4806e000 { |
| 283 | compatible = "ti,omap4-uart"; |
| 284 | reg = <0x4806e000 0x100>; |
| 285 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 286 | ti,hwmods = "uart4"; |
| 287 | clock-frequency = <48000000>; |
| 288 | status = "disabled"; |
| 289 | }; |
| 290 | |
| 291 | uart5: serial@48066000 { |
| 292 | compatible = "ti,omap4-uart"; |
| 293 | reg = <0x48066000 0x100>; |
| 294 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 295 | ti,hwmods = "uart5"; |
| 296 | clock-frequency = <48000000>; |
| 297 | status = "disabled"; |
| 298 | }; |
| 299 | |
| 300 | uart6: serial@48068000 { |
| 301 | compatible = "ti,omap4-uart"; |
| 302 | reg = <0x48068000 0x100>; |
| 303 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 304 | ti,hwmods = "uart6"; |
| 305 | clock-frequency = <48000000>; |
| 306 | status = "disabled"; |
| 307 | }; |
| 308 | |
| 309 | uart7: serial@48420000 { |
| 310 | compatible = "ti,omap4-uart"; |
| 311 | reg = <0x48420000 0x100>; |
| 312 | ti,hwmods = "uart7"; |
| 313 | clock-frequency = <48000000>; |
| 314 | status = "disabled"; |
| 315 | }; |
| 316 | |
| 317 | uart8: serial@48422000 { |
| 318 | compatible = "ti,omap4-uart"; |
| 319 | reg = <0x48422000 0x100>; |
| 320 | ti,hwmods = "uart8"; |
| 321 | clock-frequency = <48000000>; |
| 322 | status = "disabled"; |
| 323 | }; |
| 324 | |
| 325 | uart9: serial@48424000 { |
| 326 | compatible = "ti,omap4-uart"; |
| 327 | reg = <0x48424000 0x100>; |
| 328 | ti,hwmods = "uart9"; |
| 329 | clock-frequency = <48000000>; |
| 330 | status = "disabled"; |
| 331 | }; |
| 332 | |
| 333 | uart10: serial@4ae2b000 { |
| 334 | compatible = "ti,omap4-uart"; |
| 335 | reg = <0x4ae2b000 0x100>; |
| 336 | ti,hwmods = "uart10"; |
| 337 | clock-frequency = <48000000>; |
| 338 | status = "disabled"; |
| 339 | }; |
| 340 | |
| 341 | timer1: timer@4ae18000 { |
| 342 | compatible = "ti,omap5430-timer"; |
| 343 | reg = <0x4ae18000 0x80>; |
| 344 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 345 | ti,hwmods = "timer1"; |
| 346 | ti,timer-alwon; |
| 347 | }; |
| 348 | |
| 349 | timer2: timer@48032000 { |
| 350 | compatible = "ti,omap5430-timer"; |
| 351 | reg = <0x48032000 0x80>; |
| 352 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 353 | ti,hwmods = "timer2"; |
| 354 | }; |
| 355 | |
| 356 | timer3: timer@48034000 { |
| 357 | compatible = "ti,omap5430-timer"; |
| 358 | reg = <0x48034000 0x80>; |
| 359 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 360 | ti,hwmods = "timer3"; |
| 361 | }; |
| 362 | |
| 363 | timer4: timer@48036000 { |
| 364 | compatible = "ti,omap5430-timer"; |
| 365 | reg = <0x48036000 0x80>; |
| 366 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 367 | ti,hwmods = "timer4"; |
| 368 | }; |
| 369 | |
| 370 | timer5: timer@48820000 { |
| 371 | compatible = "ti,omap5430-timer"; |
| 372 | reg = <0x48820000 0x80>; |
| 373 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 374 | ti,hwmods = "timer5"; |
| 375 | ti,timer-dsp; |
| 376 | }; |
| 377 | |
| 378 | timer6: timer@48822000 { |
| 379 | compatible = "ti,omap5430-timer"; |
| 380 | reg = <0x48822000 0x80>; |
| 381 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 382 | ti,hwmods = "timer6"; |
| 383 | ti,timer-dsp; |
| 384 | ti,timer-pwm; |
| 385 | }; |
| 386 | |
| 387 | timer7: timer@48824000 { |
| 388 | compatible = "ti,omap5430-timer"; |
| 389 | reg = <0x48824000 0x80>; |
| 390 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 391 | ti,hwmods = "timer7"; |
| 392 | ti,timer-dsp; |
| 393 | }; |
| 394 | |
| 395 | timer8: timer@48826000 { |
| 396 | compatible = "ti,omap5430-timer"; |
| 397 | reg = <0x48826000 0x80>; |
| 398 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| 399 | ti,hwmods = "timer8"; |
| 400 | ti,timer-dsp; |
| 401 | ti,timer-pwm; |
| 402 | }; |
| 403 | |
| 404 | timer9: timer@4803e000 { |
| 405 | compatible = "ti,omap5430-timer"; |
| 406 | reg = <0x4803e000 0x80>; |
| 407 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 408 | ti,hwmods = "timer9"; |
| 409 | }; |
| 410 | |
| 411 | timer10: timer@48086000 { |
| 412 | compatible = "ti,omap5430-timer"; |
| 413 | reg = <0x48086000 0x80>; |
| 414 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 415 | ti,hwmods = "timer10"; |
| 416 | }; |
| 417 | |
| 418 | timer11: timer@48088000 { |
| 419 | compatible = "ti,omap5430-timer"; |
| 420 | reg = <0x48088000 0x80>; |
| 421 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 422 | ti,hwmods = "timer11"; |
| 423 | ti,timer-pwm; |
| 424 | }; |
| 425 | |
| 426 | timer13: timer@48828000 { |
| 427 | compatible = "ti,omap5430-timer"; |
| 428 | reg = <0x48828000 0x80>; |
| 429 | ti,hwmods = "timer13"; |
| 430 | status = "disabled"; |
| 431 | }; |
| 432 | |
| 433 | timer14: timer@4882a000 { |
| 434 | compatible = "ti,omap5430-timer"; |
| 435 | reg = <0x4882a000 0x80>; |
| 436 | ti,hwmods = "timer14"; |
| 437 | status = "disabled"; |
| 438 | }; |
| 439 | |
| 440 | timer15: timer@4882c000 { |
| 441 | compatible = "ti,omap5430-timer"; |
| 442 | reg = <0x4882c000 0x80>; |
| 443 | ti,hwmods = "timer15"; |
| 444 | status = "disabled"; |
| 445 | }; |
| 446 | |
| 447 | timer16: timer@4882e000 { |
| 448 | compatible = "ti,omap5430-timer"; |
| 449 | reg = <0x4882e000 0x80>; |
| 450 | ti,hwmods = "timer16"; |
| 451 | status = "disabled"; |
| 452 | }; |
| 453 | |
| 454 | wdt2: wdt@4ae14000 { |
| 455 | compatible = "ti,omap4-wdt"; |
| 456 | reg = <0x4ae14000 0x80>; |
| 457 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 458 | ti,hwmods = "wd_timer2"; |
| 459 | }; |
| 460 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 461 | hwspinlock: spinlock@4a0f6000 { |
| 462 | compatible = "ti,omap4-hwspinlock"; |
| 463 | reg = <0x4a0f6000 0x1000>; |
| 464 | ti,hwmods = "spinlock"; |
| 465 | #hwlock-cells = <1>; |
| 466 | }; |
| 467 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 468 | dmm@4e000000 { |
| 469 | compatible = "ti,omap5-dmm"; |
| 470 | reg = <0x4e000000 0x800>; |
| 471 | interrupts = <0 113 0x4>; |
| 472 | ti,hwmods = "dmm"; |
| 473 | }; |
| 474 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 475 | i2c1: i2c@48070000 { |
| 476 | compatible = "ti,omap4-i2c"; |
| 477 | reg = <0x48070000 0x100>; |
| 478 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 479 | #address-cells = <1>; |
| 480 | #size-cells = <0>; |
| 481 | ti,hwmods = "i2c1"; |
| 482 | status = "disabled"; |
| 483 | }; |
| 484 | |
| 485 | i2c2: i2c@48072000 { |
| 486 | compatible = "ti,omap4-i2c"; |
| 487 | reg = <0x48072000 0x100>; |
| 488 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 489 | #address-cells = <1>; |
| 490 | #size-cells = <0>; |
| 491 | ti,hwmods = "i2c2"; |
| 492 | status = "disabled"; |
| 493 | }; |
| 494 | |
| 495 | i2c3: i2c@48060000 { |
| 496 | compatible = "ti,omap4-i2c"; |
| 497 | reg = <0x48060000 0x100>; |
| 498 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 499 | #address-cells = <1>; |
| 500 | #size-cells = <0>; |
| 501 | ti,hwmods = "i2c3"; |
| 502 | status = "disabled"; |
| 503 | }; |
| 504 | |
| 505 | i2c4: i2c@4807a000 { |
| 506 | compatible = "ti,omap4-i2c"; |
| 507 | reg = <0x4807a000 0x100>; |
| 508 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 509 | #address-cells = <1>; |
| 510 | #size-cells = <0>; |
| 511 | ti,hwmods = "i2c4"; |
| 512 | status = "disabled"; |
| 513 | }; |
| 514 | |
| 515 | i2c5: i2c@4807c000 { |
| 516 | compatible = "ti,omap4-i2c"; |
| 517 | reg = <0x4807c000 0x100>; |
| 518 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 519 | #address-cells = <1>; |
| 520 | #size-cells = <0>; |
| 521 | ti,hwmods = "i2c5"; |
| 522 | status = "disabled"; |
| 523 | }; |
| 524 | |
| 525 | mmc1: mmc@4809c000 { |
| 526 | compatible = "ti,omap4-hsmmc"; |
| 527 | reg = <0x4809c000 0x400>; |
| 528 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 529 | ti,hwmods = "mmc1"; |
| 530 | ti,dual-volt; |
| 531 | ti,needs-special-reset; |
| 532 | dmas = <&sdma 61>, <&sdma 62>; |
| 533 | dma-names = "tx", "rx"; |
| 534 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 535 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 536 | }; |
| 537 | |
| 538 | mmc2: mmc@480b4000 { |
| 539 | compatible = "ti,omap4-hsmmc"; |
| 540 | reg = <0x480b4000 0x400>; |
| 541 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 542 | ti,hwmods = "mmc2"; |
| 543 | ti,needs-special-reset; |
| 544 | dmas = <&sdma 47>, <&sdma 48>; |
| 545 | dma-names = "tx", "rx"; |
| 546 | status = "disabled"; |
| 547 | }; |
| 548 | |
| 549 | mmc3: mmc@480ad000 { |
| 550 | compatible = "ti,omap4-hsmmc"; |
| 551 | reg = <0x480ad000 0x400>; |
| 552 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 553 | ti,hwmods = "mmc3"; |
| 554 | ti,needs-special-reset; |
| 555 | dmas = <&sdma 77>, <&sdma 78>; |
| 556 | dma-names = "tx", "rx"; |
| 557 | status = "disabled"; |
| 558 | }; |
| 559 | |
| 560 | mmc4: mmc@480d1000 { |
| 561 | compatible = "ti,omap4-hsmmc"; |
| 562 | reg = <0x480d1000 0x400>; |
| 563 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 564 | ti,hwmods = "mmc4"; |
| 565 | ti,needs-special-reset; |
| 566 | dmas = <&sdma 57>, <&sdma 58>; |
| 567 | dma-names = "tx", "rx"; |
| 568 | status = "disabled"; |
| 569 | }; |
| 570 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 571 | abb_mpu: regulator-abb-mpu { |
| 572 | compatible = "ti,abb-v3"; |
| 573 | regulator-name = "abb_mpu"; |
| 574 | #address-cells = <0>; |
| 575 | #size-cells = <0>; |
| 576 | clocks = <&sys_clkin1>; |
| 577 | ti,settling-time = <50>; |
| 578 | ti,clock-cycles = <16>; |
| 579 | |
| 580 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| 581 | <0x4ae06014 0x4>, <0x4a003b20 0x8>, |
| 582 | <0x4ae0c158 0x4>; |
| 583 | reg-names = "setup-address", "control-address", |
| 584 | "int-address", "efuse-address", |
| 585 | "ldo-address"; |
| 586 | ti,tranxdone-status-mask = <0x80>; |
| 587 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 588 | ti,ldovbb-override-mask = <0x400>; |
| 589 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 590 | ti,ldovbb-vset-mask = <0x1F>; |
| 591 | |
| 592 | /* |
| 593 | * NOTE: only FBB mode used but actual vset will |
| 594 | * determine final biasing |
| 595 | */ |
| 596 | ti,abb_info = < |
| 597 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 598 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 599 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 600 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 601 | >; |
| 602 | }; |
| 603 | |
| 604 | abb_ivahd: regulator-abb-ivahd { |
| 605 | compatible = "ti,abb-v3"; |
| 606 | regulator-name = "abb_ivahd"; |
| 607 | #address-cells = <0>; |
| 608 | #size-cells = <0>; |
| 609 | clocks = <&sys_clkin1>; |
| 610 | ti,settling-time = <50>; |
| 611 | ti,clock-cycles = <16>; |
| 612 | |
| 613 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| 614 | <0x4ae06010 0x4>, <0x4a0025cc 0x8>, |
| 615 | <0x4a002470 0x4>; |
| 616 | reg-names = "setup-address", "control-address", |
| 617 | "int-address", "efuse-address", |
| 618 | "ldo-address"; |
| 619 | ti,tranxdone-status-mask = <0x40000000>; |
| 620 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 621 | ti,ldovbb-override-mask = <0x400>; |
| 622 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 623 | ti,ldovbb-vset-mask = <0x1F>; |
| 624 | |
| 625 | /* |
| 626 | * NOTE: only FBB mode used but actual vset will |
| 627 | * determine final biasing |
| 628 | */ |
| 629 | ti,abb_info = < |
| 630 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 631 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 632 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 633 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 634 | >; |
| 635 | }; |
| 636 | |
| 637 | abb_dspeve: regulator-abb-dspeve { |
| 638 | compatible = "ti,abb-v3"; |
| 639 | regulator-name = "abb_dspeve"; |
| 640 | #address-cells = <0>; |
| 641 | #size-cells = <0>; |
| 642 | clocks = <&sys_clkin1>; |
| 643 | ti,settling-time = <50>; |
| 644 | ti,clock-cycles = <16>; |
| 645 | |
| 646 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| 647 | <0x4ae06010 0x4>, <0x4a0025e0 0x8>, |
| 648 | <0x4a00246c 0x4>; |
| 649 | reg-names = "setup-address", "control-address", |
| 650 | "int-address", "efuse-address", |
| 651 | "ldo-address"; |
| 652 | ti,tranxdone-status-mask = <0x20000000>; |
| 653 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 654 | ti,ldovbb-override-mask = <0x400>; |
| 655 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 656 | ti,ldovbb-vset-mask = <0x1F>; |
| 657 | |
| 658 | /* |
| 659 | * NOTE: only FBB mode used but actual vset will |
| 660 | * determine final biasing |
| 661 | */ |
| 662 | ti,abb_info = < |
| 663 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 664 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 665 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 666 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 667 | >; |
| 668 | }; |
| 669 | |
| 670 | abb_gpu: regulator-abb-gpu { |
| 671 | compatible = "ti,abb-v3"; |
| 672 | regulator-name = "abb_gpu"; |
| 673 | #address-cells = <0>; |
| 674 | #size-cells = <0>; |
| 675 | clocks = <&sys_clkin1>; |
| 676 | ti,settling-time = <50>; |
| 677 | ti,clock-cycles = <16>; |
| 678 | |
| 679 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| 680 | <0x4ae06010 0x4>, <0x4a003b08 0x8>, |
| 681 | <0x4ae0c154 0x4>; |
| 682 | reg-names = "setup-address", "control-address", |
| 683 | "int-address", "efuse-address", |
| 684 | "ldo-address"; |
| 685 | ti,tranxdone-status-mask = <0x10000000>; |
| 686 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 687 | ti,ldovbb-override-mask = <0x400>; |
| 688 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 689 | ti,ldovbb-vset-mask = <0x1F>; |
| 690 | |
| 691 | /* |
| 692 | * NOTE: only FBB mode used but actual vset will |
| 693 | * determine final biasing |
| 694 | */ |
| 695 | ti,abb_info = < |
| 696 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 697 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 698 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 699 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 700 | >; |
| 701 | }; |
| 702 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 703 | mcspi1: spi@48098000 { |
| 704 | compatible = "ti,omap4-mcspi"; |
| 705 | reg = <0x48098000 0x200>; |
| 706 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 707 | #address-cells = <1>; |
| 708 | #size-cells = <0>; |
| 709 | ti,hwmods = "mcspi1"; |
| 710 | ti,spi-num-cs = <4>; |
| 711 | dmas = <&sdma 35>, |
| 712 | <&sdma 36>, |
| 713 | <&sdma 37>, |
| 714 | <&sdma 38>, |
| 715 | <&sdma 39>, |
| 716 | <&sdma 40>, |
| 717 | <&sdma 41>, |
| 718 | <&sdma 42>; |
| 719 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 720 | "tx2", "rx2", "tx3", "rx3"; |
| 721 | status = "disabled"; |
| 722 | }; |
| 723 | |
| 724 | mcspi2: spi@4809a000 { |
| 725 | compatible = "ti,omap4-mcspi"; |
| 726 | reg = <0x4809a000 0x200>; |
| 727 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| 728 | #address-cells = <1>; |
| 729 | #size-cells = <0>; |
| 730 | ti,hwmods = "mcspi2"; |
| 731 | ti,spi-num-cs = <2>; |
| 732 | dmas = <&sdma 43>, |
| 733 | <&sdma 44>, |
| 734 | <&sdma 45>, |
| 735 | <&sdma 46>; |
| 736 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 737 | status = "disabled"; |
| 738 | }; |
| 739 | |
| 740 | mcspi3: spi@480b8000 { |
| 741 | compatible = "ti,omap4-mcspi"; |
| 742 | reg = <0x480b8000 0x200>; |
| 743 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 744 | #address-cells = <1>; |
| 745 | #size-cells = <0>; |
| 746 | ti,hwmods = "mcspi3"; |
| 747 | ti,spi-num-cs = <2>; |
| 748 | dmas = <&sdma 15>, <&sdma 16>; |
| 749 | dma-names = "tx0", "rx0"; |
| 750 | status = "disabled"; |
| 751 | }; |
| 752 | |
| 753 | mcspi4: spi@480ba000 { |
| 754 | compatible = "ti,omap4-mcspi"; |
| 755 | reg = <0x480ba000 0x200>; |
| 756 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 757 | #address-cells = <1>; |
| 758 | #size-cells = <0>; |
| 759 | ti,hwmods = "mcspi4"; |
| 760 | ti,spi-num-cs = <1>; |
| 761 | dmas = <&sdma 70>, <&sdma 71>; |
| 762 | dma-names = "tx0", "rx0"; |
| 763 | status = "disabled"; |
| 764 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 765 | |
| 766 | qspi: qspi@4b300000 { |
| 767 | compatible = "ti,dra7xxx-qspi"; |
| 768 | reg = <0x4b300000 0x100>; |
| 769 | reg-names = "qspi_base"; |
| 770 | #address-cells = <1>; |
| 771 | #size-cells = <0>; |
| 772 | ti,hwmods = "qspi"; |
| 773 | clocks = <&qspi_gfclk_div>; |
| 774 | clock-names = "fck"; |
| 775 | num-cs = <4>; |
| 776 | interrupts = <0 343 0x4>; |
| 777 | status = "disabled"; |
| 778 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 779 | |
| 780 | omap_control_sata: control-phy@4a002374 { |
| 781 | compatible = "ti,control-phy-pipe3"; |
| 782 | reg = <0x4a002374 0x4>; |
| 783 | reg-names = "power"; |
| 784 | clocks = <&sys_clkin1>; |
| 785 | clock-names = "sysclk"; |
| 786 | }; |
| 787 | |
| 788 | /* OCP2SCP3 */ |
| 789 | ocp2scp@4a090000 { |
| 790 | compatible = "ti,omap-ocp2scp"; |
| 791 | #address-cells = <1>; |
| 792 | #size-cells = <1>; |
| 793 | ranges; |
| 794 | reg = <0x4a090000 0x20>; |
| 795 | ti,hwmods = "ocp2scp3"; |
| 796 | sata_phy: phy@4A096000 { |
| 797 | compatible = "ti,phy-pipe3-sata"; |
| 798 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 799 | <0x4A096400 0x64>, /* phy_tx */ |
| 800 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 801 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 802 | ctrl-module = <&omap_control_sata>; |
| 803 | clocks = <&sys_clkin1>; |
| 804 | clock-names = "sysclk"; |
| 805 | #phy-cells = <0>; |
| 806 | }; |
| 807 | }; |
| 808 | |
| 809 | sata: sata@4a141100 { |
| 810 | compatible = "snps,dwc-ahci"; |
| 811 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| 812 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| 813 | phys = <&sata_phy>; |
| 814 | phy-names = "sata-phy"; |
| 815 | clocks = <&sata_ref_clk>; |
| 816 | ti,hwmods = "sata"; |
| 817 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 818 | |
| 819 | omap_control_usb2phy1: control-phy@4a002300 { |
| 820 | compatible = "ti,control-phy-usb2"; |
| 821 | reg = <0x4a002300 0x4>; |
| 822 | reg-names = "power"; |
| 823 | }; |
| 824 | |
| 825 | omap_control_usb3phy1: control-phy@4a002370 { |
| 826 | compatible = "ti,control-phy-pipe3"; |
| 827 | reg = <0x4a002370 0x4>; |
| 828 | reg-names = "power"; |
| 829 | }; |
| 830 | |
| 831 | omap_control_usb2phy2: control-phy@0x4a002e74 { |
| 832 | compatible = "ti,control-phy-usb2-dra7"; |
| 833 | reg = <0x4a002e74 0x4>; |
| 834 | reg-names = "power"; |
| 835 | }; |
| 836 | |
| 837 | /* OCP2SCP1 */ |
| 838 | ocp2scp@4a080000 { |
| 839 | compatible = "ti,omap-ocp2scp"; |
| 840 | #address-cells = <1>; |
| 841 | #size-cells = <1>; |
| 842 | ranges; |
| 843 | reg = <0x4a080000 0x20>; |
| 844 | ti,hwmods = "ocp2scp1"; |
| 845 | |
| 846 | usb2_phy1: phy@4a084000 { |
| 847 | compatible = "ti,omap-usb2"; |
| 848 | reg = <0x4a084000 0x400>; |
| 849 | ctrl-module = <&omap_control_usb2phy1>; |
| 850 | clocks = <&usb_phy1_always_on_clk32k>, |
| 851 | <&usb_otg_ss1_refclk960m>; |
| 852 | clock-names = "wkupclk", |
| 853 | "refclk"; |
| 854 | #phy-cells = <0>; |
| 855 | }; |
| 856 | |
| 857 | usb2_phy2: phy@4a085000 { |
| 858 | compatible = "ti,omap-usb2"; |
| 859 | reg = <0x4a085000 0x400>; |
| 860 | ctrl-module = <&omap_control_usb2phy2>; |
| 861 | clocks = <&usb_phy2_always_on_clk32k>, |
| 862 | <&usb_otg_ss2_refclk960m>; |
| 863 | clock-names = "wkupclk", |
| 864 | "refclk"; |
| 865 | #phy-cells = <0>; |
| 866 | }; |
| 867 | |
| 868 | usb3_phy1: phy@4a084400 { |
| 869 | compatible = "ti,omap-usb3"; |
| 870 | reg = <0x4a084400 0x80>, |
| 871 | <0x4a084800 0x64>, |
| 872 | <0x4a084c00 0x40>; |
| 873 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 874 | ctrl-module = <&omap_control_usb3phy1>; |
| 875 | clocks = <&usb_phy3_always_on_clk32k>, |
| 876 | <&sys_clkin1>, |
| 877 | <&usb_otg_ss1_refclk960m>; |
| 878 | clock-names = "wkupclk", |
| 879 | "sysclk", |
| 880 | "refclk"; |
| 881 | #phy-cells = <0>; |
| 882 | }; |
| 883 | }; |
| 884 | |
| 885 | omap_dwc3_1@48880000 { |
| 886 | compatible = "ti,dwc3"; |
| 887 | ti,hwmods = "usb_otg_ss1"; |
| 888 | reg = <0x48880000 0x10000>; |
| 889 | interrupts = <0 77 4>; |
| 890 | #address-cells = <1>; |
| 891 | #size-cells = <1>; |
| 892 | utmi-mode = <2>; |
| 893 | ranges; |
| 894 | usb1: usb@48890000 { |
| 895 | compatible = "snps,dwc3"; |
| 896 | reg = <0x48890000 0x17000>; |
| 897 | interrupts = <0 76 4>; |
| 898 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 899 | phy-names = "usb2-phy", "usb3-phy"; |
| 900 | tx-fifo-resize; |
| 901 | maximum-speed = "super-speed"; |
| 902 | dr_mode = "otg"; |
| 903 | }; |
| 904 | }; |
| 905 | |
| 906 | omap_dwc3_2@488c0000 { |
| 907 | compatible = "ti,dwc3"; |
| 908 | ti,hwmods = "usb_otg_ss2"; |
| 909 | reg = <0x488c0000 0x10000>; |
| 910 | interrupts = <0 92 4>; |
| 911 | #address-cells = <1>; |
| 912 | #size-cells = <1>; |
| 913 | utmi-mode = <2>; |
| 914 | ranges; |
| 915 | usb2: usb@488d0000 { |
| 916 | compatible = "snps,dwc3"; |
| 917 | reg = <0x488d0000 0x17000>; |
| 918 | interrupts = <0 78 4>; |
| 919 | phys = <&usb2_phy2>; |
| 920 | phy-names = "usb2-phy"; |
| 921 | tx-fifo-resize; |
| 922 | maximum-speed = "high-speed"; |
| 923 | dr_mode = "otg"; |
| 924 | }; |
| 925 | }; |
| 926 | |
| 927 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
| 928 | omap_dwc3_3@48900000 { |
| 929 | compatible = "ti,dwc3"; |
| 930 | ti,hwmods = "usb_otg_ss3"; |
| 931 | reg = <0x48900000 0x10000>; |
| 932 | /* interrupts = <0 TBD 4>; */ |
| 933 | #address-cells = <1>; |
| 934 | #size-cells = <1>; |
| 935 | utmi-mode = <2>; |
| 936 | ranges; |
| 937 | status = "disabled"; |
| 938 | usb3: usb@48910000 { |
| 939 | compatible = "snps,dwc3"; |
| 940 | reg = <0x48910000 0x17000>; |
| 941 | /* interrupts = <0 93 4>; */ |
| 942 | tx-fifo-resize; |
| 943 | maximum-speed = "high-speed"; |
| 944 | dr_mode = "otg"; |
| 945 | }; |
| 946 | }; |
| 947 | |
| 948 | omap_dwc3_4@48940000 { |
| 949 | compatible = "ti,dwc3"; |
| 950 | ti,hwmods = "usb_otg_ss4"; |
| 951 | reg = <0x48940000 0x10000>; |
| 952 | /* interrupts = <0 TBD 4>; */ |
| 953 | #address-cells = <1>; |
| 954 | #size-cells = <1>; |
| 955 | utmi-mode = <2>; |
| 956 | ranges; |
| 957 | status = "disabled"; |
| 958 | usb4: usb@48950000 { |
| 959 | compatible = "snps,dwc3"; |
| 960 | reg = <0x48950000 0x17000>; |
| 961 | /* interrupts = <0 TBD 4>; */ |
| 962 | tx-fifo-resize; |
| 963 | maximum-speed = "high-speed"; |
| 964 | dr_mode = "otg"; |
| 965 | }; |
| 966 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 967 | }; |
| 968 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 969 | |
| 970 | /include/ "dra7xx-clocks.dtsi" |