blob: d9b64a175990cfc4b9bc93c339ae3270b8dcb025 [file] [log] [blame]
Ben Hutchings94e61082008-03-05 16:52:39 +00001#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07002#include <linux/pci.h>
3#include <linux/module.h>
Al Virof6a57032006-10-18 01:47:25 -04004#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +09005#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006#include <linux/ioport.h>
Matthew Wilcox7ea7e982006-10-19 09:41:28 -06007#include <linux/wait.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07008
Adrian Bunk48b19142005-11-06 01:45:08 +01009#include "pci.h"
10
Linus Torvalds1da177e2005-04-16 15:20:36 -070011/*
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
14 */
15
Jan Kiszkaa2e27782011-11-04 09:46:00 +010016DEFINE_RAW_SPINLOCK(pci_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
18/*
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
21 * by pci_dev->ops.
22 */
23
24#define PCI_byte_BAD 0
25#define PCI_word_BAD (pos & 1)
26#define PCI_dword_BAD (pos & 3)
27
28#define PCI_OP_READ(size,type,len) \
29int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
31{ \
32 int res; \
33 unsigned long flags; \
34 u32 data = 0; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
Thomas Gleixner511dd982010-02-17 14:35:19 +000036 raw_spin_lock_irqsave(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
Thomas Gleixner511dd982010-02-17 14:35:19 +000039 raw_spin_unlock_irqrestore(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070040 return res; \
41}
42
43#define PCI_OP_WRITE(size,type,len) \
44int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
46{ \
47 int res; \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
Thomas Gleixner511dd982010-02-17 14:35:19 +000050 raw_spin_lock_irqsave(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 res = bus->ops->write(bus, devfn, pos, len, value); \
Thomas Gleixner511dd982010-02-17 14:35:19 +000052 raw_spin_unlock_irqrestore(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 return res; \
54}
55
56PCI_OP_READ(byte, u8, 1)
57PCI_OP_READ(word, u16, 2)
58PCI_OP_READ(dword, u32, 4)
59PCI_OP_WRITE(byte, u8, 1)
60PCI_OP_WRITE(word, u16, 2)
61PCI_OP_WRITE(dword, u32, 4)
62
63EXPORT_SYMBOL(pci_bus_read_config_byte);
64EXPORT_SYMBOL(pci_bus_read_config_word);
65EXPORT_SYMBOL(pci_bus_read_config_dword);
66EXPORT_SYMBOL(pci_bus_write_config_byte);
67EXPORT_SYMBOL(pci_bus_write_config_word);
68EXPORT_SYMBOL(pci_bus_write_config_dword);
Brian Kinge04b0ea2005-09-27 01:21:55 -070069
Rob Herring1f94a942015-01-09 20:34:39 -060070int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
71 int where, int size, u32 *val)
72{
73 void __iomem *addr;
74
75 addr = bus->ops->map_bus(bus, devfn, where);
76 if (!addr) {
77 *val = ~0;
78 return PCIBIOS_DEVICE_NOT_FOUND;
79 }
80
81 if (size == 1)
82 *val = readb(addr);
83 else if (size == 2)
84 *val = readw(addr);
85 else
86 *val = readl(addr);
87
88 return PCIBIOS_SUCCESSFUL;
89}
90EXPORT_SYMBOL_GPL(pci_generic_config_read);
91
92int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 val)
94{
95 void __iomem *addr;
96
97 addr = bus->ops->map_bus(bus, devfn, where);
98 if (!addr)
99 return PCIBIOS_DEVICE_NOT_FOUND;
100
101 if (size == 1)
102 writeb(val, addr);
103 else if (size == 2)
104 writew(val, addr);
105 else
106 writel(val, addr);
107
108 return PCIBIOS_SUCCESSFUL;
109}
110EXPORT_SYMBOL_GPL(pci_generic_config_write);
111
112int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
113 int where, int size, u32 *val)
114{
115 void __iomem *addr;
116
117 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
118 if (!addr) {
119 *val = ~0;
120 return PCIBIOS_DEVICE_NOT_FOUND;
121 }
122
123 *val = readl(addr);
124
125 if (size <= 2)
126 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
127
128 return PCIBIOS_SUCCESSFUL;
129}
130EXPORT_SYMBOL_GPL(pci_generic_config_read32);
131
132int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
133 int where, int size, u32 val)
134{
135 void __iomem *addr;
136 u32 mask, tmp;
137
138 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
139 if (!addr)
140 return PCIBIOS_DEVICE_NOT_FOUND;
141
142 if (size == 4) {
143 writel(val, addr);
144 return PCIBIOS_SUCCESSFUL;
145 } else {
146 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
147 }
148
149 tmp = readl(addr) & mask;
150 tmp |= val << ((where & 0x3) * 8);
151 writel(tmp, addr);
152
153 return PCIBIOS_SUCCESSFUL;
154}
155EXPORT_SYMBOL_GPL(pci_generic_config_write32);
156
Huang Yinga72b46c2009-04-24 10:45:17 +0800157/**
158 * pci_bus_set_ops - Set raw operations of pci bus
159 * @bus: pci bus struct
160 * @ops: new raw operations
161 *
162 * Return previous raw operations
163 */
164struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
165{
166 struct pci_ops *old_ops;
167 unsigned long flags;
168
Thomas Gleixner511dd982010-02-17 14:35:19 +0000169 raw_spin_lock_irqsave(&pci_lock, flags);
Huang Yinga72b46c2009-04-24 10:45:17 +0800170 old_ops = bus->ops;
171 bus->ops = ops;
Thomas Gleixner511dd982010-02-17 14:35:19 +0000172 raw_spin_unlock_irqrestore(&pci_lock, flags);
Huang Yinga72b46c2009-04-24 10:45:17 +0800173 return old_ops;
174}
175EXPORT_SYMBOL(pci_bus_set_ops);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800176
177/**
178 * pci_read_vpd - Read one entry from Vital Product Data
179 * @dev: pci device struct
180 * @pos: offset in vpd space
181 * @count: number of bytes to read
182 * @buf: pointer to where to store result
183 *
184 */
185ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
186{
187 if (!dev->vpd || !dev->vpd->ops)
188 return -ENODEV;
189 return dev->vpd->ops->read(dev, pos, count, buf);
190}
191EXPORT_SYMBOL(pci_read_vpd);
192
193/**
194 * pci_write_vpd - Write entry to Vital Product Data
195 * @dev: pci device struct
196 * @pos: offset in vpd space
Randy Dunlapcffb2fa2009-04-10 15:17:50 -0700197 * @count: number of bytes to write
198 * @buf: buffer containing write data
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800199 *
200 */
201ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
202{
203 if (!dev->vpd || !dev->vpd->ops)
204 return -ENODEV;
205 return dev->vpd->ops->write(dev, pos, count, buf);
206}
207EXPORT_SYMBOL(pci_write_vpd);
208
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600209/*
210 * The following routines are to prevent the user from accessing PCI config
211 * space when it's unsafe to do so. Some devices require this during BIST and
212 * we're required to prevent it during D-state transitions.
213 *
214 * We have a bit per device to indicate it's blocked and a global wait queue
215 * for callers to sleep on until devices are unblocked.
216 */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100217static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700218
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100219static noinline void pci_wait_cfg(struct pci_dev *dev)
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600220{
221 DECLARE_WAITQUEUE(wait, current);
222
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100223 __add_wait_queue(&pci_cfg_wait, &wait);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600224 do {
225 set_current_state(TASK_UNINTERRUPTIBLE);
Thomas Gleixner511dd982010-02-17 14:35:19 +0000226 raw_spin_unlock_irq(&pci_lock);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600227 schedule();
Thomas Gleixner511dd982010-02-17 14:35:19 +0000228 raw_spin_lock_irq(&pci_lock);
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100229 } while (dev->block_cfg_access);
230 __remove_wait_queue(&pci_cfg_wait, &wait);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700231}
232
Greg Thelen34e32072011-04-17 08:20:32 -0700233/* Returns 0 on success, negative values indicate error. */
Brian Kinge04b0ea2005-09-27 01:21:55 -0700234#define PCI_USER_READ_CONFIG(size,type) \
235int pci_user_read_config_##size \
236 (struct pci_dev *dev, int pos, type *val) \
237{ \
Gavin Shand97ffe22014-05-21 15:23:30 +1000238 int ret = PCIBIOS_SUCCESSFUL; \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700239 u32 data = -1; \
Greg Thelen34e32072011-04-17 08:20:32 -0700240 if (PCI_##size##_BAD) \
241 return -EINVAL; \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000242 raw_spin_lock_irq(&pci_lock); \
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100243 if (unlikely(dev->block_cfg_access)) \
244 pci_wait_cfg(dev); \
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600245 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700246 pos, sizeof(type), &data); \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000247 raw_spin_unlock_irq(&pci_lock); \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700248 *val = (type)data; \
Gavin Shand97ffe22014-05-21 15:23:30 +1000249 return pcibios_err_to_errno(ret); \
Alex Williamsonc63587d2012-06-11 05:27:19 +0000250} \
251EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700252
Greg Thelen34e32072011-04-17 08:20:32 -0700253/* Returns 0 on success, negative values indicate error. */
Brian Kinge04b0ea2005-09-27 01:21:55 -0700254#define PCI_USER_WRITE_CONFIG(size,type) \
255int pci_user_write_config_##size \
256 (struct pci_dev *dev, int pos, type val) \
257{ \
Gavin Shand97ffe22014-05-21 15:23:30 +1000258 int ret = PCIBIOS_SUCCESSFUL; \
Greg Thelen34e32072011-04-17 08:20:32 -0700259 if (PCI_##size##_BAD) \
260 return -EINVAL; \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000261 raw_spin_lock_irq(&pci_lock); \
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100262 if (unlikely(dev->block_cfg_access)) \
263 pci_wait_cfg(dev); \
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600264 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700265 pos, sizeof(type), val); \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000266 raw_spin_unlock_irq(&pci_lock); \
Gavin Shand97ffe22014-05-21 15:23:30 +1000267 return pcibios_err_to_errno(ret); \
Alex Williamsonc63587d2012-06-11 05:27:19 +0000268} \
269EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700270
271PCI_USER_READ_CONFIG(byte, u8)
272PCI_USER_READ_CONFIG(word, u16)
273PCI_USER_READ_CONFIG(dword, u32)
274PCI_USER_WRITE_CONFIG(byte, u8)
275PCI_USER_WRITE_CONFIG(word, u16)
276PCI_USER_WRITE_CONFIG(dword, u32)
277
Ben Hutchings94e61082008-03-05 16:52:39 +0000278/* VPD access through PCI 2.2+ VPD capability */
279
280#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
281
282struct pci_vpd_pci22 {
283 struct pci_vpd base;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800284 struct mutex lock;
285 u16 flag;
Ben Hutchings94e61082008-03-05 16:52:39 +0000286 bool busy;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800287 u8 cap;
Ben Hutchings94e61082008-03-05 16:52:39 +0000288};
289
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800290/*
291 * Wait for last operation to complete.
292 * This code has to spin since there is no other notification from the PCI
293 * hardware. Since the VPD is often implemented by serial attachment to an
294 * EEPROM, it may take many milliseconds to complete.
Greg Thelen34e32072011-04-17 08:20:32 -0700295 *
296 * Returns 0 on success, negative values indicate error.
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800297 */
Ben Hutchings94e61082008-03-05 16:52:39 +0000298static int pci_vpd_pci22_wait(struct pci_dev *dev)
299{
300 struct pci_vpd_pci22 *vpd =
301 container_of(dev->vpd, struct pci_vpd_pci22, base);
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800302 unsigned long timeout = jiffies + HZ/20 + 2;
303 u16 status;
Ben Hutchings94e61082008-03-05 16:52:39 +0000304 int ret;
305
306 if (!vpd->busy)
307 return 0;
308
Ben Hutchings94e61082008-03-05 16:52:39 +0000309 for (;;) {
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800310 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
Ben Hutchings94e61082008-03-05 16:52:39 +0000311 &status);
Greg Thelen34e32072011-04-17 08:20:32 -0700312 if (ret < 0)
Ben Hutchings94e61082008-03-05 16:52:39 +0000313 return ret;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800314
315 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
Ben Hutchings94e61082008-03-05 16:52:39 +0000316 vpd->busy = false;
317 return 0;
318 }
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800319
Prarit Bhargava50307182010-05-17 14:25:14 -0400320 if (time_after(jiffies, timeout)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400321 dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
Ben Hutchings94e61082008-03-05 16:52:39 +0000322 return -ETIMEDOUT;
Prarit Bhargava50307182010-05-17 14:25:14 -0400323 }
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800324 if (fatal_signal_pending(current))
325 return -EINTR;
326 if (!cond_resched())
327 udelay(10);
Ben Hutchings94e61082008-03-05 16:52:39 +0000328 }
329}
330
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800331static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
332 void *arg)
Ben Hutchings94e61082008-03-05 16:52:39 +0000333{
334 struct pci_vpd_pci22 *vpd =
335 container_of(dev->vpd, struct pci_vpd_pci22, base);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800336 int ret;
337 loff_t end = pos + count;
338 u8 *buf = arg;
Ben Hutchings94e61082008-03-05 16:52:39 +0000339
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800340 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
Ben Hutchings94e61082008-03-05 16:52:39 +0000341 return -EINVAL;
Ben Hutchings94e61082008-03-05 16:52:39 +0000342
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800343 if (mutex_lock_killable(&vpd->lock))
344 return -EINTR;
345
Ben Hutchings94e61082008-03-05 16:52:39 +0000346 ret = pci_vpd_pci22_wait(dev);
347 if (ret < 0)
348 goto out;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800349
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800350 while (pos < end) {
351 u32 val;
352 unsigned int i, skip;
353
354 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
355 pos & ~3);
356 if (ret < 0)
357 break;
358 vpd->busy = true;
359 vpd->flag = PCI_VPD_ADDR_F;
360 ret = pci_vpd_pci22_wait(dev);
361 if (ret < 0)
362 break;
363
364 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
365 if (ret < 0)
366 break;
367
368 skip = pos & 3;
369 for (i = 0; i < sizeof(u32); i++) {
370 if (i >= skip) {
371 *buf++ = val;
372 if (++pos == end)
373 break;
374 }
375 val >>= 8;
376 }
377 }
Ben Hutchings94e61082008-03-05 16:52:39 +0000378out:
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800379 mutex_unlock(&vpd->lock);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800380 return ret ? ret : count;
Ben Hutchings94e61082008-03-05 16:52:39 +0000381}
382
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800383static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
384 const void *arg)
Ben Hutchings94e61082008-03-05 16:52:39 +0000385{
386 struct pci_vpd_pci22 *vpd =
387 container_of(dev->vpd, struct pci_vpd_pci22, base);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800388 const u8 *buf = arg;
389 loff_t end = pos + count;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800390 int ret = 0;
Ben Hutchings94e61082008-03-05 16:52:39 +0000391
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800392 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
Ben Hutchings94e61082008-03-05 16:52:39 +0000393 return -EINVAL;
394
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800395 if (mutex_lock_killable(&vpd->lock))
396 return -EINTR;
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800397
Ben Hutchings94e61082008-03-05 16:52:39 +0000398 ret = pci_vpd_pci22_wait(dev);
399 if (ret < 0)
400 goto out;
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800401
402 while (pos < end) {
403 u32 val;
404
405 val = *buf++;
406 val |= *buf++ << 8;
407 val |= *buf++ << 16;
408 val |= *buf++ << 24;
409
410 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
411 if (ret < 0)
412 break;
413 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
414 pos | PCI_VPD_ADDR_F);
415 if (ret < 0)
416 break;
417
418 vpd->busy = true;
419 vpd->flag = 0;
420 ret = pci_vpd_pci22_wait(dev);
Greg Thelend97ecd82011-04-17 08:22:21 -0700421 if (ret < 0)
422 break;
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800423
424 pos += sizeof(u32);
425 }
Ben Hutchings94e61082008-03-05 16:52:39 +0000426out:
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800427 mutex_unlock(&vpd->lock);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800428 return ret ? ret : count;
Ben Hutchings94e61082008-03-05 16:52:39 +0000429}
430
Ben Hutchings94e61082008-03-05 16:52:39 +0000431static void pci_vpd_pci22_release(struct pci_dev *dev)
432{
433 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
434}
435
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800436static const struct pci_vpd_ops pci_vpd_pci22_ops = {
Ben Hutchings94e61082008-03-05 16:52:39 +0000437 .read = pci_vpd_pci22_read,
438 .write = pci_vpd_pci22_write,
Ben Hutchings94e61082008-03-05 16:52:39 +0000439 .release = pci_vpd_pci22_release,
440};
441
442int pci_vpd_pci22_init(struct pci_dev *dev)
443{
444 struct pci_vpd_pci22 *vpd;
445 u8 cap;
446
447 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
448 if (!cap)
449 return -ENODEV;
450 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
451 if (!vpd)
452 return -ENOMEM;
453
Benjamin Li99cb233d2008-07-02 10:59:04 -0700454 vpd->base.len = PCI_VPD_PCI22_SIZE;
Ben Hutchings94e61082008-03-05 16:52:39 +0000455 vpd->base.ops = &pci_vpd_pci22_ops;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800456 mutex_init(&vpd->lock);
Ben Hutchings94e61082008-03-05 16:52:39 +0000457 vpd->cap = cap;
458 vpd->busy = false;
459 dev->vpd = &vpd->base;
460 return 0;
461}
462
Brian Kinge04b0ea2005-09-27 01:21:55 -0700463/**
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100464 * pci_cfg_access_lock - Lock PCI config reads/writes
Brian Kinge04b0ea2005-09-27 01:21:55 -0700465 * @dev: pci device struct
466 *
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100467 * When access is locked, any userspace reads or writes to config
468 * space and concurrent lock requests will sleep until access is
469 * allowed via pci_cfg_access_unlocked again.
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600470 */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100471void pci_cfg_access_lock(struct pci_dev *dev)
Brian Kinge04b0ea2005-09-27 01:21:55 -0700472{
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100473 might_sleep();
Brian Kinge04b0ea2005-09-27 01:21:55 -0700474
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100475 raw_spin_lock_irq(&pci_lock);
476 if (dev->block_cfg_access)
477 pci_wait_cfg(dev);
478 dev->block_cfg_access = 1;
479 raw_spin_unlock_irq(&pci_lock);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700480}
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100481EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700482
483/**
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100484 * pci_cfg_access_trylock - try to lock PCI config reads/writes
Brian Kinge04b0ea2005-09-27 01:21:55 -0700485 * @dev: pci device struct
486 *
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100487 * Same as pci_cfg_access_lock, but will return 0 if access is
488 * already locked, 1 otherwise. This function can be used from
489 * atomic contexts.
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600490 */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100491bool pci_cfg_access_trylock(struct pci_dev *dev)
492{
493 unsigned long flags;
494 bool locked = true;
495
496 raw_spin_lock_irqsave(&pci_lock, flags);
497 if (dev->block_cfg_access)
498 locked = false;
499 else
500 dev->block_cfg_access = 1;
501 raw_spin_unlock_irqrestore(&pci_lock, flags);
502
503 return locked;
504}
505EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
506
507/**
508 * pci_cfg_access_unlock - Unlock PCI config reads/writes
509 * @dev: pci device struct
510 *
511 * This function allows PCI config accesses to resume.
512 */
513void pci_cfg_access_unlock(struct pci_dev *dev)
Brian Kinge04b0ea2005-09-27 01:21:55 -0700514{
515 unsigned long flags;
516
Thomas Gleixner511dd982010-02-17 14:35:19 +0000517 raw_spin_lock_irqsave(&pci_lock, flags);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600518
519 /* This indicates a problem in the caller, but we don't need
520 * to kill them, unlike a double-block above. */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100521 WARN_ON(!dev->block_cfg_access);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600522
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100523 dev->block_cfg_access = 0;
524 wake_up_all(&pci_cfg_wait);
Thomas Gleixner511dd982010-02-17 14:35:19 +0000525 raw_spin_unlock_irqrestore(&pci_lock, flags);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700526}
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100527EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800528
529static inline int pcie_cap_version(const struct pci_dev *dev)
530{
Myron Stowe1c531d82013-01-25 17:55:45 -0700531 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800532}
533
Yinghai Lu7a1562d2014-11-11 12:09:46 -0800534bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800535{
536 int type = pci_pcie_type(dev);
537
Bjorn Helgaasc8b303d2013-08-28 11:33:53 -0600538 return type == PCI_EXP_TYPE_ENDPOINT ||
Bjorn Helgaasd3694d42013-08-27 09:54:40 -0600539 type == PCI_EXP_TYPE_LEG_END ||
540 type == PCI_EXP_TYPE_ROOT_PORT ||
541 type == PCI_EXP_TYPE_UPSTREAM ||
542 type == PCI_EXP_TYPE_DOWNSTREAM ||
543 type == PCI_EXP_TYPE_PCI_BRIDGE ||
544 type == PCI_EXP_TYPE_PCIE_BRIDGE;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800545}
546
547static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
548{
549 int type = pci_pcie_type(dev);
550
Bjorn Helgaas6d3a1742013-08-28 12:01:03 -0600551 return (type == PCI_EXP_TYPE_ROOT_PORT ||
552 type == PCI_EXP_TYPE_DOWNSTREAM) &&
553 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800554}
555
556static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
557{
558 int type = pci_pcie_type(dev);
559
Bjorn Helgaasc8b303d2013-08-28 11:33:53 -0600560 return type == PCI_EXP_TYPE_ROOT_PORT ||
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800561 type == PCI_EXP_TYPE_RC_EC;
562}
563
564static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
565{
566 if (!pci_is_pcie(dev))
567 return false;
568
569 switch (pos) {
Alex Williamson969daa32013-02-14 11:35:42 -0700570 case PCI_EXP_FLAGS:
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800571 return true;
572 case PCI_EXP_DEVCAP:
573 case PCI_EXP_DEVCTL:
574 case PCI_EXP_DEVSTA:
Bjorn Helgaasfed24512013-08-28 12:03:42 -0600575 return true;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800576 case PCI_EXP_LNKCAP:
577 case PCI_EXP_LNKCTL:
578 case PCI_EXP_LNKSTA:
579 return pcie_cap_has_lnkctl(dev);
580 case PCI_EXP_SLTCAP:
581 case PCI_EXP_SLTCTL:
582 case PCI_EXP_SLTSTA:
583 return pcie_cap_has_sltctl(dev);
584 case PCI_EXP_RTCTL:
585 case PCI_EXP_RTCAP:
586 case PCI_EXP_RTSTA:
587 return pcie_cap_has_rtctl(dev);
588 case PCI_EXP_DEVCAP2:
589 case PCI_EXP_DEVCTL2:
590 case PCI_EXP_LNKCAP2:
591 case PCI_EXP_LNKCTL2:
592 case PCI_EXP_LNKSTA2:
593 return pcie_cap_version(dev) > 1;
594 default:
595 return false;
596 }
597}
598
599/*
600 * Note that these accessor functions are only for the "PCI Express
601 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
602 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
603 */
604int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
605{
606 int ret;
607
608 *val = 0;
609 if (pos & 1)
610 return -EINVAL;
611
612 if (pcie_capability_reg_implemented(dev, pos)) {
613 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
614 /*
615 * Reset *val to 0 if pci_read_config_word() fails, it may
616 * have been written as 0xFFFF if hardware error happens
617 * during pci_read_config_word().
618 */
619 if (ret)
620 *val = 0;
621 return ret;
622 }
623
624 /*
625 * For Functions that do not implement the Slot Capabilities,
626 * Slot Status, and Slot Control registers, these spaces must
627 * be hardwired to 0b, with the exception of the Presence Detect
628 * State bit in the Slot Status register of Downstream Ports,
629 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
630 */
631 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
632 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
633 *val = PCI_EXP_SLTSTA_PDS;
634 }
635
636 return 0;
637}
638EXPORT_SYMBOL(pcie_capability_read_word);
639
640int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
641{
642 int ret;
643
644 *val = 0;
645 if (pos & 3)
646 return -EINVAL;
647
648 if (pcie_capability_reg_implemented(dev, pos)) {
649 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
650 /*
651 * Reset *val to 0 if pci_read_config_dword() fails, it may
652 * have been written as 0xFFFFFFFF if hardware error happens
653 * during pci_read_config_dword().
654 */
655 if (ret)
656 *val = 0;
657 return ret;
658 }
659
660 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
661 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
662 *val = PCI_EXP_SLTSTA_PDS;
663 }
664
665 return 0;
666}
667EXPORT_SYMBOL(pcie_capability_read_dword);
668
669int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
670{
671 if (pos & 1)
672 return -EINVAL;
673
674 if (!pcie_capability_reg_implemented(dev, pos))
675 return 0;
676
677 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
678}
679EXPORT_SYMBOL(pcie_capability_write_word);
680
681int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
682{
683 if (pos & 3)
684 return -EINVAL;
685
686 if (!pcie_capability_reg_implemented(dev, pos))
687 return 0;
688
689 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
690}
691EXPORT_SYMBOL(pcie_capability_write_dword);
692
693int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
694 u16 clear, u16 set)
695{
696 int ret;
697 u16 val;
698
699 ret = pcie_capability_read_word(dev, pos, &val);
700 if (!ret) {
701 val &= ~clear;
702 val |= set;
703 ret = pcie_capability_write_word(dev, pos, val);
704 }
705
706 return ret;
707}
708EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
709
710int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
711 u32 clear, u32 set)
712{
713 int ret;
714 u32 val;
715
716 ret = pcie_capability_read_dword(dev, pos, &val);
717 if (!ret) {
718 val &= ~clear;
719 val |= set;
720 ret = pcie_capability_write_dword(dev, pos, val);
721 }
722
723 return ret;
724}
725EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);