blob: 167dbaf6574275a0fffd5590b7a169e811320b39 [file] [log] [blame]
Russell King7bedaa52012-04-13 12:10:24 +01001/*
2 * OMAP DMAengine support
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
Russell Kingfa3ad862013-11-02 17:07:09 +00008#include <linux/delay.h>
Russell King7bedaa52012-04-13 12:10:24 +01009#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/module.h>
16#include <linux/omap-dma.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
Jon Hunter8d306622013-02-26 12:27:24 -060020#include <linux/of_dma.h>
21#include <linux/of_device.h>
Russell King7bedaa52012-04-13 12:10:24 +010022
23#include "virt-dma.h"
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -070024
Russell King7bedaa52012-04-13 12:10:24 +010025struct omap_dmadev {
26 struct dma_device ddev;
27 spinlock_t lock;
28 struct tasklet_struct task;
29 struct list_head pending;
Russell King596c4712013-12-10 11:08:01 +000030 void __iomem *base;
31 const struct omap_dma_reg *reg_map;
Russell King1b416c42013-11-02 13:00:03 +000032 struct omap_system_dma_plat_info *plat;
Russell King6ddeb6d2013-12-10 19:05:50 +000033 bool legacy;
34 spinlock_t irq_lock;
35 uint32_t irq_enable_mask;
36 struct omap_chan *lch_map[32];
Russell King7bedaa52012-04-13 12:10:24 +010037};
38
39struct omap_chan {
40 struct virt_dma_chan vc;
41 struct list_head node;
Russell King596c4712013-12-10 11:08:01 +000042 void __iomem *channel_base;
43 const struct omap_dma_reg *reg_map;
Russell Kingaa4c5b92014-01-14 23:58:10 +000044 uint32_t ccr;
Russell King7bedaa52012-04-13 12:10:24 +010045
46 struct dma_slave_config cfg;
47 unsigned dma_sig;
Russell King3a774ea2012-06-21 10:40:15 +010048 bool cyclic;
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +030049 bool paused;
Russell King7bedaa52012-04-13 12:10:24 +010050
51 int dma_ch;
52 struct omap_desc *desc;
53 unsigned sgidx;
54};
55
56struct omap_sg {
57 dma_addr_t addr;
58 uint32_t en; /* number of elements (24-bit) */
59 uint32_t fn; /* number of frames (16-bit) */
60};
61
62struct omap_desc {
63 struct virt_dma_desc vd;
64 enum dma_transfer_direction dir;
65 dma_addr_t dev_addr;
66
Russell King7c836bc2012-06-18 16:45:19 +010067 int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
Russell King90438262013-11-02 19:57:06 +000068 uint8_t es; /* CSDP_DATA_TYPE_xxx */
Russell King3ed4d182013-11-02 19:16:09 +000069 uint32_t ccr; /* CCR value */
Russell King965aeb4d2013-11-06 17:12:30 +000070 uint16_t clnk_ctrl; /* CLNK_CTRL value */
Russell Kingfa3ad862013-11-02 17:07:09 +000071 uint16_t cicr; /* CICR value */
Russell King2f0d13b2013-11-02 18:51:53 +000072 uint32_t csdp; /* CSDP value */
Russell King7bedaa52012-04-13 12:10:24 +010073
74 unsigned sglen;
75 struct omap_sg sg[0];
76};
77
Russell King90438262013-11-02 19:57:06 +000078enum {
79 CCR_FS = BIT(5),
80 CCR_READ_PRIORITY = BIT(6),
81 CCR_ENABLE = BIT(7),
82 CCR_AUTO_INIT = BIT(8), /* OMAP1 only */
83 CCR_REPEAT = BIT(9), /* OMAP1 only */
84 CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */
85 CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */
86 CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */
87 CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */
88 CCR_SRC_AMODE_CONSTANT = 0 << 12,
89 CCR_SRC_AMODE_POSTINC = 1 << 12,
90 CCR_SRC_AMODE_SGLIDX = 2 << 12,
91 CCR_SRC_AMODE_DBLIDX = 3 << 12,
92 CCR_DST_AMODE_CONSTANT = 0 << 14,
93 CCR_DST_AMODE_POSTINC = 1 << 14,
94 CCR_DST_AMODE_SGLIDX = 2 << 14,
95 CCR_DST_AMODE_DBLIDX = 3 << 14,
96 CCR_CONSTANT_FILL = BIT(16),
97 CCR_TRANSPARENT_COPY = BIT(17),
98 CCR_BS = BIT(18),
99 CCR_SUPERVISOR = BIT(22),
100 CCR_PREFETCH = BIT(23),
101 CCR_TRIGGER_SRC = BIT(24),
102 CCR_BUFFERING_DISABLE = BIT(25),
103 CCR_WRITE_PRIORITY = BIT(26),
104 CCR_SYNC_ELEMENT = 0,
105 CCR_SYNC_FRAME = CCR_FS,
106 CCR_SYNC_BLOCK = CCR_BS,
107 CCR_SYNC_PACKET = CCR_BS | CCR_FS,
108
109 CSDP_DATA_TYPE_8 = 0,
110 CSDP_DATA_TYPE_16 = 1,
111 CSDP_DATA_TYPE_32 = 2,
112 CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */
113 CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */
114 CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */
115 CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */
116 CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */
117 CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */
118 CSDP_SRC_PACKED = BIT(6),
119 CSDP_SRC_BURST_1 = 0 << 7,
120 CSDP_SRC_BURST_16 = 1 << 7,
121 CSDP_SRC_BURST_32 = 2 << 7,
122 CSDP_SRC_BURST_64 = 3 << 7,
123 CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */
124 CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */
125 CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */
126 CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */
127 CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */
128 CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */
129 CSDP_DST_PACKED = BIT(13),
130 CSDP_DST_BURST_1 = 0 << 14,
131 CSDP_DST_BURST_16 = 1 << 14,
132 CSDP_DST_BURST_32 = 2 << 14,
133 CSDP_DST_BURST_64 = 3 << 14,
134
135 CICR_TOUT_IE = BIT(0), /* OMAP1 only */
136 CICR_DROP_IE = BIT(1),
137 CICR_HALF_IE = BIT(2),
138 CICR_FRAME_IE = BIT(3),
139 CICR_LAST_IE = BIT(4),
140 CICR_BLOCK_IE = BIT(5),
141 CICR_PKT_IE = BIT(7), /* OMAP2+ only */
142 CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */
143 CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */
144 CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */
145 CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */
146 CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */
147
148 CLNK_CTRL_ENABLE_LNK = BIT(15),
149};
150
Russell King7bedaa52012-04-13 12:10:24 +0100151static const unsigned es_bytes[] = {
Russell King90438262013-11-02 19:57:06 +0000152 [CSDP_DATA_TYPE_8] = 1,
153 [CSDP_DATA_TYPE_16] = 2,
154 [CSDP_DATA_TYPE_32] = 4,
Russell King7bedaa52012-04-13 12:10:24 +0100155};
156
Jon Hunter8d306622013-02-26 12:27:24 -0600157static struct of_dma_filter_info omap_dma_info = {
158 .filter_fn = omap_dma_filter_fn,
159};
160
Russell King7bedaa52012-04-13 12:10:24 +0100161static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
162{
163 return container_of(d, struct omap_dmadev, ddev);
164}
165
166static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
167{
168 return container_of(c, struct omap_chan, vc.chan);
169}
170
171static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
172{
173 return container_of(t, struct omap_desc, vd.tx);
174}
175
176static void omap_dma_desc_free(struct virt_dma_desc *vd)
177{
178 kfree(container_of(vd, struct omap_desc, vd));
179}
180
Russell King596c4712013-12-10 11:08:01 +0000181static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
182{
183 switch (type) {
184 case OMAP_DMA_REG_16BIT:
185 writew_relaxed(val, addr);
186 break;
187 case OMAP_DMA_REG_2X16BIT:
188 writew_relaxed(val, addr);
189 writew_relaxed(val >> 16, addr + 2);
190 break;
191 case OMAP_DMA_REG_32BIT:
192 writel_relaxed(val, addr);
193 break;
194 default:
195 WARN_ON(1);
196 }
197}
198
199static unsigned omap_dma_read(unsigned type, void __iomem *addr)
200{
201 unsigned val;
202
203 switch (type) {
204 case OMAP_DMA_REG_16BIT:
205 val = readw_relaxed(addr);
206 break;
207 case OMAP_DMA_REG_2X16BIT:
208 val = readw_relaxed(addr);
209 val |= readw_relaxed(addr + 2) << 16;
210 break;
211 case OMAP_DMA_REG_32BIT:
212 val = readl_relaxed(addr);
213 break;
214 default:
215 WARN_ON(1);
216 val = 0;
217 }
218
219 return val;
220}
221
Russell Kingc5ed98b2013-11-06 17:33:09 +0000222static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
223{
Russell King596c4712013-12-10 11:08:01 +0000224 const struct omap_dma_reg *r = od->reg_map + reg;
225
226 WARN_ON(r->stride);
227
228 omap_dma_write(val, r->type, od->base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000229}
230
231static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
232{
Russell King596c4712013-12-10 11:08:01 +0000233 const struct omap_dma_reg *r = od->reg_map + reg;
234
235 WARN_ON(r->stride);
236
237 return omap_dma_read(r->type, od->base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000238}
239
240static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
241{
Russell King596c4712013-12-10 11:08:01 +0000242 const struct omap_dma_reg *r = c->reg_map + reg;
243
244 omap_dma_write(val, r->type, c->channel_base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000245}
246
247static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
248{
Russell King596c4712013-12-10 11:08:01 +0000249 const struct omap_dma_reg *r = c->reg_map + reg;
250
251 return omap_dma_read(r->type, c->channel_base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000252}
253
Russell King470b23f2013-11-02 21:23:06 +0000254static void omap_dma_clear_csr(struct omap_chan *c)
255{
256 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000257 omap_dma_chan_read(c, CSR);
Russell King470b23f2013-11-02 21:23:06 +0000258 else
Russell Kingc5ed98b2013-11-06 17:33:09 +0000259 omap_dma_chan_write(c, CSR, ~0);
Russell King470b23f2013-11-02 21:23:06 +0000260}
261
Russell King6ddeb6d2013-12-10 19:05:50 +0000262static unsigned omap_dma_get_csr(struct omap_chan *c)
263{
264 unsigned val = omap_dma_chan_read(c, CSR);
265
266 if (!dma_omap1())
267 omap_dma_chan_write(c, CSR, val);
268
269 return val;
270}
271
Russell King596c4712013-12-10 11:08:01 +0000272static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
273 unsigned lch)
274{
275 c->channel_base = od->base + od->plat->channel_stride * lch;
Russell King6ddeb6d2013-12-10 19:05:50 +0000276
277 od->lch_map[lch] = c;
Russell King596c4712013-12-10 11:08:01 +0000278}
279
Russell Kingfa3ad862013-11-02 17:07:09 +0000280static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
281{
282 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
Russell Kingfa3ad862013-11-02 17:07:09 +0000283
284 if (__dma_omap15xx(od->plat->dma_attr))
Russell Kingc5ed98b2013-11-06 17:33:09 +0000285 omap_dma_chan_write(c, CPC, 0);
Russell Kingfa3ad862013-11-02 17:07:09 +0000286 else
Russell Kingc5ed98b2013-11-06 17:33:09 +0000287 omap_dma_chan_write(c, CDAC, 0);
Russell Kingfa3ad862013-11-02 17:07:09 +0000288
Russell King470b23f2013-11-02 21:23:06 +0000289 omap_dma_clear_csr(c);
Russell Kingfa3ad862013-11-02 17:07:09 +0000290
291 /* Enable interrupts */
Russell Kingc5ed98b2013-11-06 17:33:09 +0000292 omap_dma_chan_write(c, CICR, d->cicr);
Russell Kingfa3ad862013-11-02 17:07:09 +0000293
Russell King45da7b02013-11-06 17:18:42 +0000294 /* Enable channel */
Russell Kingc5ed98b2013-11-06 17:33:09 +0000295 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
Russell Kingfa3ad862013-11-02 17:07:09 +0000296}
297
298static void omap_dma_stop(struct omap_chan *c)
299{
300 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
301 uint32_t val;
302
303 /* disable irq */
Russell Kingc5ed98b2013-11-06 17:33:09 +0000304 omap_dma_chan_write(c, CICR, 0);
Russell Kingfa3ad862013-11-02 17:07:09 +0000305
Russell King470b23f2013-11-02 21:23:06 +0000306 omap_dma_clear_csr(c);
Russell Kingfa3ad862013-11-02 17:07:09 +0000307
Russell Kingc5ed98b2013-11-06 17:33:09 +0000308 val = omap_dma_chan_read(c, CCR);
Russell King90438262013-11-02 19:57:06 +0000309 if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
Russell Kingfa3ad862013-11-02 17:07:09 +0000310 uint32_t sysconfig;
311 unsigned i;
312
Russell Kingc5ed98b2013-11-06 17:33:09 +0000313 sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
Russell Kingfa3ad862013-11-02 17:07:09 +0000314 val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
315 val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000316 omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000317
Russell Kingc5ed98b2013-11-06 17:33:09 +0000318 val = omap_dma_chan_read(c, CCR);
Russell King90438262013-11-02 19:57:06 +0000319 val &= ~CCR_ENABLE;
Russell Kingc5ed98b2013-11-06 17:33:09 +0000320 omap_dma_chan_write(c, CCR, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000321
322 /* Wait for sDMA FIFO to drain */
323 for (i = 0; ; i++) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000324 val = omap_dma_chan_read(c, CCR);
Russell King90438262013-11-02 19:57:06 +0000325 if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
Russell Kingfa3ad862013-11-02 17:07:09 +0000326 break;
327
328 if (i > 100)
329 break;
330
331 udelay(5);
332 }
333
Russell King90438262013-11-02 19:57:06 +0000334 if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
Russell Kingfa3ad862013-11-02 17:07:09 +0000335 dev_err(c->vc.chan.device->dev,
336 "DMA drain did not complete on lch %d\n",
337 c->dma_ch);
338
Russell Kingc5ed98b2013-11-06 17:33:09 +0000339 omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
Russell Kingfa3ad862013-11-02 17:07:09 +0000340 } else {
Russell King90438262013-11-02 19:57:06 +0000341 val &= ~CCR_ENABLE;
Russell Kingc5ed98b2013-11-06 17:33:09 +0000342 omap_dma_chan_write(c, CCR, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000343 }
344
345 mb();
346
347 if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000348 val = omap_dma_chan_read(c, CLNK_CTRL);
Russell Kingfa3ad862013-11-02 17:07:09 +0000349
350 if (dma_omap1())
351 val |= 1 << 14; /* set the STOP_LNK bit */
352 else
Russell King90438262013-11-02 19:57:06 +0000353 val &= ~CLNK_CTRL_ENABLE_LNK;
Russell Kingfa3ad862013-11-02 17:07:09 +0000354
Russell Kingc5ed98b2013-11-06 17:33:09 +0000355 omap_dma_chan_write(c, CLNK_CTRL, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000356 }
357}
358
Russell King7bedaa52012-04-13 12:10:24 +0100359static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
360 unsigned idx)
361{
362 struct omap_sg *sg = d->sg + idx;
Russell King893e63e2013-11-03 11:17:11 +0000363 unsigned cxsa, cxei, cxfi;
Russell King7bedaa52012-04-13 12:10:24 +0100364
Russell Kingb9e97822013-11-02 13:26:57 +0000365 if (d->dir == DMA_DEV_TO_MEM) {
Russell King893e63e2013-11-03 11:17:11 +0000366 cxsa = CDSA;
367 cxei = CDEI;
368 cxfi = CDFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000369 } else {
Russell King893e63e2013-11-03 11:17:11 +0000370 cxsa = CSSA;
371 cxei = CSEI;
372 cxfi = CSFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000373 }
374
Russell Kingc5ed98b2013-11-06 17:33:09 +0000375 omap_dma_chan_write(c, cxsa, sg->addr);
376 omap_dma_chan_write(c, cxei, 0);
377 omap_dma_chan_write(c, cxfi, 0);
378 omap_dma_chan_write(c, CEN, sg->en);
379 omap_dma_chan_write(c, CFN, sg->fn);
Russell King7bedaa52012-04-13 12:10:24 +0100380
Russell Kingfa3ad862013-11-02 17:07:09 +0000381 omap_dma_start(c, d);
Russell King7bedaa52012-04-13 12:10:24 +0100382}
383
384static void omap_dma_start_desc(struct omap_chan *c)
385{
386 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
387 struct omap_desc *d;
Russell King893e63e2013-11-03 11:17:11 +0000388 unsigned cxsa, cxei, cxfi;
Russell King7bedaa52012-04-13 12:10:24 +0100389
390 if (!vd) {
391 c->desc = NULL;
392 return;
393 }
394
395 list_del(&vd->node);
396
397 c->desc = d = to_omap_dma_desc(&vd->tx);
398 c->sgidx = 0;
399
Russell King59871902013-11-06 17:15:16 +0000400 /*
401 * This provides the necessary barrier to ensure data held in
402 * DMA coherent memory is visible to the DMA engine prior to
403 * the transfer starting.
404 */
405 mb();
406
Russell Kingc5ed98b2013-11-06 17:33:09 +0000407 omap_dma_chan_write(c, CCR, d->ccr);
Russell King3ed4d182013-11-02 19:16:09 +0000408 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000409 omap_dma_chan_write(c, CCR2, d->ccr >> 16);
Russell Kingb9e97822013-11-02 13:26:57 +0000410
Russell King3ed4d182013-11-02 19:16:09 +0000411 if (d->dir == DMA_DEV_TO_MEM) {
Russell King893e63e2013-11-03 11:17:11 +0000412 cxsa = CSSA;
413 cxei = CSEI;
414 cxfi = CSFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000415 } else {
Russell King893e63e2013-11-03 11:17:11 +0000416 cxsa = CDSA;
417 cxei = CDEI;
418 cxfi = CDFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000419 }
Russell King7bedaa52012-04-13 12:10:24 +0100420
Russell Kingc5ed98b2013-11-06 17:33:09 +0000421 omap_dma_chan_write(c, cxsa, d->dev_addr);
422 omap_dma_chan_write(c, cxei, 0);
423 omap_dma_chan_write(c, cxfi, d->fi);
424 omap_dma_chan_write(c, CSDP, d->csdp);
425 omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
Russell King913a2d02013-11-02 14:41:42 +0000426
Russell King7bedaa52012-04-13 12:10:24 +0100427 omap_dma_start_sg(c, d, 0);
428}
429
430static void omap_dma_callback(int ch, u16 status, void *data)
431{
432 struct omap_chan *c = data;
433 struct omap_desc *d;
434 unsigned long flags;
435
436 spin_lock_irqsave(&c->vc.lock, flags);
437 d = c->desc;
438 if (d) {
Russell King3a774ea2012-06-21 10:40:15 +0100439 if (!c->cyclic) {
440 if (++c->sgidx < d->sglen) {
441 omap_dma_start_sg(c, d, c->sgidx);
442 } else {
443 omap_dma_start_desc(c);
444 vchan_cookie_complete(&d->vd);
445 }
Russell King7bedaa52012-04-13 12:10:24 +0100446 } else {
Russell King3a774ea2012-06-21 10:40:15 +0100447 vchan_cyclic_callback(&d->vd);
Russell King7bedaa52012-04-13 12:10:24 +0100448 }
449 }
450 spin_unlock_irqrestore(&c->vc.lock, flags);
451}
452
453/*
454 * This callback schedules all pending channels. We could be more
455 * clever here by postponing allocation of the real DMA channels to
456 * this point, and freeing them when our virtual channel becomes idle.
457 *
458 * We would then need to deal with 'all channels in-use'
459 */
460static void omap_dma_sched(unsigned long data)
461{
462 struct omap_dmadev *d = (struct omap_dmadev *)data;
463 LIST_HEAD(head);
464
465 spin_lock_irq(&d->lock);
466 list_splice_tail_init(&d->pending, &head);
467 spin_unlock_irq(&d->lock);
468
469 while (!list_empty(&head)) {
470 struct omap_chan *c = list_first_entry(&head,
471 struct omap_chan, node);
472
473 spin_lock_irq(&c->vc.lock);
474 list_del_init(&c->node);
475 omap_dma_start_desc(c);
476 spin_unlock_irq(&c->vc.lock);
477 }
478}
479
Russell King6ddeb6d2013-12-10 19:05:50 +0000480static irqreturn_t omap_dma_irq(int irq, void *devid)
481{
482 struct omap_dmadev *od = devid;
483 unsigned status, channel;
484
485 spin_lock(&od->irq_lock);
486
487 status = omap_dma_glbl_read(od, IRQSTATUS_L1);
488 status &= od->irq_enable_mask;
489 if (status == 0) {
490 spin_unlock(&od->irq_lock);
491 return IRQ_NONE;
492 }
493
494 while ((channel = ffs(status)) != 0) {
495 unsigned mask, csr;
496 struct omap_chan *c;
497
498 channel -= 1;
499 mask = BIT(channel);
500 status &= ~mask;
501
502 c = od->lch_map[channel];
503 if (c == NULL) {
504 /* This should never happen */
505 dev_err(od->ddev.dev, "invalid channel %u\n", channel);
506 continue;
507 }
508
509 csr = omap_dma_get_csr(c);
510 omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
511
512 omap_dma_callback(channel, csr, c);
513 }
514
515 spin_unlock(&od->irq_lock);
516
517 return IRQ_HANDLED;
518}
519
Russell King7bedaa52012-04-13 12:10:24 +0100520static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
521{
Russell King596c4712013-12-10 11:08:01 +0000522 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +0100523 struct omap_chan *c = to_omap_dma_chan(chan);
Russell King596c4712013-12-10 11:08:01 +0000524 int ret;
Russell King7bedaa52012-04-13 12:10:24 +0100525
Russell King6ddeb6d2013-12-10 19:05:50 +0000526 if (od->legacy) {
527 ret = omap_request_dma(c->dma_sig, "DMA engine",
528 omap_dma_callback, c, &c->dma_ch);
529 } else {
530 ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL,
531 &c->dma_ch);
532 }
Russell King7bedaa52012-04-13 12:10:24 +0100533
Russell King6ddeb6d2013-12-10 19:05:50 +0000534 dev_dbg(od->ddev.dev, "allocating channel %u for %u\n",
535 c->dma_ch, c->dma_sig);
Russell King596c4712013-12-10 11:08:01 +0000536
Russell King6ddeb6d2013-12-10 19:05:50 +0000537 if (ret >= 0) {
Russell King596c4712013-12-10 11:08:01 +0000538 omap_dma_assign(od, c, c->dma_ch);
539
Russell King6ddeb6d2013-12-10 19:05:50 +0000540 if (!od->legacy) {
541 unsigned val;
542
543 spin_lock_irq(&od->irq_lock);
544 val = BIT(c->dma_ch);
545 omap_dma_glbl_write(od, IRQSTATUS_L1, val);
546 od->irq_enable_mask |= val;
547 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
548
549 val = omap_dma_glbl_read(od, IRQENABLE_L0);
550 val &= ~BIT(c->dma_ch);
551 omap_dma_glbl_write(od, IRQENABLE_L0, val);
552 spin_unlock_irq(&od->irq_lock);
553 }
554 }
555
Russell Kingaa4c5b92014-01-14 23:58:10 +0000556 if (dma_omap1()) {
557 if (__dma_omap16xx(od->plat->dma_attr)) {
558 c->ccr = CCR_OMAP31_DISABLE;
559 /* Duplicate what plat-omap/dma.c does */
560 c->ccr |= c->dma_ch + 1;
561 } else {
562 c->ccr = c->dma_sig & 0x1f;
563 }
564 } else {
565 c->ccr = c->dma_sig & 0x1f;
566 c->ccr |= (c->dma_sig & ~0x1f) << 14;
567 }
568 if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
569 c->ccr |= CCR_BUFFERING_DISABLE;
570
Russell King596c4712013-12-10 11:08:01 +0000571 return ret;
Russell King7bedaa52012-04-13 12:10:24 +0100572}
573
574static void omap_dma_free_chan_resources(struct dma_chan *chan)
575{
Russell King6ddeb6d2013-12-10 19:05:50 +0000576 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +0100577 struct omap_chan *c = to_omap_dma_chan(chan);
578
Russell King6ddeb6d2013-12-10 19:05:50 +0000579 if (!od->legacy) {
580 spin_lock_irq(&od->irq_lock);
581 od->irq_enable_mask &= ~BIT(c->dma_ch);
582 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
583 spin_unlock_irq(&od->irq_lock);
584 }
585
Russell King596c4712013-12-10 11:08:01 +0000586 c->channel_base = NULL;
Russell King6ddeb6d2013-12-10 19:05:50 +0000587 od->lch_map[c->dma_ch] = NULL;
Russell King7bedaa52012-04-13 12:10:24 +0100588 vchan_free_chan_resources(&c->vc);
589 omap_free_dma(c->dma_ch);
590
Russell King6ddeb6d2013-12-10 19:05:50 +0000591 dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
Russell King7bedaa52012-04-13 12:10:24 +0100592}
593
Russell King3850e222012-06-21 10:37:35 +0100594static size_t omap_dma_sg_size(struct omap_sg *sg)
595{
596 return sg->en * sg->fn;
597}
598
599static size_t omap_dma_desc_size(struct omap_desc *d)
600{
601 unsigned i;
602 size_t size;
603
604 for (size = i = 0; i < d->sglen; i++)
605 size += omap_dma_sg_size(&d->sg[i]);
606
607 return size * es_bytes[d->es];
608}
609
610static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
611{
612 unsigned i;
613 size_t size, es_size = es_bytes[d->es];
614
615 for (size = i = 0; i < d->sglen; i++) {
616 size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
617
618 if (size)
619 size += this_size;
620 else if (addr >= d->sg[i].addr &&
621 addr < d->sg[i].addr + this_size)
622 size += d->sg[i].addr + this_size - addr;
623 }
624 return size;
625}
626
Russell Kingb07fd622013-11-06 19:26:45 +0000627/*
628 * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
629 * read before the DMA controller finished disabling the channel.
630 */
631static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
632{
633 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
634 uint32_t val;
635
636 val = omap_dma_chan_read(c, reg);
637 if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
638 val = omap_dma_chan_read(c, reg);
639
640 return val;
641}
642
Russell King3997cab2013-11-02 18:04:17 +0000643static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
644{
645 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
Russell Kingb07fd622013-11-06 19:26:45 +0000646 dma_addr_t addr, cdac;
Russell King3997cab2013-11-02 18:04:17 +0000647
Russell Kingb07fd622013-11-06 19:26:45 +0000648 if (__dma_omap15xx(od->plat->dma_attr)) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000649 addr = omap_dma_chan_read(c, CPC);
Russell Kingb07fd622013-11-06 19:26:45 +0000650 } else {
651 addr = omap_dma_chan_read_3_3(c, CSAC);
652 cdac = omap_dma_chan_read_3_3(c, CDAC);
Russell King3997cab2013-11-02 18:04:17 +0000653
Russell King3997cab2013-11-02 18:04:17 +0000654 /*
655 * CDAC == 0 indicates that the DMA transfer on the channel has
656 * not been started (no data has been transferred so far).
657 * Return the programmed source start address in this case.
658 */
Russell Kingb07fd622013-11-06 19:26:45 +0000659 if (cdac == 0)
Russell Kingc5ed98b2013-11-06 17:33:09 +0000660 addr = omap_dma_chan_read(c, CSSA);
Russell King3997cab2013-11-02 18:04:17 +0000661 }
662
663 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000664 addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
Russell King3997cab2013-11-02 18:04:17 +0000665
666 return addr;
667}
668
669static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
670{
671 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
672 dma_addr_t addr;
673
Russell Kingb07fd622013-11-06 19:26:45 +0000674 if (__dma_omap15xx(od->plat->dma_attr)) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000675 addr = omap_dma_chan_read(c, CPC);
Russell Kingb07fd622013-11-06 19:26:45 +0000676 } else {
677 addr = omap_dma_chan_read_3_3(c, CDAC);
Russell King3997cab2013-11-02 18:04:17 +0000678
Russell King3997cab2013-11-02 18:04:17 +0000679 /*
Russell Kingb07fd622013-11-06 19:26:45 +0000680 * CDAC == 0 indicates that the DMA transfer on the channel
681 * has not been started (no data has been transferred so
682 * far). Return the programmed destination start address in
683 * this case.
Russell King3997cab2013-11-02 18:04:17 +0000684 */
685 if (addr == 0)
Russell Kingc5ed98b2013-11-06 17:33:09 +0000686 addr = omap_dma_chan_read(c, CDSA);
Russell King3997cab2013-11-02 18:04:17 +0000687 }
688
689 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000690 addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
Russell King3997cab2013-11-02 18:04:17 +0000691
692 return addr;
693}
694
Russell King7bedaa52012-04-13 12:10:24 +0100695static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
696 dma_cookie_t cookie, struct dma_tx_state *txstate)
697{
Russell King3850e222012-06-21 10:37:35 +0100698 struct omap_chan *c = to_omap_dma_chan(chan);
699 struct virt_dma_desc *vd;
700 enum dma_status ret;
701 unsigned long flags;
702
703 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul7cce5082013-10-16 20:51:54 +0530704 if (ret == DMA_COMPLETE || !txstate)
Russell King3850e222012-06-21 10:37:35 +0100705 return ret;
706
707 spin_lock_irqsave(&c->vc.lock, flags);
708 vd = vchan_find_desc(&c->vc, cookie);
709 if (vd) {
710 txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
711 } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
712 struct omap_desc *d = c->desc;
713 dma_addr_t pos;
714
715 if (d->dir == DMA_MEM_TO_DEV)
Russell King3997cab2013-11-02 18:04:17 +0000716 pos = omap_dma_get_src_pos(c);
Russell King3850e222012-06-21 10:37:35 +0100717 else if (d->dir == DMA_DEV_TO_MEM)
Russell King3997cab2013-11-02 18:04:17 +0000718 pos = omap_dma_get_dst_pos(c);
Russell King3850e222012-06-21 10:37:35 +0100719 else
720 pos = 0;
721
722 txstate->residue = omap_dma_desc_size_pos(d, pos);
723 } else {
724 txstate->residue = 0;
725 }
726 spin_unlock_irqrestore(&c->vc.lock, flags);
727
728 return ret;
Russell King7bedaa52012-04-13 12:10:24 +0100729}
730
731static void omap_dma_issue_pending(struct dma_chan *chan)
732{
733 struct omap_chan *c = to_omap_dma_chan(chan);
734 unsigned long flags;
735
736 spin_lock_irqsave(&c->vc.lock, flags);
737 if (vchan_issue_pending(&c->vc) && !c->desc) {
Peter Ujfalusi76502462013-04-09 16:33:06 +0200738 /*
739 * c->cyclic is used only by audio and in this case the DMA need
740 * to be started without delay.
741 */
742 if (!c->cyclic) {
743 struct omap_dmadev *d = to_omap_dma_dev(chan->device);
744 spin_lock(&d->lock);
745 if (list_empty(&c->node))
746 list_add_tail(&c->node, &d->pending);
747 spin_unlock(&d->lock);
748 tasklet_schedule(&d->task);
749 } else {
750 omap_dma_start_desc(c);
751 }
Russell King7bedaa52012-04-13 12:10:24 +0100752 }
753 spin_unlock_irqrestore(&c->vc.lock, flags);
754}
755
756static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
757 struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
758 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
759{
Russell King49ae0b22013-11-02 21:09:18 +0000760 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +0100761 struct omap_chan *c = to_omap_dma_chan(chan);
762 enum dma_slave_buswidth dev_width;
763 struct scatterlist *sgent;
764 struct omap_desc *d;
765 dma_addr_t dev_addr;
Russell King3ed4d182013-11-02 19:16:09 +0000766 unsigned i, j = 0, es, en, frame_bytes;
Russell King7bedaa52012-04-13 12:10:24 +0100767 u32 burst;
768
769 if (dir == DMA_DEV_TO_MEM) {
770 dev_addr = c->cfg.src_addr;
771 dev_width = c->cfg.src_addr_width;
772 burst = c->cfg.src_maxburst;
Russell King7bedaa52012-04-13 12:10:24 +0100773 } else if (dir == DMA_MEM_TO_DEV) {
774 dev_addr = c->cfg.dst_addr;
775 dev_width = c->cfg.dst_addr_width;
776 burst = c->cfg.dst_maxburst;
Russell King7bedaa52012-04-13 12:10:24 +0100777 } else {
778 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
779 return NULL;
780 }
781
782 /* Bus width translates to the element size (ES) */
783 switch (dev_width) {
784 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Russell King90438262013-11-02 19:57:06 +0000785 es = CSDP_DATA_TYPE_8;
Russell King7bedaa52012-04-13 12:10:24 +0100786 break;
787 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Russell King90438262013-11-02 19:57:06 +0000788 es = CSDP_DATA_TYPE_16;
Russell King7bedaa52012-04-13 12:10:24 +0100789 break;
790 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Russell King90438262013-11-02 19:57:06 +0000791 es = CSDP_DATA_TYPE_32;
Russell King7bedaa52012-04-13 12:10:24 +0100792 break;
793 default: /* not reached */
794 return NULL;
795 }
796
797 /* Now allocate and setup the descriptor. */
798 d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
799 if (!d)
800 return NULL;
801
802 d->dir = dir;
803 d->dev_addr = dev_addr;
804 d->es = es;
Russell King3ed4d182013-11-02 19:16:09 +0000805
Russell Kingaa4c5b92014-01-14 23:58:10 +0000806 d->ccr = c->ccr | CCR_SYNC_FRAME;
Russell King3ed4d182013-11-02 19:16:09 +0000807 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000808 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
Russell King3ed4d182013-11-02 19:16:09 +0000809 else
Russell King90438262013-11-02 19:57:06 +0000810 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
Russell King3ed4d182013-11-02 19:16:09 +0000811
Russell King90438262013-11-02 19:57:06 +0000812 d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000813 d->csdp = es;
Russell Kingfa3ad862013-11-02 17:07:09 +0000814
Russell King2f0d13b2013-11-02 18:51:53 +0000815 if (dma_omap1()) {
Russell King90438262013-11-02 19:57:06 +0000816 d->cicr |= CICR_TOUT_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000817
818 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000819 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
Russell King2f0d13b2013-11-02 18:51:53 +0000820 else
Russell King90438262013-11-02 19:57:06 +0000821 d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
Russell King2f0d13b2013-11-02 18:51:53 +0000822 } else {
Russell King3ed4d182013-11-02 19:16:09 +0000823 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000824 d->ccr |= CCR_TRIGGER_SRC;
Russell King3ed4d182013-11-02 19:16:09 +0000825
Russell King90438262013-11-02 19:57:06 +0000826 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000827 }
Russell King965aeb4d2013-11-06 17:12:30 +0000828 if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
829 d->clnk_ctrl = c->dma_ch;
Russell King7bedaa52012-04-13 12:10:24 +0100830
831 /*
832 * Build our scatterlist entries: each contains the address,
833 * the number of elements (EN) in each frame, and the number of
834 * frames (FN). Number of bytes for this entry = ES * EN * FN.
835 *
836 * Burst size translates to number of elements with frame sync.
837 * Note: DMA engine defines burst to be the number of dev-width
838 * transfers.
839 */
840 en = burst;
841 frame_bytes = es_bytes[es] * en;
842 for_each_sg(sgl, sgent, sglen, i) {
843 d->sg[j].addr = sg_dma_address(sgent);
844 d->sg[j].en = en;
845 d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
846 j++;
847 }
848
849 d->sglen = j;
850
851 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
852}
853
Russell King3a774ea2012-06-21 10:40:15 +0100854static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
855 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200856 size_t period_len, enum dma_transfer_direction dir, unsigned long flags)
Russell King3a774ea2012-06-21 10:40:15 +0100857{
Russell Kingfa3ad862013-11-02 17:07:09 +0000858 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King3a774ea2012-06-21 10:40:15 +0100859 struct omap_chan *c = to_omap_dma_chan(chan);
860 enum dma_slave_buswidth dev_width;
861 struct omap_desc *d;
862 dma_addr_t dev_addr;
Russell King3ed4d182013-11-02 19:16:09 +0000863 unsigned es;
Russell King3a774ea2012-06-21 10:40:15 +0100864 u32 burst;
865
866 if (dir == DMA_DEV_TO_MEM) {
867 dev_addr = c->cfg.src_addr;
868 dev_width = c->cfg.src_addr_width;
869 burst = c->cfg.src_maxburst;
Russell King3a774ea2012-06-21 10:40:15 +0100870 } else if (dir == DMA_MEM_TO_DEV) {
871 dev_addr = c->cfg.dst_addr;
872 dev_width = c->cfg.dst_addr_width;
873 burst = c->cfg.dst_maxburst;
Russell King3a774ea2012-06-21 10:40:15 +0100874 } else {
875 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
876 return NULL;
877 }
878
879 /* Bus width translates to the element size (ES) */
880 switch (dev_width) {
881 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Russell King90438262013-11-02 19:57:06 +0000882 es = CSDP_DATA_TYPE_8;
Russell King3a774ea2012-06-21 10:40:15 +0100883 break;
884 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Russell King90438262013-11-02 19:57:06 +0000885 es = CSDP_DATA_TYPE_16;
Russell King3a774ea2012-06-21 10:40:15 +0100886 break;
887 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Russell King90438262013-11-02 19:57:06 +0000888 es = CSDP_DATA_TYPE_32;
Russell King3a774ea2012-06-21 10:40:15 +0100889 break;
890 default: /* not reached */
891 return NULL;
892 }
893
894 /* Now allocate and setup the descriptor. */
895 d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
896 if (!d)
897 return NULL;
898
899 d->dir = dir;
900 d->dev_addr = dev_addr;
901 d->fi = burst;
902 d->es = es;
Russell King3a774ea2012-06-21 10:40:15 +0100903 d->sg[0].addr = buf_addr;
904 d->sg[0].en = period_len / es_bytes[es];
905 d->sg[0].fn = buf_len / period_len;
906 d->sglen = 1;
Russell King3ed4d182013-11-02 19:16:09 +0000907
Russell Kingaa4c5b92014-01-14 23:58:10 +0000908 d->ccr = c->ccr;
Russell King3ed4d182013-11-02 19:16:09 +0000909 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000910 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
Russell King3ed4d182013-11-02 19:16:09 +0000911 else
Russell King90438262013-11-02 19:57:06 +0000912 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
Russell King3ed4d182013-11-02 19:16:09 +0000913
Russell King90438262013-11-02 19:57:06 +0000914 d->cicr = CICR_DROP_IE;
Russell Kingfa3ad862013-11-02 17:07:09 +0000915 if (flags & DMA_PREP_INTERRUPT)
Russell King90438262013-11-02 19:57:06 +0000916 d->cicr |= CICR_FRAME_IE;
Russell Kingfa3ad862013-11-02 17:07:09 +0000917
Russell King2f0d13b2013-11-02 18:51:53 +0000918 d->csdp = es;
919
920 if (dma_omap1()) {
Russell King90438262013-11-02 19:57:06 +0000921 d->cicr |= CICR_TOUT_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000922
923 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000924 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
Russell King2f0d13b2013-11-02 18:51:53 +0000925 else
Russell King90438262013-11-02 19:57:06 +0000926 d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
Russell King2f0d13b2013-11-02 18:51:53 +0000927 } else {
Russell King3ed4d182013-11-02 19:16:09 +0000928 if (burst)
Russell King90438262013-11-02 19:57:06 +0000929 d->ccr |= CCR_SYNC_PACKET;
930 else
931 d->ccr |= CCR_SYNC_ELEMENT;
Russell King3ed4d182013-11-02 19:16:09 +0000932
933 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000934 d->ccr |= CCR_TRIGGER_SRC;
Russell King3ed4d182013-11-02 19:16:09 +0000935
Russell King90438262013-11-02 19:57:06 +0000936 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
Russell King3a774ea2012-06-21 10:40:15 +0100937
Russell King90438262013-11-02 19:57:06 +0000938 d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
Russell King2f0d13b2013-11-02 18:51:53 +0000939 }
940
Russell King965aeb4d2013-11-06 17:12:30 +0000941 if (__dma_omap15xx(od->plat->dma_attr))
942 d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
943 else
944 d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
945
Russell King3ed4d182013-11-02 19:16:09 +0000946 c->cyclic = true;
Russell King3a774ea2012-06-21 10:40:15 +0100947
Peter Ujfalusi2dde5b92012-09-14 15:05:48 +0300948 return vchan_tx_prep(&c->vc, &d->vd, flags);
Russell King3a774ea2012-06-21 10:40:15 +0100949}
950
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100951static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
Russell King7bedaa52012-04-13 12:10:24 +0100952{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100953 struct omap_chan *c = to_omap_dma_chan(chan);
954
Russell King7bedaa52012-04-13 12:10:24 +0100955 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
956 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
957 return -EINVAL;
958
959 memcpy(&c->cfg, cfg, sizeof(c->cfg));
960
961 return 0;
962}
963
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100964static int omap_dma_terminate_all(struct dma_chan *chan)
Russell King7bedaa52012-04-13 12:10:24 +0100965{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100966 struct omap_chan *c = to_omap_dma_chan(chan);
Russell King7bedaa52012-04-13 12:10:24 +0100967 struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
968 unsigned long flags;
969 LIST_HEAD(head);
970
971 spin_lock_irqsave(&c->vc.lock, flags);
972
973 /* Prevent this channel being scheduled */
974 spin_lock(&d->lock);
975 list_del_init(&c->node);
976 spin_unlock(&d->lock);
977
978 /*
979 * Stop DMA activity: we assume the callback will not be called
Russell Kingfa3ad862013-11-02 17:07:09 +0000980 * after omap_dma_stop() returns (even if it does, it will see
Russell King7bedaa52012-04-13 12:10:24 +0100981 * c->desc is NULL and exit.)
982 */
983 if (c->desc) {
Peter Ujfalusi02d88b72015-03-27 13:35:52 +0200984 omap_dma_desc_free(&c->desc->vd);
Russell King7bedaa52012-04-13 12:10:24 +0100985 c->desc = NULL;
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +0300986 /* Avoid stopping the dma twice */
987 if (!c->paused)
Russell Kingfa3ad862013-11-02 17:07:09 +0000988 omap_dma_stop(c);
Russell King7bedaa52012-04-13 12:10:24 +0100989 }
990
Russell King3a774ea2012-06-21 10:40:15 +0100991 if (c->cyclic) {
992 c->cyclic = false;
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +0300993 c->paused = false;
Russell King3a774ea2012-06-21 10:40:15 +0100994 }
995
Russell King7bedaa52012-04-13 12:10:24 +0100996 vchan_get_all_descriptors(&c->vc, &head);
997 spin_unlock_irqrestore(&c->vc.lock, flags);
998 vchan_dma_desc_free_list(&c->vc, &head);
999
1000 return 0;
1001}
1002
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001003static int omap_dma_pause(struct dma_chan *chan)
Russell King7bedaa52012-04-13 12:10:24 +01001004{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001005 struct omap_chan *c = to_omap_dma_chan(chan);
1006
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001007 /* Pause/Resume only allowed with cyclic mode */
1008 if (!c->cyclic)
1009 return -EINVAL;
1010
1011 if (!c->paused) {
Russell Kingfa3ad862013-11-02 17:07:09 +00001012 omap_dma_stop(c);
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001013 c->paused = true;
1014 }
1015
1016 return 0;
Russell King7bedaa52012-04-13 12:10:24 +01001017}
1018
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001019static int omap_dma_resume(struct dma_chan *chan)
Russell King7bedaa52012-04-13 12:10:24 +01001020{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001021 struct omap_chan *c = to_omap_dma_chan(chan);
1022
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001023 /* Pause/Resume only allowed with cyclic mode */
1024 if (!c->cyclic)
1025 return -EINVAL;
1026
1027 if (c->paused) {
Peter Ujfalusib3d09da2014-09-16 22:45:56 +03001028 mb();
1029
Peter Ujfalusibfb60742014-09-16 22:45:57 +03001030 /* Restore channel link register */
1031 omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl);
1032
Russell Kingfa3ad862013-11-02 17:07:09 +00001033 omap_dma_start(c, c->desc);
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001034 c->paused = false;
1035 }
1036
1037 return 0;
Russell King7bedaa52012-04-13 12:10:24 +01001038}
1039
Russell King7bedaa52012-04-13 12:10:24 +01001040static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
1041{
1042 struct omap_chan *c;
1043
1044 c = kzalloc(sizeof(*c), GFP_KERNEL);
1045 if (!c)
1046 return -ENOMEM;
1047
Russell King596c4712013-12-10 11:08:01 +00001048 c->reg_map = od->reg_map;
Russell King7bedaa52012-04-13 12:10:24 +01001049 c->dma_sig = dma_sig;
1050 c->vc.desc_free = omap_dma_desc_free;
1051 vchan_init(&c->vc, &od->ddev);
1052 INIT_LIST_HEAD(&c->node);
1053
Russell King7bedaa52012-04-13 12:10:24 +01001054 return 0;
1055}
1056
1057static void omap_dma_free(struct omap_dmadev *od)
1058{
1059 tasklet_kill(&od->task);
1060 while (!list_empty(&od->ddev.channels)) {
1061 struct omap_chan *c = list_first_entry(&od->ddev.channels,
1062 struct omap_chan, vc.chan.device_node);
1063
1064 list_del(&c->vc.chan.device_node);
1065 tasklet_kill(&c->vc.task);
1066 kfree(c);
1067 }
Russell King7bedaa52012-04-13 12:10:24 +01001068}
1069
Peter Ujfalusi80b0e0a2014-03-29 19:03:30 +05301070#define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1071 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1072 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1073
Russell King7bedaa52012-04-13 12:10:24 +01001074static int omap_dma_probe(struct platform_device *pdev)
1075{
1076 struct omap_dmadev *od;
Russell King596c4712013-12-10 11:08:01 +00001077 struct resource *res;
Russell King6ddeb6d2013-12-10 19:05:50 +00001078 int rc, i, irq;
Russell King7bedaa52012-04-13 12:10:24 +01001079
Russell King104fce72013-11-02 12:58:29 +00001080 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
Russell King7bedaa52012-04-13 12:10:24 +01001081 if (!od)
1082 return -ENOMEM;
1083
Russell King596c4712013-12-10 11:08:01 +00001084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085 od->base = devm_ioremap_resource(&pdev->dev, res);
1086 if (IS_ERR(od->base))
1087 return PTR_ERR(od->base);
1088
Russell King1b416c42013-11-02 13:00:03 +00001089 od->plat = omap_get_plat_info();
1090 if (!od->plat)
1091 return -EPROBE_DEFER;
1092
Russell King596c4712013-12-10 11:08:01 +00001093 od->reg_map = od->plat->reg_map;
1094
Russell King7bedaa52012-04-13 12:10:24 +01001095 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
Russell King3a774ea2012-06-21 10:40:15 +01001096 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
Russell King7bedaa52012-04-13 12:10:24 +01001097 od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
1098 od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
1099 od->ddev.device_tx_status = omap_dma_tx_status;
1100 od->ddev.device_issue_pending = omap_dma_issue_pending;
1101 od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
Russell King3a774ea2012-06-21 10:40:15 +01001102 od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
Vinod Koul6c04cd42014-12-07 23:12:31 +05301103 od->ddev.device_config = omap_dma_slave_config;
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001104 od->ddev.device_pause = omap_dma_pause;
1105 od->ddev.device_resume = omap_dma_resume;
1106 od->ddev.device_terminate_all = omap_dma_terminate_all;
Maxime Ripard7d15b872014-11-17 14:42:49 +01001107 od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS;
1108 od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS;
1109 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1110 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Russell King7bedaa52012-04-13 12:10:24 +01001111 od->ddev.dev = &pdev->dev;
1112 INIT_LIST_HEAD(&od->ddev.channels);
1113 INIT_LIST_HEAD(&od->pending);
1114 spin_lock_init(&od->lock);
Russell King6ddeb6d2013-12-10 19:05:50 +00001115 spin_lock_init(&od->irq_lock);
Russell King7bedaa52012-04-13 12:10:24 +01001116
1117 tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
1118
1119 for (i = 0; i < 127; i++) {
1120 rc = omap_dma_chan_init(od, i);
1121 if (rc) {
1122 omap_dma_free(od);
1123 return rc;
1124 }
1125 }
1126
Russell King6ddeb6d2013-12-10 19:05:50 +00001127 irq = platform_get_irq(pdev, 1);
1128 if (irq <= 0) {
1129 dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
1130 od->legacy = true;
1131 } else {
1132 /* Disable all interrupts */
1133 od->irq_enable_mask = 0;
1134 omap_dma_glbl_write(od, IRQENABLE_L1, 0);
1135
1136 rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
1137 IRQF_SHARED, "omap-dma-engine", od);
1138 if (rc)
1139 return rc;
1140 }
1141
Russell King7bedaa52012-04-13 12:10:24 +01001142 rc = dma_async_device_register(&od->ddev);
1143 if (rc) {
1144 pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
1145 rc);
1146 omap_dma_free(od);
Jon Hunter8d306622013-02-26 12:27:24 -06001147 return rc;
1148 }
1149
1150 platform_set_drvdata(pdev, od);
1151
1152 if (pdev->dev.of_node) {
1153 omap_dma_info.dma_cap = od->ddev.cap_mask;
1154
1155 /* Device-tree DMA controller registration */
1156 rc = of_dma_controller_register(pdev->dev.of_node,
1157 of_dma_simple_xlate, &omap_dma_info);
1158 if (rc) {
1159 pr_warn("OMAP-DMA: failed to register DMA controller\n");
1160 dma_async_device_unregister(&od->ddev);
1161 omap_dma_free(od);
1162 }
Russell King7bedaa52012-04-13 12:10:24 +01001163 }
1164
1165 dev_info(&pdev->dev, "OMAP DMA engine driver\n");
1166
1167 return rc;
1168}
1169
1170static int omap_dma_remove(struct platform_device *pdev)
1171{
1172 struct omap_dmadev *od = platform_get_drvdata(pdev);
1173
Jon Hunter8d306622013-02-26 12:27:24 -06001174 if (pdev->dev.of_node)
1175 of_dma_controller_free(pdev->dev.of_node);
1176
Russell King7bedaa52012-04-13 12:10:24 +01001177 dma_async_device_unregister(&od->ddev);
Russell King6ddeb6d2013-12-10 19:05:50 +00001178
1179 if (!od->legacy) {
1180 /* Disable all interrupts */
1181 omap_dma_glbl_write(od, IRQENABLE_L0, 0);
1182 }
1183
Russell King7bedaa52012-04-13 12:10:24 +01001184 omap_dma_free(od);
1185
1186 return 0;
1187}
1188
Jon Hunter8d306622013-02-26 12:27:24 -06001189static const struct of_device_id omap_dma_match[] = {
1190 { .compatible = "ti,omap2420-sdma", },
1191 { .compatible = "ti,omap2430-sdma", },
1192 { .compatible = "ti,omap3430-sdma", },
1193 { .compatible = "ti,omap3630-sdma", },
1194 { .compatible = "ti,omap4430-sdma", },
1195 {},
1196};
1197MODULE_DEVICE_TABLE(of, omap_dma_match);
1198
Russell King7bedaa52012-04-13 12:10:24 +01001199static struct platform_driver omap_dma_driver = {
1200 .probe = omap_dma_probe,
1201 .remove = omap_dma_remove,
1202 .driver = {
1203 .name = "omap-dma-engine",
Jon Hunter8d306622013-02-26 12:27:24 -06001204 .of_match_table = of_match_ptr(omap_dma_match),
Russell King7bedaa52012-04-13 12:10:24 +01001205 },
1206};
1207
1208bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
1209{
1210 if (chan->device->dev->driver == &omap_dma_driver.driver) {
1211 struct omap_chan *c = to_omap_dma_chan(chan);
1212 unsigned req = *(unsigned *)param;
1213
1214 return req == c->dma_sig;
1215 }
1216 return false;
1217}
1218EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
1219
Russell King7bedaa52012-04-13 12:10:24 +01001220static int omap_dma_init(void)
1221{
Tony Lindgrenbe1f9482013-01-11 11:24:19 -08001222 return platform_driver_register(&omap_dma_driver);
Russell King7bedaa52012-04-13 12:10:24 +01001223}
1224subsys_initcall(omap_dma_init);
1225
1226static void __exit omap_dma_exit(void)
1227{
Russell King7bedaa52012-04-13 12:10:24 +01001228 platform_driver_unregister(&omap_dma_driver);
1229}
1230module_exit(omap_dma_exit);
1231
1232MODULE_AUTHOR("Russell King");
1233MODULE_LICENSE("GPL");