R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 10 | #include "omap5.dtsi" |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 13 | |
| 14 | / { |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 15 | model = "TI OMAP5 uEVM board"; |
| 16 | compatible = "ti,omap5-uevm", "ti,omap5"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 17 | |
| 18 | memory { |
| 19 | device_type = "memory"; |
Santosh Shilimkar | 03178c6 | 2013-01-18 11:43:16 +0530 | [diff] [blame] | 20 | reg = <0x80000000 0x7F000000>; /* 2032 MB */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 21 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 22 | |
| 23 | vmmcsd_fixed: fixedregulator-mmcsd { |
| 24 | compatible = "regulator-fixed"; |
| 25 | regulator-name = "vmmcsd_fixed"; |
| 26 | regulator-min-microvolt = <3000000>; |
| 27 | regulator-max-microvolt = <3000000>; |
| 28 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 29 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 30 | /* HS USB Port 2 RESET */ |
| 31 | hsusb2_reset: hsusb2_reset_reg { |
| 32 | compatible = "regulator-fixed"; |
| 33 | regulator-name = "hsusb2_reset"; |
| 34 | regulator-min-microvolt = <3300000>; |
| 35 | regulator-max-microvolt = <3300000>; |
| 36 | gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ |
| 37 | startup-delay-us = <70000>; |
| 38 | enable-active-high; |
| 39 | }; |
| 40 | |
| 41 | /* HS USB Host PHY on PORT 2 */ |
| 42 | hsusb2_phy: hsusb2_phy { |
| 43 | compatible = "usb-nop-xceiv"; |
| 44 | reset-supply = <&hsusb2_reset>; |
| 45 | }; |
| 46 | |
| 47 | /* HS USB Port 3 RESET */ |
| 48 | hsusb3_reset: hsusb3_reset_reg { |
| 49 | compatible = "regulator-fixed"; |
| 50 | regulator-name = "hsusb3_reset"; |
| 51 | regulator-min-microvolt = <3300000>; |
| 52 | regulator-max-microvolt = <3300000>; |
| 53 | gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ |
| 54 | startup-delay-us = <70000>; |
| 55 | enable-active-high; |
| 56 | }; |
| 57 | |
| 58 | /* HS USB Host PHY on PORT 3 */ |
| 59 | hsusb3_phy: hsusb3_phy { |
| 60 | compatible = "usb-nop-xceiv"; |
| 61 | reset-supply = <&hsusb3_reset>; |
| 62 | }; |
| 63 | |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 64 | leds { |
| 65 | compatible = "gpio-leds"; |
| 66 | led@1 { |
| 67 | label = "omap5:blue:usr1"; |
| 68 | gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ |
| 69 | linux,default-trigger = "heartbeat"; |
| 70 | default-state = "off"; |
| 71 | }; |
| 72 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 73 | }; |
| 74 | |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 75 | &omap5_pmx_core { |
| 76 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = < |
| 78 | &twl6040_pins |
| 79 | &mcpdm_pins |
| 80 | &dmic_pins |
| 81 | &mcbsp1_pins |
| 82 | &mcbsp2_pins |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 83 | &usbhost_pins |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 84 | &led_gpio_pins |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 85 | >; |
| 86 | |
| 87 | twl6040_pins: pinmux_twl6040_pins { |
| 88 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 89 | 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 90 | >; |
| 91 | }; |
| 92 | |
| 93 | mcpdm_pins: pinmux_mcpdm_pins { |
| 94 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 95 | 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 96 | 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ |
| 97 | 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ |
| 98 | 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ |
| 99 | 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 100 | >; |
| 101 | }; |
| 102 | |
| 103 | dmic_pins: pinmux_dmic_pins { |
| 104 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 105 | 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ |
| 106 | 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ |
| 107 | 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ |
| 108 | 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 109 | >; |
| 110 | }; |
| 111 | |
| 112 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 113 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 114 | 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ |
| 115 | 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ |
| 116 | 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ |
| 117 | 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 118 | >; |
| 119 | }; |
| 120 | |
| 121 | mcbsp2_pins: pinmux_mcbsp2_pins { |
| 122 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 123 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ |
| 124 | 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ |
| 125 | 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ |
| 126 | 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 127 | >; |
| 128 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 129 | |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 130 | i2c1_pins: pinmux_i2c1_pins { |
| 131 | pinctrl-single,pins = < |
| 132 | 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 133 | 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 134 | >; |
| 135 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 136 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 137 | i2c5_pins: pinmux_i2c5_pins { |
| 138 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 139 | 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ |
| 140 | 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 141 | >; |
| 142 | }; |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 143 | |
| 144 | mcspi2_pins: pinmux_mcspi2_pins { |
| 145 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 146 | 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ |
| 147 | 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ |
| 148 | 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ |
| 149 | 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 150 | >; |
| 151 | }; |
| 152 | |
| 153 | mcspi3_pins: pinmux_mcspi3_pins { |
| 154 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 155 | 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ |
| 156 | 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ |
| 157 | 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ |
| 158 | 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 159 | >; |
| 160 | }; |
| 161 | |
| 162 | mcspi4_pins: pinmux_mcspi4_pins { |
| 163 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 164 | 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ |
| 165 | 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ |
| 166 | 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ |
| 167 | 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 168 | >; |
| 169 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 170 | |
| 171 | usbhost_pins: pinmux_usbhost_pins { |
| 172 | pinctrl-single,pins = < |
| 173 | 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ |
| 174 | 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ |
| 175 | |
| 176 | 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ |
| 177 | 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ |
| 178 | |
| 179 | 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ |
| 180 | 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ |
| 181 | >; |
| 182 | }; |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 183 | |
| 184 | led_gpio_pins: pinmux_led_gpio_pins { |
| 185 | pinctrl-single,pins = < |
| 186 | 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ |
| 187 | >; |
| 188 | }; |
Sourav Poddar | ed22fee | 2013-06-07 18:52:50 +0530 | [diff] [blame] | 189 | |
| 190 | uart1_pins: pinmux_uart1_pins { |
| 191 | pinctrl-single,pins = < |
| 192 | 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ |
| 193 | 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ |
| 194 | 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ |
| 195 | 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ |
| 196 | >; |
| 197 | }; |
| 198 | |
| 199 | uart3_pins: pinmux_uart3_pins { |
| 200 | pinctrl-single,pins = < |
| 201 | 0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ |
| 202 | 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ |
| 203 | >; |
| 204 | }; |
| 205 | |
| 206 | uart5_pins: pinmux_uart5_pins { |
| 207 | pinctrl-single,pins = < |
| 208 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ |
| 209 | 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ |
| 210 | 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ |
| 211 | 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ |
| 212 | >; |
| 213 | }; |
| 214 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 215 | }; |
| 216 | |
| 217 | &omap5_pmx_wkup { |
| 218 | pinctrl-names = "default"; |
| 219 | pinctrl-0 = < |
| 220 | &usbhost_wkup_pins |
| 221 | >; |
| 222 | |
| 223 | usbhost_wkup_pins: pinmux_usbhost_wkup_pins { |
| 224 | pinctrl-single,pins = < |
| 225 | 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ |
| 226 | >; |
| 227 | }; |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 228 | }; |
| 229 | |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 230 | &mmc1 { |
| 231 | vmmc-supply = <&vmmcsd_fixed>; |
| 232 | bus-width = <4>; |
| 233 | }; |
| 234 | |
| 235 | &mmc2 { |
| 236 | vmmc-supply = <&vmmcsd_fixed>; |
| 237 | bus-width = <8>; |
| 238 | ti,non-removable; |
| 239 | }; |
| 240 | |
| 241 | &mmc3 { |
| 242 | bus-width = <4>; |
| 243 | ti,non-removable; |
| 244 | }; |
| 245 | |
| 246 | &mmc4 { |
| 247 | status = "disabled"; |
| 248 | }; |
| 249 | |
| 250 | &mmc5 { |
| 251 | status = "disabled"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 252 | }; |
Sourav Poddar | 08f3e21 | 2012-07-25 11:02:43 +0530 | [diff] [blame] | 253 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 254 | &i2c1 { |
| 255 | pinctrl-names = "default"; |
| 256 | pinctrl-0 = <&i2c1_pins>; |
| 257 | |
| 258 | clock-frequency = <400000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 259 | |
| 260 | palmas: palmas@48 { |
| 261 | compatible = "ti,palmas"; |
| 262 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
| 263 | interrupt-parent = <&gic>; |
| 264 | reg = <0x48>; |
| 265 | interrupt-controller; |
| 266 | #interrupt-cells = <2>; |
| 267 | |
| 268 | palmas_pmic { |
| 269 | compatible = "ti,palmas-pmic"; |
| 270 | interrupt-parent = <&palmas>; |
| 271 | interrupts = <14 IRQ_TYPE_NONE>; |
| 272 | interrupt-name = "short-irq"; |
| 273 | |
| 274 | ti,ldo6-vibrator; |
| 275 | |
| 276 | regulators { |
| 277 | smps123_reg: smps123 { |
| 278 | regulator-name = "smps123"; |
| 279 | regulator-min-microvolt = < 600000>; |
| 280 | regulator-max-microvolt = <1500000>; |
| 281 | regulator-always-on; |
| 282 | regulator-boot-on; |
| 283 | }; |
| 284 | |
| 285 | smps45_reg: smps45 { |
| 286 | regulator-name = "smps45"; |
| 287 | regulator-min-microvolt = < 600000>; |
| 288 | regulator-max-microvolt = <1310000>; |
| 289 | regulator-always-on; |
| 290 | regulator-boot-on; |
| 291 | }; |
| 292 | |
| 293 | smps6_reg: smps6 { |
| 294 | regulator-name = "smps6"; |
| 295 | regulator-min-microvolt = <1200000>; |
| 296 | regulator-max-microvolt = <1200000>; |
| 297 | regulator-always-on; |
| 298 | regulator-boot-on; |
| 299 | }; |
| 300 | |
| 301 | smps7_reg: smps7 { |
| 302 | regulator-name = "smps7"; |
| 303 | regulator-min-microvolt = <1800000>; |
| 304 | regulator-max-microvolt = <1800000>; |
| 305 | regulator-always-on; |
| 306 | regulator-boot-on; |
| 307 | }; |
| 308 | |
| 309 | smps8_reg: smps8 { |
| 310 | regulator-name = "smps8"; |
| 311 | regulator-min-microvolt = < 600000>; |
| 312 | regulator-max-microvolt = <1310000>; |
| 313 | regulator-always-on; |
| 314 | regulator-boot-on; |
| 315 | }; |
| 316 | |
| 317 | smps9_reg: smps9 { |
| 318 | regulator-name = "smps9"; |
| 319 | regulator-min-microvolt = <2100000>; |
| 320 | regulator-max-microvolt = <2100000>; |
| 321 | regulator-always-on; |
| 322 | regulator-boot-on; |
| 323 | ti,smps-range = <0x80>; |
| 324 | }; |
| 325 | |
| 326 | smps10_reg: smps10 { |
| 327 | regulator-name = "smps10"; |
| 328 | regulator-min-microvolt = <5000000>; |
| 329 | regulator-max-microvolt = <5000000>; |
| 330 | regulator-always-on; |
| 331 | regulator-boot-on; |
| 332 | }; |
| 333 | |
| 334 | ldo1_reg: ldo1 { |
| 335 | regulator-name = "ldo1"; |
| 336 | regulator-min-microvolt = <2800000>; |
| 337 | regulator-max-microvolt = <2800000>; |
| 338 | regulator-always-on; |
| 339 | regulator-boot-on; |
| 340 | }; |
| 341 | |
| 342 | ldo2_reg: ldo2 { |
| 343 | regulator-name = "ldo2"; |
| 344 | regulator-min-microvolt = <2900000>; |
| 345 | regulator-max-microvolt = <2900000>; |
| 346 | regulator-always-on; |
| 347 | regulator-boot-on; |
| 348 | }; |
| 349 | |
| 350 | ldo3_reg: ldo3 { |
| 351 | regulator-name = "ldo3"; |
| 352 | regulator-min-microvolt = <3000000>; |
| 353 | regulator-max-microvolt = <3000000>; |
| 354 | regulator-always-on; |
| 355 | regulator-boot-on; |
| 356 | }; |
| 357 | |
| 358 | ldo4_reg: ldo4 { |
| 359 | regulator-name = "ldo4"; |
| 360 | regulator-min-microvolt = <2200000>; |
| 361 | regulator-max-microvolt = <2200000>; |
| 362 | regulator-always-on; |
| 363 | regulator-boot-on; |
| 364 | }; |
| 365 | |
| 366 | ldo5_reg: ldo5 { |
| 367 | regulator-name = "ldo5"; |
| 368 | regulator-min-microvolt = <1800000>; |
| 369 | regulator-max-microvolt = <1800000>; |
| 370 | regulator-always-on; |
| 371 | regulator-boot-on; |
| 372 | }; |
| 373 | |
| 374 | ldo6_reg: ldo6 { |
| 375 | regulator-name = "ldo6"; |
| 376 | regulator-min-microvolt = <1500000>; |
| 377 | regulator-max-microvolt = <1500000>; |
| 378 | regulator-always-on; |
| 379 | regulator-boot-on; |
| 380 | }; |
| 381 | |
| 382 | ldo7_reg: ldo7 { |
| 383 | regulator-name = "ldo7"; |
| 384 | regulator-min-microvolt = <1500000>; |
| 385 | regulator-max-microvolt = <1500000>; |
| 386 | regulator-always-on; |
| 387 | regulator-boot-on; |
| 388 | }; |
| 389 | |
| 390 | ldo8_reg: ldo8 { |
| 391 | regulator-name = "ldo8"; |
| 392 | regulator-min-microvolt = <1500000>; |
| 393 | regulator-max-microvolt = <1500000>; |
| 394 | regulator-always-on; |
| 395 | regulator-boot-on; |
| 396 | }; |
| 397 | |
| 398 | ldo9_reg: ldo9 { |
| 399 | regulator-name = "ldo9"; |
| 400 | regulator-min-microvolt = <1800000>; |
| 401 | regulator-max-microvolt = <3300000>; |
| 402 | regulator-always-on; |
| 403 | regulator-boot-on; |
| 404 | }; |
| 405 | |
| 406 | ldoln_reg: ldoln { |
| 407 | regulator-name = "ldoln"; |
| 408 | regulator-min-microvolt = <1800000>; |
| 409 | regulator-max-microvolt = <1800000>; |
| 410 | regulator-always-on; |
| 411 | regulator-boot-on; |
| 412 | }; |
| 413 | |
| 414 | ldousb_reg: ldousb { |
| 415 | regulator-name = "ldousb"; |
| 416 | regulator-min-microvolt = <3250000>; |
| 417 | regulator-max-microvolt = <3250000>; |
| 418 | regulator-always-on; |
| 419 | regulator-boot-on; |
| 420 | }; |
| 421 | }; |
| 422 | }; |
| 423 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 424 | }; |
| 425 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 426 | &i2c5 { |
| 427 | pinctrl-names = "default"; |
| 428 | pinctrl-0 = <&i2c5_pins>; |
| 429 | |
| 430 | clock-frequency = <400000>; |
| 431 | }; |
| 432 | |
Peter Ujfalusi | 42601d5 | 2012-10-04 14:57:24 +0300 | [diff] [blame] | 433 | &mcbsp3 { |
| 434 | status = "disabled"; |
| 435 | }; |
Lokesh Vutla | 4d2750f | 2012-11-05 18:22:52 +0530 | [diff] [blame] | 436 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 437 | &usbhshost { |
| 438 | port2-mode = "ehci-hsic"; |
| 439 | port3-mode = "ehci-hsic"; |
| 440 | }; |
| 441 | |
| 442 | &usbhsehci { |
| 443 | phys = <0 &hsusb2_phy &hsusb3_phy>; |
| 444 | }; |
| 445 | |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 446 | &mcspi1 { |
| 447 | |
| 448 | }; |
| 449 | |
| 450 | &mcspi2 { |
| 451 | pinctrl-names = "default"; |
| 452 | pinctrl-0 = <&mcspi2_pins>; |
| 453 | }; |
| 454 | |
| 455 | &mcspi3 { |
| 456 | pinctrl-names = "default"; |
| 457 | pinctrl-0 = <&mcspi3_pins>; |
| 458 | }; |
| 459 | |
| 460 | &mcspi4 { |
| 461 | pinctrl-names = "default"; |
| 462 | pinctrl-0 = <&mcspi4_pins>; |
| 463 | }; |
Sourav Poddar | ed22fee | 2013-06-07 18:52:50 +0530 | [diff] [blame] | 464 | |
| 465 | &uart1 { |
| 466 | pinctrl-names = "default"; |
| 467 | pinctrl-0 = <&uart1_pins>; |
| 468 | }; |
| 469 | |
| 470 | &uart3 { |
| 471 | pinctrl-names = "default"; |
| 472 | pinctrl-0 = <&uart3_pins>; |
| 473 | }; |
| 474 | |
| 475 | &uart5 { |
| 476 | pinctrl-names = "default"; |
| 477 | pinctrl-0 = <&uart5_pins>; |
| 478 | }; |