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Fabio Estevam241f76b2018-05-07 15:23:40 -03001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
Stefan Agnera67970a2016-06-26 01:47:53 -07005
6#include "imx7s.dtsi"
Andrey Smirnova816d572017-05-15 07:53:04 -07007#include <dt-bindings/reset/imx7-reset.h>
Stefan Agnera67970a2016-06-26 01:47:53 -07008
9/ {
10 cpus {
Stefan Agnerf5bd51b2016-08-11 17:11:06 -070011 cpu0: cpu@0 {
Stefan Agner1c4e2a12016-08-11 17:11:07 -070012 clock-frequency = <996000000>;
Anson Huangbce48c92018-05-16 12:48:17 +080013 operating-points-v2 = <&cpu0_opp_table>;
Stefan Agnerf5bd51b2016-08-11 17:11:06 -070014 };
15
Stefan Agnera67970a2016-06-26 01:47:53 -070016 cpu1: cpu@1 {
17 compatible = "arm,cortex-a7";
18 device_type = "cpu";
19 reg = <1>;
Stefan Agner1c4e2a12016-08-11 17:11:07 -070020 clock-frequency = <996000000>;
Anson Huangbce48c92018-05-16 12:48:17 +080021 operating-points-v2 = <&cpu0_opp_table>;
22 };
23 };
24
25 cpu0_opp_table: opp-table {
26 compatible = "operating-points-v2";
27 opp-shared;
28
29 opp-792000000 {
30 opp-hz = /bits/ 64 <792000000>;
31 opp-microvolt = <975000>;
32 clock-latency-ns = <150000>;
33 };
34
35 opp-996000000 {
36 opp-hz = /bits/ 64 <996000000>;
37 opp-microvolt = <1075000>;
38 clock-latency-ns = <150000>;
39 opp-suspend;
Stefan Agnera67970a2016-06-26 01:47:53 -070040 };
41 };
42
Fabio Estevamdd55cb42017-11-29 16:54:39 -020043 usbphynop2: usbphynop2 {
44 compatible = "usb-nop-xceiv";
45 clocks = <&clks IMX7D_USB_PHY2_CLK>;
46 clock-names = "main_clk";
47 #phy-cells = <0>;
48 };
49
Stefan Agner974a3ab2016-07-25 23:42:35 -070050 soc {
51 etm@3007d000 {
52 compatible = "arm,coresight-etm3x", "arm,primecell";
53 reg = <0x3007d000 0x1000>;
Stefan Agnera67970a2016-06-26 01:47:53 -070054
Stefan Agner974a3ab2016-07-25 23:42:35 -070055 /*
56 * System will hang if added nosmp in kernel command line
57 * without arm,primecell-periphid because amba bus try to
58 * read id and core1 power off at this time.
59 */
60 arm,primecell-periphid = <0xbb956>;
61 cpu = <&cpu1>;
62 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
63 clock-names = "apb_pclk";
Stefan Agnera67970a2016-06-26 01:47:53 -070064
Stefan Agner974a3ab2016-07-25 23:42:35 -070065 port {
66 etm1_out_port: endpoint {
67 remote-endpoint = <&ca_funnel_in_port1>;
68 };
Stefan Agnera67970a2016-06-26 01:47:53 -070069 };
70 };
71 };
72};
73
74&aips3 {
75 usbotg2: usb@30b20000 {
76 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
77 reg = <0x30b20000 0x200>;
78 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&clks IMX7D_USB_CTRL_CLK>;
80 fsl,usbphy = <&usbphynop2>;
81 fsl,usbmisc = <&usbmisc2 0>;
82 phy-clkgate-delay-us = <400>;
83 status = "disabled";
84 };
85
86 usbmisc2: usbmisc@30b20200 {
87 #index-cells = <1>;
88 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
89 reg = <0x30b20200 0x200>;
90 };
91
Stefan Agnera67970a2016-06-26 01:47:53 -070092 fec2: ethernet@30bf0000 {
93 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
94 reg = <0x30bf0000 0x10000>;
Troy Kiskye94a2302017-11-03 10:29:58 -070095 interrupt-names = "int0", "int1", "int2", "pps";
96 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
Stefan Agnera67970a2016-06-26 01:47:53 -070098 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
Troy Kiskye94a2302017-11-03 10:29:58 -070099 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
Anson Huang64f929d2018-05-18 09:01:06 +0800100 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
Stefan Agnera67970a2016-06-26 01:47:53 -0700101 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
102 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
103 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
104 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
105 clock-names = "ipg", "ahb", "ptp",
106 "enet_clk_ref", "enet_out";
107 fsl,num-tx-queues=<3>;
108 fsl,num-rx-queues=<3>;
109 status = "disabled";
110 };
Andrey Smirnova816d572017-05-15 07:53:04 -0700111
Fabio Estevam2290ad12017-11-29 16:54:40 -0200112 pcie: pcie@33800000 {
Andrey Smirnova816d572017-05-15 07:53:04 -0700113 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
114 reg = <0x33800000 0x4000>,
115 <0x4ff00000 0x80000>;
116 reg-names = "dbi", "config";
117 #address-cells = <3>;
118 #size-cells = <2>;
119 device_type = "pci";
Fabio Estevam2290ad12017-11-29 16:54:40 -0200120 bus-range = <0x00 0xff>;
Andrey Smirnova816d572017-05-15 07:53:04 -0700121 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
122 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
123 num-lanes = <1>;
124 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-names = "msi";
126 #interrupt-cells = <1>;
127 interrupt-map-mask = <0 0 0 0x7>;
Andrey Smirnov1c86c9d2017-10-09 11:43:44 -0700128 interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
129 <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
130 <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
131 <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Andrey Smirnova816d572017-05-15 07:53:04 -0700132 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
133 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
134 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
135 clock-names = "pcie", "pcie_bus", "pcie_phy";
136 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
137 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
138 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
139 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
140
141 fsl,max-link-speed = <2>;
142 power-domains = <&pgc_pcie_phy>;
143 resets = <&src IMX7_RESET_PCIEPHY>,
144 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
145 reset-names = "pciephy", "apps";
146 status = "disabled";
147 };
Stefan Agnera67970a2016-06-26 01:47:53 -0700148};
149
150&ca_funnel_ports {
151 port@1 {
152 reg = <1>;
153 ca_funnel_in_port1: endpoint {
154 slave-mode;
155 remote-endpoint = <&etm1_out_port>;
156 };
157 };
158};