blob: e11fc8f391922a1b713630b891730301395b08ff [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
Nick Kossifidisc6e387a2008-08-29 22:45:39 +030021/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
Jiri Slabyfa1c1142007-08-12 17:33:16 +020024#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
Bruno Randolfeef39be2010-11-16 10:58:43 +090028#include <linux/average.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020029#include <net/mac80211.h>
30
Nick Kossifidisc6e387a2008-08-29 22:45:39 +030031/* RX/TX descriptor hw structs
32 * TODO: Driver part should only see sw structs */
33#include "desc.h"
34
35/* EEPROM structs/offsets
36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
37 * and clean up common bits, then introduce set/get functions in eeprom.c */
38#include "eeprom.h"
Luis R. Rodriguezdb719712009-09-10 11:20:57 -070039#include "../ath.h"
Jiri Slabyfa1c1142007-08-12 17:33:16 +020040
41/* PCI IDs */
42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
70
71/****************************\
72 GENERIC DRIVER DEFINITIONS
73\****************************/
74
75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
76
77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
78 printk(_level "ath5k %s: " _fmt, \
79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
80 ##__VA_ARGS__)
81
82#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
83 if (net_ratelimit()) \
84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
85 } while (0)
86
87#define ATH5K_INFO(_sc, _fmt, ...) \
88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
89
90#define ATH5K_WARN(_sc, _fmt, ...) \
91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
92
93#define ATH5K_ERR(_sc, _fmt, ...) \
94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
95
96/*
Nick Kossifidisc6e387a2008-08-29 22:45:39 +030097 * AR5K REGISTER ACCESS
98 */
99
100/* Some macros to read/write fields */
101
102/* First shift, then mask */
103#define AR5K_REG_SM(_val, _flags) \
104 (((_val) << _flags##_S) & (_flags))
105
106/* First mask, then shift */
107#define AR5K_REG_MS(_val, _flags) \
108 (((_val) & (_flags)) >> _flags##_S)
109
110/* Some registers can hold multiple values of interest. For this
111 * reason when we want to write to these registers we must first
112 * retrieve the values which we do not want to clear (lets call this
113 * old_data) and then set the register with this and our new_value:
114 * ( old_data | new_value) */
115#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
117 (((_val) << _flags##_S) & (_flags)), _reg)
118
119#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
121 (_mask)) | (_flags), _reg)
122
123#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
125
126#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
128
129/* Access to PHY registers */
130#define AR5K_PHY_READ(ah, _reg) \
131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
132
133#define AR5K_PHY_WRITE(ah, _reg, _val) \
134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
135
136/* Access QCU registers per queue */
137#define AR5K_REG_READ_Q(ah, _reg, _queue) \
138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
139
140#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
141 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
142
143#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
144 _reg |= 1 << _queue; \
145} while (0)
146
147#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
148 _reg &= ~(1 << _queue); \
149} while (0)
150
151/* Used while writing initvals */
152#define AR5K_REG_WAIT(_i) do { \
153 if (_i % 64) \
154 udelay(1); \
155} while (0)
156
157/* Register dumps are done per operation mode */
158#define AR5K_INI_RFGAIN_5GHZ 0
159#define AR5K_INI_RFGAIN_2GHZ 1
160
161/* TODO: Clean this up */
162#define AR5K_INI_VAL_11A 0
163#define AR5K_INI_VAL_11A_TURBO 1
164#define AR5K_INI_VAL_11B 2
165#define AR5K_INI_VAL_11G 3
166#define AR5K_INI_VAL_11G_TURBO 4
167#define AR5K_INI_VAL_XR 0
168#define AR5K_INI_VAL_MAX 5
169
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300170/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200171 * Some tuneable values (these should be changeable by the user)
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300172 * TODO: Make use of them and add more options OR use debug/configfs
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200173 */
174#define AR5K_TUNE_DMA_BEACON_RESP 2
175#define AR5K_TUNE_SW_BEACON_RESP 10
176#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
177#define AR5K_TUNE_RADAR_ALERT false
178#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
Nick Kossifidisb6127982010-08-15 13:03:11 -0400179#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200180#define AR5K_TUNE_REGISTER_TIMEOUT 20000
181/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
182 * be the max value. */
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300183#define AR5K_TUNE_RSSI_THRES 129
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200184/* This must be set when setting the RSSI threshold otherwise it can
185 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
186 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
187 * track of it. Max value depends on harware. For AR5210 this is just 7.
188 * For AR5211+ this seems to be up to 255. */
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300189#define AR5K_TUNE_BMISS_THRES 7
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200190#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
191#define AR5K_TUNE_BEACON_INTERVAL 100
192#define AR5K_TUNE_AIFS 2
193#define AR5K_TUNE_AIFS_11B 2
194#define AR5K_TUNE_AIFS_XR 0
195#define AR5K_TUNE_CWMIN 15
196#define AR5K_TUNE_CWMIN_11B 31
197#define AR5K_TUNE_CWMIN_XR 3
198#define AR5K_TUNE_CWMAX 1023
199#define AR5K_TUNE_CWMAX_11B 1023
200#define AR5K_TUNE_CWMAX_XR 7
201#define AR5K_TUNE_NOISE_FLOOR -72
Bob Copelande5e26472009-10-14 14:16:30 -0400202#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200203#define AR5K_TUNE_MAX_TXPOWER 63
204#define AR5K_TUNE_DEFAULT_TXPOWER 25
205#define AR5K_TUNE_TPC_TXPOWER false
Bruno Randolf1063b172010-03-25 14:49:03 +0900206#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */
Bruno Randolf2111ac02010-04-02 18:44:08 +0900207#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
Bruno Randolfafe86282010-05-19 10:31:10 +0900208#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200209
Bruno Randolf4edd7612010-09-17 11:36:56 +0900210#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
211
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300212#define AR5K_INIT_CARR_SENSE_EN 1
213
214/*Swap RX/TX Descriptor for big endian archs*/
215#if defined(__BIG_ENDIAN)
216#define AR5K_INIT_CFG ( \
217 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
218)
219#else
220#define AR5K_INIT_CFG 0x00000000
221#endif
222
223/* Initial values */
Nick Kossifidise8f055f2009-02-09 06:12:58 +0200224#define AR5K_INIT_CYCRSSI_THR1 2
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300225#define AR5K_INIT_TX_LATENCY 502
226#define AR5K_INIT_USEC 39
227#define AR5K_INIT_USEC_TURBO 79
228#define AR5K_INIT_USEC_32 31
Nick Kossifidis3017fca2010-11-23 21:09:11 +0200229#define AR5K_INIT_SLOT_TIME_CLOCK 396
230#define AR5K_INIT_SLOT_TIME_TURBO_CLOCK 480
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300231#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
232#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
233#define AR5K_INIT_PROG_IFS 920
234#define AR5K_INIT_PROG_IFS_TURBO 960
235#define AR5K_INIT_EIFS 3440
236#define AR5K_INIT_EIFS_TURBO 6880
Nick Kossifidis3017fca2010-11-23 21:09:11 +0200237#define AR5K_INIT_SIFS_CLOCK 560
238#define AR5K_INIT_SIFS_TURBO_CLOCK 480
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300239#define AR5K_INIT_SH_RETRY 10
240#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
241#define AR5K_INIT_SSH_RETRY 32
242#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
243#define AR5K_INIT_TX_RETRY 10
244
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300245#define AR5K_INIT_PROTO_TIME_CNTRL ( \
246 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
247 (AR5K_INIT_PROG_IFS) \
248)
249#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
250 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
251 (AR5K_INIT_PROG_IFS_TURBO) \
252)
253
Nick Kossifidis3017fca2010-11-23 21:09:11 +0200254/* Slot time */
255#define AR5K_INIT_SLOT_TIME_TURBO 6
256#define AR5K_INIT_SLOT_TIME_DEFAULT 9
257#define AR5K_INIT_SLOT_TIME_HALF_RATE 13
258#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
259#define AR5K_INIT_SLOT_TIME_B 20
260#define AR5K_SLOT_TIME_MAX 0xffff
261
262/* SIFS */
263#define AR5K_INIT_SIFS_TURBO 6
264/* XXX: 8 from initvals 10 from standard */
265#define AR5K_INIT_SIFS_DEFAULT_BG 8
266#define AR5K_INIT_SIFS_DEFAULT_A 16
267#define AR5K_INIT_SIFS_HALF_RATE 32
268#define AR5K_INIT_SIFS_QUARTER_RATE 64
269
Nick Kossifidisc2975602010-11-23 21:00:37 +0200270/* Rx latency for 5 and 10MHz operation (max ?) */
271#define AR5K_INIT_RX_LAT_MAX 63
272/* Tx latencies from initvals (5212 only but no problem
273 * because we only tweak them on 5212) */
274#define AR5K_INIT_TX_LAT_A 54
275#define AR5K_INIT_TX_LAT_BG 384
276/* Tx latency for 40MHz (turbo) operation (min ?) */
277#define AR5K_INIT_TX_LAT_MIN 32
Nick Kossifidisb4050862010-11-23 21:04:43 +0200278/* Default Tx/Rx latencies (same for 5211)*/
279#define AR5K_INIT_TX_LATENCY_5210 54
280#define AR5K_INIT_RX_LATENCY_5210 29
Nick Kossifidisc2975602010-11-23 21:00:37 +0200281
282/* Tx frame to Tx data start delay */
283#define AR5K_INIT_TXF2TXD_START_DEFAULT 14
284#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
285#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
286
Nick Kossifidisb4050862010-11-23 21:04:43 +0200287/* We need to increase PHY switch and agc settling time
288 * on turbo mode */
289#define AR5K_SWITCH_SETTLING 5760
290#define AR5K_SWITCH_SETTLING_TURBO 7168
291
292#define AR5K_AGC_SETTLING 28
293/* 38 on 5210 but shouldn't matter */
294#define AR5K_AGC_SETTLING_TURBO 37
Nick Kossifidisc2975602010-11-23 21:00:37 +0200295
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200296
297/* GENERIC CHIPSET DEFINITIONS */
298
299/* MAC Chips */
300enum ath5k_version {
301 AR5K_AR5210 = 0,
302 AR5K_AR5211 = 1,
303 AR5K_AR5212 = 2,
304};
305
306/* PHY Chips */
307enum ath5k_radio {
308 AR5K_RF5110 = 0,
309 AR5K_RF5111 = 1,
310 AR5K_RF5112 = 2,
Nick Kossifidis8daeef92008-02-28 14:40:00 -0500311 AR5K_RF2413 = 3,
312 AR5K_RF5413 = 4,
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300313 AR5K_RF2316 = 5,
314 AR5K_RF2317 = 6,
315 AR5K_RF2425 = 7,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200316};
317
318/*
319 * Common silicon revision/version values
320 */
321
322enum ath5k_srev_type {
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300323 AR5K_VERSION_MAC,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200324 AR5K_VERSION_RAD,
325};
326
327struct ath5k_srev_name {
328 const char *sr_name;
329 enum ath5k_srev_type sr_type;
330 u_int sr_val;
331};
332
333#define AR5K_SREV_UNKNOWN 0xffff
334
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300335#define AR5K_SREV_AR5210 0x00 /* Crete */
336#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
337#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
338#define AR5K_SREV_AR5311B 0x30 /* Spirit */
339#define AR5K_SREV_AR5211 0x40 /* Oahu */
340#define AR5K_SREV_AR5212 0x50 /* Venice */
Bob Copelandca5efbe2009-08-27 15:17:15 -0400341#define AR5K_SREV_AR5212_V4 0x54 /* ??? */
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300342#define AR5K_SREV_AR5213 0x55 /* ??? */
343#define AR5K_SREV_AR5213A 0x59 /* Hainan */
344#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
345#define AR5K_SREV_AR2414 0x70 /* Griffin */
346#define AR5K_SREV_AR5424 0x90 /* Condor */
347#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
348#define AR5K_SREV_AR5414 0xa0 /* Eagle */
Nick Kossifidise8f055f2009-02-09 06:12:58 +0200349#define AR5K_SREV_AR2415 0xb0 /* Talon */
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300350#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
351#define AR5K_SREV_AR5418 0xca /* PCI-E */
352#define AR5K_SREV_AR2425 0xe0 /* Swan */
353#define AR5K_SREV_AR2417 0xf0 /* Nala */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200354
355#define AR5K_SREV_RAD_5110 0x00
356#define AR5K_SREV_RAD_5111 0x10
357#define AR5K_SREV_RAD_5111A 0x15
358#define AR5K_SREV_RAD_2111 0x20
359#define AR5K_SREV_RAD_5112 0x30
360#define AR5K_SREV_RAD_5112A 0x35
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300361#define AR5K_SREV_RAD_5112B 0x36
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200362#define AR5K_SREV_RAD_2112 0x40
363#define AR5K_SREV_RAD_2112A 0x45
Nick Kossifidise5a4ad02008-07-20 06:34:39 +0300364#define AR5K_SREV_RAD_2112B 0x46
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300365#define AR5K_SREV_RAD_2413 0x50
366#define AR5K_SREV_RAD_5413 0x60
Nick Kossifidise8f055f2009-02-09 06:12:58 +0200367#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300368#define AR5K_SREV_RAD_2317 0x80
369#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
370#define AR5K_SREV_RAD_2425 0xa2
371#define AR5K_SREV_RAD_5133 0xc0
372
373#define AR5K_SREV_PHY_5211 0x30
374#define AR5K_SREV_PHY_5212 0x41
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200375#define AR5K_SREV_PHY_5212A 0x42
Nick Kossifidise8f055f2009-02-09 06:12:58 +0200376#define AR5K_SREV_PHY_5212B 0x43
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300377#define AR5K_SREV_PHY_2413 0x45
378#define AR5K_SREV_PHY_5413 0x61
379#define AR5K_SREV_PHY_2425 0x70
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200380
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200381/* TODO add support to mac80211 for vendor-specific rates and modes */
382
383/*
384 * Some of this information is based on Documentation from:
385 *
Justin P. Mattock631dd1a2010-10-18 11:03:14 +0200386 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200387 *
388 * Modulation for Atheros' eXtended Range - range enhancing extension that is
389 * supposed to double the distance an Atheros client device can keep a
390 * connection with an Atheros access point. This is achieved by increasing
391 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
392 * the 802.11 specifications demand. In addition, new (proprietary) data rates
393 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
394 *
395 * Please note that can you either use XR or TURBO but you cannot use both,
396 * they are exclusive.
397 *
398 */
399#define MODULATION_XR 0x00000200
400/*
401 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
402 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
403 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
404 * channels. To use this feature your Access Point must also suport it.
405 * There is also a distinction between "static" and "dynamic" turbo modes:
406 *
407 * - Static: is the dumb version: devices set to this mode stick to it until
408 * the mode is turned off.
409 * - Dynamic: is the intelligent version, the network decides itself if it
410 * is ok to use turbo. As soon as traffic is detected on adjacent channels
411 * (which would get used in turbo mode), or when a non-turbo station joins
412 * the network, turbo mode won't be used until the situation changes again.
413 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
414 * monitors the used radio band in order to decide whether turbo mode may
415 * be used or not.
416 *
417 * This article claims Super G sticks to bonding of channels 5 and 6 for
418 * USA:
419 *
420 * http://www.pcworld.com/article/id,113428-page,1/article.html
421 *
422 * The channel bonding seems to be driver specific though. In addition to
423 * deciding what channels will be used, these "Turbo" modes are accomplished
424 * by also enabling the following features:
425 *
426 * - Bursting: allows multiple frames to be sent at once, rather than pausing
427 * after each frame. Bursting is a standards-compliant feature that can be
428 * used with any Access Point.
429 * - Fast frames: increases the amount of information that can be sent per
430 * frame, also resulting in a reduction of transmission overhead. It is a
431 * proprietary feature that needs to be supported by the Access Point.
432 * - Compression: data frames are compressed in real time using a Lempel Ziv
433 * algorithm. This is done transparently. Once this feature is enabled,
434 * compression and decompression takes place inside the chipset, without
435 * putting additional load on the host CPU.
436 *
437 */
438#define MODULATION_TURBO 0x00000080
439
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500440enum ath5k_driver_mode {
441 AR5K_MODE_11A = 0,
442 AR5K_MODE_11A_TURBO = 1,
443 AR5K_MODE_11B = 2,
444 AR5K_MODE_11G = 3,
445 AR5K_MODE_11G_TURBO = 4,
446 AR5K_MODE_XR = 0,
447 AR5K_MODE_MAX = 5
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200448};
449
Nick Kossifidis2bed03e2009-04-30 15:55:49 -0400450enum ath5k_ant_mode {
451 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
452 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
453 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
454 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
455 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
456 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
457 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
458 AR5K_ANTMODE_MAX,
459};
460
Nick Kossifidisfa3d2fe2010-11-23 20:58:34 +0200461enum ath5k_bw_mode {
462 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */
463 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */
464 AR5K_BWMODE_10MHZ = 2, /* Half rate */
465 AR5K_BWMODE_40MHZ = 3 /* Turbo */
466};
Bruno Randolf19fd6e52008-03-05 18:35:23 +0900467
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200468/****************\
469 TX DEFINITIONS
470\****************/
471
472/*
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300473 * TX Status descriptor
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200474 */
475struct ath5k_tx_status {
476 u16 ts_seqnum;
477 u16 ts_tstamp;
478 u8 ts_status;
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200479 u8 ts_rate[4];
480 u8 ts_retry[4];
481 u8 ts_final_idx;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200482 s8 ts_rssi;
483 u8 ts_shortretry;
484 u8 ts_longretry;
485 u8 ts_virtcol;
486 u8 ts_antenna;
487};
488
489#define AR5K_TXSTAT_ALTRATE 0x80
490#define AR5K_TXERR_XRETRY 0x01
491#define AR5K_TXERR_FILT 0x02
492#define AR5K_TXERR_FIFO 0x04
493
494/**
495 * enum ath5k_tx_queue - Queue types used to classify tx queues.
496 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
497 * @AR5K_TX_QUEUE_DATA: A normal data queue
498 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
499 * @AR5K_TX_QUEUE_BEACON: The beacon queue
500 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
501 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
502 */
503enum ath5k_tx_queue {
504 AR5K_TX_QUEUE_INACTIVE = 0,
505 AR5K_TX_QUEUE_DATA,
506 AR5K_TX_QUEUE_XR_DATA,
507 AR5K_TX_QUEUE_BEACON,
508 AR5K_TX_QUEUE_CAB,
509 AR5K_TX_QUEUE_UAPSD,
510};
511
512#define AR5K_NUM_TX_QUEUES 10
513#define AR5K_NUM_TX_QUEUES_NOQCU 2
514
515/*
516 * Queue syb-types to classify normal data queues.
517 * These are the 4 Access Categories as defined in
518 * WME spec. 0 is the lowest priority and 4 is the
519 * highest. Normal data that hasn't been classified
520 * goes to the Best Effort AC.
521 */
522enum ath5k_tx_queue_subtype {
523 AR5K_WME_AC_BK = 0, /*Background traffic*/
524 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
525 AR5K_WME_AC_VI, /*Video traffic*/
526 AR5K_WME_AC_VO, /*Voice traffic*/
527};
528
529/*
530 * Queue ID numbers as returned by the hw functions, each number
531 * represents a hw queue. If hw does not support hw queues
532 * (eg 5210) all data goes in one queue. These match
533 * d80211 definitions (net80211/MadWiFi don't use them).
534 */
535enum ath5k_tx_queue_id {
536 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
537 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
538 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
539 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
540 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
541 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
542 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
543 AR5K_TX_QUEUE_ID_UAPSD = 8,
544 AR5K_TX_QUEUE_ID_XR_DATA = 9,
545};
546
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200547/*
548 * Flags to set hw queue's parameters...
549 */
550#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
551#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
552#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
553#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
554#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200555#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
556#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
557#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
558#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
559#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
560#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
561#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
562#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
563#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200564
565/*
566 * A struct to hold tx queue's parameters
567 */
568struct ath5k_txq_info {
569 enum ath5k_tx_queue tqi_type;
570 enum ath5k_tx_queue_subtype tqi_subtype;
571 u16 tqi_flags; /* Tx queue flags (see above) */
Bruno Randolfde8af452010-09-17 11:37:12 +0900572 u8 tqi_aifs; /* Arbitrated Interframe Space */
573 u16 tqi_cw_min; /* Minimum Contention Window */
574 u16 tqi_cw_max; /* Maximum Contention Window */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200575 u32 tqi_cbr_period; /* Constant bit rate period */
576 u32 tqi_cbr_overflow_limit;
577 u32 tqi_burst_time;
Bob Copelanda951ae22010-01-20 23:51:04 -0500578 u32 tqi_ready_time; /* Time queue waits after an event */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200579};
580
581/*
582 * Transmit packet types.
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300583 * used on tx control descriptor
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200584 */
585enum ath5k_pkt_type {
586 AR5K_PKT_TYPE_NORMAL = 0,
587 AR5K_PKT_TYPE_ATIM = 1,
588 AR5K_PKT_TYPE_PSPOLL = 2,
589 AR5K_PKT_TYPE_BEACON = 3,
590 AR5K_PKT_TYPE_PROBE_RESP = 4,
591 AR5K_PKT_TYPE_PIFS = 5,
592};
593
594/*
595 * TX power and TPC settings
596 */
597#define AR5K_TXPOWER_OFDM(_r, _v) ( \
598 ((0 & 1) << ((_v) + 6)) | \
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200599 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200600)
601
602#define AR5K_TXPOWER_CCK(_r, _v) ( \
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200603 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200604)
605
606/*
Bruno Randolfbeade632010-06-16 19:11:25 +0900607 * DMA size definitions (2^(n+2))
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200608 */
609enum ath5k_dmasize {
610 AR5K_DMASIZE_4B = 0,
611 AR5K_DMASIZE_8B,
612 AR5K_DMASIZE_16B,
613 AR5K_DMASIZE_32B,
614 AR5K_DMASIZE_64B,
615 AR5K_DMASIZE_128B,
616 AR5K_DMASIZE_256B,
617 AR5K_DMASIZE_512B
618};
619
620
621/****************\
622 RX DEFINITIONS
623\****************/
624
625/*
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300626 * RX Status descriptor
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200627 */
628struct ath5k_rx_status {
629 u16 rs_datalen;
630 u16 rs_tstamp;
631 u8 rs_status;
632 u8 rs_phyerr;
633 s8 rs_rssi;
634 u8 rs_keyix;
635 u8 rs_rate;
636 u8 rs_antenna;
637 u8 rs_more;
638};
639
640#define AR5K_RXERR_CRC 0x01
641#define AR5K_RXERR_PHY 0x02
642#define AR5K_RXERR_FIFO 0x04
643#define AR5K_RXERR_DECRYPT 0x08
644#define AR5K_RXERR_MIC 0x10
645#define AR5K_RXKEYIX_INVALID ((u8) - 1)
646#define AR5K_TXKEYIX_INVALID ((u32) - 1)
647
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200648
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200649/**************************\
650 BEACON TIMERS DEFINITIONS
651\**************************/
652
653#define AR5K_BEACON_PERIOD 0x0000ffff
654#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
655#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
656
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200657
658/*
659 * TSF to TU conversion:
660 *
661 * TSF is a 64bit value in usec (microseconds).
Bruno Randolfe535c1a2008-01-18 21:51:40 +0900662 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
663 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200664 */
665#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
666
667
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300668/*******************************\
669 GAIN OPTIMIZATION DEFINITIONS
670\*******************************/
671
672enum ath5k_rfgain {
673 AR5K_RFGAIN_INACTIVE = 0,
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200674 AR5K_RFGAIN_ACTIVE,
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300675 AR5K_RFGAIN_READ_REQUESTED,
676 AR5K_RFGAIN_NEED_CHANGE,
677};
678
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300679struct ath5k_gain {
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200680 u8 g_step_idx;
681 u8 g_current;
682 u8 g_target;
683 u8 g_low;
684 u8 g_high;
685 u8 g_f_corr;
686 u8 g_state;
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300687};
688
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200689/********************\
690 COMMON DEFINITIONS
691\********************/
692
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200693#define AR5K_SLOT_TIME_9 396
694#define AR5K_SLOT_TIME_20 880
695#define AR5K_SLOT_TIME_MAX 0xffff
696
697/* channel_flags */
698#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
699#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
700#define CHANNEL_CCK 0x0020 /* CCK channel */
701#define CHANNEL_OFDM 0x0040 /* OFDM channel */
702#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
703#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
704#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
705#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
706#define CHANNEL_XR 0x0800 /* XR channel */
707
708#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
709#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
710#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
711#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
712#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
713#define CHANNEL_108A CHANNEL_T
714#define CHANNEL_108G CHANNEL_TG
715#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
716
717#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
718 CHANNEL_TURBO)
719
720#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
721#define CHANNEL_MODES CHANNEL_ALL
722
723/*
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300724 * Used internaly for reset_tx_queue).
725 * Also see struct struct ieee80211_channel.
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200726 */
Bob Copeland46026e82009-06-10 22:22:20 -0400727#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
728#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200729
730/*
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300731 * The following structure is used to map 2GHz channels to
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200732 * 5GHz Atheros channels.
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300733 * TODO: Clean up
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200734 */
735struct ath5k_athchan_2ghz {
736 u32 a2_flags;
737 u16 a2_athchan;
738};
739
Bruno Randolf63266a62008-07-30 17:12:58 +0200740
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300741/******************\
742 RATE DEFINITIONS
743\******************/
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200744
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200745/**
Bruno Randolf63266a62008-07-30 17:12:58 +0200746 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200747 *
Bruno Randolf63266a62008-07-30 17:12:58 +0200748 * The rate code is used to get the RX rate or set the TX rate on the
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200749 * hardware descriptors. It is also used for internal modulation control
750 * and settings.
751 *
Bruno Randolf63266a62008-07-30 17:12:58 +0200752 * This is the hardware rate map we are aware of:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200753 *
Bruno Randolf63266a62008-07-30 17:12:58 +0200754 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200755 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
756 *
Bruno Randolf63266a62008-07-30 17:12:58 +0200757 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200758 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
759 *
760 * rate_code 17 18 19 20 21 22 23 24
761 * rate_kbps ? ? ? ? ? ? ? 11000
762 *
763 * rate_code 25 26 27 28 29 30 31 32
Bruno Randolf63266a62008-07-30 17:12:58 +0200764 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200765 *
Bruno Randolf63266a62008-07-30 17:12:58 +0200766 * "S" indicates CCK rates with short preamble.
767 *
768 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
769 * lowest 4 bits, so they are the same as below with a 0xF mask.
770 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
771 * We handle this in ath5k_setup_bands().
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200772 */
Bruno Randolf63266a62008-07-30 17:12:58 +0200773#define AR5K_MAX_RATES 32
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200774
Bruno Randolf63266a62008-07-30 17:12:58 +0200775/* B */
776#define ATH5K_RATE_CODE_1M 0x1B
777#define ATH5K_RATE_CODE_2M 0x1A
778#define ATH5K_RATE_CODE_5_5M 0x19
779#define ATH5K_RATE_CODE_11M 0x18
780/* A and G */
781#define ATH5K_RATE_CODE_6M 0x0B
782#define ATH5K_RATE_CODE_9M 0x0F
783#define ATH5K_RATE_CODE_12M 0x0A
784#define ATH5K_RATE_CODE_18M 0x0E
785#define ATH5K_RATE_CODE_24M 0x09
786#define ATH5K_RATE_CODE_36M 0x0D
787#define ATH5K_RATE_CODE_48M 0x08
788#define ATH5K_RATE_CODE_54M 0x0C
789/* XR */
790#define ATH5K_RATE_CODE_XR_500K 0x07
791#define ATH5K_RATE_CODE_XR_1M 0x02
792#define ATH5K_RATE_CODE_XR_2M 0x06
793#define ATH5K_RATE_CODE_XR_3M 0x01
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200794
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300795/* adding this flag to rate_code enables short preamble */
796#define AR5K_SET_SHORT_PREAMBLE 0x04
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200797
798/*
799 * Crypto definitions
800 */
801
802#define AR5K_KEYCACHE_SIZE 8
803
804/***********************\
805 HW RELATED DEFINITIONS
806\***********************/
807
808/*
809 * Misc definitions
810 */
811#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
812
813#define AR5K_ASSERT_ENTRY(_e, _s) do { \
814 if (_e >= _s) \
815 return (false); \
816} while (0)
817
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200818/*
819 * Hardware interrupt abstraction
820 */
821
822/**
823 * enum ath5k_int - Hardware interrupt masks helpers
824 *
825 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
826 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
827 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
828 * @AR5K_INT_RXNOFRM: No frame received (?)
829 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
830 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
831 * LinkPtr is NULL. For more details, refer to:
832 * http://www.freepatentsonline.com/20030225739.html
833 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
834 * Note that Rx overrun is not always fatal, on some chips we can continue
835 * operation without reseting the card, that's why int_fatal is not
836 * common for all chips.
837 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
838 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
839 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
840 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
841 * We currently do increments on interrupt by
842 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
Bruno Randolf2111ac02010-04-02 18:44:08 +0900843 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
844 * one of the PHY error counters reached the maximum value and should be
845 * read and cleared.
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200846 * @AR5K_INT_RXPHY: RX PHY Error
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200847 * @AR5K_INT_RXKCM: RX Key cache miss
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200848 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
849 * beacon that must be handled in software. The alternative is if you
850 * have VEOL support, in that case you let the hardware deal with things.
851 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
852 * beacons from the AP have associated with, we should probably try to
853 * reassociate. When in IBSS mode this might mean we have not received
854 * any beacons from any local stations. Note that every station in an
855 * IBSS schedules to send beacons at the Target Beacon Transmission Time
856 * (TBTT) with a random backoff.
857 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
858 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
859 * until properly handled
860 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
861 * errors. These types of errors we can enable seem to be of type
862 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200863 * @AR5K_INT_GLOBAL: Used to clear and set the IER
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200864 * @AR5K_INT_NOCARD: signals the card has been removed
865 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
866 * bit value
867 *
868 * These are mapped to take advantage of some common bits
869 * between the MACs, to be able to set intr properties
870 * easier. Some of them are not used yet inside hw.c. Most map
871 * to the respective hw interrupt value as they are common amogst different
872 * MACs.
873 */
874enum ath5k_int {
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200875 AR5K_INT_RXOK = 0x00000001,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200876 AR5K_INT_RXDESC = 0x00000002,
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200877 AR5K_INT_RXERR = 0x00000004,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200878 AR5K_INT_RXNOFRM = 0x00000008,
879 AR5K_INT_RXEOL = 0x00000010,
880 AR5K_INT_RXORN = 0x00000020,
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200881 AR5K_INT_TXOK = 0x00000040,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200882 AR5K_INT_TXDESC = 0x00000080,
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200883 AR5K_INT_TXERR = 0x00000100,
884 AR5K_INT_TXNOFRM = 0x00000200,
885 AR5K_INT_TXEOL = 0x00000400,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200886 AR5K_INT_TXURN = 0x00000800,
887 AR5K_INT_MIB = 0x00001000,
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200888 AR5K_INT_SWI = 0x00002000,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200889 AR5K_INT_RXPHY = 0x00004000,
890 AR5K_INT_RXKCM = 0x00008000,
891 AR5K_INT_SWBA = 0x00010000,
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200892 AR5K_INT_BRSSI = 0x00020000,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200893 AR5K_INT_BMISS = 0x00040000,
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200894 AR5K_INT_FATAL = 0x00080000, /* Non common */
895 AR5K_INT_BNR = 0x00100000, /* Non common */
896 AR5K_INT_TIM = 0x00200000, /* Non common */
897 AR5K_INT_DTIM = 0x00400000, /* Non common */
898 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
899 AR5K_INT_GPIO = 0x01000000,
900 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
901 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
902 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
903 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
904 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
905 AR5K_INT_QTRIG = 0x40000000, /* Non common */
906 AR5K_INT_GLOBAL = 0x80000000,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200907
Nick Kossifidis4c674c62008-10-26 20:40:25 +0200908 AR5K_INT_COMMON = AR5K_INT_RXOK
909 | AR5K_INT_RXDESC
910 | AR5K_INT_RXERR
911 | AR5K_INT_RXNOFRM
912 | AR5K_INT_RXEOL
913 | AR5K_INT_RXORN
914 | AR5K_INT_TXOK
915 | AR5K_INT_TXDESC
916 | AR5K_INT_TXERR
917 | AR5K_INT_TXNOFRM
918 | AR5K_INT_TXEOL
919 | AR5K_INT_TXURN
920 | AR5K_INT_MIB
921 | AR5K_INT_SWI
922 | AR5K_INT_RXPHY
923 | AR5K_INT_RXKCM
924 | AR5K_INT_SWBA
925 | AR5K_INT_BRSSI
926 | AR5K_INT_BMISS
927 | AR5K_INT_GPIO
928 | AR5K_INT_GLOBAL,
929
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200930 AR5K_INT_NOCARD = 0xffffffff
931};
932
Bruno Randolfe65e1d72010-03-25 14:49:09 +0900933/* mask which calibration is active at the moment */
934enum ath5k_calibration_mask {
935 AR5K_CALIBRATION_FULL = 0x01,
936 AR5K_CALIBRATION_SHORT = 0x02,
Bruno Randolf2111ac02010-04-02 18:44:08 +0900937 AR5K_CALIBRATION_ANI = 0x04,
Nick Kossifidis6e2206622009-08-10 03:31:31 +0300938};
939
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200940/*
941 * Power management
942 */
943enum ath5k_power_mode {
944 AR5K_PM_UNDEFINED = 0,
945 AR5K_PM_AUTO,
946 AR5K_PM_AWAKE,
947 AR5K_PM_FULL_SLEEP,
948 AR5K_PM_NETWORK_SLEEP,
949};
950
951/*
952 * These match net80211 definitions (not used in
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300953 * mac80211).
954 * TODO: Clean this up
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200955 */
956#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
957#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
958#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
959#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
960#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
961
962/* GPIO-controlled software LED */
963#define AR5K_SOFTLED_PIN 0
964#define AR5K_SOFTLED_ON 0
965#define AR5K_SOFTLED_OFF 1
966
967/*
968 * Chipset capabilities -see ath5k_hw_get_capability-
969 * get_capability function is not yet fully implemented
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300970 * in ath5k so most of these don't work yet...
971 * TODO: Implement these & merge with _TUNE_ stuff above
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200972 */
973enum ath5k_capability_type {
974 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
975 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
976 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
977 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
978 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
979 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
980 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
981 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
982 AR5K_CAP_BURST = 9, /* Supports packet bursting */
983 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
984 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
985 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
986 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
987 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
988 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
989 AR5K_CAP_XR = 16, /* Supports XR mode */
990 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
991 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
992 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
993 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
994};
995
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500996
997/* XXX: we *may* move cap_range stuff to struct wiphy */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200998struct ath5k_capabilities {
999 /*
1000 * Supported PHY modes
1001 * (ie. CHANNEL_A, CHANNEL_B, ...)
1002 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -05001003 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001004
1005 /*
1006 * Frequency range (without regulation restrictions)
1007 */
1008 struct {
1009 u16 range_2ghz_min;
1010 u16 range_2ghz_max;
1011 u16 range_5ghz_min;
1012 u16 range_5ghz_max;
1013 } cap_range;
1014
1015 /*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001016 * Values stored in the EEPROM (some of them...)
1017 */
1018 struct ath5k_eeprom_info cap_eeprom;
1019
1020 /*
1021 * Queue information
1022 */
1023 struct {
1024 u8 q_tx_num;
1025 } cap_queues;
Bruno Randolfa8c944f2010-03-25 14:49:47 +09001026
1027 bool cap_has_phyerr_counters;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001028};
1029
Bob Copelande5e26472009-10-14 14:16:30 -04001030/* size of noise floor history (keep it a power of two) */
1031#define ATH5K_NF_CAL_HIST_MAX 8
1032struct ath5k_nfcal_hist
1033{
1034 s16 index; /* current index into nfval */
1035 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1036};
1037
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001038/**
1039 * struct avg_val - Helper structure for average calculation
1040 * @avg: contains the actual average value
1041 * @avg_weight: is used internally during calculation to prevent rounding errors
1042 */
1043struct ath5k_avg_val {
1044 int avg;
1045 int avg_weight;
1046};
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001047
1048/***************************************\
1049 HARDWARE ABSTRACTION LAYER STRUCTURE
1050\***************************************/
1051
1052/*
1053 * Misc defines
1054 */
1055
1056#define AR5K_MAX_GPIO 10
1057#define AR5K_MAX_RF_BANKS 8
1058
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001059/* TODO: Clean up and merge with ath5k_softc */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001060struct ath5k_hw {
Luis R. Rodriguezdb719712009-09-10 11:20:57 -07001061 struct ath_common common;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001062
1063 struct ath5k_softc *ah_sc;
1064 void __iomem *ah_iobase;
1065
1066 enum ath5k_int ah_imr;
1067
Bob Copeland46026e82009-06-10 22:22:20 -04001068 struct ieee80211_channel *ah_current_channel;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001069 bool ah_calibration;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001070 bool ah_single_chip;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001071
Bob Copeland46026e82009-06-10 22:22:20 -04001072 enum ath5k_version ah_version;
1073 enum ath5k_radio ah_radio;
1074 u32 ah_phy;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001075 u32 ah_mac_srev;
1076 u16 ah_mac_version;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001077 u16 ah_phy_revision;
1078 u16 ah_radio_5ghz_revision;
1079 u16 ah_radio_2ghz_revision;
1080
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001081#define ah_modes ah_capabilities.cap_mode
1082#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1083
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001084 u32 ah_limit_tx_retries;
Lukáš Turek6e08d222009-12-21 22:50:51 +01001085 u8 ah_coverage_class;
Nick Kossifidisfa3d2fe2010-11-23 20:58:34 +02001086 u8 ah_bwmode;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001087
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001088 /* Antenna Control */
1089 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1090 u8 ah_ant_mode;
1091 u8 ah_tx_ant;
1092 u8 ah_def_ant;
Bob Copeland46026e82009-06-10 22:22:20 -04001093 bool ah_software_retry;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001094
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001095 struct ath5k_capabilities ah_capabilities;
1096
1097 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1098 u32 ah_txq_status;
1099 u32 ah_txq_imr_txok;
1100 u32 ah_txq_imr_txerr;
1101 u32 ah_txq_imr_txurn;
1102 u32 ah_txq_imr_txdesc;
1103 u32 ah_txq_imr_txeol;
Nick Kossifidis4c674c62008-10-26 20:40:25 +02001104 u32 ah_txq_imr_cbrorn;
1105 u32 ah_txq_imr_cbrurn;
1106 u32 ah_txq_imr_qtrig;
1107 u32 ah_txq_imr_nofrm;
1108 u32 ah_txq_isr;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001109 u32 *ah_rf_banks;
1110 size_t ah_rf_banks_size;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +02001111 size_t ah_rf_regs_count;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001112 struct ath5k_gain ah_gain;
Nick Kossifidis8892e4e2009-02-09 06:06:34 +02001113 u8 ah_offset[AR5K_MAX_RF_BANKS];
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001114
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001115
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001116 struct {
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001117 /* Temporary tables used for interpolation */
1118 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1119 [AR5K_EEPROM_POWER_TABLE_SIZE];
1120 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1121 [AR5K_EEPROM_POWER_TABLE_SIZE];
1122 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1123 u16 txp_rates_power_table[AR5K_MAX_RATES];
1124 u8 txp_min_idx;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001125 bool txp_tpc;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001126 /* Values in 0.25dB units */
1127 s16 txp_min_pwr;
1128 s16 txp_max_pwr;
Nick Kossifidisa0823812009-04-30 15:55:44 -04001129 /* Values in 0.5dB units */
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001130 s16 txp_offset;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001131 s16 txp_ofdm;
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001132 s16 txp_cck_ofdm_gainf_delta;
Nick Kossifidisa0823812009-04-30 15:55:44 -04001133 /* Value in dB units */
1134 s16 txp_cck_ofdm_pwr_delta;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001135 } ah_txpower;
1136
1137 struct {
1138 bool r_enabled;
1139 int r_last_alert;
1140 struct ieee80211_channel r_last_channel;
1141 } ah_radar;
1142
Bob Copelande5e26472009-10-14 14:16:30 -04001143 struct ath5k_nfcal_hist ah_nfcal_hist;
1144
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001145 /* average beacon RSSI in our BSS (used by ANI) */
Bruno Randolfeef39be2010-11-16 10:58:43 +09001146 struct ewma ah_beacon_rssi_avg;
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001147
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001148 /* noise floor from last periodic calibration */
1149 s32 ah_noise_floor;
1150
Nick Kossifidis6e2206622009-08-10 03:31:31 +03001151 /* Calibration timestamp */
Bruno Randolfa9167f92010-03-25 14:49:14 +09001152 unsigned long ah_cal_next_full;
Bruno Randolf2111ac02010-04-02 18:44:08 +09001153 unsigned long ah_cal_next_ani;
Bruno Randolfafe86282010-05-19 10:31:10 +09001154 unsigned long ah_cal_next_nf;
Nick Kossifidis6e2206622009-08-10 03:31:31 +03001155
Bruno Randolfe65e1d72010-03-25 14:49:09 +09001156 /* Calibration mask */
1157 u8 ah_cal_mask;
Nick Kossifidis6e2206622009-08-10 03:31:31 +03001158
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001159 /*
1160 * Function pointers
1161 */
1162 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001163 unsigned int, unsigned int, int, enum ath5k_pkt_type,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001164 unsigned int, unsigned int, unsigned int, unsigned int,
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001165 unsigned int, unsigned int, unsigned int, unsigned int);
Bruno Randolfb47f4072008-03-05 18:35:45 +09001166 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1167 struct ath5k_tx_status *);
1168 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1169 struct ath5k_rx_status *);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001170};
1171
1172/*
1173 * Prototypes
1174 */
1175
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001176/* Attach/Detach Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001177int ath5k_hw_attach(struct ath5k_softc *sc);
1178void ath5k_hw_detach(struct ath5k_hw *ah);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001179
Bruno Randolf40ca22e2010-05-19 10:31:32 +09001180int ath5k_sysfs_register(struct ath5k_softc *sc);
1181void ath5k_sysfs_unregister(struct ath5k_softc *sc);
1182
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001183
Bob Copeland0ed45482009-03-08 00:10:20 -05001184/* LED functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001185int ath5k_init_leds(struct ath5k_softc *sc);
1186void ath5k_led_enable(struct ath5k_softc *sc);
1187void ath5k_led_off(struct ath5k_softc *sc);
1188void ath5k_unregister_leds(struct ath5k_softc *sc);
Bob Copeland0ed45482009-03-08 00:10:20 -05001189
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001190
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001191/* Reset Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001192int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1193int ath5k_hw_on_hold(struct ath5k_hw *ah);
1194int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1195 struct ieee80211_channel *channel, bool change_channel);
Pavel Roskinec182d92010-02-18 20:28:41 -05001196int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1197 bool is_set);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001198/* Power management functions */
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001199
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001200
1201/* Clock rate related functions */
1202unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1203unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1204void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1205
1206
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001207/* DMA Related Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001208void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001209u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
Nick Kossifidise8325ed2010-11-23 20:52:24 +02001210int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001211int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
Nick Kossifidis14fae2d2010-11-23 20:55:17 +02001212int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001213u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1214int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001215 u32 phys_addr);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001216int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001217/* Interrupt handling */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001218bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1219int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1220enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
Bruno Randolf495391d2010-03-25 14:49:36 +09001221void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
Nick Kossifidisd41174f2010-11-23 20:41:15 +02001222/* Init/Stop functions */
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001223void ath5k_hw_dma_init(struct ath5k_hw *ah);
Nick Kossifidisd41174f2010-11-23 20:41:15 +02001224int ath5k_hw_dma_stop(struct ath5k_hw *ah);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001225
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001226/* EEPROM access functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001227int ath5k_eeprom_init(struct ath5k_hw *ah);
1228void ath5k_eeprom_detach(struct ath5k_hw *ah);
1229int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001230
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001231
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001232/* Protocol Control Unit Functions */
Bruno Randolfccfe5552010-03-09 16:55:38 +09001233extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001234void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001235/* RX filter control*/
Pavel Roskina25d1e42010-02-18 20:28:23 -05001236int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
Nick Kossifidis418de6d2010-08-15 13:03:10 -04001237void ath5k_hw_set_bssid(struct ath5k_hw *ah);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001238void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001239void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1240u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1241void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001242/* Receive (DRU) start/stop functions */
1243void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1244void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001245/* Beacon control functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001246u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1247void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1248void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1249void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
Bruno Randolf7f896122010-09-27 12:22:21 +09001250bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001251/* ACK bit rate */
1252void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001253/* Init function */
1254void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1255 u8 mode);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001256
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001257/* Queue Control Unit, DFS Control Unit Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001258int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1259 struct ath5k_txq_info *queue_info);
1260int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1261 const struct ath5k_txq_info *queue_info);
1262int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1263 enum ath5k_tx_queue queue_type,
1264 struct ath5k_txq_info *queue_info);
1265u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1266void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1267int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1268int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001269/* Init function */
1270int ath5k_hw_init_queues(struct ath5k_hw *ah);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001271
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001272/* Hardware Descriptor Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001273int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
Bruno Randolfa6668192010-06-16 19:12:01 +09001274int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1275 u32 size, unsigned int flags);
1276int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1277 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1278 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001279
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001280
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001281/* GPIO Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001282void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1283int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1284int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1285u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1286int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1287void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1288 u32 interrupt_level);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001289
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001290
1291/* RFkill Functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001292void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1293void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
Tobias Doerffele6a3b612009-06-09 17:33:27 +02001294
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001295
1296/* Misc functions TODO: Cleanup */
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001297int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001298int ath5k_hw_get_capability(struct ath5k_hw *ah,
1299 enum ath5k_capability_type cap_type, u32 capability,
1300 u32 *result);
1301int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1302int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001303
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001304
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001305/* Initial register settings functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001306int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001307
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001308
1309/* PHY functions */
1310/* Misc PHY functions */
1311u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1312int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1313/* Gain_F optimization */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001314enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1315int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001316/* PHY/RF channel functions */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001317bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001318/* PHY calibration */
Bob Copelande5e26472009-10-14 14:16:30 -04001319void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
Pavel Roskina25d1e42010-02-18 20:28:23 -05001320int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1321 struct ieee80211_channel *channel);
Bruno Randolf9e04a7e2010-05-19 10:31:00 +09001322void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
Nick Kossifidis57e6c562009-04-30 15:55:50 -04001323/* Spur mitigation */
1324bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
Pavel Roskina25d1e42010-02-18 20:28:23 -05001325 struct ieee80211_channel *channel);
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001326/* Antenna control */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001327void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
Bruno Randolf0ca74022010-06-07 13:11:30 +09001328void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001329/* TX power setup */
Pavel Roskina25d1e42010-02-18 20:28:23 -05001330int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
Nick Kossifidis9320b5c42010-11-23 20:36:45 +02001331/* Init function */
1332int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1333 u8 mode, u8 ee_mode, u8 freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001334
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001335/*
1336 * Functions used internaly
1337 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001338
Luis R. Rodrigueze5aa8472009-09-10 16:55:11 -07001339static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1340{
1341 return &ah->common;
1342}
1343
1344static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1345{
1346 return &(ath5k_hw_common(ah)->regulatory);
1347}
1348
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001349static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1350{
1351 return ioread32(ah->ah_iobase + reg);
1352}
1353
1354static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1355{
1356 iowrite32(val, ah->ah_iobase + reg);
1357}
1358
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001359static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1360{
1361 u32 retval = 0, bit, i;
1362
1363 for (i = 0; i < bits; i++) {
1364 bit = (val >> i) & 1;
1365 retval = (retval << 1) | bit;
1366 }
1367
1368 return retval;
1369}
1370
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001371#endif