blob: 7770a7e4162f4b3f288607ca27493b188a92dd79 [file] [log] [blame]
Jeeja KPd255b092015-07-21 23:53:56 +05301/*
2 * skl-message.c - HDA DSP interface for FW registration, Pipe and Module
3 * configurations
4 *
5 * Copyright (C) 2015 Intel Corp
6 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
7 * Jeeja KP <jeeja.kp@intel.com>
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/slab.h>
21#include <linux/pci.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl.h"
27#include "../common/sst-dsp.h"
28#include "../common/sst-dsp-priv.h"
Jeeja KP23db4722015-08-01 19:40:41 +053029#include "skl-topology.h"
30#include "skl-tplg-interface.h"
Jeeja KPd255b092015-07-21 23:53:56 +053031
32static int skl_alloc_dma_buf(struct device *dev,
33 struct snd_dma_buffer *dmab, size_t size)
34{
35 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
36 struct hdac_bus *bus = ebus_to_hbus(ebus);
37
38 if (!bus)
39 return -ENODEV;
40
41 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, size, dmab);
42}
43
44static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab)
45{
46 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
47 struct hdac_bus *bus = ebus_to_hbus(ebus);
48
49 if (!bus)
50 return -ENODEV;
51
52 bus->io_ops->dma_free_pages(bus, dmab);
53
54 return 0;
55}
56
Jeeja KP4e109962015-10-22 23:22:39 +053057#define NOTIFICATION_PARAM_ID 3
58#define NOTIFICATION_MASK 0xf
59
60/* disable notfication for underruns/overruns from firmware module */
61static void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable)
62{
63 struct notification_mask mask;
64 struct skl_ipc_large_config_msg msg = {0};
65
66 mask.notify = NOTIFICATION_MASK;
67 mask.enable = enable;
68
69 msg.large_param_id = NOTIFICATION_PARAM_ID;
70 msg.param_data_size = sizeof(mask);
71
72 skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)&mask);
73}
74
Jeeja KPd255b092015-07-21 23:53:56 +053075int skl_init_dsp(struct skl *skl)
76{
77 void __iomem *mmio_base;
78 struct hdac_ext_bus *ebus = &skl->ebus;
79 struct hdac_bus *bus = ebus_to_hbus(ebus);
80 int irq = bus->irq;
81 struct skl_dsp_loader_ops loader_ops;
82 int ret;
83
84 loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
85 loader_ops.free_dma_buf = skl_free_dma_buf;
86
87 /* enable ppcap interrupt */
88 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
89 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
90
91 /* read the BAR of the ADSP MMIO */
92 mmio_base = pci_ioremap_bar(skl->pci, 4);
93 if (mmio_base == NULL) {
94 dev_err(bus->dev, "ioremap error\n");
95 return -ENXIO;
96 }
97
98 ret = skl_sst_dsp_init(bus->dev, mmio_base, irq,
Vinod Koulaecf6fd2015-11-05 21:34:15 +053099 skl->fw_name, loader_ops, &skl->skl_sst);
Jeeja KP2ac454f2015-10-22 23:22:40 +0530100 if (ret < 0)
101 return ret;
102
Jeeja KP4e109962015-10-22 23:22:39 +0530103 skl_dsp_enable_notification(skl->skl_sst, false);
Jeeja KPd255b092015-07-21 23:53:56 +0530104 dev_dbg(bus->dev, "dsp registration status=%d\n", ret);
105
106 return ret;
107}
108
109void skl_free_dsp(struct skl *skl)
110{
111 struct hdac_ext_bus *ebus = &skl->ebus;
112 struct hdac_bus *bus = ebus_to_hbus(ebus);
113 struct skl_sst *ctx = skl->skl_sst;
114
115 /* disable ppcap interrupt */
116 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
117
118 skl_sst_dsp_cleanup(bus->dev, ctx);
119 if (ctx->dsp->addr.lpe)
120 iounmap(ctx->dsp->addr.lpe);
121}
122
123int skl_suspend_dsp(struct skl *skl)
124{
125 struct skl_sst *ctx = skl->skl_sst;
126 int ret;
127
128 /* if ppcap is not supported return 0 */
129 if (!skl->ebus.ppcap)
130 return 0;
131
132 ret = skl_dsp_sleep(ctx->dsp);
133 if (ret < 0)
134 return ret;
135
136 /* disable ppcap interrupt */
137 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
138 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, false);
139
140 return 0;
141}
142
143int skl_resume_dsp(struct skl *skl)
144{
145 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP4e109962015-10-22 23:22:39 +0530146 int ret;
Jeeja KPd255b092015-07-21 23:53:56 +0530147
148 /* if ppcap is not supported return 0 */
149 if (!skl->ebus.ppcap)
150 return 0;
151
152 /* enable ppcap interrupt */
153 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
154 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
155
Jeeja KP4e109962015-10-22 23:22:39 +0530156 ret = skl_dsp_wake(ctx->dsp);
157 if (ret < 0)
158 return ret;
159
160 skl_dsp_enable_notification(skl->skl_sst, false);
161 return ret;
Jeeja KPd255b092015-07-21 23:53:56 +0530162}
Jeeja KP23db4722015-08-01 19:40:41 +0530163
164enum skl_bitdepth skl_get_bit_depth(int params)
165{
166 switch (params) {
167 case 8:
168 return SKL_DEPTH_8BIT;
169
170 case 16:
171 return SKL_DEPTH_16BIT;
172
173 case 24:
174 return SKL_DEPTH_24BIT;
175
176 case 32:
177 return SKL_DEPTH_32BIT;
178
179 default:
180 return SKL_DEPTH_INVALID;
181
182 }
183}
184
Jeeja KP23db4722015-08-01 19:40:41 +0530185/*
186 * Each module in DSP expects a base module configuration, which consists of
187 * PCM format information, which we calculate in driver and resource values
188 * which are read from widget information passed through topology binary
189 * This is send when we create a module with INIT_INSTANCE IPC msg
190 */
191static void skl_set_base_module_format(struct skl_sst *ctx,
192 struct skl_module_cfg *mconfig,
193 struct skl_base_cfg *base_cfg)
194{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900195 struct skl_module_fmt *format = &mconfig->in_fmt[0];
Jeeja KP23db4722015-08-01 19:40:41 +0530196
197 base_cfg->audio_fmt.number_of_channels = (u8)format->channels;
198
199 base_cfg->audio_fmt.s_freq = format->s_freq;
200 base_cfg->audio_fmt.bit_depth = format->bit_depth;
201 base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth;
202 base_cfg->audio_fmt.ch_cfg = format->ch_cfg;
203
204 dev_dbg(ctx->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n",
205 format->bit_depth, format->valid_bit_depth,
206 format->ch_cfg);
207
Jeeja KP3e81f1a2015-10-27 09:22:59 +0900208 base_cfg->audio_fmt.channel_map = format->ch_map;
Jeeja KP23db4722015-08-01 19:40:41 +0530209
Jeeja KP3e81f1a2015-10-27 09:22:59 +0900210 base_cfg->audio_fmt.interleaving = format->interleaving_style;
Jeeja KP23db4722015-08-01 19:40:41 +0530211
212 base_cfg->cps = mconfig->mcps;
213 base_cfg->ibs = mconfig->ibs;
214 base_cfg->obs = mconfig->obs;
215}
216
217/*
218 * Copies copier capabilities into copier module and updates copier module
219 * config size.
220 */
221static void skl_copy_copier_caps(struct skl_module_cfg *mconfig,
222 struct skl_cpr_cfg *cpr_mconfig)
223{
224 if (mconfig->formats_config.caps_size == 0)
225 return;
226
227 memcpy(cpr_mconfig->gtw_cfg.config_data,
228 mconfig->formats_config.caps,
229 mconfig->formats_config.caps_size);
230
231 cpr_mconfig->gtw_cfg.config_length =
232 (mconfig->formats_config.caps_size) / 4;
233}
234
Jeeja KPbfa764a2015-10-22 23:22:41 +0530235#define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF
Jeeja KP23db4722015-08-01 19:40:41 +0530236/*
237 * Calculate the gatewat settings required for copier module, type of
238 * gateway and index of gateway to use
239 */
240static void skl_setup_cpr_gateway_cfg(struct skl_sst *ctx,
241 struct skl_module_cfg *mconfig,
242 struct skl_cpr_cfg *cpr_mconfig)
243{
244 union skl_connector_node_id node_id = {0};
Jeeja KPd7b18812015-10-22 23:22:38 +0530245 union skl_ssp_dma_node ssp_node = {0};
Jeeja KP23db4722015-08-01 19:40:41 +0530246 struct skl_pipe_params *params = mconfig->pipe->p_params;
247
248 switch (mconfig->dev_type) {
249 case SKL_DEVICE_BT:
250 node_id.node.dma_type =
251 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
252 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
253 SKL_DMA_I2S_LINK_INPUT_CLASS;
254 node_id.node.vindex = params->host_dma_id +
255 (mconfig->vbus_id << 3);
256 break;
257
258 case SKL_DEVICE_I2S:
259 node_id.node.dma_type =
260 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
261 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
262 SKL_DMA_I2S_LINK_INPUT_CLASS;
Jeeja KPd7b18812015-10-22 23:22:38 +0530263 ssp_node.dma_node.time_slot_index = mconfig->time_slot;
264 ssp_node.dma_node.i2s_instance = mconfig->vbus_id;
265 node_id.node.vindex = ssp_node.val;
Jeeja KP23db4722015-08-01 19:40:41 +0530266 break;
267
268 case SKL_DEVICE_DMIC:
269 node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS;
270 node_id.node.vindex = mconfig->vbus_id +
271 (mconfig->time_slot);
272 break;
273
274 case SKL_DEVICE_HDALINK:
275 node_id.node.dma_type =
276 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
277 SKL_DMA_HDA_LINK_OUTPUT_CLASS :
278 SKL_DMA_HDA_LINK_INPUT_CLASS;
279 node_id.node.vindex = params->link_dma_id;
280 break;
281
Jeeja KPbfa764a2015-10-22 23:22:41 +0530282 case SKL_DEVICE_HDAHOST:
Jeeja KP23db4722015-08-01 19:40:41 +0530283 node_id.node.dma_type =
284 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
285 SKL_DMA_HDA_HOST_OUTPUT_CLASS :
286 SKL_DMA_HDA_HOST_INPUT_CLASS;
287 node_id.node.vindex = params->host_dma_id;
288 break;
Jeeja KPbfa764a2015-10-22 23:22:41 +0530289
290 default:
291 cpr_mconfig->gtw_cfg.node_id = SKL_NON_GATEWAY_CPR_NODE_ID;
292 cpr_mconfig->cpr_feature_mask = 0;
293 return;
Jeeja KP23db4722015-08-01 19:40:41 +0530294 }
295
296 cpr_mconfig->gtw_cfg.node_id = node_id.val;
297
298 if (SKL_CONN_SOURCE == mconfig->hw_conn_type)
299 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->obs;
300 else
301 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->ibs;
302
303 cpr_mconfig->cpr_feature_mask = 0;
304 cpr_mconfig->gtw_cfg.config_length = 0;
305
306 skl_copy_copier_caps(mconfig, cpr_mconfig);
307}
308
309static void skl_setup_out_format(struct skl_sst *ctx,
310 struct skl_module_cfg *mconfig,
311 struct skl_audio_data_format *out_fmt)
312{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900313 struct skl_module_fmt *format = &mconfig->out_fmt[0];
Jeeja KP23db4722015-08-01 19:40:41 +0530314
315 out_fmt->number_of_channels = (u8)format->channels;
316 out_fmt->s_freq = format->s_freq;
317 out_fmt->bit_depth = format->bit_depth;
318 out_fmt->valid_bit_depth = format->valid_bit_depth;
319 out_fmt->ch_cfg = format->ch_cfg;
320
Jeeja KP3e81f1a2015-10-27 09:22:59 +0900321 out_fmt->channel_map = format->ch_map;
322 out_fmt->interleaving = format->interleaving_style;
323 out_fmt->sample_type = format->sample_type;
Jeeja KP23db4722015-08-01 19:40:41 +0530324
325 dev_dbg(ctx->dev, "copier out format chan=%d fre=%d bitdepth=%d\n",
326 out_fmt->number_of_channels, format->s_freq, format->bit_depth);
327}
328
329/*
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530330 * DSP needs SRC module for frequency conversion, SRC takes base module
331 * configuration and the target frequency as extra parameter passed as src
332 * config
333 */
334static void skl_set_src_format(struct skl_sst *ctx,
335 struct skl_module_cfg *mconfig,
336 struct skl_src_module_cfg *src_mconfig)
337{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900338 struct skl_module_fmt *fmt = &mconfig->out_fmt[0];
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530339
340 skl_set_base_module_format(ctx, mconfig,
341 (struct skl_base_cfg *)src_mconfig);
342
343 src_mconfig->src_cfg = fmt->s_freq;
344}
345
346/*
347 * DSP needs updown module to do channel conversion. updown module take base
348 * module configuration and channel configuration
349 * It also take coefficients and now we have defaults applied here
350 */
351static void skl_set_updown_mixer_format(struct skl_sst *ctx,
352 struct skl_module_cfg *mconfig,
353 struct skl_up_down_mixer_cfg *mixer_mconfig)
354{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900355 struct skl_module_fmt *fmt = &mconfig->out_fmt[0];
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530356 int i = 0;
357
358 skl_set_base_module_format(ctx, mconfig,
359 (struct skl_base_cfg *)mixer_mconfig);
360 mixer_mconfig->out_ch_cfg = fmt->ch_cfg;
361
362 /* Select F/W default coefficient */
363 mixer_mconfig->coeff_sel = 0x0;
364
365 /* User coeff, don't care since we are selecting F/W defaults */
366 for (i = 0; i < UP_DOWN_MIXER_MAX_COEFF; i++)
367 mixer_mconfig->coeff[i] = 0xDEADBEEF;
368}
369
370/*
Jeeja KP23db4722015-08-01 19:40:41 +0530371 * 'copier' is DSP internal module which copies data from Host DMA (HDA host
372 * dma) or link (hda link, SSP, PDM)
373 * Here we calculate the copier module parameters, like PCM format, output
374 * format, gateway settings
375 * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg
376 */
377static void skl_set_copier_format(struct skl_sst *ctx,
378 struct skl_module_cfg *mconfig,
379 struct skl_cpr_cfg *cpr_mconfig)
380{
381 struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt;
382 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig;
383
384 skl_set_base_module_format(ctx, mconfig, base_cfg);
385
386 skl_setup_out_format(ctx, mconfig, out_fmt);
387 skl_setup_cpr_gateway_cfg(ctx, mconfig, cpr_mconfig);
388}
389
Jeeja KP399b2102015-11-28 15:01:48 +0530390/*
391 * Algo module are DSP pre processing modules. Algo module take base module
392 * configuration and params
393 */
394
395static void skl_set_algo_format(struct skl_sst *ctx,
396 struct skl_module_cfg *mconfig,
397 struct skl_algo_cfg *algo_mcfg)
398{
399 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)algo_mcfg;
400
401 skl_set_base_module_format(ctx, mconfig, base_cfg);
402
403 if (mconfig->formats_config.caps_size == 0)
404 return;
405
406 memcpy(algo_mcfg->params,
407 mconfig->formats_config.caps,
408 mconfig->formats_config.caps_size);
409
410}
411
Jeeja KP23db4722015-08-01 19:40:41 +0530412static u16 skl_get_module_param_size(struct skl_sst *ctx,
413 struct skl_module_cfg *mconfig)
414{
415 u16 param_size;
416
417 switch (mconfig->m_type) {
418 case SKL_MODULE_TYPE_COPIER:
419 param_size = sizeof(struct skl_cpr_cfg);
420 param_size += mconfig->formats_config.caps_size;
421 return param_size;
422
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530423 case SKL_MODULE_TYPE_SRCINT:
424 return sizeof(struct skl_src_module_cfg);
425
426 case SKL_MODULE_TYPE_UPDWMIX:
427 return sizeof(struct skl_up_down_mixer_cfg);
428
Jeeja KP399b2102015-11-28 15:01:48 +0530429 case SKL_MODULE_TYPE_ALGO:
430 param_size = sizeof(struct skl_base_cfg);
431 param_size += mconfig->formats_config.caps_size;
432 return param_size;
433
Jeeja KP23db4722015-08-01 19:40:41 +0530434 default:
435 /*
436 * return only base cfg when no specific module type is
437 * specified
438 */
439 return sizeof(struct skl_base_cfg);
440 }
441
442 return 0;
443}
444
445/*
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530446 * DSP firmware supports various modules like copier, SRC, updown etc.
447 * These modules required various parameters to be calculated and sent for
448 * the module initialization to DSP. By default a generic module needs only
449 * base module format configuration
Jeeja KP23db4722015-08-01 19:40:41 +0530450 */
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530451
Jeeja KP23db4722015-08-01 19:40:41 +0530452static int skl_set_module_format(struct skl_sst *ctx,
453 struct skl_module_cfg *module_config,
454 u16 *module_config_size,
455 void **param_data)
456{
457 u16 param_size;
458
459 param_size = skl_get_module_param_size(ctx, module_config);
460
461 *param_data = kzalloc(param_size, GFP_KERNEL);
462 if (NULL == *param_data)
463 return -ENOMEM;
464
465 *module_config_size = param_size;
466
467 switch (module_config->m_type) {
468 case SKL_MODULE_TYPE_COPIER:
469 skl_set_copier_format(ctx, module_config, *param_data);
470 break;
471
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530472 case SKL_MODULE_TYPE_SRCINT:
473 skl_set_src_format(ctx, module_config, *param_data);
474 break;
475
476 case SKL_MODULE_TYPE_UPDWMIX:
477 skl_set_updown_mixer_format(ctx, module_config, *param_data);
478 break;
479
Jeeja KP399b2102015-11-28 15:01:48 +0530480 case SKL_MODULE_TYPE_ALGO:
481 skl_set_algo_format(ctx, module_config, *param_data);
482 break;
483
Jeeja KP23db4722015-08-01 19:40:41 +0530484 default:
485 skl_set_base_module_format(ctx, module_config, *param_data);
486 break;
487
488 }
489
490 dev_dbg(ctx->dev, "Module type=%d config size: %d bytes\n",
491 module_config->id.module_id, param_size);
492 print_hex_dump(KERN_DEBUG, "Module params:", DUMP_PREFIX_OFFSET, 8, 4,
493 *param_data, param_size, false);
494 return 0;
495}
496
497static int skl_get_queue_index(struct skl_module_pin *mpin,
498 struct skl_module_inst_id id, int max)
499{
500 int i;
501
502 for (i = 0; i < max; i++) {
503 if (mpin[i].id.module_id == id.module_id &&
504 mpin[i].id.instance_id == id.instance_id)
505 return i;
506 }
507
508 return -EINVAL;
509}
510
511/*
512 * Allocates queue for each module.
513 * if dynamic, the pin_index is allocated 0 to max_pin.
514 * In static, the pin_index is fixed based on module_id and instance id
515 */
516static int skl_alloc_queue(struct skl_module_pin *mpin,
Jeeja KP4f745702015-10-27 09:22:49 +0900517 struct skl_module_cfg *tgt_cfg, int max)
Jeeja KP23db4722015-08-01 19:40:41 +0530518{
519 int i;
Jeeja KP4f745702015-10-27 09:22:49 +0900520 struct skl_module_inst_id id = tgt_cfg->id;
Jeeja KP23db4722015-08-01 19:40:41 +0530521 /*
522 * if pin in dynamic, find first free pin
523 * otherwise find match module and instance id pin as topology will
524 * ensure a unique pin is assigned to this so no need to
525 * allocate/free
526 */
527 for (i = 0; i < max; i++) {
528 if (mpin[i].is_dynamic) {
Jeeja KP4f745702015-10-27 09:22:49 +0900529 if (!mpin[i].in_use &&
530 mpin[i].pin_state == SKL_PIN_UNBIND) {
531
Jeeja KP23db4722015-08-01 19:40:41 +0530532 mpin[i].in_use = true;
533 mpin[i].id.module_id = id.module_id;
534 mpin[i].id.instance_id = id.instance_id;
Jeeja KP4f745702015-10-27 09:22:49 +0900535 mpin[i].tgt_mcfg = tgt_cfg;
Jeeja KP23db4722015-08-01 19:40:41 +0530536 return i;
537 }
538 } else {
539 if (mpin[i].id.module_id == id.module_id &&
Jeeja KP4f745702015-10-27 09:22:49 +0900540 mpin[i].id.instance_id == id.instance_id &&
541 mpin[i].pin_state == SKL_PIN_UNBIND) {
542
543 mpin[i].tgt_mcfg = tgt_cfg;
Jeeja KP23db4722015-08-01 19:40:41 +0530544 return i;
Jeeja KP4f745702015-10-27 09:22:49 +0900545 }
Jeeja KP23db4722015-08-01 19:40:41 +0530546 }
547 }
548
549 return -EINVAL;
550}
551
552static void skl_free_queue(struct skl_module_pin *mpin, int q_index)
553{
554 if (mpin[q_index].is_dynamic) {
555 mpin[q_index].in_use = false;
556 mpin[q_index].id.module_id = 0;
557 mpin[q_index].id.instance_id = 0;
558 }
Jeeja KP4f745702015-10-27 09:22:49 +0900559 mpin[q_index].pin_state = SKL_PIN_UNBIND;
560 mpin[q_index].tgt_mcfg = NULL;
561}
562
563/* Module state will be set to unint, if all the out pin state is UNBIND */
564
565static void skl_clear_module_state(struct skl_module_pin *mpin, int max,
566 struct skl_module_cfg *mcfg)
567{
568 int i;
569 bool found = false;
570
571 for (i = 0; i < max; i++) {
572 if (mpin[i].pin_state == SKL_PIN_UNBIND)
573 continue;
574 found = true;
575 break;
576 }
577
578 if (!found)
579 mcfg->m_state = SKL_MODULE_UNINIT;
580 return;
Jeeja KP23db4722015-08-01 19:40:41 +0530581}
Jeeja KPbeb73b22015-08-01 19:40:43 +0530582
583/*
584 * A module needs to be instanataited in DSP. A mdoule is present in a
585 * collection of module referred as a PIPE.
586 * We first calculate the module format, based on module type and then
587 * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper
588 */
589int skl_init_module(struct skl_sst *ctx,
Jeeja KP9939a9c2015-11-28 15:01:47 +0530590 struct skl_module_cfg *mconfig)
Jeeja KPbeb73b22015-08-01 19:40:43 +0530591{
592 u16 module_config_size = 0;
593 void *param_data = NULL;
594 int ret;
595 struct skl_ipc_init_instance_msg msg;
596
597 dev_dbg(ctx->dev, "%s: module_id = %d instance=%d\n", __func__,
598 mconfig->id.module_id, mconfig->id.instance_id);
599
600 if (mconfig->pipe->state != SKL_PIPE_CREATED) {
601 dev_err(ctx->dev, "Pipe not created state= %d pipe_id= %d\n",
602 mconfig->pipe->state, mconfig->pipe->ppl_id);
603 return -EIO;
604 }
605
606 ret = skl_set_module_format(ctx, mconfig,
607 &module_config_size, &param_data);
608 if (ret < 0) {
609 dev_err(ctx->dev, "Failed to set module format ret=%d\n", ret);
610 return ret;
611 }
612
613 msg.module_id = mconfig->id.module_id;
614 msg.instance_id = mconfig->id.instance_id;
615 msg.ppl_instance_id = mconfig->pipe->ppl_id;
616 msg.param_data_size = module_config_size;
617 msg.core_id = mconfig->core_id;
618
619 ret = skl_ipc_init_instance(&ctx->ipc, &msg, param_data);
620 if (ret < 0) {
621 dev_err(ctx->dev, "Failed to init instance ret=%d\n", ret);
622 kfree(param_data);
623 return ret;
624 }
625 mconfig->m_state = SKL_MODULE_INIT_DONE;
626
627 return ret;
628}
629
630static void skl_dump_bind_info(struct skl_sst *ctx, struct skl_module_cfg
631 *src_module, struct skl_module_cfg *dst_module)
632{
633 dev_dbg(ctx->dev, "%s: src module_id = %d src_instance=%d\n",
634 __func__, src_module->id.module_id, src_module->id.instance_id);
635 dev_dbg(ctx->dev, "%s: dst_module=%d dst_instacne=%d\n", __func__,
636 dst_module->id.module_id, dst_module->id.instance_id);
637
638 dev_dbg(ctx->dev, "src_module state = %d dst module state = %d\n",
639 src_module->m_state, dst_module->m_state);
640}
641
642/*
643 * On module freeup, we need to unbind the module with modules
644 * it is already bind.
645 * Find the pin allocated and unbind then using bind_unbind IPC
646 */
647int skl_unbind_modules(struct skl_sst *ctx,
648 struct skl_module_cfg *src_mcfg,
649 struct skl_module_cfg *dst_mcfg)
650{
651 int ret;
652 struct skl_ipc_bind_unbind_msg msg;
653 struct skl_module_inst_id src_id = src_mcfg->id;
654 struct skl_module_inst_id dst_id = dst_mcfg->id;
655 int in_max = dst_mcfg->max_in_queue;
656 int out_max = src_mcfg->max_out_queue;
Jeeja KP4f745702015-10-27 09:22:49 +0900657 int src_index, dst_index, src_pin_state, dst_pin_state;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530658
659 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
660
Jeeja KPbeb73b22015-08-01 19:40:43 +0530661 /* get src queue index */
662 src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max);
663 if (src_index < 0)
664 return -EINVAL;
665
Jeeja KP4f745702015-10-27 09:22:49 +0900666 msg.src_queue = src_index;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530667
668 /* get dst queue index */
669 dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max);
670 if (dst_index < 0)
671 return -EINVAL;
672
Jeeja KP4f745702015-10-27 09:22:49 +0900673 msg.dst_queue = dst_index;
674
675 src_pin_state = src_mcfg->m_out_pin[src_index].pin_state;
676 dst_pin_state = dst_mcfg->m_in_pin[dst_index].pin_state;
677
678 if (src_pin_state != SKL_PIN_BIND_DONE ||
679 dst_pin_state != SKL_PIN_BIND_DONE)
680 return 0;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530681
682 msg.module_id = src_mcfg->id.module_id;
683 msg.instance_id = src_mcfg->id.instance_id;
684 msg.dst_module_id = dst_mcfg->id.module_id;
685 msg.dst_instance_id = dst_mcfg->id.instance_id;
686 msg.bind = false;
687
688 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
689 if (!ret) {
Jeeja KPbeb73b22015-08-01 19:40:43 +0530690 /* free queue only if unbind is success */
691 skl_free_queue(src_mcfg->m_out_pin, src_index);
692 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
Jeeja KP4f745702015-10-27 09:22:49 +0900693
694 /*
695 * check only if src module bind state, bind is
696 * always from src -> sink
697 */
698 skl_clear_module_state(src_mcfg->m_out_pin, out_max, src_mcfg);
Jeeja KPbeb73b22015-08-01 19:40:43 +0530699 }
700
701 return ret;
702}
703
704/*
705 * Once a module is instantiated it need to be 'bind' with other modules in
706 * the pipeline. For binding we need to find the module pins which are bind
707 * together
708 * This function finds the pins and then sends bund_unbind IPC message to
709 * DSP using IPC helper
710 */
711int skl_bind_modules(struct skl_sst *ctx,
712 struct skl_module_cfg *src_mcfg,
713 struct skl_module_cfg *dst_mcfg)
714{
715 int ret;
716 struct skl_ipc_bind_unbind_msg msg;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530717 int in_max = dst_mcfg->max_in_queue;
718 int out_max = src_mcfg->max_out_queue;
719 int src_index, dst_index;
720
721 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
722
723 if (src_mcfg->m_state < SKL_MODULE_INIT_DONE &&
724 dst_mcfg->m_state < SKL_MODULE_INIT_DONE)
725 return 0;
726
Jeeja KP4f745702015-10-27 09:22:49 +0900727 src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_mcfg, out_max);
Jeeja KPbeb73b22015-08-01 19:40:43 +0530728 if (src_index < 0)
729 return -EINVAL;
730
Jeeja KP4f745702015-10-27 09:22:49 +0900731 msg.src_queue = src_index;
732 dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_mcfg, in_max);
Jeeja KPbeb73b22015-08-01 19:40:43 +0530733 if (dst_index < 0) {
734 skl_free_queue(src_mcfg->m_out_pin, src_index);
735 return -EINVAL;
736 }
737
Jeeja KP4f745702015-10-27 09:22:49 +0900738 msg.dst_queue = dst_index;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530739
740 dev_dbg(ctx->dev, "src queue = %d dst queue =%d\n",
741 msg.src_queue, msg.dst_queue);
742
743 msg.module_id = src_mcfg->id.module_id;
744 msg.instance_id = src_mcfg->id.instance_id;
745 msg.dst_module_id = dst_mcfg->id.module_id;
746 msg.dst_instance_id = dst_mcfg->id.instance_id;
747 msg.bind = true;
748
749 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
750
751 if (!ret) {
752 src_mcfg->m_state = SKL_MODULE_BIND_DONE;
Jeeja KP4f745702015-10-27 09:22:49 +0900753 src_mcfg->m_out_pin[src_index].pin_state = SKL_PIN_BIND_DONE;
754 dst_mcfg->m_in_pin[dst_index].pin_state = SKL_PIN_BIND_DONE;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530755 } else {
756 /* error case , if IPC fails, clear the queue index */
757 skl_free_queue(src_mcfg->m_out_pin, src_index);
758 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
759 }
760
761 return ret;
762}
Jeeja KPc9b1e832015-08-01 19:40:44 +0530763
764static int skl_set_pipe_state(struct skl_sst *ctx, struct skl_pipe *pipe,
765 enum skl_ipc_pipeline_state state)
766{
767 dev_dbg(ctx->dev, "%s: pipe_satate = %d\n", __func__, state);
768
769 return skl_ipc_set_pipeline_state(&ctx->ipc, pipe->ppl_id, state);
770}
771
772/*
773 * A pipeline is a collection of modules. Before a module in instantiated a
774 * pipeline needs to be created for it.
775 * This function creates pipeline, by sending create pipeline IPC messages
776 * to FW
777 */
778int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe)
779{
780 int ret;
781
782 dev_dbg(ctx->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id);
783
784 ret = skl_ipc_create_pipeline(&ctx->ipc, pipe->memory_pages,
785 pipe->pipe_priority, pipe->ppl_id);
786 if (ret < 0) {
787 dev_err(ctx->dev, "Failed to create pipeline\n");
788 return ret;
789 }
790
791 pipe->state = SKL_PIPE_CREATED;
792
793 return 0;
794}
795
796/*
797 * A pipeline needs to be deleted on cleanup. If a pipeline is running, then
798 * pause the pipeline first and then delete it
799 * The pipe delete is done by sending delete pipeline IPC. DSP will stop the
800 * DMA engines and releases resources
801 */
802int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
803{
804 int ret;
805
806 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
807
808 /* If pipe is not started, do not try to stop the pipe in FW. */
809 if (pipe->state > SKL_PIPE_STARTED) {
810 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
811 if (ret < 0) {
812 dev_err(ctx->dev, "Failed to stop pipeline\n");
813 return ret;
814 }
815
816 pipe->state = SKL_PIPE_PAUSED;
817 } else {
818 /* If pipe was not created in FW, do not try to delete it */
819 if (pipe->state < SKL_PIPE_CREATED)
820 return 0;
821
822 ret = skl_ipc_delete_pipeline(&ctx->ipc, pipe->ppl_id);
823 if (ret < 0)
824 dev_err(ctx->dev, "Failed to delete pipeline\n");
825 }
826
827 return ret;
828}
829
830/*
831 * A pipeline is also a scheduling entity in DSP which can be run, stopped
832 * For processing data the pipe need to be run by sending IPC set pipe state
833 * to DSP
834 */
835int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
836{
837 int ret;
838
839 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
840
841 /* If pipe was not created in FW, do not try to pause or delete */
842 if (pipe->state < SKL_PIPE_CREATED)
843 return 0;
844
845 /* Pipe has to be paused before it is started */
846 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
847 if (ret < 0) {
848 dev_err(ctx->dev, "Failed to pause pipe\n");
849 return ret;
850 }
851
852 pipe->state = SKL_PIPE_PAUSED;
853
854 ret = skl_set_pipe_state(ctx, pipe, PPL_RUNNING);
855 if (ret < 0) {
856 dev_err(ctx->dev, "Failed to start pipe\n");
857 return ret;
858 }
859
860 pipe->state = SKL_PIPE_STARTED;
861
862 return 0;
863}
864
865/*
866 * Stop the pipeline by sending set pipe state IPC
867 * DSP doesnt implement stop so we always send pause message
868 */
869int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
870{
871 int ret;
872
873 dev_dbg(ctx->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id);
874
875 /* If pipe was not created in FW, do not try to pause or delete */
876 if (pipe->state < SKL_PIPE_PAUSED)
877 return 0;
878
879 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
880 if (ret < 0) {
881 dev_dbg(ctx->dev, "Failed to stop pipe\n");
882 return ret;
883 }
884
885 pipe->state = SKL_PIPE_CREATED;
886
887 return 0;
888}
Jeeja KP9939a9c2015-11-28 15:01:47 +0530889
890/* Algo parameter set helper function */
891int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
892 u32 param_id, struct skl_module_cfg *mcfg)
893{
894 struct skl_ipc_large_config_msg msg;
895
896 msg.module_id = mcfg->id.module_id;
897 msg.instance_id = mcfg->id.instance_id;
898 msg.param_data_size = size;
899 msg.large_param_id = param_id;
900
901 return skl_ipc_set_large_config(&ctx->ipc, &msg, params);
902}