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Jon Loeligeref82a302006-06-17 17:52:55 -05001/*
2 * Driver for Vitesse PHYs
3 *
4 * Author: Kriston Carson
5 *
Madalin Bucur3fb69bc2013-11-20 16:38:19 -06006 * Copyright (c) 2005, 2009, 2011 Freescale Semiconductor, Inc.
Jon Loeligeref82a302006-06-17 17:52:55 -05007 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
Jon Loeligeref82a302006-06-17 17:52:55 -050015#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mii.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20
Madalin Bucur3fb69bc2013-11-20 16:38:19 -060021/* Vitesse Extended Page Magic Register(s) */
22#define MII_VSC82X4_EXT_PAGE_16E 0x10
23#define MII_VSC82X4_EXT_PAGE_17E 0x11
24#define MII_VSC82X4_EXT_PAGE_18E 0x12
25
Jon Loeligeref82a302006-06-17 17:52:55 -050026/* Vitesse Extended Control Register 1 */
27#define MII_VSC8244_EXT_CON1 0x17
28#define MII_VSC8244_EXTCON1_INIT 0x0000
Andy Flemingaf2d9402007-07-11 11:42:35 -050029#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
30#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
31#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
32#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
Jon Loeligeref82a302006-06-17 17:52:55 -050033
34/* Vitesse Interrupt Mask Register */
35#define MII_VSC8244_IMASK 0x19
36#define MII_VSC8244_IMASK_IEN 0x8000
37#define MII_VSC8244_IMASK_SPEED 0x4000
38#define MII_VSC8244_IMASK_LINK 0x2000
39#define MII_VSC8244_IMASK_DUPLEX 0x1000
40#define MII_VSC8244_IMASK_MASK 0xf000
41
Trent Piepho11c6dd22008-11-25 01:00:47 -080042#define MII_VSC8221_IMASK_MASK 0xa000
43
Jon Loeligeref82a302006-06-17 17:52:55 -050044/* Vitesse Interrupt Status Register */
45#define MII_VSC8244_ISTAT 0x1a
46#define MII_VSC8244_ISTAT_STATUS 0x8000
47#define MII_VSC8244_ISTAT_SPEED 0x4000
48#define MII_VSC8244_ISTAT_LINK 0x2000
49#define MII_VSC8244_ISTAT_DUPLEX 0x1000
50
51/* Vitesse Auxiliary Control/Status Register */
Michal Simek2a8626d2013-05-30 20:08:23 +000052#define MII_VSC8244_AUX_CONSTAT 0x1c
53#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
54#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
55#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
56#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
57#define MII_VSC8244_AUXCONSTAT_100 0x0008
Jon Loeligeref82a302006-06-17 17:52:55 -050058
Trent Piepho11c6dd22008-11-25 01:00:47 -080059#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
60#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
61
Madalin Bucur3fb69bc2013-11-20 16:38:19 -060062/* Vitesse Extended Page Access Register */
63#define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
64
Andy Fleming05080192013-11-20 16:38:16 -060065#define PHY_ID_VSC8234 0x000fc620
Trent Piepho11c6dd22008-11-25 01:00:47 -080066#define PHY_ID_VSC8244 0x000fc6c0
shaohui xiec2efef72013-11-20 16:38:17 -060067#define PHY_ID_VSC8574 0x000704a0
Sandeep Singh06ae4f82013-11-20 16:38:18 -060068#define PHY_ID_VSC8662 0x00070660
Trent Piepho11c6dd22008-11-25 01:00:47 -080069#define PHY_ID_VSC8221 0x000fc550
Michal Simek5a1cebd2013-05-30 20:08:24 +000070#define PHY_ID_VSC8211 0x000fc4b0
Trent Piepho11c6dd22008-11-25 01:00:47 -080071
Jon Loeligeref82a302006-06-17 17:52:55 -050072MODULE_DESCRIPTION("Vitesse PHY driver");
73MODULE_AUTHOR("Kriston Carson");
74MODULE_LICENSE("GPL");
75
stephen hemmingerbaec1262013-03-08 09:07:42 +000076static int vsc824x_add_skew(struct phy_device *phydev)
Andy Flemingfddf86f2011-10-13 04:33:55 +000077{
78 int err;
79 int extcon;
80
81 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
82
83 if (extcon < 0)
84 return extcon;
85
86 extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
87 MII_VSC8244_EXTCON1_RX_SKEW_MASK);
88
89 extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
90 MII_VSC8244_EXTCON1_RX_SKEW);
91
92 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
93
94 return err;
95}
Andy Flemingfddf86f2011-10-13 04:33:55 +000096
Jon Loeligeref82a302006-06-17 17:52:55 -050097static int vsc824x_config_init(struct phy_device *phydev)
98{
99 int err;
100
101 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
102 MII_VSC8244_AUXCONSTAT_INIT);
103 if (err < 0)
104 return err;
105
Andy Flemingaf2d9402007-07-11 11:42:35 -0500106 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
Andy Flemingfddf86f2011-10-13 04:33:55 +0000107 err = vsc824x_add_skew(phydev);
Andy Flemingaf2d9402007-07-11 11:42:35 -0500108
Jon Loeligeref82a302006-06-17 17:52:55 -0500109 return err;
110}
111
112static int vsc824x_ack_interrupt(struct phy_device *phydev)
113{
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500114 int err = 0;
Michal Simek2a8626d2013-05-30 20:08:23 +0000115
116 /* Don't bother to ACK the interrupts if interrupts
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500117 * are disabled. The 824x cannot clear the interrupts
118 * if they are disabled.
119 */
120 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
121 err = phy_read(phydev, MII_VSC8244_ISTAT);
Jon Loeligeref82a302006-06-17 17:52:55 -0500122
123 return (err < 0) ? err : 0;
124}
125
Trent Piepho11c6dd22008-11-25 01:00:47 -0800126static int vsc82xx_config_intr(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500127{
128 int err;
129
130 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
131 err = phy_write(phydev, MII_VSC8244_IMASK,
Andy Fleming05080192013-11-20 16:38:16 -0600132 (phydev->drv->phy_id == PHY_ID_VSC8234 ||
shaohui xiec2efef72013-11-20 16:38:17 -0600133 phydev->drv->phy_id == PHY_ID_VSC8244 ||
134 phydev->drv->phy_id == PHY_ID_VSC8574) ?
Trent Piepho11c6dd22008-11-25 01:00:47 -0800135 MII_VSC8244_IMASK_MASK :
136 MII_VSC8221_IMASK_MASK);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500137 else {
Michal Simek2a8626d2013-05-30 20:08:23 +0000138 /* The Vitesse PHY cannot clear the interrupt
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500139 * once it has disabled them, so we clear them first
140 */
141 err = phy_read(phydev, MII_VSC8244_ISTAT);
142
Andy Fleming52cb1c22007-07-18 01:06:28 -0500143 if (err < 0)
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500144 return err;
145
Jon Loeligeref82a302006-06-17 17:52:55 -0500146 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500147 }
148
Jon Loeligeref82a302006-06-17 17:52:55 -0500149 return err;
150}
151
Trent Piepho11c6dd22008-11-25 01:00:47 -0800152static int vsc8221_config_init(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500153{
Trent Piepho11c6dd22008-11-25 01:00:47 -0800154 int err;
155
156 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
157 MII_VSC8221_AUXCONSTAT_INIT);
158 return err;
159
160 /* Perhaps we should set EXT_CON1 based on the interface?
Michal Simek2a8626d2013-05-30 20:08:23 +0000161 * Options are 802.3Z SerDes or SGMII
162 */
Jon Loeligeref82a302006-06-17 17:52:55 -0500163}
164
Madalin Bucur3fb69bc2013-11-20 16:38:19 -0600165/* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
166 * @phydev: target phy_device struct
167 *
168 * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
169 * special values in the VSC8234/VSC8244 extended reserved registers
170 */
171static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
172{
173 int ret;
174
175 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
176 return 0;
177
178 /* map extended registers set 0x10 - 0x1e */
179 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
180 if (ret >= 0)
181 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
182 if (ret >= 0)
183 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
184 if (ret >= 0)
185 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
186 /* map standard registers set 0x10 - 0x1e */
187 if (ret >= 0)
188 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
189 else
190 phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
191
192 return ret;
193}
194
195/* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
196 * @phydev: target phy_device struct
197 *
198 * Description: If auto-negotiation is enabled, we configure the
199 * advertising, and then restart auto-negotiation. If it is not
200 * enabled, then we write the BMCR and also start the auto
201 * MDI/MDI-X feature
202 */
203static int vsc82x4_config_aneg(struct phy_device *phydev)
204{
205 int ret;
206
207 /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
208 * writing special values in the VSC8234 extended reserved registers
209 */
210 if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
211 ret = genphy_setup_forced(phydev);
212
213 if (ret < 0) /* error */
214 return ret;
215
216 return vsc82x4_config_autocross_enable(phydev);
217 }
218
219 return genphy_config_aneg(phydev);
220}
221
Andy Fleming05080192013-11-20 16:38:16 -0600222/* Vitesse 82xx */
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000223static struct phy_driver vsc82xx_driver[] = {
224{
Andy Fleming05080192013-11-20 16:38:16 -0600225 .phy_id = PHY_ID_VSC8234,
226 .name = "Vitesse VSC8234",
227 .phy_id_mask = 0x000ffff0,
228 .features = PHY_GBIT_FEATURES,
229 .flags = PHY_HAS_INTERRUPT,
230 .config_init = &vsc824x_config_init,
Madalin Bucur3fb69bc2013-11-20 16:38:19 -0600231 .config_aneg = &vsc82x4_config_aneg,
Andy Fleming05080192013-11-20 16:38:16 -0600232 .read_status = &genphy_read_status,
233 .ack_interrupt = &vsc824x_ack_interrupt,
234 .config_intr = &vsc82xx_config_intr,
235 .driver = { .owner = THIS_MODULE,},
236}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000237 .phy_id = PHY_ID_VSC8244,
238 .name = "Vitesse VSC8244",
239 .phy_id_mask = 0x000fffc0,
240 .features = PHY_GBIT_FEATURES,
241 .flags = PHY_HAS_INTERRUPT,
242 .config_init = &vsc824x_config_init,
Madalin Bucur3fb69bc2013-11-20 16:38:19 -0600243 .config_aneg = &vsc82x4_config_aneg,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000244 .read_status = &genphy_read_status,
245 .ack_interrupt = &vsc824x_ack_interrupt,
246 .config_intr = &vsc82xx_config_intr,
247 .driver = { .owner = THIS_MODULE,},
248}, {
shaohui xiec2efef72013-11-20 16:38:17 -0600249 .phy_id = PHY_ID_VSC8574,
250 .name = "Vitesse VSC8574",
251 .phy_id_mask = 0x000ffff0,
252 .features = PHY_GBIT_FEATURES,
253 .flags = PHY_HAS_INTERRUPT,
254 .config_init = &vsc824x_config_init,
Madalin Bucur3fb69bc2013-11-20 16:38:19 -0600255 .config_aneg = &vsc82x4_config_aneg,
shaohui xiec2efef72013-11-20 16:38:17 -0600256 .read_status = &genphy_read_status,
257 .ack_interrupt = &vsc824x_ack_interrupt,
258 .config_intr = &vsc82xx_config_intr,
259 .driver = { .owner = THIS_MODULE,},
260}, {
Sandeep Singh06ae4f82013-11-20 16:38:18 -0600261 .phy_id = PHY_ID_VSC8662,
262 .name = "Vitesse VSC8662",
263 .phy_id_mask = 0x000ffff0,
264 .features = PHY_GBIT_FEATURES,
265 .flags = PHY_HAS_INTERRUPT,
266 .config_init = &vsc824x_config_init,
Madalin Bucur3fb69bc2013-11-20 16:38:19 -0600267 .config_aneg = &vsc82x4_config_aneg,
Sandeep Singh06ae4f82013-11-20 16:38:18 -0600268 .read_status = &genphy_read_status,
269 .ack_interrupt = &vsc824x_ack_interrupt,
270 .config_intr = &vsc82xx_config_intr,
271 .driver = { .owner = THIS_MODULE,},
272}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000273 /* Vitesse 8221 */
Trent Piepho11c6dd22008-11-25 01:00:47 -0800274 .phy_id = PHY_ID_VSC8221,
275 .phy_id_mask = 0x000ffff0,
276 .name = "Vitesse VSC8221",
277 .features = PHY_GBIT_FEATURES,
278 .flags = PHY_HAS_INTERRUPT,
279 .config_init = &vsc8221_config_init,
280 .config_aneg = &genphy_config_aneg,
281 .read_status = &genphy_read_status,
282 .ack_interrupt = &vsc824x_ack_interrupt,
283 .config_intr = &vsc82xx_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000284 .driver = { .owner = THIS_MODULE,},
Michal Simek5a1cebd2013-05-30 20:08:24 +0000285}, {
286 /* Vitesse 8211 */
287 .phy_id = PHY_ID_VSC8211,
288 .phy_id_mask = 0x000ffff0,
289 .name = "Vitesse VSC8211",
290 .features = PHY_GBIT_FEATURES,
291 .flags = PHY_HAS_INTERRUPT,
292 .config_init = &vsc8221_config_init,
293 .config_aneg = &genphy_config_aneg,
294 .read_status = &genphy_read_status,
295 .ack_interrupt = &vsc824x_ack_interrupt,
296 .config_intr = &vsc82xx_config_intr,
297 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000298} };
Trent Piepho11c6dd22008-11-25 01:00:47 -0800299
300static int __init vsc82xx_init(void)
301{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000302 return phy_drivers_register(vsc82xx_driver,
303 ARRAY_SIZE(vsc82xx_driver));
Trent Piepho11c6dd22008-11-25 01:00:47 -0800304}
305
306static void __exit vsc82xx_exit(void)
Jon Loeligeref82a302006-06-17 17:52:55 -0500307{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000308 return phy_drivers_unregister(vsc82xx_driver,
309 ARRAY_SIZE(vsc82xx_driver));
Jon Loeligeref82a302006-06-17 17:52:55 -0500310}
311
Trent Piepho11c6dd22008-11-25 01:00:47 -0800312module_init(vsc82xx_init);
313module_exit(vsc82xx_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000314
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000315static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
Andy Fleming05080192013-11-20 16:38:16 -0600316 { PHY_ID_VSC8234, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000317 { PHY_ID_VSC8244, 0x000fffc0 },
shaohui xiec2efef72013-11-20 16:38:17 -0600318 { PHY_ID_VSC8574, 0x000ffff0 },
Sandeep Singh06ae4f82013-11-20 16:38:18 -0600319 { PHY_ID_VSC8662, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000320 { PHY_ID_VSC8221, 0x000ffff0 },
Michal Simek5a1cebd2013-05-30 20:08:24 +0000321 { PHY_ID_VSC8211, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000322 { }
323};
324
325MODULE_DEVICE_TABLE(mdio, vitesse_tbl);