blob: 523f9d05a810f175582e5b1474f4d398bfa0aea2 [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -07001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Mark Rustad37689012016-01-07 10:13:03 -08004 Copyright(c) 1999 - 2016 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Jacob Kellerb89aae72014-02-22 01:23:50 +000023 Linux NICS <linux.nics@intel.com>
Auke Kok9a799d72007-09-15 14:07:45 -070024 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
Stephen Hemminger9c8eb722007-10-29 10:46:24 -070033#include "ixgbe.h"
Auke Kok9a799d72007-09-15 14:07:45 -070034#include "ixgbe_phy.h"
35
36#define IXGBE_82598_MAX_TX_QUEUES 32
37#define IXGBE_82598_MAX_RX_QUEUES 64
38#define IXGBE_82598_RAR_ENTRIES 16
Christopher Leech2c5645c2008-08-26 04:27:02 -070039#define IXGBE_82598_MC_TBL_SIZE 128
40#define IXGBE_82598_VFT_TBL_SIZE 128
John Fastabende09ad232011-04-04 04:29:41 +000041#define IXGBE_82598_RX_PB_SIZE 512
Auke Kok9a799d72007-09-15 14:07:45 -070042
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000043static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +000044 ixgbe_link_speed speed,
45 bool autoneg_wait_to_complete);
Donald Skidmorec4900be2008-11-20 21:11:42 -080046static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
Jacob Kellere7cf7452014-04-09 06:03:10 +000047 u8 *eeprom_data);
Auke Kok9a799d72007-09-15 14:07:45 -070048
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070049/**
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000050 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
51 * @hw: pointer to the HW structure
52 *
53 * The defaults for 82598 should be in the range of 50us to 50ms,
54 * however the hardware default for these parts is 500us to 1ms which is less
55 * than the 10ms recommended by the pci-e spec. To address this we need to
56 * increase the value to either 10ms to 250ms for capability version 1 config,
57 * or 16ms to 55ms for version 2.
58 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +000059static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000060{
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000061 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
62 u16 pcie_devctl2;
63
Mark Rustad14438462014-02-28 15:48:57 -080064 if (ixgbe_removed(hw->hw_addr))
65 return;
66
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000067 /* only take action if timeout value is defaulted to 0 */
68 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
69 goto out;
70
71 /*
72 * if capababilities version is type 1 we can write the
73 * timeout of 10ms to 250ms through the GCR register
74 */
75 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
76 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
77 goto out;
78 }
79
80 /*
81 * for version 2 capabilities we need to write the config space
82 * directly in order to set the completion timeout value for
83 * 16ms to 55ms
84 */
Mark Rustad14438462014-02-28 15:48:57 -080085 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000086 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
Jacob Kellered192312014-02-22 01:23:53 +000087 ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +000088out:
89 /* disable completion timeout resend */
90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
92}
93
Auke Kok9a799d72007-09-15 14:07:45 -070094static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
95{
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070096 struct ixgbe_mac_info *mac = &hw->mac;
PJ Waskiewicz03cfa202009-03-19 01:23:29 +000097
Jesse Brandeburgc44ade92008-09-11 19:59:59 -070098 /* Call PHY identify routine to get the phy type */
99 ixgbe_identify_phy_generic(hw);
Auke Kok3957d632007-10-31 15:22:10 -0700100
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000101 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
102 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
103 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
Jacob Keller6997d4d2014-02-22 01:23:49 +0000104 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000105 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
106 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
Emil Tantilov71161302012-03-22 03:00:29 +0000107 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000108
109 return 0;
110}
111
112/**
113 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
114 * @hw: pointer to hardware structure
115 *
116 * Initialize any function pointers that were not able to be
117 * set during get_invariants because the PHY/SFP type was
118 * not known. Perform the SFP init if necessary.
119 *
120 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000121static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000122{
123 struct ixgbe_mac_info *mac = &hw->mac;
124 struct ixgbe_phy_info *phy = &hw->phy;
Mark Rustade90dd262014-07-22 06:51:08 +0000125 s32 ret_val;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000126 u16 list_offset, data_offset;
127
128 /* Identify the PHY */
129 phy->ops.identify(hw);
130
131 /* Overwrite the link function pointers if copper PHY */
132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
133 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000134 mac->ops.get_link_capabilities =
Don Skidmorea391f1d2010-11-16 19:27:15 -0800135 &ixgbe_get_copper_link_capabilities_generic;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000136 }
137
138 switch (hw->phy.type) {
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700139 case ixgbe_phy_tn:
Emil Tantilov9dda1732011-03-05 01:28:07 +0000140 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700141 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700142 break;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800143 case ixgbe_phy_nl:
144 phy->ops.reset = &ixgbe_reset_phy_nl;
145
146 /* Call SFP+ identify routine to get the SFP+ module type */
147 ret_val = phy->ops.identify_sfp(hw);
Mark Rustade90dd262014-07-22 06:51:08 +0000148 if (ret_val)
149 return ret_val;
150 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
151 return IXGBE_ERR_SFP_NOT_SUPPORTED;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800152
153 /* Check to see if SFP+ module is supported */
154 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000155 &list_offset,
156 &data_offset);
Mark Rustade90dd262014-07-22 06:51:08 +0000157 if (ret_val)
158 return IXGBE_ERR_SFP_NOT_SUPPORTED;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800159 break;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700160 default:
161 break;
Auke Kok3957d632007-10-31 15:22:10 -0700162 }
163
Mark Rustade90dd262014-07-22 06:51:08 +0000164 return 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700165}
166
167/**
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000168 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
169 * @hw: pointer to hardware structure
170 *
171 * Starts the hardware using the generic start_hw function.
Jeff Kirsher887012e2015-03-13 14:04:35 -0700172 * Disables relaxed ordering for archs other than SPARC
173 * Then set pcie completion timeout
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000174 *
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000175 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000176static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000177{
Jeff Kirsher887012e2015-03-13 14:04:35 -0700178#ifndef CONFIG_SPARC
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000179 u32 regval;
180 u32 i;
Jeff Kirsher887012e2015-03-13 14:04:35 -0700181#endif
Mark Rustade90dd262014-07-22 06:51:08 +0000182 s32 ret_val;
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000183
184 ret_val = ixgbe_start_hw_generic(hw);
185
Jeff Kirsher887012e2015-03-13 14:04:35 -0700186#ifndef CONFIG_SPARC
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000187 /* Disable relaxed ordering */
188 for (i = 0; ((i < hw->mac.max_tx_queues) &&
189 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
190 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
Alexander Duyckbdda1a62012-02-08 07:50:14 +0000191 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000192 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
193 }
194
195 for (i = 0; ((i < hw->mac.max_rx_queues) &&
196 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
197 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
Alexander Duyckbdda1a62012-02-08 07:50:14 +0000198 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
199 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
Emil Tantilov3d5c5202011-03-19 01:32:46 +0000200 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
201 }
Jeff Kirsher887012e2015-03-13 14:04:35 -0700202#endif
Mark Rustade90dd262014-07-22 06:51:08 +0000203 if (ret_val)
204 return ret_val;
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000205
Mark Rustade90dd262014-07-22 06:51:08 +0000206 /* set the completion timeout for interface */
207 ixgbe_set_pcie_completion_timeout(hw);
208
209 return 0;
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +0000210}
211
212/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700213 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
Auke Kok9a799d72007-09-15 14:07:45 -0700214 * @hw: pointer to hardware structure
215 * @speed: pointer to link speed
216 * @autoneg: boolean auto-negotiation value
217 *
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700218 * Determines the link capabilities by reading the AUTOC register.
Auke Kok9a799d72007-09-15 14:07:45 -0700219 **/
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700220static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000221 ixgbe_link_speed *speed,
222 bool *autoneg)
Auke Kok9a799d72007-09-15 14:07:45 -0700223{
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000224 u32 autoc = 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700225
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800226 /*
227 * Determine link capabilities based on the stored value of AUTOC,
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000228 * which represents EEPROM defaults. If AUTOC value has not been
229 * stored, use the current register value.
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800230 */
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000231 if (hw->mac.orig_link_settings_stored)
232 autoc = hw->mac.orig_autoc;
233 else
234 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
235
236 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
Auke Kok9a799d72007-09-15 14:07:45 -0700237 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
238 *speed = IXGBE_LINK_SPEED_1GB_FULL;
239 *autoneg = false;
240 break;
241
242 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
243 *speed = IXGBE_LINK_SPEED_10GB_FULL;
244 *autoneg = false;
245 break;
246
247 case IXGBE_AUTOC_LMS_1G_AN:
248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
249 *autoneg = true;
250 break;
251
252 case IXGBE_AUTOC_LMS_KX4_AN:
253 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
254 *speed = IXGBE_LINK_SPEED_UNKNOWN;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
Auke Kok9a799d72007-09-15 14:07:45 -0700256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000257 if (autoc & IXGBE_AUTOC_KX_SUPP)
Auke Kok9a799d72007-09-15 14:07:45 -0700258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *autoneg = true;
260 break;
261
262 default:
Mark Rustade90dd262014-07-22 06:51:08 +0000263 return IXGBE_ERR_LINK_SETUP;
Auke Kok9a799d72007-09-15 14:07:45 -0700264 }
265
Mark Rustade90dd262014-07-22 06:51:08 +0000266 return 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700267}
268
269/**
Auke Kok9a799d72007-09-15 14:07:45 -0700270 * ixgbe_get_media_type_82598 - Determines media type
271 * @hw: pointer to hardware structure
272 *
273 * Returns the media type (fiber, copper, backplane)
274 **/
275static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
276{
Emil Tantilov037c6d02011-02-25 07:49:39 +0000277 /* Detect if there is a copper PHY attached. */
278 switch (hw->phy.type) {
279 case ixgbe_phy_cu_unknown:
280 case ixgbe_phy_tn:
Mark Rustade90dd262014-07-22 06:51:08 +0000281 return ixgbe_media_type_copper;
282
Emil Tantilov037c6d02011-02-25 07:49:39 +0000283 default:
284 break;
285 }
286
Auke Kok9a799d72007-09-15 14:07:45 -0700287 /* Media type for I82598 is based on device ID */
288 switch (hw->device_id) {
Don Skidmore1e336d02009-01-26 20:57:51 -0800289 case IXGBE_DEV_ID_82598:
Don Skidmore2f21bdd2009-02-01 01:18:23 -0800290 case IXGBE_DEV_ID_82598_BX:
Emil Tantilov037c6d02011-02-25 07:49:39 +0000291 /* Default device ID is mezzanine card KX/KX4 */
Mark Rustade90dd262014-07-22 06:51:08 +0000292 return ixgbe_media_type_backplane;
293
Auke Kok9a799d72007-09-15 14:07:45 -0700294 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
295 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
Donald Skidmorec4900be2008-11-20 21:11:42 -0800296 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
297 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
Jesse Brandeburgb95f5fc2008-09-11 19:58:59 -0700298 case IXGBE_DEV_ID_82598EB_XF_LR:
Donald Skidmorec4900be2008-11-20 21:11:42 -0800299 case IXGBE_DEV_ID_82598EB_SFP_LOM:
Mark Rustade90dd262014-07-22 06:51:08 +0000300 return ixgbe_media_type_fiber;
301
Peter P Waskiewicz Jr6b1be192009-09-14 07:48:10 +0000302 case IXGBE_DEV_ID_82598EB_CX4:
303 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
Mark Rustade90dd262014-07-22 06:51:08 +0000304 return ixgbe_media_type_cx4;
305
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700306 case IXGBE_DEV_ID_82598AT:
Peter P Waskiewicz Jr3845bec2009-07-16 15:50:52 +0000307 case IXGBE_DEV_ID_82598AT2:
Mark Rustade90dd262014-07-22 06:51:08 +0000308 return ixgbe_media_type_copper;
309
Auke Kok9a799d72007-09-15 14:07:45 -0700310 default:
Mark Rustade90dd262014-07-22 06:51:08 +0000311 return ixgbe_media_type_unknown;
Auke Kok9a799d72007-09-15 14:07:45 -0700312 }
Auke Kok9a799d72007-09-15 14:07:45 -0700313}
314
315/**
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800316 * ixgbe_fc_enable_82598 - Enable flow control
317 * @hw: pointer to hardware structure
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800318 *
319 * Enable flow control according to the current settings.
320 **/
Alexander Duyck041441d2012-04-19 17:48:48 +0000321static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800322{
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800323 u32 fctrl_reg;
324 u32 rmcs_reg;
325 u32 reg;
Alexander Duyck041441d2012-04-19 17:48:48 +0000326 u32 fcrtl, fcrth;
Don Skidmorea626e842010-02-11 04:13:49 +0000327 u32 link_speed = 0;
Alexander Duyck041441d2012-04-19 17:48:48 +0000328 int i;
Don Skidmorea626e842010-02-11 04:13:49 +0000329 bool link_up;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800330
Jacob Kellere5776622014-04-05 02:35:52 +0000331 /* Validate the water mark configuration */
Mark Rustade90dd262014-07-22 06:51:08 +0000332 if (!hw->fc.pause_time)
333 return IXGBE_ERR_INVALID_LINK_SETTINGS;
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000334
Jacob Kellere5776622014-04-05 02:35:52 +0000335 /* Low water mark of zero causes XOFF floods */
336 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
337 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
338 hw->fc.high_water[i]) {
339 if (!hw->fc.low_water[i] ||
340 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
341 hw_dbg(hw, "Invalid water mark configuration\n");
Mark Rustade90dd262014-07-22 06:51:08 +0000342 return IXGBE_ERR_INVALID_LINK_SETTINGS;
Jacob Kellere5776622014-04-05 02:35:52 +0000343 }
344 }
345 }
346
Don Skidmorea626e842010-02-11 04:13:49 +0000347 /*
348 * On 82598 having Rx FC on causes resets while doing 1G
349 * so if it's on turn it off once we know link_speed. For
350 * more details see 82598 Specification update.
351 */
352 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
353 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
354 switch (hw->fc.requested_mode) {
355 case ixgbe_fc_full:
356 hw->fc.requested_mode = ixgbe_fc_tx_pause;
357 break;
358 case ixgbe_fc_rx_pause:
359 hw->fc.requested_mode = ixgbe_fc_none;
360 break;
361 default:
362 /* no change */
363 break;
364 }
365 }
366
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000367 /* Negotiate the fc mode to use */
Don Skidmore29165002016-09-27 14:31:12 -0400368 hw->mac.ops.fc_autoneg(hw);
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000369
370 /* Disable any previous flow control settings */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800371 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
372 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
373
374 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
375 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
376
377 /*
378 * The possible values of fc.current_mode are:
379 * 0: Flow control is completely disabled
380 * 1: Rx flow control is enabled (we can receive pause frames,
381 * but not send pause frames).
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000382 * 2: Tx flow control is enabled (we can send pause frames but
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800383 * we do not support receiving pause frames).
384 * 3: Both Rx and Tx flow control (symmetric) are enabled.
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000385 * other: Invalid.
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800386 */
387 switch (hw->fc.current_mode) {
388 case ixgbe_fc_none:
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000389 /*
390 * Flow control is disabled by software override or autoneg.
391 * The code below will actually disable it in the HW.
392 */
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800393 break;
394 case ixgbe_fc_rx_pause:
395 /*
396 * Rx Flow control is enabled and Tx Flow control is
397 * disabled by software override. Since there really
398 * isn't a way to advertise that we are capable of RX
399 * Pause ONLY, we will advertise that we support both
400 * symmetric and asymmetric Rx PAUSE. Later, we will
401 * disable the adapter's ability to send PAUSE frames.
402 */
403 fctrl_reg |= IXGBE_FCTRL_RFCE;
404 break;
405 case ixgbe_fc_tx_pause:
406 /*
407 * Tx Flow control is enabled, and Rx Flow control is
408 * disabled by software override.
409 */
410 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
411 break;
412 case ixgbe_fc_full:
413 /* Flow control (both Rx and Tx) is enabled by SW override. */
414 fctrl_reg |= IXGBE_FCTRL_RFCE;
415 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
416 break;
417 default:
418 hw_dbg(hw, "Flow control param set incorrectly\n");
Mark Rustade90dd262014-07-22 06:51:08 +0000419 return IXGBE_ERR_CONFIG;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800420 }
421
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000422 /* Set 802.3x based flow control settings. */
PJ Waskiewicz2132d382009-04-09 22:26:21 +0000423 fctrl_reg |= IXGBE_FCTRL_DPF;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800424 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
425 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
426
427 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
Alexander Duyck041441d2012-04-19 17:48:48 +0000428 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
429 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
430 hw->fc.high_water[i]) {
Jacob Kellere5776622014-04-05 02:35:52 +0000431 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
Alexander Duyck041441d2012-04-19 17:48:48 +0000432 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
433 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
434 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
435 } else {
436 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
437 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
438 }
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000439
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800440 }
441
442 /* Configure pause time (2 TCs per register) */
Alexander Duyck041441d2012-04-19 17:48:48 +0000443 reg = hw->fc.pause_time * 0x00010001;
444 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
445 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800446
Alexander Duyck041441d2012-04-19 17:48:48 +0000447 /* Configure flow control refresh threshold value */
448 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800449
Mark Rustade90dd262014-07-22 06:51:08 +0000450 return 0;
Peter P Waskiewicz Jr0ecc0612009-02-06 21:46:54 -0800451}
452
453/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000454 * ixgbe_start_mac_link_82598 - Configures MAC link settings
Auke Kok9a799d72007-09-15 14:07:45 -0700455 * @hw: pointer to hardware structure
456 *
457 * Configures link settings based on values in the ixgbe_hw struct.
458 * Restarts the link. Performs autonegotiation if needed.
459 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000460static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000461 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700462{
463 u32 autoc_reg;
464 u32 links_reg;
465 u32 i;
466 s32 status = 0;
467
Auke Kok9a799d72007-09-15 14:07:45 -0700468 /* Restart link */
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800469 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
Auke Kok9a799d72007-09-15 14:07:45 -0700470 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
471 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
472
473 /* Only poll for autoneg to complete if specified to do so */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000474 if (autoneg_wait_to_complete) {
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800475 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
476 IXGBE_AUTOC_LMS_KX4_AN ||
477 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
478 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
Auke Kok9a799d72007-09-15 14:07:45 -0700479 links_reg = 0; /* Just in case Autoneg time = 0 */
480 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
481 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
482 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
483 break;
484 msleep(100);
485 }
486 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
487 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700488 hw_dbg(hw, "Autonegotiation did not complete.\n");
Auke Kok9a799d72007-09-15 14:07:45 -0700489 }
490 }
491 }
492
Auke Kok9a799d72007-09-15 14:07:45 -0700493 /* Add delay to filter out noises during initial link setup */
494 msleep(50);
495
496 return status;
497}
498
499/**
Mallikarjuna R Chilakala734e9792009-12-15 11:57:20 +0000500 * ixgbe_validate_link_ready - Function looks for phy link
501 * @hw: pointer to hardware structure
502 *
503 * Function indicates success when phy link is available. If phy is not ready
504 * within 5 seconds of MAC indicating link, the function returns error.
505 **/
506static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
507{
508 u32 timeout;
509 u16 an_reg;
510
511 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
512 return 0;
513
514 for (timeout = 0;
515 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
516 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
517
518 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
519 (an_reg & MDIO_STAT1_LSTATUS))
520 break;
521
522 msleep(100);
523 }
524
525 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
526 hw_dbg(hw, "Link was indicated but link is down\n");
527 return IXGBE_ERR_LINK_SETUP;
528 }
529
530 return 0;
531}
532
533/**
Auke Kok9a799d72007-09-15 14:07:45 -0700534 * ixgbe_check_mac_link_82598 - Get link/speed status
535 * @hw: pointer to hardware structure
536 * @speed: pointer to link speed
537 * @link_up: true is link is up, false otherwise
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700538 * @link_up_wait_to_complete: bool used to wait for link up or not
Auke Kok9a799d72007-09-15 14:07:45 -0700539 *
540 * Reads the links register to determine if link is up and the current speed
541 **/
Peter P Waskiewiczb4617242008-09-11 20:04:46 -0700542static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000543 ixgbe_link_speed *speed, bool *link_up,
544 bool link_up_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700545{
546 u32 links_reg;
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700547 u32 i;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800548 u16 link_reg, adapt_comp_reg;
549
550 /*
551 * SERDES PHY requires us to read link status from register 0xC79F.
552 * Bit 0 set indicates link is up/ready; clear indicates link down.
553 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
554 * clear indicates active; set indicates inactive.
555 */
556 if (hw->phy.type == ixgbe_phy_nl) {
Ben Hutchings6b73e102009-04-29 08:08:58 +0000557 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
558 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
559 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000560 &adapt_comp_reg);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800561 if (link_up_wait_to_complete) {
562 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
563 if ((link_reg & 1) &&
564 ((adapt_comp_reg & 1) == 0)) {
565 *link_up = true;
566 break;
567 } else {
568 *link_up = false;
569 }
570 msleep(100);
571 hw->phy.ops.read_reg(hw, 0xC79F,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000572 MDIO_MMD_PMAPMD,
573 &link_reg);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800574 hw->phy.ops.read_reg(hw, 0xC00C,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000575 MDIO_MMD_PMAPMD,
576 &adapt_comp_reg);
Donald Skidmorec4900be2008-11-20 21:11:42 -0800577 }
578 } else {
579 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
580 *link_up = true;
581 else
582 *link_up = false;
583 }
584
Joe Perches23677ce2012-02-09 11:17:23 +0000585 if (!*link_up)
Mark Rustade90dd262014-07-22 06:51:08 +0000586 return 0;
Donald Skidmorec4900be2008-11-20 21:11:42 -0800587 }
Auke Kok9a799d72007-09-15 14:07:45 -0700588
589 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
Jesse Brandeburgcf8280e2008-09-11 19:55:32 -0700590 if (link_up_wait_to_complete) {
591 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
592 if (links_reg & IXGBE_LINKS_UP) {
593 *link_up = true;
594 break;
595 } else {
596 *link_up = false;
597 }
598 msleep(100);
599 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
600 }
601 } else {
602 if (links_reg & IXGBE_LINKS_UP)
603 *link_up = true;
604 else
605 *link_up = false;
606 }
Auke Kok9a799d72007-09-15 14:07:45 -0700607
608 if (links_reg & IXGBE_LINKS_SPEED)
609 *speed = IXGBE_LINK_SPEED_10GB_FULL;
610 else
611 *speed = IXGBE_LINK_SPEED_1GB_FULL;
612
Joe Perches23677ce2012-02-09 11:17:23 +0000613 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
Mallikarjuna R Chilakala734e9792009-12-15 11:57:20 +0000614 (ixgbe_validate_link_ready(hw) != 0))
615 *link_up = false;
616
Auke Kok9a799d72007-09-15 14:07:45 -0700617 return 0;
618}
619
620/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000621 * ixgbe_setup_mac_link_82598 - Set MAC link speed
Auke Kok9a799d72007-09-15 14:07:45 -0700622 * @hw: pointer to hardware structure
623 * @speed: new link speed
Emil Tantilov037c6d02011-02-25 07:49:39 +0000624 * @autoneg_wait_to_complete: true when waiting for completion is needed
Auke Kok9a799d72007-09-15 14:07:45 -0700625 *
626 * Set the link speed in the AUTOC register and restarts link.
627 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000628static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
Josh Hayfd0326f2012-12-15 03:28:30 +0000629 ixgbe_link_speed speed,
630 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700631{
Josh Hayfd0326f2012-12-15 03:28:30 +0000632 bool autoneg = false;
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800633 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
634 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
635 u32 autoc = curr_autoc;
636 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
Auke Kok9a799d72007-09-15 14:07:45 -0700637
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800638 /* Check to see if speed passed in is supported. */
639 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
640 speed &= link_capabilities;
641
642 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
Mark Rustade90dd262014-07-22 06:51:08 +0000643 return IXGBE_ERR_LINK_SETUP;
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800644
645 /* Set KX4/KX support according to speed requested */
646 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
Jacob Kellere7cf7452014-04-09 06:03:10 +0000647 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800648 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
649 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
650 autoc |= IXGBE_AUTOC_KX4_SUPP;
651 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
652 autoc |= IXGBE_AUTOC_KX_SUPP;
653 if (autoc != curr_autoc)
654 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
Auke Kok9a799d72007-09-15 14:07:45 -0700655 }
656
Mark Rustade90dd262014-07-22 06:51:08 +0000657 /* Setup and restart the link based on the new values in
658 * ixgbe_hw This will write the AUTOC register based on the new
659 * stored values
660 */
661 return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700662}
663
664
665/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000666 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
Auke Kok9a799d72007-09-15 14:07:45 -0700667 * @hw: pointer to hardware structure
668 * @speed: new link speed
Auke Kok9a799d72007-09-15 14:07:45 -0700669 * @autoneg_wait_to_complete: true if waiting is needed to complete
670 *
671 * Sets the link speed in the AUTOC register in the MAC and restarts link.
672 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000673static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000674 ixgbe_link_speed speed,
675 bool autoneg_wait_to_complete)
Auke Kok9a799d72007-09-15 14:07:45 -0700676{
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700677 s32 status;
Auke Kok9a799d72007-09-15 14:07:45 -0700678
679 /* Setup the PHY according to input speed */
Josh Hay99b76642012-12-15 03:28:24 +0000680 status = hw->phy.ops.setup_link_speed(hw, speed,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000681 autoneg_wait_to_complete);
Auke Kok3957d632007-10-31 15:22:10 -0700682 /* Set up MAC */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000683 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
Auke Kok9a799d72007-09-15 14:07:45 -0700684
685 return status;
686}
687
688/**
689 * ixgbe_reset_hw_82598 - Performs hardware reset
690 * @hw: pointer to hardware structure
691 *
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700692 * Resets the hardware by resetting the transmit and receive units, masks and
Auke Kok9a799d72007-09-15 14:07:45 -0700693 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
694 * reset.
695 **/
696static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
697{
Mark Rustade90dd262014-07-22 06:51:08 +0000698 s32 status;
Don Skidmore8ca783a2009-05-26 20:40:47 -0700699 s32 phy_status = 0;
Auke Kok9a799d72007-09-15 14:07:45 -0700700 u32 ctrl;
701 u32 gheccr;
702 u32 i;
703 u32 autoc;
704 u8 analog_val;
705
706 /* Call adapter stop to disable tx/rx and clear interrupts */
Emil Tantilovff9d1a52011-08-16 04:35:11 +0000707 status = hw->mac.ops.stop_adapter(hw);
Mark Rustade90dd262014-07-22 06:51:08 +0000708 if (status)
709 return status;
Auke Kok9a799d72007-09-15 14:07:45 -0700710
711 /*
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700712 * Power up the Atlas Tx lanes if they are currently powered down.
713 * Atlas Tx lanes are powered down for MAC loopback tests, but
Auke Kok9a799d72007-09-15 14:07:45 -0700714 * they are not automatically restored on reset.
715 */
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700716 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700717 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700718 /* Enable Tx Atlas so packets can be transmitted again */
719 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000720 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700721 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700722 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000723 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700724
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700725 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000726 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700727 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700728 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000729 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700730
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700731 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000732 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700733 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700734 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000735 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700736
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700737 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000738 &analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700739 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700740 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000741 analog_val);
Auke Kok9a799d72007-09-15 14:07:45 -0700742 }
743
744 /* Reset PHY */
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000745 if (hw->phy.reset_disable == false) {
746 /* PHY ops must be identified and initialized prior to reset */
747
748 /* Init PHY and function pointers, perform SFP setup */
Don Skidmore8ca783a2009-05-26 20:40:47 -0700749 phy_status = hw->phy.ops.init(hw);
750 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
Mark Rustade90dd262014-07-22 06:51:08 +0000751 return phy_status;
Emil Tantilovff9d1a52011-08-16 04:35:11 +0000752 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
753 goto mac_reset_top;
Don Skidmore8ca783a2009-05-26 20:40:47 -0700754
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700755 hw->phy.ops.reset(hw);
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000756 }
Auke Kok9a799d72007-09-15 14:07:45 -0700757
Emil Tantilova4297dc2011-02-14 08:45:13 +0000758mac_reset_top:
Auke Kok9a799d72007-09-15 14:07:45 -0700759 /*
760 * Issue global reset to the MAC. This needs to be a SW reset.
761 * If link reset is used, it might reset the MAC when mng is using it
762 */
Alexander Duyck8132b542011-07-15 07:29:44 +0000763 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
764 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
Auke Kok9a799d72007-09-15 14:07:45 -0700765 IXGBE_WRITE_FLUSH(hw);
Mark Rustadefff2e02015-10-27 13:23:14 -0700766 usleep_range(1000, 1200);
Auke Kok9a799d72007-09-15 14:07:45 -0700767
768 /* Poll for reset bit to self-clear indicating reset is complete */
769 for (i = 0; i < 10; i++) {
Auke Kok9a799d72007-09-15 14:07:45 -0700770 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
771 if (!(ctrl & IXGBE_CTRL_RST))
772 break;
Mark Rustadefff2e02015-10-27 13:23:14 -0700773 udelay(1);
Auke Kok9a799d72007-09-15 14:07:45 -0700774 }
775 if (ctrl & IXGBE_CTRL_RST) {
776 status = IXGBE_ERR_RESET_FAILED;
777 hw_dbg(hw, "Reset polling failed to complete.\n");
778 }
779
Alexander Duyck8132b542011-07-15 07:29:44 +0000780 msleep(50);
781
Emil Tantilova4297dc2011-02-14 08:45:13 +0000782 /*
783 * Double resets are required for recovery from certain error
784 * conditions. Between resets, it is necessary to stall to allow time
Alexander Duyck8132b542011-07-15 07:29:44 +0000785 * for any pending HW events to complete.
Emil Tantilova4297dc2011-02-14 08:45:13 +0000786 */
787 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
788 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
Emil Tantilova4297dc2011-02-14 08:45:13 +0000789 goto mac_reset_top;
790 }
791
Auke Kok9a799d72007-09-15 14:07:45 -0700792 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
Jacob Kellerb4f47a42016-04-13 16:08:22 -0700793 gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6));
Auke Kok9a799d72007-09-15 14:07:45 -0700794 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
795
796 /*
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800797 * Store the original AUTOC value if it has not been
798 * stored off yet. Otherwise restore the stored original
799 * AUTOC value since the reset operation sets back to deaults.
Auke Kok9a799d72007-09-15 14:07:45 -0700800 */
801 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
Peter P Waskiewicz Jr3201d312009-02-05 23:54:21 -0800802 if (hw->mac.orig_link_settings_stored == false) {
803 hw->mac.orig_autoc = autoc;
804 hw->mac.orig_link_settings_stored = true;
805 } else if (autoc != hw->mac.orig_autoc) {
806 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
Auke Kok9a799d72007-09-15 14:07:45 -0700807 }
808
Emil Tantilov278675d2011-02-19 08:43:49 +0000809 /* Store the permanent mac address */
810 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
811
Waskiewicz Jr, Peter Paca6bee2009-05-17 12:32:48 +0000812 /*
813 * Store MAC address from RAR0, clear receive address registers, and
814 * clear the multicast table
815 */
816 hw->mac.ops.init_rx_addrs(hw);
817
Don Skidmore8ca783a2009-05-26 20:40:47 -0700818 if (phy_status)
819 status = phy_status;
820
Auke Kok9a799d72007-09-15 14:07:45 -0700821 return status;
822}
823
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700824/**
825 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
826 * @hw: pointer to hardware struct
827 * @rar: receive address register index to associate with a VMDq index
828 * @vmdq: VMDq set index
829 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800830static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700831{
832 u32 rar_high;
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000833 u32 rar_entries = hw->mac.num_rar_entries;
834
835 /* Make sure we are using a valid rar index range */
836 if (rar >= rar_entries) {
837 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
838 return IXGBE_ERR_INVALID_ARGUMENT;
839 }
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700840
841 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
842 rar_high &= ~IXGBE_RAH_VIND_MASK;
843 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
844 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
845 return 0;
846}
847
848/**
849 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
850 * @hw: pointer to hardware struct
851 * @rar: receive address register index to associate with a VMDq index
852 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
853 **/
854static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
855{
856 u32 rar_high;
857 u32 rar_entries = hw->mac.num_rar_entries;
858
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000859
860 /* Make sure we are using a valid rar index range */
861 if (rar >= rar_entries) {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700862 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
Emil Tantilovc700f4e2011-02-17 11:34:58 +0000863 return IXGBE_ERR_INVALID_ARGUMENT;
864 }
865
866 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
867 if (rar_high & IXGBE_RAH_VIND_MASK) {
868 rar_high &= ~IXGBE_RAH_VIND_MASK;
869 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700870 }
871
872 return 0;
873}
874
875/**
876 * ixgbe_set_vfta_82598 - Set VLAN filter table
877 * @hw: pointer to hardware structure
878 * @vlan: VLAN id to write to VLAN filter
879 * @vind: VMDq output index that maps queue to VLAN id in VFTA
880 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
Alexander Duyckb6488b62015-11-02 17:10:01 -0800881 * @vlvf_bypass: boolean flag - unused
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700882 *
883 * Turn on/off specified VLAN in the VLAN filter table.
884 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800885static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
Alexander Duyckb6488b62015-11-02 17:10:01 -0800886 bool vlan_on, bool vlvf_bypass)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700887{
888 u32 regindex;
889 u32 bitindex;
890 u32 bits;
891 u32 vftabyte;
892
893 if (vlan > 4095)
894 return IXGBE_ERR_PARAM;
895
896 /* Determine 32-bit word position in array */
897 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
898
899 /* Determine the location of the (VMD) queue index */
900 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
901 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
902
903 /* Set the nibble for VMD queue index */
904 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
905 bits &= (~(0x0F << bitindex));
906 bits |= (vind << bitindex);
907 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
908
909 /* Determine the location of the bit for this VLAN id */
910 bitindex = vlan & 0x1F; /* lower five bits */
911
912 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
913 if (vlan_on)
914 /* Turn on this VLAN id */
Jacob Kellerb4f47a42016-04-13 16:08:22 -0700915 bits |= BIT(bitindex);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700916 else
917 /* Turn off this VLAN id */
Jacob Kellerb4f47a42016-04-13 16:08:22 -0700918 bits &= ~BIT(bitindex);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700919 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
920
921 return 0;
922}
923
924/**
925 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
926 * @hw: pointer to hardware structure
927 *
928 * Clears the VLAN filer table, and the VMDq index associated with the filter
929 **/
930static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
931{
932 u32 offset;
933 u32 vlanbyte;
934
935 for (offset = 0; offset < hw->mac.vft_size; offset++)
936 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
937
938 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
939 for (offset = 0; offset < hw->mac.vft_size; offset++)
940 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
Jacob Kellere7cf7452014-04-09 06:03:10 +0000941 0);
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700942
943 return 0;
944}
945
946/**
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700947 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
948 * @hw: pointer to hardware structure
949 * @reg: analog register to read
950 * @val: read value
951 *
952 * Performs read operation to Atlas analog register specified.
953 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800954static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700955{
956 u32 atlas_ctl;
957
958 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
Jacob Kellere7cf7452014-04-09 06:03:10 +0000959 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700960 IXGBE_WRITE_FLUSH(hw);
961 udelay(10);
962 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
963 *val = (u8)atlas_ctl;
964
965 return 0;
966}
967
968/**
969 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
970 * @hw: pointer to hardware structure
971 * @reg: atlas register to write
972 * @val: value to write
973 *
974 * Performs write operation to Atlas analog register specified.
975 **/
Hannes Edere855aac2008-12-26 00:03:59 -0800976static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700977{
978 u32 atlas_ctl;
979
980 atlas_ctl = (reg << 8) | val;
981 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
982 IXGBE_WRITE_FLUSH(hw);
983 udelay(10);
984
985 return 0;
986}
987
988/**
Emil Tantilov07ce8702012-12-19 07:14:17 +0000989 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
Donald Skidmorec4900be2008-11-20 21:11:42 -0800990 * @hw: pointer to hardware structure
Emil Tantilov07ce8702012-12-19 07:14:17 +0000991 * @dev_addr: address to read from
992 * @byte_offset: byte offset to read from dev_addr
Donald Skidmorec4900be2008-11-20 21:11:42 -0800993 * @eeprom_data: value read
994 *
Emil Tantilov07ce8702012-12-19 07:14:17 +0000995 * Performs 8 byte read operation to SFP module's data over I2C interface.
Donald Skidmorec4900be2008-11-20 21:11:42 -0800996 **/
Emil Tantilov07ce8702012-12-19 07:14:17 +0000997static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
998 u8 byte_offset, u8 *eeprom_data)
Donald Skidmorec4900be2008-11-20 21:11:42 -0800999{
1000 s32 status = 0;
1001 u16 sfp_addr = 0;
1002 u16 sfp_data = 0;
1003 u16 sfp_stat = 0;
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001004 u16 gssr;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001005 u32 i;
1006
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001007 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1008 gssr = IXGBE_GSSR_PHY1_SM;
1009 else
1010 gssr = IXGBE_GSSR_PHY0_SM;
1011
1012 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
1013 return IXGBE_ERR_SWFW_SYNC;
1014
Donald Skidmorec4900be2008-11-20 21:11:42 -08001015 if (hw->phy.type == ixgbe_phy_nl) {
1016 /*
1017 * phy SDA/SCL registers are at addresses 0xC30A to
1018 * 0xC30D. These registers are used to talk to the SFP+
1019 * module's EEPROM through the SDA/SCL (I2C) interface.
1020 */
Emil Tantilov07ce8702012-12-19 07:14:17 +00001021 sfp_addr = (dev_addr << 8) + byte_offset;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001022 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001023 hw->phy.ops.write_reg_mdi(hw,
1024 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1025 MDIO_MMD_PMAPMD,
1026 sfp_addr);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001027
1028 /* Poll status */
1029 for (i = 0; i < 100; i++) {
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001030 hw->phy.ops.read_reg_mdi(hw,
1031 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1032 MDIO_MMD_PMAPMD,
1033 &sfp_stat);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001034 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1035 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1036 break;
Don Skidmore032b4322011-03-18 09:32:53 +00001037 usleep_range(10000, 20000);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001038 }
1039
1040 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1041 hw_dbg(hw, "EEPROM read did not pass.\n");
1042 status = IXGBE_ERR_SFP_NOT_PRESENT;
1043 goto out;
1044 }
1045
1046 /* Read data */
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001047 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1048 MDIO_MMD_PMAPMD, &sfp_data);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001049
1050 *eeprom_data = (u8)(sfp_data >> 8);
1051 } else {
1052 status = IXGBE_ERR_PHY;
Donald Skidmorec4900be2008-11-20 21:11:42 -08001053 }
1054
1055out:
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001056 hw->mac.ops.release_swfw_sync(hw, gssr);
Donald Skidmorec4900be2008-11-20 21:11:42 -08001057 return status;
1058}
1059
1060/**
Emil Tantilov07ce8702012-12-19 07:14:17 +00001061 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1062 * @hw: pointer to hardware structure
1063 * @byte_offset: EEPROM byte offset to read
1064 * @eeprom_data: value read
1065 *
1066 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1067 **/
1068static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1069 u8 *eeprom_data)
1070{
1071 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1072 byte_offset, eeprom_data);
1073}
1074
1075/**
1076 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1077 * @hw: pointer to hardware structure
1078 * @byte_offset: byte offset at address 0xA2
1079 * @eeprom_data: value read
1080 *
1081 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1082 **/
1083static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1084 u8 *sff8472_data)
1085{
1086 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1087 byte_offset, sff8472_data);
1088}
1089
1090/**
Emil Tantilovc9130182011-03-16 01:55:55 +00001091 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1092 * port devices.
1093 * @hw: pointer to the HW structure
1094 *
1095 * Calls common function and corrects issue with some single port devices
1096 * that enable LAN1 but not LAN0.
1097 **/
1098static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1099{
1100 struct ixgbe_bus_info *bus = &hw->bus;
1101 u16 pci_gen = 0;
1102 u16 pci_ctrl2 = 0;
1103
1104 ixgbe_set_lan_id_multi_port_pcie(hw);
1105
1106 /* check if LAN0 is disabled */
1107 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1108 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1109
1110 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1111
1112 /* if LAN0 is completely disabled force function to 0 */
1113 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1114 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1115 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1116
1117 bus->func = 0;
1118 }
1119 }
1120}
1121
John Fastabend80605c652011-05-02 12:34:10 +00001122/**
Jacob Keller44834702014-02-22 01:23:51 +00001123 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
John Fastabend80605c652011-05-02 12:34:10 +00001124 * @hw: pointer to hardware structure
Jacob Keller44834702014-02-22 01:23:51 +00001125 * @num_pb: number of packet buffers to allocate
1126 * @headroom: reserve n KB of headroom
1127 * @strategy: packet buffer allocation strategy
1128 **/
1129static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1130 u32 headroom, int strategy)
John Fastabend80605c652011-05-02 12:34:10 +00001131{
1132 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1133 u8 i = 0;
1134
1135 if (!num_pb)
1136 return;
1137
1138 /* Setup Rx packet buffer sizes */
1139 switch (strategy) {
1140 case PBA_STRATEGY_WEIGHTED:
1141 /* Setup the first four at 80KB */
1142 rxpktsize = IXGBE_RXPBSIZE_80KB;
1143 for (; i < 4; i++)
1144 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1145 /* Setup the last four at 48KB...don't re-init i */
1146 rxpktsize = IXGBE_RXPBSIZE_48KB;
1147 /* Fall Through */
1148 case PBA_STRATEGY_EQUAL:
1149 default:
1150 /* Divide the remaining Rx packet buffer evenly among the TCs */
1151 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1152 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1153 break;
1154 }
1155
1156 /* Setup Tx packet buffer sizes */
1157 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1158 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
John Fastabend80605c652011-05-02 12:34:10 +00001159}
1160
Mark Rustad37689012016-01-07 10:13:03 -08001161static const struct ixgbe_mac_operations mac_ops_82598 = {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001162 .init_hw = &ixgbe_init_hw_generic,
1163 .reset_hw = &ixgbe_reset_hw_82598,
Mallikarjuna R Chilakala202ff1e2009-08-03 07:20:38 +00001164 .start_hw = &ixgbe_start_hw_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001165 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
Auke Kok9a799d72007-09-15 14:07:45 -07001166 .get_media_type = &ixgbe_get_media_type_82598,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001167 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001168 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1169 .stop_adapter = &ixgbe_stop_adapter_generic,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001170 .get_bus_info = &ixgbe_get_bus_info_generic,
Emil Tantilovc9130182011-03-16 01:55:55 +00001171 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001172 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1173 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
Auke Kok3957d632007-10-31 15:22:10 -07001174 .setup_link = &ixgbe_setup_mac_link_82598,
John Fastabend80605c652011-05-02 12:34:10 +00001175 .set_rxpba = &ixgbe_set_rxpba_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001176 .check_link = &ixgbe_check_mac_link_82598,
1177 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1178 .led_on = &ixgbe_led_on_generic,
1179 .led_off = &ixgbe_led_off_generic,
Don Skidmore805cedd2016-10-20 21:42:00 -04001180 .init_led_link_act = ixgbe_init_led_link_act_generic,
PJ Waskiewicz87c12012009-04-08 13:20:31 +00001181 .blink_led_start = &ixgbe_blink_led_start_generic,
1182 .blink_led_stop = &ixgbe_blink_led_stop_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001183 .set_rar = &ixgbe_set_rar_generic,
1184 .clear_rar = &ixgbe_clear_rar_generic,
1185 .set_vmdq = &ixgbe_set_vmdq_82598,
1186 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1187 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001188 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1189 .enable_mc = &ixgbe_enable_mc_generic,
1190 .disable_mc = &ixgbe_disable_mc_generic,
1191 .clear_vfta = &ixgbe_clear_vfta_82598,
1192 .set_vfta = &ixgbe_set_vfta_82598,
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +00001193 .fc_enable = &ixgbe_fc_enable_82598,
Mark Rustadafdc71e2016-01-25 16:32:10 -08001194 .setup_fc = ixgbe_setup_fc_generic,
Don Skidmore29165002016-09-27 14:31:12 -04001195 .fc_autoneg = ixgbe_fc_autoneg,
Emil Tantilov9612de92011-05-07 07:40:20 +00001196 .set_fw_drv_ver = NULL,
Don Skidmore5e655102011-02-25 01:58:04 +00001197 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1198 .release_swfw_sync = &ixgbe_release_swfw_sync,
Don Skidmoredbd15b82016-03-09 16:45:00 -05001199 .init_swfw_sync = NULL,
Don Skidmore3ca8bc62012-04-12 00:33:31 +00001200 .get_thermal_sensor_data = NULL,
1201 .init_thermal_sensor_thresh = NULL,
Don Skidmore429d6a32014-02-27 20:32:41 -08001202 .prot_autoc_read = &prot_autoc_read_generic,
1203 .prot_autoc_write = &prot_autoc_write_generic,
Don Skidmore1f9ac572015-03-13 13:54:30 -07001204 .enable_rx = &ixgbe_enable_rx_generic,
1205 .disable_rx = &ixgbe_disable_rx_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001206};
1207
Mark Rustad37689012016-01-07 10:13:03 -08001208static const struct ixgbe_eeprom_operations eeprom_ops_82598 = {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001209 .init_params = &ixgbe_init_eeprom_params_generic,
Mallikarjuna R Chilakala21ce8492010-05-13 17:33:41 +00001210 .read = &ixgbe_read_eerd_generic,
Emil Tantilov2fa5eef2011-10-06 08:57:04 +00001211 .write = &ixgbe_write_eeprom_generic,
1212 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
Emil Tantilov68c70052011-04-20 08:49:06 +00001213 .read_buffer = &ixgbe_read_eerd_buffer_generic,
Don Skidmorea391f1d2010-11-16 19:27:15 -08001214 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001215 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1216 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1217};
1218
Mark Rustad37689012016-01-07 10:13:03 -08001219static const struct ixgbe_phy_operations phy_ops_82598 = {
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001220 .identify = &ixgbe_identify_phy_generic,
Don Skidmore8f583322013-07-27 06:25:38 +00001221 .identify_sfp = &ixgbe_identify_module_generic,
PJ Waskiewicz04f165e2009-04-09 22:27:57 +00001222 .init = &ixgbe_init_phy_ops_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001223 .reset = &ixgbe_reset_phy_generic,
1224 .read_reg = &ixgbe_read_phy_reg_generic,
1225 .write_reg = &ixgbe_write_phy_reg_generic,
Emil Tantilov3dcc2f412013-05-29 06:23:05 +00001226 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
1227 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001228 .setup_link = &ixgbe_setup_phy_link_generic,
1229 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
Emil Tantilov07ce8702012-12-19 07:14:17 +00001230 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
Donald Skidmorec4900be2008-11-20 21:11:42 -08001231 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
Don Skidmore961fac82015-06-09 16:09:47 -07001232 .check_overtemp = &ixgbe_tn_check_overtemp,
Auke Kok9a799d72007-09-15 14:07:45 -07001233};
1234
Mark Rustad37689012016-01-07 10:13:03 -08001235const struct ixgbe_info ixgbe_82598_info = {
Auke Kok9a799d72007-09-15 14:07:45 -07001236 .mac = ixgbe_mac_82598EB,
1237 .get_invariants = &ixgbe_get_invariants_82598,
1238 .mac_ops = &mac_ops_82598,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -07001239 .eeprom_ops = &eeprom_ops_82598,
1240 .phy_ops = &phy_ops_82598,
Don Skidmore9a900ec2015-06-09 17:15:01 -07001241 .mvals = ixgbe_mvals_8259X,
Auke Kok9a799d72007-09-15 14:07:45 -07001242};