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Felipe Balbi72246da2011-08-19 18:10:58 +03001/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
Felipe Balbi72246da2011-08-19 18:10:58 +03005 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
Felipe Balbi5945f782013-06-30 14:15:11 +03009 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
Felipe Balbi72246da2011-08-19 18:10:58 +030012 *
Felipe Balbi5945f782013-06-30 14:15:11 +030013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Felipe Balbi72246da2011-08-19 18:10:58 +030017 */
18
19#ifndef __DRIVERS_USB_DWC3_CORE_H
20#define __DRIVERS_USB_DWC3_CORE_H
21
22#include <linux/device.h>
23#include <linux/spinlock.h>
Felipe Balbid07e8812011-10-12 14:08:26 +030024#include <linux/ioport.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030025#include <linux/list.h>
26#include <linux/dma-mapping.h>
27#include <linux/mm.h>
28#include <linux/debugfs.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
Ruchika Kharwara45c82b82013-07-06 07:52:49 -050032#include <linux/usb/otg.h>
Heikki Krogerus88bc9d12015-05-13 15:26:51 +030033#include <linux/ulpi/interface.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030034
Kishon Vijay Abraham I57303482014-03-03 17:08:11 +053035#include <linux/phy/phy.h>
36
Felipe Balbi2c4cbe6e52014-04-30 17:45:10 -050037#define DWC3_MSG_MAX 500
38
Felipe Balbi72246da2011-08-19 18:10:58 +030039/* Global constants */
Felipe Balbi04c03d12015-12-02 10:06:45 -060040#define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
Felipe Balbi3ef35fa2012-05-04 12:58:14 +030041#define DWC3_EP0_BOUNCE_SIZE 512
Felipe Balbi72246da2011-08-19 18:10:58 +030042#define DWC3_ENDPOINTS_NUM 32
Ido Shayevitz51249dc2012-04-24 14:18:39 +030043#define DWC3_XHCI_RESOURCES_NUM 2
Felipe Balbi72246da2011-08-19 18:10:58 +030044
Felipe Balbi0ffcaf32013-12-19 13:04:28 -060045#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
Felipe Balbi5da93472012-12-07 21:42:03 +020046#define DWC3_EVENT_SIZE 4 /* bytes */
47#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
48#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
Felipe Balbi72246da2011-08-19 18:10:58 +030049#define DWC3_EVENT_TYPE_MASK 0xfe
50
51#define DWC3_EVENT_TYPE_DEV 0
52#define DWC3_EVENT_TYPE_CARKIT 3
53#define DWC3_EVENT_TYPE_I2C 4
54
55#define DWC3_DEVICE_EVENT_DISCONNECT 0
56#define DWC3_DEVICE_EVENT_RESET 1
57#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59#define DWC3_DEVICE_EVENT_WAKEUP 4
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -080060#define DWC3_DEVICE_EVENT_HIBER_REQ 5
Felipe Balbi72246da2011-08-19 18:10:58 +030061#define DWC3_DEVICE_EVENT_EOPF 6
62#define DWC3_DEVICE_EVENT_SOF 7
63#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64#define DWC3_DEVICE_EVENT_CMD_CMPL 10
65#define DWC3_DEVICE_EVENT_OVERFLOW 11
66
67#define DWC3_GEVNTCOUNT_MASK 0xfffc
68#define DWC3_GSNPSID_MASK 0xffff0000
69#define DWC3_GSNPSREV_MASK 0xffff
70
Ido Shayevitz51249dc2012-04-24 14:18:39 +030071/* DWC3 registers memory space boundries */
72#define DWC3_XHCI_REGS_START 0x0
73#define DWC3_XHCI_REGS_END 0x7fff
74#define DWC3_GLOBALS_REGS_START 0xc100
75#define DWC3_GLOBALS_REGS_END 0xc6ff
76#define DWC3_DEVICE_REGS_START 0xc700
77#define DWC3_DEVICE_REGS_END 0xcbff
78#define DWC3_OTG_REGS_START 0xcc00
79#define DWC3_OTG_REGS_END 0xccff
80
Felipe Balbi72246da2011-08-19 18:10:58 +030081/* Global Registers */
82#define DWC3_GSBUSCFG0 0xc100
83#define DWC3_GSBUSCFG1 0xc104
84#define DWC3_GTXTHRCFG 0xc108
85#define DWC3_GRXTHRCFG 0xc10c
86#define DWC3_GCTL 0xc110
87#define DWC3_GEVTEN 0xc114
88#define DWC3_GSTS 0xc118
William Wu475c8be2016-05-13 18:13:46 +080089#define DWC3_GUCTL1 0xc11c
Felipe Balbi72246da2011-08-19 18:10:58 +030090#define DWC3_GSNPSID 0xc120
91#define DWC3_GGPIO 0xc124
92#define DWC3_GUID 0xc128
93#define DWC3_GUCTL 0xc12c
94#define DWC3_GBUSERRADDR0 0xc130
95#define DWC3_GBUSERRADDR1 0xc134
96#define DWC3_GPRTBIMAP0 0xc138
97#define DWC3_GPRTBIMAP1 0xc13c
98#define DWC3_GHWPARAMS0 0xc140
99#define DWC3_GHWPARAMS1 0xc144
100#define DWC3_GHWPARAMS2 0xc148
101#define DWC3_GHWPARAMS3 0xc14c
102#define DWC3_GHWPARAMS4 0xc150
103#define DWC3_GHWPARAMS5 0xc154
104#define DWC3_GHWPARAMS6 0xc158
105#define DWC3_GHWPARAMS7 0xc15c
106#define DWC3_GDBGFIFOSPACE 0xc160
107#define DWC3_GDBGLTSSM 0xc164
108#define DWC3_GPRTBIMAP_HS0 0xc180
109#define DWC3_GPRTBIMAP_HS1 0xc184
110#define DWC3_GPRTBIMAP_FS0 0xc188
111#define DWC3_GPRTBIMAP_FS1 0xc18c
112
John Youn690fb372015-09-04 19:15:10 -0700113#define DWC3_VER_NUMBER 0xc1a0
114#define DWC3_VER_TYPE 0xc1a4
115
Felipe Balbi72246da2011-08-19 18:10:58 +0300116#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
117#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
118
119#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
120
121#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
122
123#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
124#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
125
126#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
127#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
128#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
129#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
130
131#define DWC3_GHWPARAMS8 0xc600
Nikhil Badoladb2be4e2015-09-04 10:15:58 +0530132#define DWC3_GFLADJ 0xc630
Felipe Balbi72246da2011-08-19 18:10:58 +0300133
134/* Device Registers */
135#define DWC3_DCFG 0xc700
136#define DWC3_DCTL 0xc704
137#define DWC3_DEVTEN 0xc708
138#define DWC3_DSTS 0xc70c
139#define DWC3_DGCMDPAR 0xc710
140#define DWC3_DGCMD 0xc714
141#define DWC3_DALEPENA 0xc720
Felipe Balbi2eb88012016-04-12 16:53:39 +0300142
143#define DWC3_DEP_BASE(n) (0xc800 + (n * 0x10))
144#define DWC3_DEPCMDPAR2 0x00
145#define DWC3_DEPCMDPAR1 0x04
146#define DWC3_DEPCMDPAR0 0x08
147#define DWC3_DEPCMD 0x0c
Felipe Balbi72246da2011-08-19 18:10:58 +0300148
149/* OTG Registers */
150#define DWC3_OCFG 0xcc00
151#define DWC3_OCTL 0xcc04
George Cheriand4436c32013-03-14 16:05:24 +0530152#define DWC3_OEVT 0xcc08
153#define DWC3_OEVTEN 0xcc0C
154#define DWC3_OSTS 0xcc10
Felipe Balbi72246da2011-08-19 18:10:58 +0300155
156/* Bit fields */
157
Felipe Balbicf6d8672016-04-14 15:03:39 +0300158/* Global Debug Queue/FIFO Space Available Register */
159#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
160#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
161#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
162
163#define DWC3_TXFIFOQ 1
164#define DWC3_RXFIFOQ 3
165#define DWC3_TXREQQ 5
166#define DWC3_RXREQQ 7
167#define DWC3_RXINFOQ 9
168#define DWC3_DESCFETCHQ 13
169#define DWC3_EVENTQ 15
170
Felipe Balbi2a58f9c2016-04-28 10:56:28 +0300171/* Global RX Threshold Configuration Register */
172#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
173#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
174#define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29)
175
Felipe Balbi72246da2011-08-19 18:10:58 +0300176/* Global Configuration Register */
Paul Zimmerman1d046792012-02-15 18:56:56 -0800177#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
Felipe Balbif4aadbe2011-09-08 17:39:59 +0300178#define DWC3_GCTL_U2RSTECN (1 << 16)
Paul Zimmerman1d046792012-02-15 18:56:56 -0800179#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
Felipe Balbi72246da2011-08-19 18:10:58 +0300180#define DWC3_GCTL_CLK_BUS (0)
181#define DWC3_GCTL_CLK_PIPE (1)
182#define DWC3_GCTL_CLK_PIPEHALF (2)
183#define DWC3_GCTL_CLK_MASK (3)
184
Felipe Balbi0b9fe322011-10-17 08:50:39 +0300185#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
Paul Zimmerman1d046792012-02-15 18:56:56 -0800186#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
Felipe Balbi72246da2011-08-19 18:10:58 +0300187#define DWC3_GCTL_PRTCAP_HOST 1
188#define DWC3_GCTL_PRTCAP_DEVICE 2
189#define DWC3_GCTL_PRTCAP_OTG 3
190
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800191#define DWC3_GCTL_CORESOFTRESET (1 << 11)
Felipe Balbi183ca112014-02-25 14:08:51 -0600192#define DWC3_GCTL_SOFITPSYNC (1 << 10)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800193#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
194#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
195#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
Huang Rui9a5b2f32014-10-28 19:54:27 +0800196#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800197#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
198#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
Felipe Balbi72246da2011-08-19 18:10:58 +0300199
200/* Global USB2 PHY Configuration Register */
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800201#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
202#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
Heikki Krogerusf699b942015-05-13 15:26:44 +0300203#define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
John Younec791d12015-10-02 20:30:57 -0700204#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
Felipe Balbi72246da2011-08-19 18:10:58 +0300205
Heikki Krogerusb5699ee2015-05-13 15:26:43 +0300206/* Global USB2 PHY Vendor Control Register */
207#define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
208#define DWC3_GUSB2PHYACC_BUSY (1 << 23)
209#define DWC3_GUSB2PHYACC_WRITE (1 << 22)
210#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
211#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
212#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
213
Felipe Balbi72246da2011-08-19 18:10:58 +0300214/* Global USB3 PIPE Control Register */
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800215#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
Huang Ruib5a65c42014-10-28 19:54:28 +0800216#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
Rajesh Bhagate58dd352016-03-14 14:40:50 +0530217#define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28)
Huang Ruidf31f5b2014-10-28 19:54:29 +0800218#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
Huang Ruia2a1d0f2014-10-28 19:54:30 +0800219#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
220#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
221#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
Huang Rui41c06ff2014-10-28 19:54:31 +0800222#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800223#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
Huang Ruifb67afc2014-10-28 19:54:32 +0800224#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
Huang Rui14f4ac52014-10-28 19:54:33 +0800225#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
Huang Rui6b6a0c92014-10-31 11:11:12 +0800226#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
227#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
Felipe Balbi72246da2011-08-19 18:10:58 +0300228
Felipe Balbi457e84b2012-01-18 18:04:09 +0200229/* Global TX Fifo Size Register */
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800230#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
231#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
Felipe Balbi457e84b2012-01-18 18:04:09 +0200232
Felipe Balbi68d6a012013-06-12 21:09:26 +0300233/* Global Event Size Registers */
234#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
235#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
236
Felipe Balbi4e994722016-05-13 14:09:59 +0300237/* Global HWPARAMS0 Register */
238#define DWC3_GHWPARAMS0_USB3_MODE(n) ((n) & 0x3)
239#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
240#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
241#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
242#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
243#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
244
Felipe Balbiaabb7072011-09-30 10:58:50 +0300245/* Global HWPARAMS1 Register */
Paul Zimmerman1d046792012-02-15 18:56:56 -0800246#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
Felipe Balbiaabb7072011-09-30 10:58:50 +0300247#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
248#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800249#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
250#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
251#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
252
Paul Zimmerman0e1e5c42014-05-23 11:39:24 -0700253/* Global HWPARAMS3 Register */
254#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
255#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
John Youn1f38f882016-02-05 17:08:31 -0800256#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
257#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
Paul Zimmerman0e1e5c42014-05-23 11:39:24 -0700258#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
259#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
260#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
261#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
262#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
263#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
264#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
265#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
266
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800267/* Global HWPARAMS4 Register */
268#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
269#define DWC3_MAX_HIBER_SCRATCHBUFS 15
Felipe Balbiaabb7072011-09-30 10:58:50 +0300270
Huang Rui946bd572014-10-28 19:54:23 +0800271/* Global HWPARAMS6 Register */
272#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
273
Felipe Balbi4e994722016-05-13 14:09:59 +0300274/* Global HWPARAMS7 Register */
275#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
276#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
277
Nikhil Badoladb2be4e2015-09-04 10:15:58 +0530278/* Global Frame Length Adjustment Register */
279#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
280#define DWC3_GFLADJ_30MHZ_MASK 0x3f
281
Felipe Balbi72246da2011-08-19 18:10:58 +0300282/* Device Configuration Register */
283#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
284#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
285
286#define DWC3_DCFG_SPEED_MASK (7 << 0)
John Youn1f38f882016-02-05 17:08:31 -0800287#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
Felipe Balbi72246da2011-08-19 18:10:58 +0300288#define DWC3_DCFG_SUPERSPEED (4 << 0)
289#define DWC3_DCFG_HIGHSPEED (0 << 0)
290#define DWC3_DCFG_FULLSPEED2 (1 << 0)
291#define DWC3_DCFG_LOWSPEED (2 << 0)
292#define DWC3_DCFG_FULLSPEED1 (3 << 0)
293
Felipe Balbi676e3492016-04-26 10:49:07 +0300294#define DWC3_DCFG_NUMP_SHIFT 17
Dan Carpenter97398612016-05-03 10:49:00 +0300295#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
Felipe Balbi676e3492016-04-26 10:49:07 +0300296#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800297#define DWC3_DCFG_LPM_CAP (1 << 22)
298
Felipe Balbi72246da2011-08-19 18:10:58 +0300299/* Device Control Register */
300#define DWC3_DCTL_RUN_STOP (1 << 31)
301#define DWC3_DCTL_CSFTRST (1 << 30)
302#define DWC3_DCTL_LSFTRST (1 << 29)
303
304#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
Pratyush Anand7e39b812012-06-06 19:18:29 +0530305#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
Felipe Balbi72246da2011-08-19 18:10:58 +0300306
307#define DWC3_DCTL_APPL1RES (1 << 23)
308
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800309/* These apply for core versions 1.87a and earlier */
310#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
311#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
312#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
313#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
314#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
315#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
316#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
Felipe Balbi8db7ed12012-01-18 18:32:29 +0200317
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800318/* These apply for core versions 1.94a and later */
Huang Rui80caf7d2014-10-28 19:54:26 +0800319#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
320#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
Felipe Balbi8db7ed12012-01-18 18:32:29 +0200321
Huang Rui80caf7d2014-10-28 19:54:26 +0800322#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
323#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
324#define DWC3_DCTL_CRS (1 << 17)
325#define DWC3_DCTL_CSS (1 << 16)
326
327#define DWC3_DCTL_INITU2ENA (1 << 12)
328#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
329#define DWC3_DCTL_INITU1ENA (1 << 10)
330#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
331#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
Felipe Balbi72246da2011-08-19 18:10:58 +0300332
333#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
334#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
335
336#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
337#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
338#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
339#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
340#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
341#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
342#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
343
344/* Device Event Enable Register */
345#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
346#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
347#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
348#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
349#define DWC3_DEVTEN_SOFEN (1 << 7)
350#define DWC3_DEVTEN_EOPFEN (1 << 6)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800351#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
Felipe Balbi72246da2011-08-19 18:10:58 +0300352#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
353#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
354#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
355#define DWC3_DEVTEN_USBRSTEN (1 << 1)
356#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
357
358/* Device Status Register */
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800359#define DWC3_DSTS_DCNRD (1 << 29)
360
361/* This applies for core versions 1.87a and earlier */
Felipe Balbi72246da2011-08-19 18:10:58 +0300362#define DWC3_DSTS_PWRUPREQ (1 << 24)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800363
364/* These apply for core versions 1.94a and later */
365#define DWC3_DSTS_RSS (1 << 25)
366#define DWC3_DSTS_SSS (1 << 24)
367
Felipe Balbi72246da2011-08-19 18:10:58 +0300368#define DWC3_DSTS_COREIDLE (1 << 23)
369#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
370
371#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
372#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
373
374#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
375
Pratyush Anandd05b8182012-05-21 14:51:30 +0530376#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
Felipe Balbi72246da2011-08-19 18:10:58 +0300377#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
378
379#define DWC3_DSTS_CONNECTSPD (7 << 0)
380
John Youn1f38f882016-02-05 17:08:31 -0800381#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
Felipe Balbi72246da2011-08-19 18:10:58 +0300382#define DWC3_DSTS_SUPERSPEED (4 << 0)
383#define DWC3_DSTS_HIGHSPEED (0 << 0)
384#define DWC3_DSTS_FULLSPEED2 (1 << 0)
385#define DWC3_DSTS_LOWSPEED (2 << 0)
386#define DWC3_DSTS_FULLSPEED1 (3 << 0)
387
388/* Device Generic Command Register */
389#define DWC3_DGCMD_SET_LMP 0x01
390#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
391#define DWC3_DGCMD_XMIT_FUNCTION 0x03
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800392
393/* These apply for core versions 1.94a and later */
394#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
395#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
396
Felipe Balbi72246da2011-08-19 18:10:58 +0300397#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
398#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
399#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
400#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
401
Subbaraya Sundeep Bhatta459e2102015-05-21 15:46:46 +0530402#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
Felipe Balbib09bb642012-04-24 16:19:11 +0300403#define DWC3_DGCMD_CMDACT (1 << 10)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800404#define DWC3_DGCMD_CMDIOC (1 << 8)
405
406/* Device Generic Command Parameter Register */
407#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
408#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
409#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
410#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
411#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
412#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
Felipe Balbib09bb642012-04-24 16:19:11 +0300413
Felipe Balbi72246da2011-08-19 18:10:58 +0300414/* Device Endpoint Command Register */
415#define DWC3_DEPCMD_PARAM_SHIFT 16
Paul Zimmerman1d046792012-02-15 18:56:56 -0800416#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
Felipe Balbi835fadb2013-12-19 14:02:53 -0600417#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
Subbaraya Sundeep Bhatta459e2102015-05-21 15:46:46 +0530418#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
Felipe Balbi72246da2011-08-19 18:10:58 +0300419#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
John Youn50c763f2016-05-31 17:49:56 -0700420#define DWC3_DEPCMD_CLEARPENDIN (1 << 11)
Felipe Balbi72246da2011-08-19 18:10:58 +0300421#define DWC3_DEPCMD_CMDACT (1 << 10)
422#define DWC3_DEPCMD_CMDIOC (1 << 8)
423
424#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
425#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
426#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
427#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
428#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
429#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800430/* This applies for core versions 1.90a and earlier */
Felipe Balbi72246da2011-08-19 18:10:58 +0300431#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800432/* This applies for core versions 1.94a and later */
433#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
Felipe Balbi72246da2011-08-19 18:10:58 +0300434#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
435#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
436
437/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
438#define DWC3_DALEPENA_EP(n) (1 << n)
439
440#define DWC3_DEPCMD_TYPE_CONTROL 0
441#define DWC3_DEPCMD_TYPE_ISOC 1
442#define DWC3_DEPCMD_TYPE_BULK 2
443#define DWC3_DEPCMD_TYPE_INTR 3
444
445/* Structures */
446
Felipe Balbif6bafc62012-02-06 11:04:53 +0200447struct dwc3_trb;
Felipe Balbi72246da2011-08-19 18:10:58 +0300448
449/**
450 * struct dwc3_event_buffer - Software event buffer representation
Felipe Balbi72246da2011-08-19 18:10:58 +0300451 * @buf: _THE_ buffer
452 * @length: size of this buffer
Felipe Balbiabed4112011-07-04 20:20:04 +0300453 * @lpos: event offset
Felipe Balbi60d04bb2011-07-04 20:23:14 +0300454 * @count: cache of last read event count register
Felipe Balbiabed4112011-07-04 20:20:04 +0300455 * @flags: flags related to this event buffer
Felipe Balbi72246da2011-08-19 18:10:58 +0300456 * @dma: dma_addr_t
457 * @dwc: pointer to DWC controller
458 */
459struct dwc3_event_buffer {
460 void *buf;
461 unsigned length;
462 unsigned int lpos;
Felipe Balbi60d04bb2011-07-04 20:23:14 +0300463 unsigned int count;
Felipe Balbiabed4112011-07-04 20:20:04 +0300464 unsigned int flags;
465
466#define DWC3_EVENT_PENDING BIT(0)
Felipe Balbi72246da2011-08-19 18:10:58 +0300467
468 dma_addr_t dma;
469
470 struct dwc3 *dwc;
471};
472
473#define DWC3_EP_FLAG_STALLED (1 << 0)
474#define DWC3_EP_FLAG_WEDGED (1 << 1)
475
476#define DWC3_EP_DIRECTION_TX true
477#define DWC3_EP_DIRECTION_RX false
478
Felipe Balbi84950362016-03-10 14:40:31 +0200479#define DWC3_TRB_NUM 256
Felipe Balbi72246da2011-08-19 18:10:58 +0300480
481/**
482 * struct dwc3_ep - device side endpoint representation
483 * @endpoint: usb endpoint
Felipe Balbiaa3342c2016-03-14 11:01:31 +0200484 * @pending_list: list of pending requests for this endpoint
485 * @started_list: list of started requests on this endpoint
Felipe Balbi74674cb2016-04-13 16:44:39 +0300486 * @lock: spinlock for endpoint request queue traversal
Felipe Balbi2eb88012016-04-12 16:53:39 +0300487 * @regs: pointer to first endpoint register
Felipe Balbi72246da2011-08-19 18:10:58 +0300488 * @trb_pool: array of transaction buffers
489 * @trb_pool_dma: dma address of @trb_pool
Felipe Balbi53fd8812016-04-04 15:33:41 +0300490 * @trb_enqueue: enqueue 'pointer' into TRB array
491 * @trb_dequeue: dequeue 'pointer' into TRB array
Felipe Balbi72246da2011-08-19 18:10:58 +0300492 * @desc: usb_endpoint_descriptor pointer
493 * @dwc: pointer to DWC controller
Paul Zimmerman4cfcf872012-04-27 13:56:23 +0300494 * @saved_state: ep state saved during hibernation
Felipe Balbi72246da2011-08-19 18:10:58 +0300495 * @flags: endpoint flags (wedged, stalled, ...)
Felipe Balbi72246da2011-08-19 18:10:58 +0300496 * @number: endpoint number (1 - 15)
497 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
Felipe Balbib4996a82012-06-06 12:04:13 +0300498 * @resource_index: Resource transfer index
Huang Ruic75f52f2013-06-12 23:43:11 +0800499 * @interval: the interval on which the ISOC transfer is started
Felipe Balbi72246da2011-08-19 18:10:58 +0300500 * @name: a human readable name e.g. ep1out-bulk
501 * @direction: true for TX, false for RX
Felipe Balbi879631a2011-09-30 10:58:47 +0300502 * @stream_capable: true when streams are enabled
Felipe Balbi72246da2011-08-19 18:10:58 +0300503 */
504struct dwc3_ep {
505 struct usb_ep endpoint;
Felipe Balbiaa3342c2016-03-14 11:01:31 +0200506 struct list_head pending_list;
507 struct list_head started_list;
Felipe Balbi72246da2011-08-19 18:10:58 +0300508
Felipe Balbi74674cb2016-04-13 16:44:39 +0300509 spinlock_t lock;
Felipe Balbi2eb88012016-04-12 16:53:39 +0300510 void __iomem *regs;
511
Felipe Balbif6bafc62012-02-06 11:04:53 +0200512 struct dwc3_trb *trb_pool;
Felipe Balbi72246da2011-08-19 18:10:58 +0300513 dma_addr_t trb_pool_dma;
Felipe Balbic90bfae2011-11-29 13:11:21 +0200514 const struct usb_ss_ep_comp_descriptor *comp_desc;
Felipe Balbi72246da2011-08-19 18:10:58 +0300515 struct dwc3 *dwc;
516
Paul Zimmerman4cfcf872012-04-27 13:56:23 +0300517 u32 saved_state;
Felipe Balbi72246da2011-08-19 18:10:58 +0300518 unsigned flags;
519#define DWC3_EP_ENABLED (1 << 0)
520#define DWC3_EP_STALL (1 << 1)
521#define DWC3_EP_WEDGE (1 << 2)
522#define DWC3_EP_BUSY (1 << 4)
523#define DWC3_EP_PENDING_REQUEST (1 << 5)
Pratyush Anandd6d6ec72012-05-25 18:54:56 +0530524#define DWC3_EP_MISSED_ISOC (1 << 6)
Felipe Balbi72246da2011-08-19 18:10:58 +0300525
Felipe Balbi984f66a2011-08-27 22:26:00 +0300526 /* This last one is specific to EP0 */
527#define DWC3_EP0_DIR_IN (1 << 31)
528
Felipe Balbic28f8252016-04-05 12:42:15 +0300529 /*
530 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
531 * use a u8 type here. If anybody decides to increase number of TRBs to
532 * anything larger than 256 - I can't see why people would want to do
533 * this though - then this type needs to be changed.
534 *
535 * By using u8 types we ensure that our % operator when incrementing
536 * enqueue and dequeue get optimized away by the compiler.
537 */
538 u8 trb_enqueue;
539 u8 trb_dequeue;
540
Felipe Balbi72246da2011-08-19 18:10:58 +0300541 u8 number;
542 u8 type;
Felipe Balbib4996a82012-06-06 12:04:13 +0300543 u8 resource_index;
Felipe Balbi72246da2011-08-19 18:10:58 +0300544 u32 interval;
545
546 char name[20];
547
548 unsigned direction:1;
Felipe Balbi879631a2011-09-30 10:58:47 +0300549 unsigned stream_capable:1;
Felipe Balbi72246da2011-08-19 18:10:58 +0300550};
551
552enum dwc3_phy {
553 DWC3_PHY_UNKNOWN = 0,
554 DWC3_PHY_USB3,
555 DWC3_PHY_USB2,
556};
557
Felipe Balbib53c7722011-08-30 15:50:40 +0300558enum dwc3_ep0_next {
559 DWC3_EP0_UNKNOWN = 0,
560 DWC3_EP0_COMPLETE,
Felipe Balbib53c7722011-08-30 15:50:40 +0300561 DWC3_EP0_NRDY_DATA,
562 DWC3_EP0_NRDY_STATUS,
563};
564
Felipe Balbi72246da2011-08-19 18:10:58 +0300565enum dwc3_ep0_state {
566 EP0_UNCONNECTED = 0,
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300567 EP0_SETUP_PHASE,
568 EP0_DATA_PHASE,
569 EP0_STATUS_PHASE,
Felipe Balbi72246da2011-08-19 18:10:58 +0300570};
571
572enum dwc3_link_state {
573 /* In SuperSpeed */
574 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
575 DWC3_LINK_STATE_U1 = 0x01,
576 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
577 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
578 DWC3_LINK_STATE_SS_DIS = 0x04,
579 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
580 DWC3_LINK_STATE_SS_INACT = 0x06,
581 DWC3_LINK_STATE_POLL = 0x07,
582 DWC3_LINK_STATE_RECOV = 0x08,
583 DWC3_LINK_STATE_HRESET = 0x09,
584 DWC3_LINK_STATE_CMPLY = 0x0a,
585 DWC3_LINK_STATE_LPBK = 0x0b,
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800586 DWC3_LINK_STATE_RESET = 0x0e,
587 DWC3_LINK_STATE_RESUME = 0x0f,
Felipe Balbi72246da2011-08-19 18:10:58 +0300588 DWC3_LINK_STATE_MASK = 0x0f,
589};
590
Felipe Balbif6bafc62012-02-06 11:04:53 +0200591/* TRB Length, PCM and Status */
592#define DWC3_TRB_SIZE_MASK (0x00ffffff)
593#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
594#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
Pratyush Anand389f2822012-05-21 12:46:26 +0530595#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
Felipe Balbi72246da2011-08-19 18:10:58 +0300596
Felipe Balbif6bafc62012-02-06 11:04:53 +0200597#define DWC3_TRBSTS_OK 0
598#define DWC3_TRBSTS_MISSED_ISOC 1
599#define DWC3_TRBSTS_SETUP_PENDING 2
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800600#define DWC3_TRB_STS_XFER_IN_PROG 4
Felipe Balbi72246da2011-08-19 18:10:58 +0300601
Felipe Balbif6bafc62012-02-06 11:04:53 +0200602/* TRB Control */
603#define DWC3_TRB_CTRL_HWO (1 << 0)
604#define DWC3_TRB_CTRL_LST (1 << 1)
605#define DWC3_TRB_CTRL_CHN (1 << 2)
606#define DWC3_TRB_CTRL_CSP (1 << 3)
607#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
608#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
609#define DWC3_TRB_CTRL_IOC (1 << 11)
610#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
611
Felipe Balbib058f3e2016-04-14 16:05:54 +0300612#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
Felipe Balbif6bafc62012-02-06 11:04:53 +0200613#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
614#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
615#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
616#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
617#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
618#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
619#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
620#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
Felipe Balbi72246da2011-08-19 18:10:58 +0300621
622/**
Felipe Balbif6bafc62012-02-06 11:04:53 +0200623 * struct dwc3_trb - transfer request block (hw format)
Felipe Balbi72246da2011-08-19 18:10:58 +0300624 * @bpl: DW0-3
625 * @bph: DW4-7
626 * @size: DW8-B
627 * @trl: DWC-F
628 */
Felipe Balbif6bafc62012-02-06 11:04:53 +0200629struct dwc3_trb {
630 u32 bpl;
631 u32 bph;
632 u32 size;
633 u32 ctrl;
Felipe Balbi72246da2011-08-19 18:10:58 +0300634} __packed;
635
Felipe Balbi72246da2011-08-19 18:10:58 +0300636/**
Felipe Balbia3299492011-09-30 10:58:48 +0300637 * dwc3_hwparams - copy of HWPARAMS registers
638 * @hwparams0 - GHWPARAMS0
639 * @hwparams1 - GHWPARAMS1
640 * @hwparams2 - GHWPARAMS2
641 * @hwparams3 - GHWPARAMS3
642 * @hwparams4 - GHWPARAMS4
643 * @hwparams5 - GHWPARAMS5
644 * @hwparams6 - GHWPARAMS6
645 * @hwparams7 - GHWPARAMS7
646 * @hwparams8 - GHWPARAMS8
647 */
648struct dwc3_hwparams {
649 u32 hwparams0;
650 u32 hwparams1;
651 u32 hwparams2;
652 u32 hwparams3;
653 u32 hwparams4;
654 u32 hwparams5;
655 u32 hwparams6;
656 u32 hwparams7;
657 u32 hwparams8;
658};
659
Felipe Balbi0949e992011-10-12 10:44:56 +0300660/* HWPARAMS0 */
661#define DWC3_MODE(n) ((n) & 0x7)
662
Felipe Balbi457e84b2012-01-18 18:04:09 +0200663#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
664
Felipe Balbi0949e992011-10-12 10:44:56 +0300665/* HWPARAMS1 */
Felipe Balbi457e84b2012-01-18 18:04:09 +0200666#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
667
Felipe Balbi789451f62011-05-05 15:53:10 +0300668/* HWPARAMS3 */
669#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
670#define DWC3_NUM_EPS_MASK (0x3f << 12)
671#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
672 (DWC3_NUM_EPS_MASK)) >> 12)
673#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
674 (DWC3_NUM_IN_EPS_MASK)) >> 18)
675
Felipe Balbi457e84b2012-01-18 18:04:09 +0200676/* HWPARAMS7 */
677#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
Felipe Balbi9f622b22011-10-12 10:31:04 +0300678
Felipe Balbi5ef68c52016-04-05 11:33:30 +0300679/**
680 * struct dwc3_request - representation of a transfer request
681 * @request: struct usb_request to be transferred
682 * @list: a list_head used for request queueing
683 * @dep: struct dwc3_ep owning this request
684 * @first_trb_index: index to first trb used by this request
685 * @epnum: endpoint number to which this request refers
686 * @trb: pointer to struct dwc3_trb
687 * @trb_dma: DMA address of @trb
688 * @direction: IN or OUT direction flag
689 * @mapped: true when request has been dma-mapped
690 * @queued: true when request has been queued to HW
691 */
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100692struct dwc3_request {
693 struct usb_request request;
694 struct list_head list;
695 struct dwc3_ep *dep;
696
Felipe Balbic28f8252016-04-05 12:42:15 +0300697 u8 first_trb_index;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100698 u8 epnum;
Felipe Balbif6bafc62012-02-06 11:04:53 +0200699 struct dwc3_trb *trb;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100700 dma_addr_t trb_dma;
701
702 unsigned direction:1;
703 unsigned mapped:1;
Felipe Balbiaa3342c2016-03-14 11:01:31 +0200704 unsigned started:1;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100705};
706
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800707/*
708 * struct dwc3_scratchpad_array - hibernation scratchpad array
709 * (format defined by hw)
710 */
711struct dwc3_scratchpad_array {
712 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
713};
714
Felipe Balbia3299492011-09-30 10:58:48 +0300715/**
Felipe Balbi72246da2011-08-19 18:10:58 +0300716 * struct dwc3 - representation of our controller
Felipe Balbi91db07d2011-08-27 01:40:52 +0300717 * @ctrl_req: usb control request which is used for ep0
718 * @ep0_trb: trb which is used for the ctrl_req
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300719 * @ep0_bounce: bounce buffer for ep0
Felipe Balbi04c03d12015-12-02 10:06:45 -0600720 * @zlp_buf: used when request->zero is set
Felipe Balbi91db07d2011-08-27 01:40:52 +0300721 * @setup_buf: used while precessing STD USB requests
722 * @ctrl_req_addr: dma address of ctrl_req
723 * @ep0_trb: dma address of ep0_trb
724 * @ep0_usb_req: dummy req used while handling STD USB requests
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300725 * @ep0_bounce_addr: dma address of ep0_bounce
Felipe Balbi0ffcaf32013-12-19 13:04:28 -0600726 * @scratch_addr: dma address of scratchbuf
Felipe Balbi72246da2011-08-19 18:10:58 +0300727 * @lock: for synchronizing
728 * @dev: pointer to our struct device
Felipe Balbid07e8812011-10-12 14:08:26 +0300729 * @xhci: pointer to our xHCI child
Felipe Balbi72246da2011-08-19 18:10:58 +0300730 * @event_buffer_list: a list of event buffers
731 * @gadget: device side representation of the peripheral controller
732 * @gadget_driver: pointer to the gadget driver
733 * @regs: base address for our registers
734 * @regs_size: address space size
Felipe Balbibcdb3272016-05-16 10:42:23 +0300735 * @fladj: frame length adjustment
Felipe Balbi3f308d12016-05-16 14:17:06 +0300736 * @irq_gadget: peripheral controller's IRQ number
Felipe Balbi0ffcaf32013-12-19 13:04:28 -0600737 * @nr_scratch: number of scratch buffers
Felipe Balbifae2b902011-10-14 13:00:30 +0300738 * @u1u2: only used on revisions <1.83a for workaround
Felipe Balbi6c167fc2011-10-07 22:55:04 +0300739 * @maximum_speed: maximum speed requested (mainly for testing purposes)
Felipe Balbi72246da2011-08-19 18:10:58 +0300740 * @revision: revision register contents
Ruchika Kharwara45c82b82013-07-06 07:52:49 -0500741 * @dr_mode: requested mode of operation
Felipe Balbi51e1e7b2012-07-19 14:09:48 +0300742 * @usb2_phy: pointer to USB2 PHY
743 * @usb3_phy: pointer to USB3 PHY
Kishon Vijay Abraham I57303482014-03-03 17:08:11 +0530744 * @usb2_generic_phy: pointer to USB2 PHY
745 * @usb3_generic_phy: pointer to USB3 PHY
Heikki Krogerus88bc9d12015-05-13 15:26:51 +0300746 * @ulpi: pointer to ulpi interface
Felipe Balbi7415f172012-04-30 14:56:33 +0300747 * @dcfg: saved contents of DCFG register
748 * @gctl: saved contents of GCTL register
Felipe Balbic12a0d82012-04-25 10:45:05 +0300749 * @isoch_delay: wValue from Set Isochronous Delay request;
Felipe Balbi865e09e2012-04-24 16:19:49 +0300750 * @u2sel: parameter from Set SEL request.
751 * @u2pel: parameter from Set SEL request.
752 * @u1sel: parameter from Set SEL request.
753 * @u1pel: parameter from Set SEL request.
Felipe Balbi789451f62011-05-05 15:53:10 +0300754 * @num_out_eps: number of out endpoints
755 * @num_in_eps: number of in endpoints
Felipe Balbib53c7722011-08-30 15:50:40 +0300756 * @ep0_next_event: hold the next expected event
Felipe Balbi72246da2011-08-19 18:10:58 +0300757 * @ep0state: state of endpoint zero
758 * @link_state: link state
759 * @speed: device speed (super, high, full, low)
760 * @mem: points to start of memory which is used for this struct.
Felipe Balbia3299492011-09-30 10:58:48 +0300761 * @hwparams: copy of hwparams registers
Felipe Balbi72246da2011-08-19 18:10:58 +0300762 * @root: debugfs root folder pointer
Felipe Balbif2b685d2013-12-19 12:12:37 -0600763 * @regset: debugfs pointer to regdump file
764 * @test_mode: true when we're entering a USB test mode
765 * @test_mode_nr: test feature selector
Huang Rui80caf7d2014-10-28 19:54:26 +0800766 * @lpm_nyet_threshold: LPM NYET response threshold
Huang Rui460d0982014-10-31 11:11:18 +0800767 * @hird_threshold: HIRD threshold
Heikki Krogerus3e10a2c2015-05-13 15:26:49 +0300768 * @hsphy_interface: "utmi" or "ulpi"
Felipe Balbifc8bb912016-05-16 13:14:48 +0300769 * @connected: true when we're connected to a host, false otherwise
Felipe Balbif2b685d2013-12-19 12:12:37 -0600770 * @delayed_status: true when gadget driver asks for delayed status
771 * @ep0_bounced: true when we used bounce buffer
772 * @ep0_expect_in: true when we expect a DATA IN transfer
Felipe Balbi81bc5592013-12-19 12:14:29 -0600773 * @has_hibernation: true when dwc3 was configured with Hibernation
Huang Rui80caf7d2014-10-28 19:54:26 +0800774 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
775 * there's now way for software to detect this in runtime.
Huang Rui460d0982014-10-31 11:11:18 +0800776 * @is_utmi_l1_suspend: the core asserts output signal
777 * 0 - utmi_sleep_n
778 * 1 - utmi_l1_suspend_n
Huang Rui946bd572014-10-28 19:54:23 +0800779 * @is_fpga: true when we are using the FPGA board
Felipe Balbifc8bb912016-05-16 13:14:48 +0300780 * @pending_events: true when we have pending IRQs to be handled
Felipe Balbif2b685d2013-12-19 12:12:37 -0600781 * @pullups_connected: true when Run/Stop bit is set
Felipe Balbif2b685d2013-12-19 12:12:37 -0600782 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
783 * @start_config_issued: true when StartConfig command has been issued
784 * @three_stage_setup: set if we perform a three phase setup
Robert Baldygaeac68e82015-03-09 15:06:12 +0100785 * @usb3_lpm_capable: set if hadrware supports Link Power Management
Huang Rui3b812212014-10-28 19:54:25 +0800786 * @disable_scramble_quirk: set if we enable the disable scramble quirk
Huang Rui9a5b2f32014-10-28 19:54:27 +0800787 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
Huang Ruib5a65c42014-10-28 19:54:28 +0800788 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
Huang Ruidf31f5b2014-10-28 19:54:29 +0800789 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
Huang Ruia2a1d0f2014-10-28 19:54:30 +0800790 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
Huang Rui41c06ff2014-10-28 19:54:31 +0800791 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
Huang Ruifb67afc2014-10-28 19:54:32 +0800792 * @lfps_filter_quirk: set if we enable LFPS filter quirk
Huang Rui14f4ac52014-10-28 19:54:33 +0800793 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
Huang Rui59acfa22014-10-31 11:11:13 +0800794 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
Huang Rui0effe0a2014-10-31 11:11:14 +0800795 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
John Younec791d12015-10-02 20:30:57 -0700796 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
797 * disabling the suspend signal to the PHY.
Huang Rui6b6a0c92014-10-31 11:11:12 +0800798 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
799 * @tx_de_emphasis: Tx de-emphasis value
800 * 0 - -6dB de-emphasis
801 * 1 - -3.5dB de-emphasis
802 * 2 - No de-emphasis
803 * 3 - Reserved
Felipe Balbi72246da2011-08-19 18:10:58 +0300804 */
805struct dwc3 {
806 struct usb_ctrlrequest *ctrl_req;
Felipe Balbif6bafc62012-02-06 11:04:53 +0200807 struct dwc3_trb *ep0_trb;
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300808 void *ep0_bounce;
Felipe Balbi04c03d12015-12-02 10:06:45 -0600809 void *zlp_buf;
Felipe Balbi0ffcaf32013-12-19 13:04:28 -0600810 void *scratchbuf;
Felipe Balbi72246da2011-08-19 18:10:58 +0300811 u8 *setup_buf;
812 dma_addr_t ctrl_req_addr;
813 dma_addr_t ep0_trb_addr;
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300814 dma_addr_t ep0_bounce_addr;
Felipe Balbi0ffcaf32013-12-19 13:04:28 -0600815 dma_addr_t scratch_addr;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100816 struct dwc3_request ep0_usb_req;
Felipe Balbi789451f62011-05-05 15:53:10 +0300817
Felipe Balbi72246da2011-08-19 18:10:58 +0300818 /* device lock */
819 spinlock_t lock;
Felipe Balbi789451f62011-05-05 15:53:10 +0300820
Felipe Balbi72246da2011-08-19 18:10:58 +0300821 struct device *dev;
822
Felipe Balbid07e8812011-10-12 14:08:26 +0300823 struct platform_device *xhci;
Ido Shayevitz51249dc2012-04-24 14:18:39 +0300824 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
Felipe Balbid07e8812011-10-12 14:08:26 +0300825
Felipe Balbi696c8b12016-03-30 09:37:03 +0300826 struct dwc3_event_buffer *ev_buf;
Felipe Balbi72246da2011-08-19 18:10:58 +0300827 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
828
829 struct usb_gadget gadget;
830 struct usb_gadget_driver *gadget_driver;
831
Felipe Balbi51e1e7b2012-07-19 14:09:48 +0300832 struct usb_phy *usb2_phy;
833 struct usb_phy *usb3_phy;
834
Kishon Vijay Abraham I57303482014-03-03 17:08:11 +0530835 struct phy *usb2_generic_phy;
836 struct phy *usb3_generic_phy;
837
Heikki Krogerus88bc9d12015-05-13 15:26:51 +0300838 struct ulpi *ulpi;
839
Felipe Balbi72246da2011-08-19 18:10:58 +0300840 void __iomem *regs;
841 size_t regs_size;
842
Ruchika Kharwara45c82b82013-07-06 07:52:49 -0500843 enum usb_dr_mode dr_mode;
844
Felipe Balbibcdb3272016-05-16 10:42:23 +0300845 u32 fladj;
Felipe Balbi3f308d12016-05-16 14:17:06 +0300846 u32 irq_gadget;
Felipe Balbi0ffcaf32013-12-19 13:04:28 -0600847 u32 nr_scratch;
Felipe Balbifae2b902011-10-14 13:00:30 +0300848 u32 u1u2;
Felipe Balbi6c167fc2011-10-07 22:55:04 +0300849 u32 maximum_speed;
John Youn690fb372015-09-04 19:15:10 -0700850
851 /*
852 * All 3.1 IP version constants are greater than the 3.0 IP
853 * version constants. This works for most version checks in
854 * dwc3. However, in the future, this may not apply as
855 * features may be developed on newer versions of the 3.0 IP
856 * that are not in the 3.1 IP.
857 */
Felipe Balbi72246da2011-08-19 18:10:58 +0300858 u32 revision;
859
860#define DWC3_REVISION_173A 0x5533173a
861#define DWC3_REVISION_175A 0x5533175a
862#define DWC3_REVISION_180A 0x5533180a
863#define DWC3_REVISION_183A 0x5533183a
864#define DWC3_REVISION_185A 0x5533185a
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800865#define DWC3_REVISION_187A 0x5533187a
Felipe Balbi72246da2011-08-19 18:10:58 +0300866#define DWC3_REVISION_188A 0x5533188a
867#define DWC3_REVISION_190A 0x5533190a
Paul Zimmerman2c61a8e2012-02-15 18:56:58 -0800868#define DWC3_REVISION_194A 0x5533194a
Felipe Balbi1522d702012-03-23 12:10:48 +0200869#define DWC3_REVISION_200A 0x5533200a
870#define DWC3_REVISION_202A 0x5533202a
871#define DWC3_REVISION_210A 0x5533210a
872#define DWC3_REVISION_220A 0x5533220a
Felipe Balbi7ac6a592012-09-18 21:22:32 +0300873#define DWC3_REVISION_230A 0x5533230a
874#define DWC3_REVISION_240A 0x5533240a
875#define DWC3_REVISION_250A 0x5533250a
Felipe Balbidbf5aaf2014-03-04 09:35:02 -0600876#define DWC3_REVISION_260A 0x5533260a
877#define DWC3_REVISION_270A 0x5533270a
878#define DWC3_REVISION_280A 0x5533280a
Felipe Balbi72246da2011-08-19 18:10:58 +0300879
John Youn690fb372015-09-04 19:15:10 -0700880/*
881 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
882 * just so dwc31 revisions are always larger than dwc3.
883 */
884#define DWC3_REVISION_IS_DWC31 0x80000000
John Youne77c5612016-05-20 16:34:23 -0700885#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
John Youn690fb372015-09-04 19:15:10 -0700886
Felipe Balbib53c7722011-08-30 15:50:40 +0300887 enum dwc3_ep0_next ep0_next_event;
Felipe Balbi72246da2011-08-19 18:10:58 +0300888 enum dwc3_ep0_state ep0state;
889 enum dwc3_link_state link_state;
Felipe Balbi72246da2011-08-19 18:10:58 +0300890
Felipe Balbic12a0d82012-04-25 10:45:05 +0300891 u16 isoch_delay;
Felipe Balbi865e09e2012-04-24 16:19:49 +0300892 u16 u2sel;
893 u16 u2pel;
894 u8 u1sel;
895 u8 u1pel;
896
Felipe Balbi72246da2011-08-19 18:10:58 +0300897 u8 speed;
Felipe Balbi865e09e2012-04-24 16:19:49 +0300898
Felipe Balbi789451f62011-05-05 15:53:10 +0300899 u8 num_out_eps;
900 u8 num_in_eps;
901
Felipe Balbi72246da2011-08-19 18:10:58 +0300902 void *mem;
903
Felipe Balbia3299492011-09-30 10:58:48 +0300904 struct dwc3_hwparams hwparams;
Felipe Balbi72246da2011-08-19 18:10:58 +0300905 struct dentry *root;
Felipe Balbid76680242013-01-18 10:21:34 +0200906 struct debugfs_regset32 *regset;
Gerard Cauvy3b637362012-02-10 12:21:18 +0200907
908 u8 test_mode;
909 u8 test_mode_nr;
Huang Rui80caf7d2014-10-28 19:54:26 +0800910 u8 lpm_nyet_threshold;
Huang Rui460d0982014-10-31 11:11:18 +0800911 u8 hird_threshold;
Felipe Balbif2b685d2013-12-19 12:12:37 -0600912
Heikki Krogerus3e10a2c2015-05-13 15:26:49 +0300913 const char *hsphy_interface;
914
Felipe Balbifc8bb912016-05-16 13:14:48 +0300915 unsigned connected:1;
Felipe Balbif2b685d2013-12-19 12:12:37 -0600916 unsigned delayed_status:1;
917 unsigned ep0_bounced:1;
918 unsigned ep0_expect_in:1;
Felipe Balbi81bc5592013-12-19 12:14:29 -0600919 unsigned has_hibernation:1;
Huang Rui80caf7d2014-10-28 19:54:26 +0800920 unsigned has_lpm_erratum:1;
Huang Rui460d0982014-10-31 11:11:18 +0800921 unsigned is_utmi_l1_suspend:1;
Huang Rui946bd572014-10-28 19:54:23 +0800922 unsigned is_fpga:1;
Felipe Balbifc8bb912016-05-16 13:14:48 +0300923 unsigned pending_events:1;
Felipe Balbif2b685d2013-12-19 12:12:37 -0600924 unsigned pullups_connected:1;
Felipe Balbif2b685d2013-12-19 12:12:37 -0600925 unsigned setup_packet_pending:1;
Felipe Balbif2b685d2013-12-19 12:12:37 -0600926 unsigned three_stage_setup:1;
Robert Baldygaeac68e82015-03-09 15:06:12 +0100927 unsigned usb3_lpm_capable:1;
Huang Rui3b812212014-10-28 19:54:25 +0800928
929 unsigned disable_scramble_quirk:1;
Huang Rui9a5b2f32014-10-28 19:54:27 +0800930 unsigned u2exit_lfps_quirk:1;
Huang Ruib5a65c42014-10-28 19:54:28 +0800931 unsigned u2ss_inp3_quirk:1;
Huang Ruidf31f5b2014-10-28 19:54:29 +0800932 unsigned req_p1p2p3_quirk:1;
Huang Ruia2a1d0f2014-10-28 19:54:30 +0800933 unsigned del_p1p2p3_quirk:1;
Huang Rui41c06ff2014-10-28 19:54:31 +0800934 unsigned del_phy_power_chg_quirk:1;
Huang Ruifb67afc2014-10-28 19:54:32 +0800935 unsigned lfps_filter_quirk:1;
Huang Rui14f4ac52014-10-28 19:54:33 +0800936 unsigned rx_detect_poll_quirk:1;
Huang Rui59acfa22014-10-31 11:11:13 +0800937 unsigned dis_u3_susphy_quirk:1;
Huang Rui0effe0a2014-10-31 11:11:14 +0800938 unsigned dis_u2_susphy_quirk:1;
John Younec791d12015-10-02 20:30:57 -0700939 unsigned dis_enblslpm_quirk:1;
Rajesh Bhagate58dd352016-03-14 14:40:50 +0530940 unsigned dis_rxdet_inp3_quirk:1;
Huang Rui6b6a0c92014-10-31 11:11:12 +0800941
942 unsigned tx_de_emphasis_quirk:1;
943 unsigned tx_de_emphasis:2;
Felipe Balbi72246da2011-08-19 18:10:58 +0300944};
945
946/* -------------------------------------------------------------------------- */
947
Felipe Balbi72246da2011-08-19 18:10:58 +0300948/* -------------------------------------------------------------------------- */
949
950struct dwc3_event_type {
951 u32 is_devspec:1;
Huang Rui1974d492013-06-27 01:08:11 +0800952 u32 type:7;
953 u32 reserved8_31:24;
Felipe Balbi72246da2011-08-19 18:10:58 +0300954} __packed;
955
956#define DWC3_DEPEVT_XFERCOMPLETE 0x01
957#define DWC3_DEPEVT_XFERINPROGRESS 0x02
958#define DWC3_DEPEVT_XFERNOTREADY 0x03
959#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
960#define DWC3_DEPEVT_STREAMEVT 0x06
961#define DWC3_DEPEVT_EPCMDCMPLT 0x07
962
963/**
964 * struct dwc3_event_depvt - Device Endpoint Events
965 * @one_bit: indicates this is an endpoint event (not used)
966 * @endpoint_number: number of the endpoint
967 * @endpoint_event: The event we have:
968 * 0x00 - Reserved
969 * 0x01 - XferComplete
970 * 0x02 - XferInProgress
971 * 0x03 - XferNotReady
972 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
973 * 0x05 - Reserved
974 * 0x06 - StreamEvt
975 * 0x07 - EPCmdCmplt
976 * @reserved11_10: Reserved, don't use.
977 * @status: Indicates the status of the event. Refer to databook for
978 * more information.
979 * @parameters: Parameters of the current event. Refer to databook for
980 * more information.
981 */
982struct dwc3_event_depevt {
983 u32 one_bit:1;
984 u32 endpoint_number:5;
985 u32 endpoint_event:4;
986 u32 reserved11_10:2;
987 u32 status:4;
Felipe Balbi40aa41f2012-01-18 17:06:03 +0200988
989/* Within XferNotReady */
990#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
991
992/* Within XferComplete */
Paul Zimmerman1d046792012-02-15 18:56:56 -0800993#define DEPEVT_STATUS_BUSERR (1 << 0)
994#define DEPEVT_STATUS_SHORT (1 << 1)
995#define DEPEVT_STATUS_IOC (1 << 2)
Felipe Balbi72246da2011-08-19 18:10:58 +0300996#define DEPEVT_STATUS_LST (1 << 3)
Felipe Balbidc137f02011-08-27 22:04:32 +0300997
Felipe Balbi879631a2011-09-30 10:58:47 +0300998/* Stream event only */
999#define DEPEVT_STREAMEVT_FOUND 1
1000#define DEPEVT_STREAMEVT_NOTFOUND 2
1001
Felipe Balbidc137f02011-08-27 22:04:32 +03001002/* Control-only Status */
Felipe Balbidc137f02011-08-27 22:04:32 +03001003#define DEPEVT_STATUS_CONTROL_DATA 1
1004#define DEPEVT_STATUS_CONTROL_STATUS 2
1005
Konrad Leszczynski7b9cc7a2016-02-12 15:21:46 +00001006/* In response to Start Transfer */
1007#define DEPEVT_TRANSFER_NO_RESOURCE 1
1008#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1009
Felipe Balbi72246da2011-08-19 18:10:58 +03001010 u32 parameters:16;
1011} __packed;
1012
1013/**
1014 * struct dwc3_event_devt - Device Events
1015 * @one_bit: indicates this is a non-endpoint event (not used)
1016 * @device_event: indicates it's a device event. Should read as 0x00
1017 * @type: indicates the type of device event.
1018 * 0 - DisconnEvt
1019 * 1 - USBRst
1020 * 2 - ConnectDone
1021 * 3 - ULStChng
1022 * 4 - WkUpEvt
1023 * 5 - Reserved
1024 * 6 - EOPF
1025 * 7 - SOF
1026 * 8 - Reserved
1027 * 9 - ErrticErr
1028 * 10 - CmdCmplt
1029 * 11 - EvntOverflow
1030 * 12 - VndrDevTstRcved
1031 * @reserved15_12: Reserved, not used
1032 * @event_info: Information about this event
Huang Rui06f9b6e2014-01-07 17:45:50 +08001033 * @reserved31_25: Reserved, not used
Felipe Balbi72246da2011-08-19 18:10:58 +03001034 */
1035struct dwc3_event_devt {
1036 u32 one_bit:1;
1037 u32 device_event:7;
1038 u32 type:4;
1039 u32 reserved15_12:4;
Huang Rui06f9b6e2014-01-07 17:45:50 +08001040 u32 event_info:9;
1041 u32 reserved31_25:7;
Felipe Balbi72246da2011-08-19 18:10:58 +03001042} __packed;
1043
1044/**
1045 * struct dwc3_event_gevt - Other Core Events
1046 * @one_bit: indicates this is a non-endpoint event (not used)
1047 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1048 * @phy_port_number: self-explanatory
1049 * @reserved31_12: Reserved, not used.
1050 */
1051struct dwc3_event_gevt {
1052 u32 one_bit:1;
1053 u32 device_event:7;
1054 u32 phy_port_number:4;
1055 u32 reserved31_12:20;
1056} __packed;
1057
1058/**
1059 * union dwc3_event - representation of Event Buffer contents
1060 * @raw: raw 32-bit event
1061 * @type: the type of the event
1062 * @depevt: Device Endpoint Event
1063 * @devt: Device Event
1064 * @gevt: Global Event
1065 */
1066union dwc3_event {
1067 u32 raw;
1068 struct dwc3_event_type type;
1069 struct dwc3_event_depevt depevt;
1070 struct dwc3_event_devt devt;
1071 struct dwc3_event_gevt gevt;
1072};
1073
Felipe Balbi61018302014-03-04 09:23:50 -06001074/**
1075 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1076 * parameters
1077 * @param2: third parameter
1078 * @param1: second parameter
1079 * @param0: first parameter
1080 */
1081struct dwc3_gadget_ep_cmd_params {
1082 u32 param2;
1083 u32 param1;
1084 u32 param0;
1085};
1086
Felipe Balbi72246da2011-08-19 18:10:58 +03001087/*
1088 * DWC3 Features to be used as Driver Data
1089 */
1090
1091#define DWC3_HAS_PERIPHERAL BIT(0)
1092#define DWC3_HAS_XHCI BIT(1)
1093#define DWC3_HAS_OTG BIT(3)
1094
Felipe Balbid07e8812011-10-12 14:08:26 +03001095/* prototypes */
Sebastian Andrzej Siewior3140e8cb2011-10-31 22:25:40 +01001096void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
Felipe Balbicf6d8672016-04-14 15:03:39 +03001097u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
Sebastian Andrzej Siewior3140e8cb2011-10-31 22:25:40 +01001098
John Younc4137a92016-02-05 17:08:18 -08001099/* check whether we are on the DWC_usb31 core */
1100static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1101{
1102 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1103}
1104
Vivek Gautam388e5c52013-01-15 16:09:21 +05301105#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
Felipe Balbid07e8812011-10-12 14:08:26 +03001106int dwc3_host_init(struct dwc3 *dwc);
1107void dwc3_host_exit(struct dwc3 *dwc);
Vivek Gautam388e5c52013-01-15 16:09:21 +05301108#else
1109static inline int dwc3_host_init(struct dwc3 *dwc)
1110{ return 0; }
1111static inline void dwc3_host_exit(struct dwc3 *dwc)
1112{ }
1113#endif
Felipe Balbid07e8812011-10-12 14:08:26 +03001114
Vivek Gautam388e5c52013-01-15 16:09:21 +05301115#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
Felipe Balbif80b45e2011-10-12 14:15:49 +03001116int dwc3_gadget_init(struct dwc3 *dwc);
1117void dwc3_gadget_exit(struct dwc3 *dwc);
Felipe Balbi61018302014-03-04 09:23:50 -06001118int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1119int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1120int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
Felipe Balbi2cd47182016-04-12 16:42:43 +03001121int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1122 struct dwc3_gadget_ep_cmd_params *params);
Felipe Balbi3ece0ec2014-09-05 09:47:44 -05001123int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
Vivek Gautam388e5c52013-01-15 16:09:21 +05301124#else
1125static inline int dwc3_gadget_init(struct dwc3 *dwc)
1126{ return 0; }
1127static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1128{ }
Felipe Balbi61018302014-03-04 09:23:50 -06001129static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1130{ return 0; }
1131static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1132{ return 0; }
1133static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1134 enum dwc3_link_state state)
1135{ return 0; }
1136
Felipe Balbi2cd47182016-04-12 16:42:43 +03001137static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1138 struct dwc3_gadget_ep_cmd_params *params)
Felipe Balbi61018302014-03-04 09:23:50 -06001139{ return 0; }
1140static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1141 int cmd, u32 param)
1142{ return 0; }
Vivek Gautam388e5c52013-01-15 16:09:21 +05301143#endif
Felipe Balbif80b45e2011-10-12 14:15:49 +03001144
Felipe Balbi7415f172012-04-30 14:56:33 +03001145/* power management interface */
1146#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
Felipe Balbi7415f172012-04-30 14:56:33 +03001147int dwc3_gadget_suspend(struct dwc3 *dwc);
1148int dwc3_gadget_resume(struct dwc3 *dwc);
Felipe Balbifc8bb912016-05-16 13:14:48 +03001149void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
Felipe Balbi7415f172012-04-30 14:56:33 +03001150#else
Felipe Balbi7415f172012-04-30 14:56:33 +03001151static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1152{
1153 return 0;
1154}
1155
1156static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1157{
1158 return 0;
1159}
Felipe Balbifc8bb912016-05-16 13:14:48 +03001160
1161static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1162{
1163}
Felipe Balbi7415f172012-04-30 14:56:33 +03001164#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1165
Heikki Krogerus88bc9d12015-05-13 15:26:51 +03001166#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1167int dwc3_ulpi_init(struct dwc3 *dwc);
1168void dwc3_ulpi_exit(struct dwc3 *dwc);
1169#else
1170static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1171{ return 0; }
1172static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1173{ }
1174#endif
1175
Felipe Balbi72246da2011-08-19 18:10:58 +03001176#endif /* __DRIVERS_USB_DWC3_CORE_H */