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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl-topology.h"
27#include "skl.h"
28#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053029#include "../common/sst-dsp.h"
30#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010031
Jeeja KPf7590d42015-10-07 11:31:53 +010032#define SKL_CH_FIXUP_MASK (1 << 0)
33#define SKL_RATE_FIXUP_MASK (1 << 1)
34#define SKL_FMT_FIXUP_MASK (1 << 2)
35
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010036/*
37 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
38 * ignore. This helpers checks if the SKL driver handles this widget type
39 */
40static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
41{
42 switch (w->id) {
43 case snd_soc_dapm_dai_link:
44 case snd_soc_dapm_dai_in:
45 case snd_soc_dapm_aif_in:
46 case snd_soc_dapm_aif_out:
47 case snd_soc_dapm_dai_out:
48 case snd_soc_dapm_switch:
49 return false;
50 default:
51 return true;
52 }
53}
54
55/*
56 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053057 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010058 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053059static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010060 struct skl_module_cfg *mconfig)
61{
62 struct skl_sst *ctx = skl->skl_sst;
63
64 if (skl->resource.mem + mconfig->pipe->memory_pages >
65 skl->resource.max_mem) {
66 dev_err(ctx->dev,
67 "%s: module_id %d instance %d\n", __func__,
68 mconfig->id.module_id,
69 mconfig->id.instance_id);
70 dev_err(ctx->dev,
71 "exceeds ppl memory available %d mem %d\n",
72 skl->resource.max_mem, skl->resource.mem);
73 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053074 } else {
75 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010076 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053077}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010078
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053079/*
80 * Add the mem to the mem pool. This is freed when pipe is deleted.
81 * Note: DSP does actual memory management we only keep track for complete
82 * pool
83 */
84static void skl_tplg_alloc_pipe_mem(struct skl *skl,
85 struct skl_module_cfg *mconfig)
86{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010087 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010088}
89
90/*
91 * Pipeline needs needs DSP CPU resources for computation, this is
92 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
93 *
94 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053095 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010096 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053097
98static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 struct skl_module_cfg *mconfig)
100{
101 struct skl_sst *ctx = skl->skl_sst;
102
103 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
104 dev_err(ctx->dev,
105 "%s: module_id %d instance %d\n", __func__,
106 mconfig->id.module_id, mconfig->id.instance_id);
107 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530108 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100109 skl->resource.max_mcps, skl->resource.mcps);
110 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530111 } else {
112 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100113 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530114}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100115
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530116static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
117 struct skl_module_cfg *mconfig)
118{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100120}
121
122/*
123 * Free the mcps when tearing down
124 */
125static void
126skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
127{
128 skl->resource.mcps -= mconfig->mcps;
129}
130
131/*
132 * Free the memory when tearing down
133 */
134static void
135skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
136{
137 skl->resource.mem -= mconfig->pipe->memory_pages;
138}
139
Jeeja KPf7590d42015-10-07 11:31:53 +0100140
141static void skl_dump_mconfig(struct skl_sst *ctx,
142 struct skl_module_cfg *mcfg)
143{
144 dev_dbg(ctx->dev, "Dumping config\n");
145 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900146 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
147 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
148 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
149 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100150 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900151 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
152 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
153 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
154 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100155}
156
157static void skl_tplg_update_params(struct skl_module_fmt *fmt,
158 struct skl_pipe_params *params, int fixup)
159{
160 if (fixup & SKL_RATE_FIXUP_MASK)
161 fmt->s_freq = params->s_freq;
162 if (fixup & SKL_CH_FIXUP_MASK)
163 fmt->channels = params->ch;
Jeeja KP98256f82015-11-23 22:26:25 +0530164 if (fixup & SKL_FMT_FIXUP_MASK) {
165 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
166
167 /*
168 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
169 * container so update bit depth accordingly
170 */
171 switch (fmt->valid_bit_depth) {
172 case SKL_DEPTH_16BIT:
173 fmt->bit_depth = fmt->valid_bit_depth;
174 break;
175
176 default:
177 fmt->bit_depth = SKL_DEPTH_32BIT;
178 break;
179 }
180 }
181
Jeeja KPf7590d42015-10-07 11:31:53 +0100182}
183
184/*
185 * A pipeline may have modules which impact the pcm parameters, like SRC,
186 * channel converter, format converter.
187 * We need to calculate the output params by applying the 'fixup'
188 * Topology will tell driver which type of fixup is to be applied by
189 * supplying the fixup mask, so based on that we calculate the output
190 *
191 * Now In FE the pcm hw_params is source/target format. Same is applicable
192 * for BE with its hw_params invoked.
193 * here based on FE, BE pipeline and direction we calculate the input and
194 * outfix and then apply that for a module
195 */
196static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
197 struct skl_pipe_params *params, bool is_fe)
198{
199 int in_fixup, out_fixup;
200 struct skl_module_fmt *in_fmt, *out_fmt;
201
Hardik T Shah4cd98992015-10-27 09:22:55 +0900202 /* Fixups will be applied to pin 0 only */
203 in_fmt = &m_cfg->in_fmt[0];
204 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100205
206 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
207 if (is_fe) {
208 in_fixup = m_cfg->params_fixup;
209 out_fixup = (~m_cfg->converter) &
210 m_cfg->params_fixup;
211 } else {
212 out_fixup = m_cfg->params_fixup;
213 in_fixup = (~m_cfg->converter) &
214 m_cfg->params_fixup;
215 }
216 } else {
217 if (is_fe) {
218 out_fixup = m_cfg->params_fixup;
219 in_fixup = (~m_cfg->converter) &
220 m_cfg->params_fixup;
221 } else {
222 in_fixup = m_cfg->params_fixup;
223 out_fixup = (~m_cfg->converter) &
224 m_cfg->params_fixup;
225 }
226 }
227
228 skl_tplg_update_params(in_fmt, params, in_fixup);
229 skl_tplg_update_params(out_fmt, params, out_fixup);
230}
231
232/*
233 * A module needs input and output buffers, which are dependent upon pcm
234 * params, so once we have calculate params, we need buffer calculation as
235 * well.
236 */
237static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
238 struct skl_module_cfg *mcfg)
239{
240 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900241 struct skl_module_fmt *in_fmt, *out_fmt;
242
243
244 /* Since fixups is applied to pin 0 only, ibs, obs needs
245 * change for pin 0 only
246 */
247 in_fmt = &mcfg->in_fmt[0];
248 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100249
250 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
251 multiplier = 5;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900252 mcfg->ibs = (in_fmt->s_freq / 1000) *
253 (mcfg->in_fmt->channels) *
254 (mcfg->in_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100255 multiplier;
256
Hardik T Shah4cd98992015-10-27 09:22:55 +0900257 mcfg->obs = (mcfg->out_fmt->s_freq / 1000) *
258 (mcfg->out_fmt->channels) *
259 (mcfg->out_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100260 multiplier;
261}
262
263static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
264 struct skl_sst *ctx)
265{
266 struct skl_module_cfg *m_cfg = w->priv;
267 struct skl_pipe_params *params = m_cfg->pipe->p_params;
268 int p_conn_type = m_cfg->pipe->conn_type;
269 bool is_fe;
270
271 if (!m_cfg->params_fixup)
272 return;
273
274 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
275 w->name);
276
277 skl_dump_mconfig(ctx, m_cfg);
278
279 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
280 is_fe = true;
281 else
282 is_fe = false;
283
284 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
285 skl_tplg_update_buffer_size(ctx, m_cfg);
286
287 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
288 w->name);
289
290 skl_dump_mconfig(ctx, m_cfg);
291}
292
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100293/*
294 * A pipe can have multiple modules, each of them will be a DAPM widget as
295 * well. While managing a pipeline we need to get the list of all the
296 * widgets in a pipelines, so this helper - skl_tplg_get_pipe_widget() helps
297 * to get the SKL type widgets in that pipeline
298 */
299static int skl_tplg_alloc_pipe_widget(struct device *dev,
300 struct snd_soc_dapm_widget *w, struct skl_pipe *pipe)
301{
302 struct skl_module_cfg *src_module = NULL;
303 struct snd_soc_dapm_path *p = NULL;
304 struct skl_pipe_module *p_module = NULL;
305
306 p_module = devm_kzalloc(dev, sizeof(*p_module), GFP_KERNEL);
307 if (!p_module)
308 return -ENOMEM;
309
310 p_module->w = w;
311 list_add_tail(&p_module->node, &pipe->w_list);
312
313 snd_soc_dapm_widget_for_each_sink_path(w, p) {
314 if ((p->sink->priv == NULL)
315 && (!is_skl_dsp_widget_type(w)))
316 continue;
317
318 if ((p->sink->priv != NULL) && p->connect
319 && is_skl_dsp_widget_type(p->sink)) {
320
321 src_module = p->sink->priv;
322 if (pipe->ppl_id == src_module->pipe->ppl_id)
323 skl_tplg_alloc_pipe_widget(dev,
324 p->sink, pipe);
325 }
326 }
327 return 0;
328}
329
330/*
Jeeja KPabb74002015-11-28 15:01:49 +0530331 * some modules can have multiple params set from user control and
332 * need to be set after module is initialized. If set_param flag is
333 * set module params will be done after module is initialised.
334 */
335static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
336 struct skl_sst *ctx)
337{
338 int i, ret;
339 struct skl_module_cfg *mconfig = w->priv;
340 const struct snd_kcontrol_new *k;
341 struct soc_bytes_ext *sb;
342 struct skl_algo_data *bc;
343 struct skl_specific_cfg *sp_cfg;
344
345 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530346 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530347 sp_cfg = &mconfig->formats_config;
348 ret = skl_set_module_params(ctx, sp_cfg->caps,
349 sp_cfg->caps_size,
350 sp_cfg->param_id, mconfig);
351 if (ret < 0)
352 return ret;
353 }
354
355 for (i = 0; i < w->num_kcontrols; i++) {
356 k = &w->kcontrol_news[i];
357 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
358 sb = (void *) k->private_value;
359 bc = (struct skl_algo_data *)sb->dobj.private;
360
Jeeja KP4ced1822015-12-03 23:29:53 +0530361 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530362 ret = skl_set_module_params(ctx,
363 (u32 *)bc->params, bc->max,
364 bc->param_id, mconfig);
365 if (ret < 0)
366 return ret;
367 }
368 }
369 }
370
371 return 0;
372}
373
374/*
375 * some module param can set from user control and this is required as
376 * when module is initailzed. if module param is required in init it is
377 * identifed by set_param flag. if set_param flag is not set, then this
378 * parameter needs to set as part of module init.
379 */
380static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
381{
382 const struct snd_kcontrol_new *k;
383 struct soc_bytes_ext *sb;
384 struct skl_algo_data *bc;
385 struct skl_module_cfg *mconfig = w->priv;
386 int i;
387
388 for (i = 0; i < w->num_kcontrols; i++) {
389 k = &w->kcontrol_news[i];
390 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
391 sb = (struct soc_bytes_ext *)k->private_value;
392 bc = (struct skl_algo_data *)sb->dobj.private;
393
Jeeja KP4ced1822015-12-03 23:29:53 +0530394 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530395 continue;
396
397 mconfig->formats_config.caps = (u32 *)&bc->params;
398 mconfig->formats_config.caps_size = bc->max;
399
400 break;
401 }
402 }
403
404 return 0;
405}
406
407/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100408 * Inside a pipe instance, we can have various modules. These modules need
409 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
410 * skl_init_module() routine, so invoke that for all modules in a pipeline
411 */
412static int
413skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
414{
415 struct skl_pipe_module *w_module;
416 struct snd_soc_dapm_widget *w;
417 struct skl_module_cfg *mconfig;
418 struct skl_sst *ctx = skl->skl_sst;
419 int ret = 0;
420
421 list_for_each_entry(w_module, &pipe->w_list, node) {
422 w = w_module->w;
423 mconfig = w->priv;
424
425 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530426 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100427 return -ENOMEM;
428
Dharageswari R6c5768b2015-12-03 23:29:50 +0530429 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
430 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
431 mconfig->id.module_id, mconfig->guid);
432 if (ret < 0)
433 return ret;
434 }
435
Jeeja KPf7590d42015-10-07 11:31:53 +0100436 /*
437 * apply fix/conversion to module params based on
438 * FE/BE params
439 */
440 skl_tplg_update_module_params(w, ctx);
Jeeja KPabb74002015-11-28 15:01:49 +0530441
442 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530443 ret = skl_init_module(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100444 if (ret < 0)
445 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530446
447 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100448 if (ret < 0)
449 return ret;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530450 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100451 }
452
453 return 0;
454}
Vinod Kould93f8e52015-10-07 11:31:54 +0100455
Dharageswari R6c5768b2015-12-03 23:29:50 +0530456static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
457 struct skl_pipe *pipe)
458{
459 struct skl_pipe_module *w_module = NULL;
460 struct skl_module_cfg *mconfig = NULL;
461
462 list_for_each_entry(w_module, &pipe->w_list, node) {
463 mconfig = w_module->w->priv;
464
465 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod)
466 return ctx->dsp->fw_ops.unload_mod(ctx->dsp,
467 mconfig->id.module_id);
468 }
469
470 /* no modules to unload in this path, so return */
471 return 0;
472}
473
Vinod Kould93f8e52015-10-07 11:31:54 +0100474/*
475 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
476 * need create the pipeline. So we do following:
477 * - check the resources
478 * - Create the pipeline
479 * - Initialize the modules in pipeline
480 * - finally bind all modules together
481 */
482static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
483 struct skl *skl)
484{
485 int ret;
486 struct skl_module_cfg *mconfig = w->priv;
487 struct skl_pipe_module *w_module;
488 struct skl_pipe *s_pipe = mconfig->pipe;
489 struct skl_module_cfg *src_module = NULL, *dst_module;
490 struct skl_sst *ctx = skl->skl_sst;
491
492 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530493 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100494 return -EBUSY;
495
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530496 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100497 return -ENOMEM;
498
499 /*
500 * Create a list of modules for pipe.
501 * This list contains modules from source to sink
502 */
503 ret = skl_create_pipeline(ctx, mconfig->pipe);
504 if (ret < 0)
505 return ret;
506
507 /*
508 * we create a w_list of all widgets in that pipe. This list is not
509 * freed on PMD event as widgets within a pipe are static. This
510 * saves us cycles to get widgets in pipe every time.
511 *
512 * So if we have already initialized all the widgets of a pipeline
513 * we skip, so check for list_empty and create the list if empty
514 */
515 if (list_empty(&s_pipe->w_list)) {
516 ret = skl_tplg_alloc_pipe_widget(ctx->dev, w, s_pipe);
517 if (ret < 0)
518 return ret;
519 }
520
521 /* Init all pipe modules from source to sink */
522 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
523 if (ret < 0)
524 return ret;
525
526 /* Bind modules from source to sink */
527 list_for_each_entry(w_module, &s_pipe->w_list, node) {
528 dst_module = w_module->w->priv;
529
530 if (src_module == NULL) {
531 src_module = dst_module;
532 continue;
533 }
534
535 ret = skl_bind_modules(ctx, src_module, dst_module);
536 if (ret < 0)
537 return ret;
538
539 src_module = dst_module;
540 }
541
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530542 skl_tplg_alloc_pipe_mem(skl, mconfig);
543 skl_tplg_alloc_pipe_mcps(skl, mconfig);
544
Vinod Kould93f8e52015-10-07 11:31:54 +0100545 return 0;
546}
547
Jeeja KP8724ff12015-10-27 09:22:52 +0900548static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
549 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530550 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900551 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100552{
553 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530554 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900555 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100556 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900557 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100558
Jeeja KP8724ff12015-10-27 09:22:52 +0900559 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100560 if (!p->connect)
561 continue;
562
563 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
564 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
565
Jeeja KP0ed95d72015-11-13 19:22:11 +0530566 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530567
568 if (!is_skl_dsp_widget_type(p->sink))
569 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
570
Vinod Kould93f8e52015-10-07 11:31:54 +0100571 /*
572 * here we will check widgets in sink pipelines, so that
573 * can be any widgets type and we are only interested if
574 * they are ones used for SKL so check that first
575 */
576 if ((p->sink->priv != NULL) &&
577 is_skl_dsp_widget_type(p->sink)) {
578
579 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100580 sink_mconfig = sink->priv;
581
582 /* Bind source to sink, mixin is always source */
583 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
584 if (ret)
585 return ret;
586
587 /* Start sinks pipe first */
588 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900589 if (sink_mconfig->pipe->conn_type !=
590 SKL_PIPE_CONN_TYPE_FE)
591 ret = skl_run_pipe(ctx,
592 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100593 if (ret)
594 return ret;
595 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100596 }
597 }
598
Jeeja KP8724ff12015-10-27 09:22:52 +0900599 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530600 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900601
602 return 0;
603}
604
Vinod Kould93f8e52015-10-07 11:31:54 +0100605/*
606 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
607 * we need to do following:
608 * - Bind to sink pipeline
609 * Since the sink pipes can be running and we don't get mixer event on
610 * connect for already running mixer, we need to find the sink pipes
611 * here and bind to them. This way dynamic connect works.
612 * - Start sink pipeline, if not running
613 * - Then run current pipe
614 */
615static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900616 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100617{
Jeeja KP8724ff12015-10-27 09:22:52 +0900618 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100619 struct skl_sst *ctx = skl->skl_sst;
620 int ret = 0;
621
Jeeja KP8724ff12015-10-27 09:22:52 +0900622 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100623
624 /*
625 * find which sink it is connected to, bind with the sink,
626 * if sink is not started, start sink pipe first, then start
627 * this pipe
628 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530629 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100630 if (ret)
631 return ret;
632
Vinod Kould93f8e52015-10-07 11:31:54 +0100633 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900634 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
635 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100636
637 return 0;
638}
639
Jeeja KP8724ff12015-10-27 09:22:52 +0900640static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
641 struct snd_soc_dapm_widget *w, struct skl *skl)
642{
643 struct snd_soc_dapm_path *p;
644 struct snd_soc_dapm_widget *src_w = NULL;
645 struct skl_sst *ctx = skl->skl_sst;
646
647 snd_soc_dapm_widget_for_each_source_path(w, p) {
648 src_w = p->source;
649 if (!p->connect)
650 continue;
651
652 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
653 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
654
655 /*
656 * here we will check widgets in sink pipelines, so that can
657 * be any widgets type and we are only interested if they are
658 * ones used for SKL so check that first
659 */
660 if ((p->source->priv != NULL) &&
661 is_skl_dsp_widget_type(p->source)) {
662 return p->source;
663 }
664 }
665
666 if (src_w != NULL)
667 return skl_get_src_dsp_widget(src_w, skl);
668
669 return NULL;
670}
671
Vinod Kould93f8e52015-10-07 11:31:54 +0100672/*
673 * in the Post-PMU event of mixer we need to do following:
674 * - Check if this pipe is running
675 * - if not, then
676 * - bind this pipeline to its source pipeline
677 * if source pipe is already running, this means it is a dynamic
678 * connection and we need to bind only to that pipe
679 * - start this pipeline
680 */
681static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
682 struct skl *skl)
683{
684 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100685 struct snd_soc_dapm_widget *source, *sink;
686 struct skl_module_cfg *src_mconfig, *sink_mconfig;
687 struct skl_sst *ctx = skl->skl_sst;
688 int src_pipe_started = 0;
689
690 sink = w;
691 sink_mconfig = sink->priv;
692
693 /*
694 * If source pipe is already started, that means source is driving
695 * one more sink before this sink got connected, Since source is
696 * started, bind this sink to source and start this pipe.
697 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900698 source = skl_get_src_dsp_widget(w, skl);
699 if (source != NULL) {
700 src_mconfig = source->priv;
701 sink_mconfig = sink->priv;
702 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100703
704 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900705 * check pipe state, then no need to bind or start the
706 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100707 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900708 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
709 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100710 }
711
712 if (src_pipe_started) {
713 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
714 if (ret)
715 return ret;
716
Jeeja KPd1730c32015-10-27 09:22:53 +0900717 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
718 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100719 }
720
721 return ret;
722}
723
724/*
725 * in the Pre-PMD event of mixer we need to do following:
726 * - Stop the pipe
727 * - find the source connections and remove that from dapm_path_list
728 * - unbind with source pipelines if still connected
729 */
730static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
731 struct skl *skl)
732{
Vinod Kould93f8e52015-10-07 11:31:54 +0100733 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900734 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100735 struct skl_sst *ctx = skl->skl_sst;
736
Jeeja KPce1b5552015-10-27 09:22:51 +0900737 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100738
739 /* Stop the pipe */
740 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
741 if (ret)
742 return ret;
743
Jeeja KPce1b5552015-10-27 09:22:51 +0900744 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
745 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
746 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
747 if (!src_mconfig)
748 continue;
749 /*
750 * If path_found == 1, that means pmd for source
751 * pipe has not occurred, source is connected to
752 * some other sink. so its responsibility of sink
753 * to unbind itself from source.
754 */
755 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
756 if (ret < 0)
757 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100758
Jeeja KPce1b5552015-10-27 09:22:51 +0900759 ret = skl_unbind_modules(ctx,
760 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100761 }
762 }
763
Vinod Kould93f8e52015-10-07 11:31:54 +0100764 return ret;
765}
766
767/*
768 * in the Post-PMD event of mixer we need to do following:
769 * - Free the mcps used
770 * - Free the mem used
771 * - Unbind the modules within the pipeline
772 * - Delete the pipeline (modules are not required to be explicitly
773 * deleted, pipeline delete is enough here
774 */
775static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
776 struct skl *skl)
777{
778 struct skl_module_cfg *mconfig = w->priv;
779 struct skl_pipe_module *w_module;
780 struct skl_module_cfg *src_module = NULL, *dst_module;
781 struct skl_sst *ctx = skl->skl_sst;
782 struct skl_pipe *s_pipe = mconfig->pipe;
783 int ret = 0;
784
785 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +0530786 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100787
788 list_for_each_entry(w_module, &s_pipe->w_list, node) {
789 dst_module = w_module->w->priv;
790
Vinod Koul7ae3cb12015-11-05 21:34:10 +0530791 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100792 if (src_module == NULL) {
793 src_module = dst_module;
794 continue;
795 }
796
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530797 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100798 src_module = dst_module;
799 }
800
801 ret = skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100802
Dharageswari R6c5768b2015-12-03 23:29:50 +0530803 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100804}
805
806/*
807 * in the Post-PMD event of PGA we need to do following:
808 * - Free the mcps used
809 * - Stop the pipeline
810 * - In source pipe is connected, unbind with source pipelines
811 */
812static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
813 struct skl *skl)
814{
Vinod Kould93f8e52015-10-07 11:31:54 +0100815 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900816 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100817 struct skl_sst *ctx = skl->skl_sst;
818
Jeeja KPce1b5552015-10-27 09:22:51 +0900819 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100820
Vinod Kould93f8e52015-10-07 11:31:54 +0100821 /* Stop the pipe since this is a mixin module */
822 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
823 if (ret)
824 return ret;
825
Jeeja KPce1b5552015-10-27 09:22:51 +0900826 for (i = 0; i < src_mconfig->max_out_queue; i++) {
827 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
828 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
829 if (!sink_mconfig)
830 continue;
831 /*
832 * This is a connecter and if path is found that means
833 * unbind between source and sink has not happened yet
834 */
Jeeja KPce1b5552015-10-27 09:22:51 +0900835 ret = skl_unbind_modules(ctx, src_mconfig,
836 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100837 }
838 }
839
Vinod Kould93f8e52015-10-07 11:31:54 +0100840 return ret;
841}
842
843/*
844 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
845 * mixer is not required then it is treated as static mixer aka vmixer with
846 * a hard path to source module
847 * So we don't need to check if source is started or not as hard path puts
848 * dependency on each other
849 */
850static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
851 struct snd_kcontrol *k, int event)
852{
853 struct snd_soc_dapm_context *dapm = w->dapm;
854 struct skl *skl = get_skl_ctx(dapm->dev);
855
856 switch (event) {
857 case SND_SOC_DAPM_PRE_PMU:
858 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
859
860 case SND_SOC_DAPM_POST_PMD:
861 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
862 }
863
864 return 0;
865}
866
867/*
868 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
869 * second one is required that is created as another pipe entity.
870 * The mixer is responsible for pipe management and represent a pipeline
871 * instance
872 */
873static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
874 struct snd_kcontrol *k, int event)
875{
876 struct snd_soc_dapm_context *dapm = w->dapm;
877 struct skl *skl = get_skl_ctx(dapm->dev);
878
879 switch (event) {
880 case SND_SOC_DAPM_PRE_PMU:
881 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
882
883 case SND_SOC_DAPM_POST_PMU:
884 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
885
886 case SND_SOC_DAPM_PRE_PMD:
887 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
888
889 case SND_SOC_DAPM_POST_PMD:
890 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
891 }
892
893 return 0;
894}
895
896/*
897 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
898 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
899 * the sink when it is running (two FE to one BE or one FE to two BE)
900 * scenarios
901 */
902static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
903 struct snd_kcontrol *k, int event)
904
905{
906 struct snd_soc_dapm_context *dapm = w->dapm;
907 struct skl *skl = get_skl_ctx(dapm->dev);
908
909 switch (event) {
910 case SND_SOC_DAPM_PRE_PMU:
911 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
912
913 case SND_SOC_DAPM_POST_PMD:
914 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
915 }
916
917 return 0;
918}
Vinod Koulcfb0a872015-10-07 11:31:55 +0100919
Jeeja KP140adfb2015-11-28 15:01:50 +0530920static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
921 unsigned int __user *data, unsigned int size)
922{
923 struct soc_bytes_ext *sb =
924 (struct soc_bytes_ext *)kcontrol->private_value;
925 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +0530926 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
927 struct skl_module_cfg *mconfig = w->priv;
928 struct skl *skl = get_skl_ctx(w->dapm->dev);
929
930 if (w->power)
931 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
932 bc->max, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +0530933
Vinod Koul41556f62016-02-03 17:59:44 +0530934 /* decrement size for TLV header */
935 size -= 2 * sizeof(u32);
936
937 /* check size as we don't want to send kernel data */
938 if (size > bc->max)
939 size = bc->max;
940
Jeeja KP140adfb2015-11-28 15:01:50 +0530941 if (bc->params) {
942 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
943 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +0300944 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +0530945 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +0300946 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +0530947 return -EFAULT;
948 }
949
950 return 0;
951}
952
953#define SKL_PARAM_VENDOR_ID 0xff
954
955static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
956 const unsigned int __user *data, unsigned int size)
957{
958 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
959 struct skl_module_cfg *mconfig = w->priv;
960 struct soc_bytes_ext *sb =
961 (struct soc_bytes_ext *)kcontrol->private_value;
962 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
963 struct skl *skl = get_skl_ctx(w->dapm->dev);
964
965 if (ac->params) {
966 /*
967 * if the param_is is of type Vendor, firmware expects actual
968 * parameter id and size from the control.
969 */
970 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
971 if (copy_from_user(ac->params, data, size))
972 return -EFAULT;
973 } else {
974 if (copy_from_user(ac->params,
975 data + 2 * sizeof(u32), size))
976 return -EFAULT;
977 }
978
979 if (w->power)
980 return skl_set_module_params(skl->skl_sst,
981 (u32 *)ac->params, ac->max,
982 ac->param_id, mconfig);
983 }
984
985 return 0;
986}
987
Vinod Koulcfb0a872015-10-07 11:31:55 +0100988/*
989 * The FE params are passed by hw_params of the DAI.
990 * On hw_params, the params are stored in Gateway module of the FE and we
991 * need to calculate the format in DSP module configuration, that
992 * conversion is done here
993 */
994int skl_tplg_update_pipe_params(struct device *dev,
995 struct skl_module_cfg *mconfig,
996 struct skl_pipe_params *params)
997{
998 struct skl_pipe *pipe = mconfig->pipe;
999 struct skl_module_fmt *format = NULL;
1000
1001 memcpy(pipe->p_params, params, sizeof(*params));
1002
1003 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001004 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001005 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001006 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001007
1008 /* set the hw_params */
1009 format->s_freq = params->s_freq;
1010 format->channels = params->ch;
1011 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1012
1013 /*
1014 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1015 * container so update bit depth accordingly
1016 */
1017 switch (format->valid_bit_depth) {
1018 case SKL_DEPTH_16BIT:
1019 format->bit_depth = format->valid_bit_depth;
1020 break;
1021
1022 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001023 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001024 format->bit_depth = SKL_DEPTH_32BIT;
1025 break;
1026
1027 default:
1028 dev_err(dev, "Invalid bit depth %x for pipe\n",
1029 format->valid_bit_depth);
1030 return -EINVAL;
1031 }
1032
1033 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1034 mconfig->ibs = (format->s_freq / 1000) *
1035 (format->channels) *
1036 (format->bit_depth >> 3);
1037 } else {
1038 mconfig->obs = (format->s_freq / 1000) *
1039 (format->channels) *
1040 (format->bit_depth >> 3);
1041 }
1042
1043 return 0;
1044}
1045
1046/*
1047 * Query the module config for the FE DAI
1048 * This is used to find the hw_params set for that DAI and apply to FE
1049 * pipeline
1050 */
1051struct skl_module_cfg *
1052skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1053{
1054 struct snd_soc_dapm_widget *w;
1055 struct snd_soc_dapm_path *p = NULL;
1056
1057 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1058 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301059 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001060 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001061 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001062 continue;
1063
1064 if (p->sink->priv) {
1065 dev_dbg(dai->dev, "set params for %s\n",
1066 p->sink->name);
1067 return p->sink->priv;
1068 }
1069 }
1070 } else {
1071 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301072 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001073 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001074 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001075 continue;
1076
1077 if (p->source->priv) {
1078 dev_dbg(dai->dev, "set params for %s\n",
1079 p->source->name);
1080 return p->source->priv;
1081 }
1082 }
1083 }
1084
1085 return NULL;
1086}
1087
1088static u8 skl_tplg_be_link_type(int dev_type)
1089{
1090 int ret;
1091
1092 switch (dev_type) {
1093 case SKL_DEVICE_BT:
1094 ret = NHLT_LINK_SSP;
1095 break;
1096
1097 case SKL_DEVICE_DMIC:
1098 ret = NHLT_LINK_DMIC;
1099 break;
1100
1101 case SKL_DEVICE_I2S:
1102 ret = NHLT_LINK_SSP;
1103 break;
1104
1105 case SKL_DEVICE_HDALINK:
1106 ret = NHLT_LINK_HDA;
1107 break;
1108
1109 default:
1110 ret = NHLT_LINK_INVALID;
1111 break;
1112 }
1113
1114 return ret;
1115}
1116
1117/*
1118 * Fill the BE gateway parameters
1119 * The BE gateway expects a blob of parameters which are kept in the ACPI
1120 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1121 * The port can have multiple settings so pick based on the PCM
1122 * parameters
1123 */
1124static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1125 struct skl_module_cfg *mconfig,
1126 struct skl_pipe_params *params)
1127{
1128 struct skl_pipe *pipe = mconfig->pipe;
1129 struct nhlt_specific_cfg *cfg;
1130 struct skl *skl = get_skl_ctx(dai->dev);
1131 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
1132
1133 memcpy(pipe->p_params, params, sizeof(*params));
1134
Jeeja KPb30c2752015-10-27 09:22:48 +09001135 if (link_type == NHLT_LINK_HDA)
1136 return 0;
1137
Vinod Koulcfb0a872015-10-07 11:31:55 +01001138 /* update the blob based on virtual bus_id*/
1139 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1140 params->s_fmt, params->ch,
1141 params->s_freq, params->stream);
1142 if (cfg) {
1143 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301144 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001145 } else {
1146 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1147 mconfig->vbus_id, link_type,
1148 params->stream);
1149 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1150 params->ch, params->s_freq, params->s_fmt);
1151 return -EINVAL;
1152 }
1153
1154 return 0;
1155}
1156
1157static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1158 struct snd_soc_dapm_widget *w,
1159 struct skl_pipe_params *params)
1160{
1161 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301162 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001163
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301164 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001165 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1166 p->source->priv) {
1167
Jeeja KP9a03cb42015-10-27 09:22:54 +09001168 ret = skl_tplg_be_fill_pipe_params(dai,
1169 p->source->priv, params);
1170 if (ret < 0)
1171 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001172 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001173 ret = skl_tplg_be_set_src_pipe_params(dai,
1174 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301175 if (ret < 0)
1176 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001177 }
1178 }
1179
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301180 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001181}
1182
1183static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1184 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1185{
1186 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301187 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001188
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301189 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001190 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1191 p->sink->priv) {
1192
Jeeja KP9a03cb42015-10-27 09:22:54 +09001193 ret = skl_tplg_be_fill_pipe_params(dai,
1194 p->sink->priv, params);
1195 if (ret < 0)
1196 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001197 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301198 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001199 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301200 if (ret < 0)
1201 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001202 }
1203 }
1204
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301205 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001206}
1207
1208/*
1209 * BE hw_params can be a source parameters (capture) or sink parameters
1210 * (playback). Based on sink and source we need to either find the source
1211 * list or the sink list and set the pipeline parameters
1212 */
1213int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1214 struct skl_pipe_params *params)
1215{
1216 struct snd_soc_dapm_widget *w;
1217
1218 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1219 w = dai->playback_widget;
1220
1221 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1222
1223 } else {
1224 w = dai->capture_widget;
1225
1226 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1227 }
1228
1229 return 0;
1230}
Vinod Koul3af36702015-10-07 11:31:56 +01001231
1232static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1233 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1234 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1235 {SKL_PGA_EVENT, skl_tplg_pga_event},
1236};
1237
Jeeja KP140adfb2015-11-28 15:01:50 +05301238static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1239 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1240 skl_tplg_tlv_control_set},
1241};
1242
Vinod Koul3af36702015-10-07 11:31:56 +01001243/*
1244 * The topology binary passes the pin info for a module so initialize the pin
1245 * info passed into module instance
1246 */
Jeeja KP6abca1d2015-10-22 23:22:42 +05301247static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin,
1248 struct skl_module_pin *m_pin,
1249 bool is_dynamic, int max_pin)
Vinod Koul3af36702015-10-07 11:31:56 +01001250{
1251 int i;
1252
1253 for (i = 0; i < max_pin; i++) {
Jeeja KP6abca1d2015-10-22 23:22:42 +05301254 m_pin[i].id.module_id = dfw_pin[i].module_id;
1255 m_pin[i].id.instance_id = dfw_pin[i].instance_id;
Vinod Koul3af36702015-10-07 11:31:56 +01001256 m_pin[i].in_use = false;
Jeeja KP6abca1d2015-10-22 23:22:42 +05301257 m_pin[i].is_dynamic = is_dynamic;
Jeeja KP4f745702015-10-27 09:22:49 +09001258 m_pin[i].pin_state = SKL_PIN_UNBIND;
Vinod Koul3af36702015-10-07 11:31:56 +01001259 }
1260}
1261
1262/*
1263 * Add pipeline from topology binary into driver pipeline list
1264 *
1265 * If already added we return that instance
1266 * Otherwise we create a new instance and add into driver list
1267 */
1268static struct skl_pipe *skl_tplg_add_pipe(struct device *dev,
1269 struct skl *skl, struct skl_dfw_pipe *dfw_pipe)
1270{
1271 struct skl_pipeline *ppl;
1272 struct skl_pipe *pipe;
1273 struct skl_pipe_params *params;
1274
1275 list_for_each_entry(ppl, &skl->ppl_list, node) {
1276 if (ppl->pipe->ppl_id == dfw_pipe->pipe_id)
1277 return ppl->pipe;
1278 }
1279
1280 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1281 if (!ppl)
1282 return NULL;
1283
1284 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1285 if (!pipe)
1286 return NULL;
1287
1288 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1289 if (!params)
1290 return NULL;
1291
1292 pipe->ppl_id = dfw_pipe->pipe_id;
1293 pipe->memory_pages = dfw_pipe->memory_pages;
1294 pipe->pipe_priority = dfw_pipe->pipe_priority;
1295 pipe->conn_type = dfw_pipe->conn_type;
1296 pipe->state = SKL_PIPE_INVALID;
1297 pipe->p_params = params;
1298 INIT_LIST_HEAD(&pipe->w_list);
1299
1300 ppl->pipe = pipe;
1301 list_add(&ppl->node, &skl->ppl_list);
1302
1303 return ppl->pipe;
1304}
1305
Hardik T Shah4cd98992015-10-27 09:22:55 +09001306static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt,
1307 struct skl_dfw_module_fmt *src_fmt,
1308 int pins)
1309{
1310 int i;
1311
1312 for (i = 0; i < pins; i++) {
1313 dst_fmt[i].channels = src_fmt[i].channels;
1314 dst_fmt[i].s_freq = src_fmt[i].freq;
1315 dst_fmt[i].bit_depth = src_fmt[i].bit_depth;
1316 dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth;
1317 dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg;
1318 dst_fmt[i].ch_map = src_fmt[i].ch_map;
1319 dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style;
1320 dst_fmt[i].sample_type = src_fmt[i].sample_type;
1321 }
1322}
1323
Vinod Koul3af36702015-10-07 11:31:56 +01001324/*
1325 * Topology core widget load callback
1326 *
1327 * This is used to save the private data for each widget which gives
1328 * information to the driver about module and pipeline parameters which DSP
1329 * FW expects like ids, resource values, formats etc
1330 */
1331static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001332 struct snd_soc_dapm_widget *w,
1333 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01001334{
1335 int ret;
1336 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1337 struct skl *skl = ebus_to_skl(ebus);
1338 struct hdac_bus *bus = ebus_to_hbus(ebus);
1339 struct skl_module_cfg *mconfig;
1340 struct skl_pipe *pipe;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001341 struct skl_dfw_module *dfw_config =
1342 (struct skl_dfw_module *)tplg_w->priv.data;
Vinod Koul3af36702015-10-07 11:31:56 +01001343
1344 if (!tplg_w->priv.size)
1345 goto bind_event;
1346
1347 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
1348
1349 if (!mconfig)
1350 return -ENOMEM;
1351
1352 w->priv = mconfig;
1353 mconfig->id.module_id = dfw_config->module_id;
1354 mconfig->id.instance_id = dfw_config->instance_id;
1355 mconfig->mcps = dfw_config->max_mcps;
1356 mconfig->ibs = dfw_config->ibs;
1357 mconfig->obs = dfw_config->obs;
1358 mconfig->core_id = dfw_config->core_id;
1359 mconfig->max_in_queue = dfw_config->max_in_queue;
1360 mconfig->max_out_queue = dfw_config->max_out_queue;
1361 mconfig->is_loadable = dfw_config->is_loadable;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001362 skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt,
1363 MODULE_MAX_IN_PINS);
1364 skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt,
1365 MODULE_MAX_OUT_PINS);
1366
Vinod Koul3af36702015-10-07 11:31:56 +01001367 mconfig->params_fixup = dfw_config->params_fixup;
1368 mconfig->converter = dfw_config->converter;
1369 mconfig->m_type = dfw_config->module_type;
1370 mconfig->vbus_id = dfw_config->vbus_id;
Jeeja KPb18c4582015-12-03 23:29:51 +05301371 mconfig->mem_pages = dfw_config->mem_pages;
Vinod Koul3af36702015-10-07 11:31:56 +01001372
1373 pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe);
1374 if (pipe)
1375 mconfig->pipe = pipe;
1376
1377 mconfig->dev_type = dfw_config->dev_type;
1378 mconfig->hw_conn_type = dfw_config->hw_conn_type;
1379 mconfig->time_slot = dfw_config->time_slot;
1380 mconfig->formats_config.caps_size = dfw_config->caps.caps_size;
1381
Hardik T Shah65aecfa2015-10-27 09:22:57 +09001382 if (dfw_config->is_loadable)
1383 memcpy(mconfig->guid, dfw_config->uuid,
1384 ARRAY_SIZE(dfw_config->uuid));
1385
Hardik T Shah4cd98992015-10-27 09:22:55 +09001386 mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) *
1387 sizeof(*mconfig->m_in_pin),
1388 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001389 if (!mconfig->m_in_pin)
1390 return -ENOMEM;
1391
Jeeja KP6abca1d2015-10-22 23:22:42 +05301392 mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) *
1393 sizeof(*mconfig->m_out_pin),
1394 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001395 if (!mconfig->m_out_pin)
1396 return -ENOMEM;
1397
Jeeja KP6abca1d2015-10-22 23:22:42 +05301398 skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin,
1399 dfw_config->is_dynamic_in_pin,
1400 mconfig->max_in_queue);
1401
1402 skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin,
1403 dfw_config->is_dynamic_out_pin,
1404 mconfig->max_out_queue);
1405
Vinod Koul3af36702015-10-07 11:31:56 +01001406
1407 if (mconfig->formats_config.caps_size == 0)
1408 goto bind_event;
1409
1410 mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001411 mconfig->formats_config.caps_size, GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001412
1413 if (mconfig->formats_config.caps == NULL)
1414 return -ENOMEM;
1415
1416 memcpy(mconfig->formats_config.caps, dfw_config->caps.caps,
Jeeja KPabb74002015-11-28 15:01:49 +05301417 dfw_config->caps.caps_size);
1418 mconfig->formats_config.param_id = dfw_config->caps.param_id;
1419 mconfig->formats_config.set_params = dfw_config->caps.set_params;
Vinod Koul3af36702015-10-07 11:31:56 +01001420
1421bind_event:
1422 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01001423 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01001424 return 0;
1425 }
1426
1427 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001428 ARRAY_SIZE(skl_tplg_widget_ops),
1429 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01001430
1431 if (ret) {
1432 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
1433 __func__, tplg_w->event_type);
1434 return -EINVAL;
1435 }
1436
1437 return 0;
1438}
1439
Jeeja KP140adfb2015-11-28 15:01:50 +05301440static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
1441 struct snd_soc_tplg_bytes_control *bc)
1442{
1443 struct skl_algo_data *ac;
1444 struct skl_dfw_algo_data *dfw_ac =
1445 (struct skl_dfw_algo_data *)bc->priv.data;
1446
1447 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
1448 if (!ac)
1449 return -ENOMEM;
1450
1451 /* Fill private data */
1452 ac->max = dfw_ac->max;
1453 ac->param_id = dfw_ac->param_id;
1454 ac->set_params = dfw_ac->set_params;
1455
1456 if (ac->max) {
1457 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
1458 if (!ac->params)
1459 return -ENOMEM;
1460
1461 if (dfw_ac->params)
1462 memcpy(ac->params, dfw_ac->params, ac->max);
1463 }
1464
1465 be->dobj.private = ac;
1466 return 0;
1467}
1468
1469static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
1470 struct snd_kcontrol_new *kctl,
1471 struct snd_soc_tplg_ctl_hdr *hdr)
1472{
1473 struct soc_bytes_ext *sb;
1474 struct snd_soc_tplg_bytes_control *tplg_bc;
1475 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1476 struct hdac_bus *bus = ebus_to_hbus(ebus);
1477
1478 switch (hdr->ops.info) {
1479 case SND_SOC_TPLG_CTL_BYTES:
1480 tplg_bc = container_of(hdr,
1481 struct snd_soc_tplg_bytes_control, hdr);
1482 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1483 sb = (struct soc_bytes_ext *)kctl->private_value;
1484 if (tplg_bc->priv.size)
1485 return skl_init_algo_data(
1486 bus->dev, sb, tplg_bc);
1487 }
1488 break;
1489
1490 default:
1491 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
1492 hdr->ops.get, hdr->ops.put, hdr->ops.info);
1493 break;
1494 }
1495
1496 return 0;
1497}
1498
Vinod Koul3af36702015-10-07 11:31:56 +01001499static struct snd_soc_tplg_ops skl_tplg_ops = {
1500 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05301501 .control_load = skl_tplg_control_load,
1502 .bytes_ext_ops = skl_tlv_ops,
1503 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Vinod Koul3af36702015-10-07 11:31:56 +01001504};
1505
1506/* This will be read from topology manifest, currently defined here */
1507#define SKL_MAX_MCPS 30000000
1508#define SKL_FW_MAX_MEM 1000000
1509
1510/*
1511 * SKL topology init routine
1512 */
1513int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
1514{
1515 int ret;
1516 const struct firmware *fw;
1517 struct hdac_bus *bus = ebus_to_hbus(ebus);
1518 struct skl *skl = ebus_to_skl(ebus);
1519
1520 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
1521 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001522 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul3af36702015-10-07 11:31:56 +01001523 "dfw_sst.bin", ret);
1524 return ret;
1525 }
1526
1527 /*
1528 * The complete tplg for SKL is loaded as index 0, we don't use
1529 * any other index
1530 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01001531 ret = snd_soc_tplg_component_load(&platform->component,
1532 &skl_tplg_ops, fw, 0);
Sudip Mukherjee87b5ed82015-11-23 16:38:48 +05301533 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01001534 if (ret < 0) {
1535 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05301536 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01001537 return -EINVAL;
1538 }
1539
1540 skl->resource.max_mcps = SKL_MAX_MCPS;
1541 skl->resource.max_mem = SKL_FW_MAX_MEM;
1542
1543 return 0;
1544}