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Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _MACB_H
11#define _MACB_H
12
Russell Kingfc182b82017-02-07 15:02:56 -080013#include <linux/phy.h>
Rafal Oziebloab91f0a2017-06-29 07:14:16 +010014#include <linux/ptp_clock_kernel.h>
15#include <linux/net_tstamp.h>
Russell Kingfc182b82017-02-07 15:02:56 -080016
Rafal Ozieblo7b429612017-06-29 07:12:51 +010017#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
18#define MACB_EXT_DESC
19#endif
20
Nicolas Ferred1d1b532012-10-31 06:04:56 +000021#define MACB_GREGS_NBR 16
Nicolas Ferre7c399942015-03-31 15:02:04 +020022#define MACB_GREGS_VERSION 2
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010023#define MACB_MAX_QUEUES 8
Nicolas Ferred1d1b532012-10-31 06:04:56 +000024
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010025/* MACB register offsets */
Xander Huff6f79eed2015-01-15 15:55:18 -060026#define MACB_NCR 0x0000 /* Network Control */
27#define MACB_NCFGR 0x0004 /* Network Config */
28#define MACB_NSR 0x0008 /* Network Status */
29#define MACB_TAR 0x000c /* AT91RM9200 only */
30#define MACB_TCR 0x0010 /* AT91RM9200 only */
31#define MACB_TSR 0x0014 /* Transmit Status */
32#define MACB_RBQP 0x0018 /* RX Q Base Address */
33#define MACB_TBQP 0x001c /* TX Q Base Address */
34#define MACB_RSR 0x0020 /* Receive Status */
35#define MACB_ISR 0x0024 /* Interrupt Status */
36#define MACB_IER 0x0028 /* Interrupt Enable */
37#define MACB_IDR 0x002c /* Interrupt Disable */
38#define MACB_IMR 0x0030 /* Interrupt Mask */
39#define MACB_MAN 0x0034 /* PHY Maintenance */
40#define MACB_PTR 0x0038
41#define MACB_PFR 0x003c
42#define MACB_FTO 0x0040
43#define MACB_SCF 0x0044
44#define MACB_MCF 0x0048
45#define MACB_FRO 0x004c
46#define MACB_FCSE 0x0050
47#define MACB_ALE 0x0054
48#define MACB_DTF 0x0058
49#define MACB_LCOL 0x005c
50#define MACB_EXCOL 0x0060
51#define MACB_TUND 0x0064
52#define MACB_CSE 0x0068
53#define MACB_RRE 0x006c
54#define MACB_ROVR 0x0070
55#define MACB_RSE 0x0074
56#define MACB_ELE 0x0078
57#define MACB_RJA 0x007c
58#define MACB_USF 0x0080
59#define MACB_STE 0x0084
60#define MACB_RLE 0x0088
61#define MACB_TPF 0x008c
62#define MACB_HRB 0x0090
63#define MACB_HRT 0x0094
64#define MACB_SA1B 0x0098
65#define MACB_SA1T 0x009c
66#define MACB_SA2B 0x00a0
67#define MACB_SA2T 0x00a4
68#define MACB_SA3B 0x00a8
69#define MACB_SA3T 0x00ac
70#define MACB_SA4B 0x00b0
71#define MACB_SA4T 0x00b4
72#define MACB_TID 0x00b8
73#define MACB_TPQ 0x00bc
74#define MACB_USRIO 0x00c0
75#define MACB_WOL 0x00c4
76#define MACB_MID 0x00fc
Harini Katakamfff80192016-08-09 13:15:53 +053077#define MACB_TBQPH 0x04C8
78#define MACB_RBQPH 0x04D4
Jamie Ilesf75ba502011-11-08 10:12:32 +000079
80/* GEM register offsets. */
Xander Huff6f79eed2015-01-15 15:55:18 -060081#define GEM_NCFGR 0x0004 /* Network Config */
82#define GEM_USRIO 0x000c /* User IO */
83#define GEM_DMACFG 0x0010 /* DMA Configuration */
Harini Katakam98b5a0f42015-05-06 22:27:17 +053084#define GEM_JML 0x0048 /* Jumbo Max Length */
Xander Huff6f79eed2015-01-15 15:55:18 -060085#define GEM_HRB 0x0080 /* Hash Bottom */
86#define GEM_HRT 0x0084 /* Hash Top */
87#define GEM_SA1B 0x0088 /* Specific1 Bottom */
88#define GEM_SA1T 0x008C /* Specific1 Top */
89#define GEM_SA2B 0x0090 /* Specific2 Bottom */
90#define GEM_SA2T 0x0094 /* Specific2 Top */
91#define GEM_SA3B 0x0098 /* Specific3 Bottom */
92#define GEM_SA3T 0x009C /* Specific3 Top */
93#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
94#define GEM_SA4T 0x00A4 /* Specific4 Top */
Rafal Oziebloab91f0a2017-06-29 07:14:16 +010095#define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
96#define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
97#define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
98#define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
Xander Huff6f79eed2015-01-15 15:55:18 -060099#define GEM_OTX 0x0100 /* Octets transmitted */
100#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
101#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
102#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
103#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
104#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
105#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
106#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
107#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
108#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
109#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
110#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
111#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
112#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
113#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
114#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
115#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
116#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
117#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
118#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
119#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
120#define GEM_ORX 0x0150 /* Octets received */
121#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
122#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
123#define GEM_RXCNT 0x0158 /* Frames Received Counter */
124#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
125#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
126#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
127#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
128#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
129#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
130#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
131#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
132#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
133#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
134#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
135#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
136#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
137#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
138#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
139#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
140#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
141#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
142#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
143#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
144#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
145#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200146#define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
147#define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
148#define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
149#define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
150#define GEM_TA 0x01d8 /* 1588 Timer Adjust */
151#define GEM_TI 0x01dc /* 1588 Timer Increment */
152#define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
153#define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
154#define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
155#define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
156#define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
157#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
158#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
159#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
Xander Huff6f79eed2015-01-15 15:55:18 -0600160#define GEM_DCFG1 0x0280 /* Design Config 1 */
161#define GEM_DCFG2 0x0284 /* Design Config 2 */
162#define GEM_DCFG3 0x0288 /* Design Config 3 */
163#define GEM_DCFG4 0x028c /* Design Config 4 */
164#define GEM_DCFG5 0x0290 /* Design Config 5 */
165#define GEM_DCFG6 0x0294 /* Design Config 6 */
166#define GEM_DCFG7 0x0298 /* Design Config 7 */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100167
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100168#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
169#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
170
Xander Huff6f79eed2015-01-15 15:55:18 -0600171#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
172#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
Harini Katakamfff80192016-08-09 13:15:53 +0530173#define GEM_TBQPH(hw_q) (0x04C8)
Xander Huff6f79eed2015-01-15 15:55:18 -0600174#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
175#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
176#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
177#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100178
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100179/* Bitfields in NCR */
Xander Huff6f79eed2015-01-15 15:55:18 -0600180#define MACB_LB_OFFSET 0 /* reserved */
181#define MACB_LB_SIZE 1
182#define MACB_LLB_OFFSET 1 /* Loop back local */
183#define MACB_LLB_SIZE 1
184#define MACB_RE_OFFSET 2 /* Receive enable */
185#define MACB_RE_SIZE 1
186#define MACB_TE_OFFSET 3 /* Transmit enable */
187#define MACB_TE_SIZE 1
188#define MACB_MPE_OFFSET 4 /* Management port enable */
189#define MACB_MPE_SIZE 1
190#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
191#define MACB_CLRSTAT_SIZE 1
192#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
193#define MACB_INCSTAT_SIZE 1
194#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
195#define MACB_WESTAT_SIZE 1
196#define MACB_BP_OFFSET 8 /* Back pressure */
197#define MACB_BP_SIZE 1
198#define MACB_TSTART_OFFSET 9 /* Start transmission */
199#define MACB_TSTART_SIZE 1
200#define MACB_THALT_OFFSET 10 /* Transmit halt */
201#define MACB_THALT_SIZE 1
202#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
203#define MACB_NCR_TPF_SIZE 1
204#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
205#define MACB_TZQ_SIZE 1
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200206#define MACB_SRTSM_OFFSET 15
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100207#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
208#define MACB_OSSMODE_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100209
210/* Bitfields in NCFGR */
Xander Huff6f79eed2015-01-15 15:55:18 -0600211#define MACB_SPD_OFFSET 0 /* Speed */
212#define MACB_SPD_SIZE 1
213#define MACB_FD_OFFSET 1 /* Full duplex */
214#define MACB_FD_SIZE 1
215#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
216#define MACB_BIT_RATE_SIZE 1
217#define MACB_JFRAME_OFFSET 3 /* reserved */
218#define MACB_JFRAME_SIZE 1
219#define MACB_CAF_OFFSET 4 /* Copy all frames */
220#define MACB_CAF_SIZE 1
221#define MACB_NBC_OFFSET 5 /* No broadcast */
222#define MACB_NBC_SIZE 1
223#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
224#define MACB_NCFGR_MTI_SIZE 1
225#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
226#define MACB_UNI_SIZE 1
227#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
228#define MACB_BIG_SIZE 1
229#define MACB_EAE_OFFSET 9 /* External address match enable */
230#define MACB_EAE_SIZE 1
231#define MACB_CLK_OFFSET 10
232#define MACB_CLK_SIZE 2
233#define MACB_RTY_OFFSET 12 /* Retry test */
234#define MACB_RTY_SIZE 1
235#define MACB_PAE_OFFSET 13 /* Pause enable */
236#define MACB_PAE_SIZE 1
237#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
238#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
239#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
240#define MACB_RBOF_SIZE 2
241#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
242#define MACB_RLCE_SIZE 1
243#define MACB_DRFCS_OFFSET 17 /* FCS remove */
244#define MACB_DRFCS_SIZE 1
245#define MACB_EFRHD_OFFSET 18
246#define MACB_EFRHD_SIZE 1
247#define MACB_IRXFCS_OFFSET 19
248#define MACB_IRXFCS_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100249
Jamie Iles70c9f3d2011-03-09 16:22:54 +0000250/* GEM specific NCFGR bitfields. */
Xander Huff6f79eed2015-01-15 15:55:18 -0600251#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
252#define GEM_GBE_SIZE 1
Punnaiah Choudary Kalluri022be252015-11-18 09:03:50 +0530253#define GEM_PCSSEL_OFFSET 11
254#define GEM_PCSSEL_SIZE 1
Xander Huff6f79eed2015-01-15 15:55:18 -0600255#define GEM_CLK_OFFSET 18 /* MDC clock division */
256#define GEM_CLK_SIZE 3
257#define GEM_DBW_OFFSET 21 /* Data bus width */
258#define GEM_DBW_SIZE 2
259#define GEM_RXCOEN_OFFSET 24
260#define GEM_RXCOEN_SIZE 1
Punnaiah Choudary Kalluri022be252015-11-18 09:03:50 +0530261#define GEM_SGMIIEN_OFFSET 27
262#define GEM_SGMIIEN_SIZE 1
263
Jamie Iles757a03c2011-03-09 16:29:59 +0000264
265/* Constants for data bus width. */
Xander Huff6f79eed2015-01-15 15:55:18 -0600266#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
267#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
268#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
Jamie Iles757a03c2011-03-09 16:29:59 +0000269
Jamie Iles0116da42011-03-14 17:38:30 +0000270/* Bitfields in DMACFG. */
Xander Huff6f79eed2015-01-15 15:55:18 -0600271#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
272#define GEM_FBLDO_SIZE 5
Arun Chandrana50dad32015-02-18 16:59:35 +0530273#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
Arun Chandranea373042015-03-01 11:38:03 +0530274#define GEM_ENDIA_DESC_SIZE 1
Arun Chandrana50dad32015-02-18 16:59:35 +0530275#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
Arun Chandranea373042015-03-01 11:38:03 +0530276#define GEM_ENDIA_PKT_SIZE 1
Xander Huff6f79eed2015-01-15 15:55:18 -0600277#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
278#define GEM_RXBMS_SIZE 2
279#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
280#define GEM_TXPBMS_SIZE 1
281#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
282#define GEM_TXCOEN_SIZE 1
283#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
284#define GEM_RXBS_SIZE 8
285#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
286#define GEM_DDRP_SIZE 1
Rafal Ozieblo7b429612017-06-29 07:12:51 +0100287#define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
288#define GEM_RXEXT_SIZE 1
289#define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
290#define GEM_TXEXT_SIZE 1
Harini Katakamfff80192016-08-09 13:15:53 +0530291#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
292#define GEM_ADDR64_SIZE 1
Nicolas Ferreb3e3bd712012-11-23 03:49:01 +0000293
Jamie Iles0116da42011-03-14 17:38:30 +0000294
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100295/* Bitfields in NSR */
Xander Huff6f79eed2015-01-15 15:55:18 -0600296#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
297#define MACB_NSR_LINK_SIZE 1
298#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
299#define MACB_MDIO_SIZE 1
300#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
301#define MACB_IDLE_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100302
303/* Bitfields in TSR */
Xander Huff6f79eed2015-01-15 15:55:18 -0600304#define MACB_UBR_OFFSET 0 /* Used bit read */
305#define MACB_UBR_SIZE 1
306#define MACB_COL_OFFSET 1 /* Collision occurred */
307#define MACB_COL_SIZE 1
308#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
309#define MACB_TSR_RLE_SIZE 1
310#define MACB_TGO_OFFSET 3 /* Transmit go */
311#define MACB_TGO_SIZE 1
312#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
313#define MACB_BEX_SIZE 1
314#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
315#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
316#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
317#define MACB_COMP_SIZE 1
318#define MACB_UND_OFFSET 6 /* Trnasmit under run */
319#define MACB_UND_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100320
321/* Bitfields in RSR */
Xander Huff6f79eed2015-01-15 15:55:18 -0600322#define MACB_BNA_OFFSET 0 /* Buffer not available */
323#define MACB_BNA_SIZE 1
324#define MACB_REC_OFFSET 1 /* Frame received */
325#define MACB_REC_SIZE 1
326#define MACB_OVR_OFFSET 2 /* Receive overrun */
327#define MACB_OVR_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100328
329/* Bitfields in ISR/IER/IDR/IMR */
Xander Huff6f79eed2015-01-15 15:55:18 -0600330#define MACB_MFD_OFFSET 0 /* Management frame sent */
331#define MACB_MFD_SIZE 1
332#define MACB_RCOMP_OFFSET 1 /* Receive complete */
333#define MACB_RCOMP_SIZE 1
334#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
335#define MACB_RXUBR_SIZE 1
336#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
337#define MACB_TXUBR_SIZE 1
338#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
339#define MACB_ISR_TUND_SIZE 1
340#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
341#define MACB_ISR_RLE_SIZE 1
342#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
343#define MACB_TXERR_SIZE 1
344#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
345#define MACB_TCOMP_SIZE 1
346#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
347#define MACB_ISR_LINK_SIZE 1
348#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
349#define MACB_ISR_ROVR_SIZE 1
350#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
351#define MACB_HRESP_SIZE 1
352#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
353#define MACB_PFR_SIZE 1
354#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
355#define MACB_PTZ_SIZE 1
Sergio Prado3e2a5e12016-02-09 12:07:16 -0200356#define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
357#define MACB_WOL_SIZE 1
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200358#define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
359#define MACB_DRQFR_SIZE 1
360#define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
361#define MACB_SFR_SIZE 1
362#define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
363#define MACB_DRQFT_SIZE 1
364#define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
365#define MACB_SFT_SIZE 1
366#define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
367#define MACB_PDRQFR_SIZE 1
368#define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
369#define MACB_PDRSFR_SIZE 1
370#define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
371#define MACB_PDRQFT_SIZE 1
372#define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
373#define MACB_PDRSFT_SIZE 1
374#define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
375#define MACB_SRI_SIZE 1
376
377/* Timer increment fields */
378#define MACB_TI_CNS_OFFSET 0
379#define MACB_TI_CNS_SIZE 8
380#define MACB_TI_ACNS_OFFSET 8
381#define MACB_TI_ACNS_SIZE 8
382#define MACB_TI_NIT_OFFSET 16
383#define MACB_TI_NIT_SIZE 8
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100384
385/* Bitfields in MAN */
Xander Huff6f79eed2015-01-15 15:55:18 -0600386#define MACB_DATA_OFFSET 0 /* data */
387#define MACB_DATA_SIZE 16
388#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
389#define MACB_CODE_SIZE 2
390#define MACB_REGA_OFFSET 18 /* Register address */
391#define MACB_REGA_SIZE 5
392#define MACB_PHYA_OFFSET 23 /* PHY address */
393#define MACB_PHYA_SIZE 5
394#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
395#define MACB_RW_SIZE 2
396#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
397#define MACB_SOF_SIZE 2
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100398
Andrew Victor0cc86742007-02-07 16:40:44 +0100399/* Bitfields in USRIO (AVR32) */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100400#define MACB_MII_OFFSET 0
401#define MACB_MII_SIZE 1
402#define MACB_EAM_OFFSET 1
403#define MACB_EAM_SIZE 1
404#define MACB_TX_PAUSE_OFFSET 2
405#define MACB_TX_PAUSE_SIZE 1
406#define MACB_TX_PAUSE_ZERO_OFFSET 3
407#define MACB_TX_PAUSE_ZERO_SIZE 1
408
Andrew Victor0cc86742007-02-07 16:40:44 +0100409/* Bitfields in USRIO (AT91) */
410#define MACB_RMII_OFFSET 0
411#define MACB_RMII_SIZE 1
Xander Huff5c2fa0f2015-01-13 16:15:50 -0600412#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
Patrice Vilchez140b7552012-10-31 06:04:50 +0000413#define GEM_RGMII_SIZE 1
Andrew Victor0cc86742007-02-07 16:40:44 +0100414#define MACB_CLKEN_OFFSET 1
415#define MACB_CLKEN_SIZE 1
416
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100417/* Bitfields in WOL */
418#define MACB_IP_OFFSET 0
419#define MACB_IP_SIZE 16
420#define MACB_MAG_OFFSET 16
421#define MACB_MAG_SIZE 1
422#define MACB_ARP_OFFSET 17
423#define MACB_ARP_SIZE 1
424#define MACB_SA1_OFFSET 18
425#define MACB_SA1_SIZE 1
426#define MACB_WOL_MTI_OFFSET 19
427#define MACB_WOL_MTI_SIZE 1
428
Jamie Ilesf75ba502011-11-08 10:12:32 +0000429/* Bitfields in MID */
430#define MACB_IDNUM_OFFSET 16
Punnaiah Choudary Kallurid941beb2015-03-05 15:02:10 +0100431#define MACB_IDNUM_SIZE 12
Jamie Ilesf75ba502011-11-08 10:12:32 +0000432#define MACB_REV_OFFSET 0
433#define MACB_REV_SIZE 16
434
Jamie Iles757a03c2011-03-09 16:29:59 +0000435/* Bitfields in DCFG1. */
Nicolas Ferre581df9e2013-05-14 03:00:16 +0000436#define GEM_IRQCOR_OFFSET 23
437#define GEM_IRQCOR_SIZE 1
Jamie Iles757a03c2011-03-09 16:29:59 +0000438#define GEM_DBWDEF_OFFSET 25
439#define GEM_DBWDEF_SIZE 3
440
Nicolas Ferree1755872014-07-24 13:50:58 +0200441/* Bitfields in DCFG2. */
442#define GEM_RX_PKT_BUFF_OFFSET 20
443#define GEM_RX_PKT_BUFF_SIZE 1
444#define GEM_TX_PKT_BUFF_OFFSET 21
445#define GEM_TX_PKT_BUFF_SIZE 1
446
Rafal Ozieblo7b429612017-06-29 07:12:51 +0100447
448/* Bitfields in DCFG5. */
449#define GEM_TSU_OFFSET 8
450#define GEM_TSU_SIZE 1
451
Rafal Ozieblo1629dd42016-11-16 10:02:34 +0000452/* Bitfields in DCFG6. */
453#define GEM_PBUF_LSO_OFFSET 27
454#define GEM_PBUF_LSO_SIZE 1
Rafal Ozieblodc97a892017-01-27 15:08:20 +0000455#define GEM_DAW64_OFFSET 23
456#define GEM_DAW64_SIZE 1
Rafal Ozieblo1629dd42016-11-16 10:02:34 +0000457
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200458/* Bitfields in TISUBN */
459#define GEM_SUBNSINCR_OFFSET 0
460#define GEM_SUBNSINCR_SIZE 16
461
462/* Bitfields in TI */
463#define GEM_NSINCR_OFFSET 0
464#define GEM_NSINCR_SIZE 8
465
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100466/* Bitfields in TSH */
467#define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
468#define GEM_TSH_SIZE 16
469
470/* Bitfields in TSL */
471#define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
472#define GEM_TSL_SIZE 32
473
474/* Bitfields in TN */
475#define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
476#define GEM_TN_SIZE 30
477
478/* Bitfields in TXBDCTRL */
479#define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
480#define GEM_TXTSMODE_SIZE 2
481
482/* Bitfields in RXBDCTRL */
483#define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
484#define GEM_RXTSMODE_SIZE 2
485
486/* Transmit DMA buffer descriptor Word 1 */
487#define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
488#define GEM_DMA_TXVALID_SIZE 1
489
490/* Receive DMA buffer descriptor Word 0 */
491#define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
492#define GEM_DMA_RXVALID_SIZE 1
493
494/* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
495#define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
496#define GEM_DMA_SECL_SIZE 2
497#define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
498#define GEM_DMA_NSEC_SIZE 30
499
500/* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
501
502/* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
503 * Old hardware supports only 6 bit precision but it is enough for PTP.
504 * Less accuracy is used always instead of checking hardware version.
505 */
506#define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
507#define GEM_DMA_SECH_SIZE 4
508#define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
509#define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
510#define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
511
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200512/* Bitfields in ADJ */
513#define GEM_ADDSUB_OFFSET 31
514#define GEM_ADDSUB_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100515/* Constants for CLK */
516#define MACB_CLK_DIV8 0
517#define MACB_CLK_DIV16 1
518#define MACB_CLK_DIV32 2
519#define MACB_CLK_DIV64 3
520
Jamie Iles70c9f3d2011-03-09 16:22:54 +0000521/* GEM specific constants for CLK. */
522#define GEM_CLK_DIV8 0
523#define GEM_CLK_DIV16 1
524#define GEM_CLK_DIV32 2
525#define GEM_CLK_DIV48 3
526#define GEM_CLK_DIV64 4
527#define GEM_CLK_DIV96 5
528
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100529/* Constants for MAN register */
530#define MACB_MAN_SOF 1
531#define MACB_MAN_WRITE 1
532#define MACB_MAN_READ 2
533#define MACB_MAN_CODE 2
534
Nicolas Ferre581df9e2013-05-14 03:00:16 +0000535/* Capability mask bits */
Nicolas Ferree1755872014-07-24 13:50:58 +0200536#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
Boris BREZILLONa8487482015-03-07 07:23:30 +0100537#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
Nicolas Ferre6bdaa5e2016-03-10 16:44:32 +0100538#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
Nathan Sullivan222ca8e2015-05-22 09:22:10 -0500539#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
Neil Armstrongce721a72016-01-05 14:39:16 +0100540#define MACB_CAPS_USRIO_DISABLED 0x00000010
Harini Katakamc5181892016-08-05 10:31:58 +0530541#define MACB_CAPS_JUMBO 0x00000020
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200542#define MACB_CAPS_GEM_HAS_PTP 0x00000040
Nicolas Ferree1755872014-07-24 13:50:58 +0200543#define MACB_CAPS_FIFO_MODE 0x10000000
544#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200545#define MACB_CAPS_SG_DISABLED 0x40000000
Nicolas Ferree1755872014-07-24 13:50:58 +0200546#define MACB_CAPS_MACB_IS_GEM 0x80000000
Nicolas Ferre581df9e2013-05-14 03:00:16 +0000547
Rafal Ozieblo1629dd42016-11-16 10:02:34 +0000548/* LSO settings */
549#define MACB_LSO_UFO_ENABLE 0x01
550#define MACB_LSO_TSO_ENABLE 0x02
551
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100552/* Bit manipulation macros */
553#define MACB_BIT(name) \
554 (1 << MACB_##name##_OFFSET)
555#define MACB_BF(name,value) \
556 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
557 << MACB_##name##_OFFSET)
558#define MACB_BFEXT(name,value)\
559 (((value) >> MACB_##name##_OFFSET) \
560 & ((1 << MACB_##name##_SIZE) - 1))
561#define MACB_BFINS(name,value,old) \
562 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
563 << MACB_##name##_OFFSET)) \
564 | MACB_BF(name,value))
565
Jamie Ilesf75ba502011-11-08 10:12:32 +0000566#define GEM_BIT(name) \
567 (1 << GEM_##name##_OFFSET)
568#define GEM_BF(name, value) \
569 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
570 << GEM_##name##_OFFSET)
571#define GEM_BFEXT(name, value)\
572 (((value) >> GEM_##name##_OFFSET) \
573 & ((1 << GEM_##name##_SIZE) - 1))
574#define GEM_BFINS(name, value, old) \
575 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
576 << GEM_##name##_OFFSET)) \
577 | GEM_BF(name, value))
578
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100579/* Register access macros */
David S. Miller7a6e0702015-07-27 14:24:48 -0700580#define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
581#define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
582#define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
583#define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
584#define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
585#define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
Jamie Ilesf75ba502011-11-08 10:12:32 +0000586
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100587#define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
588
Xander Huff6f79eed2015-01-15 15:55:18 -0600589/* Conditional GEM/MACB macros. These perform the operation to the correct
Jamie Ilesf75ba502011-11-08 10:12:32 +0000590 * register dependent on whether the device is a GEM or a MACB. For registers
591 * and bitfields that are common across both devices, use macb_{read,write}l
592 * to avoid the cost of the conditional.
593 */
594#define macb_or_gem_writel(__bp, __reg, __value) \
595 ({ \
596 if (macb_is_gem((__bp))) \
597 gem_writel((__bp), __reg, __value); \
598 else \
599 macb_writel((__bp), __reg, __value); \
600 })
601
602#define macb_or_gem_readl(__bp, __reg) \
603 ({ \
604 u32 __v; \
605 if (macb_is_gem((__bp))) \
606 __v = gem_readl((__bp), __reg); \
607 else \
608 __v = macb_readl((__bp), __reg); \
609 __v; \
610 })
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100611
Xander Huff6f79eed2015-01-15 15:55:18 -0600612/* struct macb_dma_desc - Hardware DMA descriptor
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000613 * @addr: DMA address of data buffer
614 * @ctrl: Control and status bits
615 */
616struct macb_dma_desc {
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100617 u32 addr;
618 u32 ctrl;
619};
620
Rafal Ozieblo7b429612017-06-29 07:12:51 +0100621#ifdef MACB_EXT_DESC
622#define HW_DMA_CAP_32B 0
623#define HW_DMA_CAP_64B (1 << 0)
624#define HW_DMA_CAP_PTP (1 << 1)
625#define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
Rafal Ozieblodc97a892017-01-27 15:08:20 +0000626
627struct macb_dma_desc_64 {
628 u32 addrh;
629 u32 resvd;
630};
Rafal Ozieblo7b429612017-06-29 07:12:51 +0100631
632struct macb_dma_desc_ptp {
633 u32 ts_1;
634 u32 ts_2;
635};
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100636
637struct gem_tx_ts {
638 struct sk_buff *skb;
639 struct macb_dma_desc_ptp desc_ptp;
640};
Rafal Ozieblodc97a892017-01-27 15:08:20 +0000641#endif
642
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100643/* DMA descriptor bitfields */
644#define MACB_RX_USED_OFFSET 0
645#define MACB_RX_USED_SIZE 1
646#define MACB_RX_WRAP_OFFSET 1
647#define MACB_RX_WRAP_SIZE 1
648#define MACB_RX_WADDR_OFFSET 2
649#define MACB_RX_WADDR_SIZE 30
650
651#define MACB_RX_FRMLEN_OFFSET 0
652#define MACB_RX_FRMLEN_SIZE 12
653#define MACB_RX_OFFSET_OFFSET 12
654#define MACB_RX_OFFSET_SIZE 2
655#define MACB_RX_SOF_OFFSET 14
656#define MACB_RX_SOF_SIZE 1
657#define MACB_RX_EOF_OFFSET 15
658#define MACB_RX_EOF_SIZE 1
659#define MACB_RX_CFI_OFFSET 16
660#define MACB_RX_CFI_SIZE 1
661#define MACB_RX_VLAN_PRI_OFFSET 17
662#define MACB_RX_VLAN_PRI_SIZE 3
663#define MACB_RX_PRI_TAG_OFFSET 20
664#define MACB_RX_PRI_TAG_SIZE 1
665#define MACB_RX_VLAN_TAG_OFFSET 21
666#define MACB_RX_VLAN_TAG_SIZE 1
667#define MACB_RX_TYPEID_MATCH_OFFSET 22
668#define MACB_RX_TYPEID_MATCH_SIZE 1
669#define MACB_RX_SA4_MATCH_OFFSET 23
670#define MACB_RX_SA4_MATCH_SIZE 1
671#define MACB_RX_SA3_MATCH_OFFSET 24
672#define MACB_RX_SA3_MATCH_SIZE 1
673#define MACB_RX_SA2_MATCH_OFFSET 25
674#define MACB_RX_SA2_MATCH_SIZE 1
675#define MACB_RX_SA1_MATCH_OFFSET 26
676#define MACB_RX_SA1_MATCH_SIZE 1
677#define MACB_RX_EXT_MATCH_OFFSET 28
678#define MACB_RX_EXT_MATCH_SIZE 1
679#define MACB_RX_UHASH_MATCH_OFFSET 29
680#define MACB_RX_UHASH_MATCH_SIZE 1
681#define MACB_RX_MHASH_MATCH_OFFSET 30
682#define MACB_RX_MHASH_MATCH_SIZE 1
683#define MACB_RX_BROADCAST_OFFSET 31
684#define MACB_RX_BROADCAST_SIZE 1
685
Harini Katakam98b5a0f42015-05-06 22:27:17 +0530686#define MACB_RX_FRMLEN_MASK 0xFFF
687#define MACB_RX_JFRMLEN_MASK 0x3FFF
688
Cyrille Pitchen924ec532014-07-24 13:51:01 +0200689/* RX checksum offload disabled: bit 24 clear in NCFGR */
690#define GEM_RX_TYPEID_MATCH_OFFSET 22
691#define GEM_RX_TYPEID_MATCH_SIZE 2
692
693/* RX checksum offload enabled: bit 24 set in NCFGR */
694#define GEM_RX_CSUM_OFFSET 22
695#define GEM_RX_CSUM_SIZE 2
696
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100697#define MACB_TX_FRMLEN_OFFSET 0
698#define MACB_TX_FRMLEN_SIZE 11
699#define MACB_TX_LAST_OFFSET 15
700#define MACB_TX_LAST_SIZE 1
701#define MACB_TX_NOCRC_OFFSET 16
702#define MACB_TX_NOCRC_SIZE 1
Rafal Ozieblo1629dd42016-11-16 10:02:34 +0000703#define MACB_MSS_MFS_OFFSET 16
704#define MACB_MSS_MFS_SIZE 14
705#define MACB_TX_LSO_OFFSET 17
706#define MACB_TX_LSO_SIZE 2
707#define MACB_TX_TCP_SEQ_SRC_OFFSET 19
708#define MACB_TX_TCP_SEQ_SRC_SIZE 1
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100709#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
710#define MACB_TX_BUF_EXHAUSTED_SIZE 1
711#define MACB_TX_UNDERRUN_OFFSET 28
712#define MACB_TX_UNDERRUN_SIZE 1
713#define MACB_TX_ERROR_OFFSET 29
714#define MACB_TX_ERROR_SIZE 1
715#define MACB_TX_WRAP_OFFSET 30
716#define MACB_TX_WRAP_SIZE 1
717#define MACB_TX_USED_OFFSET 31
718#define MACB_TX_USED_SIZE 1
719
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200720#define GEM_TX_FRMLEN_OFFSET 0
721#define GEM_TX_FRMLEN_SIZE 14
722
Cyrille Pitchen924ec532014-07-24 13:51:01 +0200723/* Buffer descriptor constants */
724#define GEM_RX_CSUM_NONE 0
725#define GEM_RX_CSUM_IP_ONLY 1
726#define GEM_RX_CSUM_IP_TCP 2
727#define GEM_RX_CSUM_IP_UDP 3
728
729/* limit RX checksum offload to TCP and UDP packets */
730#define GEM_RX_CSUM_CHECKED_MASK 2
731
Xander Huff6f79eed2015-01-15 15:55:18 -0600732/* struct macb_tx_skb - data about an skb which is being transmitted
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200733 * @skb: skb currently being transmitted, only set for the last buffer
734 * of the frame
735 * @mapping: DMA address of the skb's fragment buffer
736 * @size: size of the DMA mapped buffer
737 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
738 * false when buffer was mapped with dma_map_single()
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000739 */
740struct macb_tx_skb {
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100741 struct sk_buff *skb;
742 dma_addr_t mapping;
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200743 size_t size;
744 bool mapped_as_page;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100745};
746
Xander Huff6f79eed2015-01-15 15:55:18 -0600747/* Hardware-collected statistics. Used when updating the network
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100748 * device stats by a periodic timer.
749 */
750struct macb_stats {
751 u32 rx_pause_frames;
752 u32 tx_ok;
753 u32 tx_single_cols;
754 u32 tx_multiple_cols;
755 u32 rx_ok;
756 u32 rx_fcs_errors;
757 u32 rx_align_errors;
758 u32 tx_deferred;
759 u32 tx_late_cols;
760 u32 tx_excessive_cols;
761 u32 tx_underruns;
762 u32 tx_carrier_errors;
763 u32 rx_resource_errors;
764 u32 rx_overruns;
765 u32 rx_symbol_errors;
766 u32 rx_oversize_pkts;
767 u32 rx_jabbers;
768 u32 rx_undersize_pkts;
769 u32 sqe_test_errors;
770 u32 rx_length_mismatch;
771 u32 tx_pause_frames;
772};
773
Jamie Ilesa494ed82011-03-09 16:26:35 +0000774struct gem_stats {
775 u32 tx_octets_31_0;
776 u32 tx_octets_47_32;
777 u32 tx_frames;
778 u32 tx_broadcast_frames;
779 u32 tx_multicast_frames;
780 u32 tx_pause_frames;
781 u32 tx_64_byte_frames;
782 u32 tx_65_127_byte_frames;
783 u32 tx_128_255_byte_frames;
784 u32 tx_256_511_byte_frames;
785 u32 tx_512_1023_byte_frames;
786 u32 tx_1024_1518_byte_frames;
787 u32 tx_greater_than_1518_byte_frames;
788 u32 tx_underrun;
789 u32 tx_single_collision_frames;
790 u32 tx_multiple_collision_frames;
791 u32 tx_excessive_collisions;
792 u32 tx_late_collisions;
793 u32 tx_deferred_frames;
794 u32 tx_carrier_sense_errors;
795 u32 rx_octets_31_0;
796 u32 rx_octets_47_32;
797 u32 rx_frames;
798 u32 rx_broadcast_frames;
799 u32 rx_multicast_frames;
800 u32 rx_pause_frames;
801 u32 rx_64_byte_frames;
802 u32 rx_65_127_byte_frames;
803 u32 rx_128_255_byte_frames;
804 u32 rx_256_511_byte_frames;
805 u32 rx_512_1023_byte_frames;
806 u32 rx_1024_1518_byte_frames;
807 u32 rx_greater_than_1518_byte_frames;
808 u32 rx_undersized_frames;
809 u32 rx_oversize_frames;
810 u32 rx_jabbers;
811 u32 rx_frame_check_sequence_errors;
812 u32 rx_length_field_frame_errors;
813 u32 rx_symbol_errors;
814 u32 rx_alignment_errors;
815 u32 rx_resource_errors;
816 u32 rx_overruns;
817 u32 rx_ip_header_checksum_errors;
818 u32 rx_tcp_checksum_errors;
819 u32 rx_udp_checksum_errors;
820};
821
Xander Huff3ff13f12015-01-13 16:15:51 -0600822/* Describes the name and offset of an individual statistic register, as
823 * returned by `ethtool -S`. Also describes which net_device_stats statistics
824 * this register should contribute to.
825 */
826struct gem_statistic {
827 char stat_string[ETH_GSTRING_LEN];
828 int offset;
829 u32 stat_bits;
830};
831
832/* Bitfield defs for net_device_stat statistics */
833#define GEM_NDS_RXERR_OFFSET 0
834#define GEM_NDS_RXLENERR_OFFSET 1
835#define GEM_NDS_RXOVERERR_OFFSET 2
836#define GEM_NDS_RXCRCERR_OFFSET 3
837#define GEM_NDS_RXFRAMEERR_OFFSET 4
838#define GEM_NDS_RXFIFOERR_OFFSET 5
839#define GEM_NDS_TXERR_OFFSET 6
840#define GEM_NDS_TXABORTEDERR_OFFSET 7
841#define GEM_NDS_TXCARRIERERR_OFFSET 8
842#define GEM_NDS_TXFIFOERR_OFFSET 9
843#define GEM_NDS_COLLISIONS_OFFSET 10
844
845#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
846#define GEM_STAT_TITLE_BITS(name, title, bits) { \
847 .stat_string = title, \
848 .offset = GEM_##name, \
849 .stat_bits = bits \
850}
851
852/* list of gem statistic registers. The names MUST match the
853 * corresponding GEM_* definitions.
854 */
855static const struct gem_statistic gem_statistics[] = {
856 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
857 GEM_STAT_TITLE(TXCNT, "tx_frames"),
858 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
859 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
860 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
861 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
862 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
863 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
864 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
865 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
866 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
867 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
868 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
869 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
870 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
871 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
872 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
873 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
874 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
875 GEM_BIT(NDS_TXERR)|
876 GEM_BIT(NDS_TXABORTEDERR)|
877 GEM_BIT(NDS_COLLISIONS)),
878 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
879 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
880 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
881 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
882 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
883 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
884 GEM_STAT_TITLE(RXCNT, "rx_frames"),
885 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
886 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
887 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
888 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
889 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
890 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
891 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
892 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
893 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
894 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
895 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
896 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
897 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
898 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
899 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
900 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
901 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
902 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
903 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
904 GEM_BIT(NDS_RXERR)),
905 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
906 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
907 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
908 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
909 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
910 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
911 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
912 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
913 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
914 GEM_BIT(NDS_RXERR)),
915 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
916 GEM_BIT(NDS_RXERR)),
917 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
918 GEM_BIT(NDS_RXERR)),
919};
920
921#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
922
Nicolas Ferre4df95132013-06-04 21:57:12 +0000923struct macb;
924
925struct macb_or_gem_ops {
926 int (*mog_alloc_rx_buffers)(struct macb *bp);
927 void (*mog_free_rx_buffers)(struct macb *bp);
928 void (*mog_init_rings)(struct macb *bp);
929 int (*mog_rx)(struct macb *bp, int budget);
930};
931
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +0200932/* MACB-PTP interface: adapt to platform needs. */
933struct macb_ptp_info {
934 void (*ptp_init)(struct net_device *ndev);
935 void (*ptp_remove)(struct net_device *ndev);
936 s32 (*get_ptp_max_adj)(void);
937 unsigned int (*get_tsu_rate)(struct macb *bp);
938 int (*get_ts_info)(struct net_device *dev,
939 struct ethtool_ts_info *info);
940 int (*get_hwtst)(struct net_device *netdev,
941 struct ifreq *ifr);
942 int (*set_hwtst)(struct net_device *netdev,
943 struct ifreq *ifr, int cmd);
944};
945
Nicolas Ferree1755872014-07-24 13:50:58 +0200946struct macb_config {
947 u32 caps;
948 unsigned int dma_burst_length;
Nicolas Ferrec69618b2015-03-31 15:02:03 +0200949 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
shubhrajyoti.datta@xilinx.comaead88b2016-08-16 10:14:50 +0530950 struct clk **hclk, struct clk **tx_clk,
951 struct clk **rx_clk);
Cyrille Pitchen421d9df2015-03-07 07:23:32 +0100952 int (*init)(struct platform_device *pdev);
Harini Katakam98b5a0f42015-05-06 22:27:17 +0530953 int jumbo_max_len;
Nicolas Ferree1755872014-07-24 13:50:58 +0200954};
955
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100956struct tsu_incr {
957 u32 sub_ns;
958 u32 ns;
959};
960
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100961struct macb_queue {
962 struct macb *bp;
963 int irq;
964
965 unsigned int ISR;
966 unsigned int IER;
967 unsigned int IDR;
968 unsigned int IMR;
969 unsigned int TBQP;
Harini Katakamfff80192016-08-09 13:15:53 +0530970 unsigned int TBQPH;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100971
972 unsigned int tx_head, tx_tail;
973 struct macb_dma_desc *tx_ring;
974 struct macb_tx_skb *tx_skb;
975 dma_addr_t tx_ring_dma;
976 struct work_struct tx_error_task;
Rafal Oziebloab91f0a2017-06-29 07:14:16 +0100977
978#ifdef CONFIG_MACB_USE_HWSTAMP
979 struct work_struct tx_ts_task;
980 unsigned int tx_ts_head, tx_ts_tail;
981 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
982#endif
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100983};
984
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100985struct macb {
986 void __iomem *regs;
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +0300987 bool native_io;
988
989 /* hardware IO accessors */
David S. Miller7a6e0702015-07-27 14:24:48 -0700990 u32 (*macb_reg_readl)(struct macb *bp, int offset);
991 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100992
993 unsigned int rx_tail;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000994 unsigned int rx_prepared_head;
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000995 struct macb_dma_desc *rx_ring;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000996 struct sk_buff **rx_skbuff;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100997 void *rx_buffers;
Nicolas Ferre1b447912013-06-04 21:57:11 +0000998 size_t rx_buffer_size;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100999
Zach Brownb410d132016-10-19 09:56:57 -05001000 unsigned int rx_ring_size;
1001 unsigned int tx_ring_size;
1002
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001003 unsigned int num_queues;
Nicolas Ferrebfa09142015-03-31 15:01:59 +02001004 unsigned int queue_mask;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001005 struct macb_queue queues[MACB_MAX_QUEUES];
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001006
1007 spinlock_t lock;
1008 struct platform_device *pdev;
1009 struct clk *pclk;
1010 struct clk *hclk;
Soren Brinkmanne1824df2013-12-10 16:07:23 -08001011 struct clk *tx_clk;
shubhrajyoti.datta@xilinx.comaead88b2016-08-16 10:14:50 +05301012 struct clk *rx_clk;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001013 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001014 struct napi_struct napi;
Jamie Ilesa494ed82011-03-09 16:26:35 +00001015 union {
1016 struct macb_stats macb;
1017 struct gem_stats gem;
1018 } hw_stats;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001019
1020 dma_addr_t rx_ring_dma;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001021 dma_addr_t rx_buffers_dma;
1022
Nicolas Ferre4df95132013-06-04 21:57:12 +00001023 struct macb_or_gem_ops macbgem_ops;
1024
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001025 struct mii_bus *mii_bus;
Michael Grzeschikdacdbb42017-06-23 16:54:10 +02001026 struct device_node *phy_node;
Andy Shevchenko8bcbf822015-07-24 21:24:02 +03001027 int link;
1028 int speed;
1029 int duplex;
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +01001030
Nicolas Ferre581df9e2013-05-14 03:00:16 +00001031 u32 caps;
Nicolas Ferree1755872014-07-24 13:50:58 +02001032 unsigned int dma_burst_length;
Nicolas Ferre581df9e2013-05-14 03:00:16 +00001033
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +01001034 phy_interface_t phy_interface;
Gregory CLEMENT5833e052015-12-11 11:34:53 +01001035 struct gpio_desc *reset_gpio;
Joachim Eastwoodb85008b2012-10-18 11:01:10 +00001036
Joachim Eastwood4dda6f62012-11-07 08:14:55 +00001037 /* AT91RM9200 transmit */
Joachim Eastwoodb85008b2012-10-18 11:01:10 +00001038 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
1039 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
1040 int skb_length; /* saved skb length for pci_unmap_single */
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001041 unsigned int max_tx_length;
Xander Huff3ff13f12015-01-13 16:15:51 -06001042
1043 u64 ethtool_stats[GEM_STATS_LEN];
Harini Katakam98b5a0f42015-05-06 22:27:17 +05301044
1045 unsigned int rx_frm_len_mask;
1046 unsigned int jumbo_max_len;
Sergio Prado3e2a5e12016-02-09 12:07:16 -02001047
1048 u32 wol;
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +02001049
1050 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
Rafal Ozieblo7b429612017-06-29 07:12:51 +01001051#ifdef MACB_EXT_DESC
1052 uint8_t hw_dma_cap;
Rafal Ozieblodc97a892017-01-27 15:08:20 +00001053#endif
Rafal Oziebloab91f0a2017-06-29 07:14:16 +01001054 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1055 unsigned int tsu_rate;
1056 struct ptp_clock *ptp_clock;
1057 struct ptp_clock_info ptp_clock_info;
1058 struct tsu_incr tsu_incr;
1059 struct hwtstamp_config tstamp_config;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001060};
1061
Rafal Oziebloab91f0a2017-06-29 07:14:16 +01001062#ifdef CONFIG_MACB_USE_HWSTAMP
1063#define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1064#define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1065#define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1066
1067enum macb_bd_control {
1068 TSTAMP_DISABLED,
1069 TSTAMP_FRAME_PTP_EVENT_ONLY,
1070 TSTAMP_ALL_PTP_FRAMES,
1071 TSTAMP_ALL_FRAMES,
1072};
1073
1074void gem_ptp_init(struct net_device *ndev);
1075void gem_ptp_remove(struct net_device *ndev);
1076int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1077void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1078static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1079{
1080 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1081 return -ENOTSUPP;
1082
1083 return gem_ptp_txstamp(queue, skb, desc);
1084}
1085
1086static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1087{
1088 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1089 return;
1090
1091 gem_ptp_rxstamp(bp, skb, desc);
1092}
1093int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1094int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1095#else
1096static inline void gem_ptp_init(struct net_device *ndev) { }
1097static inline void gem_ptp_remove(struct net_device *ndev) { }
1098
1099static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1100{
1101 return -1;
1102}
1103
1104static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1105#endif
1106
Jamie Ilesf75ba502011-11-08 10:12:32 +00001107static inline bool macb_is_gem(struct macb *bp)
1108{
Nicolas Ferree1755872014-07-24 13:50:58 +02001109 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
Jamie Ilesf75ba502011-11-08 10:12:32 +00001110}
1111
Andrei.Pistirica@microchip.comc2594d82017-01-19 17:56:15 +02001112static inline bool gem_has_ptp(struct macb *bp)
1113{
1114 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1115}
1116
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001117#endif /* _MACB_H */