blob: f3a1d6a5cabe9fcf76f5812dc526781b678f7e41 [file] [log] [blame]
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
Rodrigo Vivi94b83952014-12-08 06:46:31 -080024/**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020030 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
Rodrigo Vivi94b83952014-12-08 06:46:31 -080032 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020034 *
Rodrigo Vivi94b83952014-12-08 06:46:31 -080035 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -020039 */
40
Rodrigo Vivi94b83952014-12-08 06:46:31 -080041#include "intel_drv.h"
42#include "i915_drv.h"
43
Paulo Zanoni9f218332015-09-23 12:52:27 -030044static inline bool fbc_supported(struct drm_i915_private *dev_priv)
45{
Paulo Zanoni8c400742016-01-29 18:57:39 -020046 return HAS_FBC(dev_priv);
Paulo Zanoni9f218332015-09-23 12:52:27 -030047}
48
Paulo Zanoni57105022015-11-04 17:10:46 -020049static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
50{
Paulo Zanoni5697d602016-11-11 14:57:41 -020051 return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
Paulo Zanoni57105022015-11-04 17:10:46 -020052}
53
Paulo Zanonie6cd6dc2015-10-16 17:55:40 -030054static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
55{
Paulo Zanoni5697d602016-11-11 14:57:41 -020056 return INTEL_GEN(dev_priv) < 4;
Paulo Zanonie6cd6dc2015-10-16 17:55:40 -030057}
58
Paulo Zanoni010cf732016-01-19 11:35:48 -020059static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
60{
Paulo Zanoni5697d602016-11-11 14:57:41 -020061 return INTEL_GEN(dev_priv) <= 3;
Paulo Zanoni010cf732016-01-19 11:35:48 -020062}
63
Paulo Zanoni2db33662015-09-14 15:20:03 -030064/*
65 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
66 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
67 * origin so the x and y offsets can actually fit the registers. As a
68 * consequence, the fence doesn't really start exactly at the display plane
69 * address we program because it starts at the real start of the buffer, so we
70 * have to take this into consideration here.
71 */
72static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
73{
74 return crtc->base.y - crtc->adjusted_y;
75}
76
Paulo Zanonic5ecd462015-10-15 14:19:21 -030077/*
78 * For SKL+, the plane source size used by the hardware is based on the value we
79 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
80 * we wrote to PIPESRC.
81 */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -020082static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
Paulo Zanonic5ecd462015-10-15 14:19:21 -030083 int *width, int *height)
84{
Paulo Zanonic5ecd462015-10-15 14:19:21 -030085 int w, h;
86
Ville Syrjäläbd2ef252016-09-26 19:30:46 +030087 if (drm_rotation_90_or_270(cache->plane.rotation)) {
Paulo Zanoniaaf78d22016-01-19 11:35:42 -020088 w = cache->plane.src_h;
89 h = cache->plane.src_w;
Paulo Zanonic5ecd462015-10-15 14:19:21 -030090 } else {
Paulo Zanoniaaf78d22016-01-19 11:35:42 -020091 w = cache->plane.src_w;
92 h = cache->plane.src_h;
Paulo Zanonic5ecd462015-10-15 14:19:21 -030093 }
94
95 if (width)
96 *width = w;
97 if (height)
98 *height = h;
99}
100
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200101static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
102 struct intel_fbc_state_cache *cache)
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300103{
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300104 int lines;
105
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200106 intel_fbc_get_plane_source_size(cache, NULL, &lines);
Paulo Zanoni79f26242016-10-21 13:55:45 -0200107 if (INTEL_GEN(dev_priv) == 7)
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300108 lines = min(lines, 2048);
Paulo Zanoni79f26242016-10-21 13:55:45 -0200109 else if (INTEL_GEN(dev_priv) >= 8)
110 lines = min(lines, 2560);
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300111
112 /* Hardware needs the full buffer stride, not just the active area. */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200113 return lines * cache->fb.stride;
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300114}
115
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300116static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200117{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200118 u32 fbc_ctl;
119
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200120 /* Disable compression */
121 fbc_ctl = I915_READ(FBC_CONTROL);
122 if ((fbc_ctl & FBC_CTL_EN) == 0)
123 return;
124
125 fbc_ctl &= ~FBC_CTL_EN;
126 I915_WRITE(FBC_CONTROL, fbc_ctl);
127
128 /* Wait for compressing bit to clear */
Chris Wilson8d90dfd2016-06-30 15:33:21 +0100129 if (intel_wait_for_register(dev_priv,
130 FBC_STATUS, FBC_STAT_COMPRESSING, 0,
131 10)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200132 DRM_DEBUG_KMS("FBC idle timed out\n");
133 return;
134 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200135}
136
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200137static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200138{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200139 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200140 int cfb_pitch;
141 int i;
142 u32 fbc_ctl;
143
Jani Nikula60ee5cd2015-02-05 12:04:27 +0200144 /* Note: fbc.threshold == 1 for i8xx */
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200145 cfb_pitch = params->cfb_size / FBC_LL_SIZE;
146 if (params->fb.stride < cfb_pitch)
147 cfb_pitch = params->fb.stride;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200148
149 /* FBC_CTL wants 32B or 64B units */
Paulo Zanoni7733b492015-07-07 15:26:04 -0300150 if (IS_GEN2(dev_priv))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200151 cfb_pitch = (cfb_pitch / 32) - 1;
152 else
153 cfb_pitch = (cfb_pitch / 64) - 1;
154
155 /* Clear old tags */
156 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
Ville Syrjälä4d110c72015-09-18 20:03:18 +0300157 I915_WRITE(FBC_TAG(i), 0);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200158
Paulo Zanoni7733b492015-07-07 15:26:04 -0300159 if (IS_GEN4(dev_priv)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200160 u32 fbc_ctl2;
161
162 /* Set it up... */
163 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200164 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200165 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200166 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200167 }
168
169 /* enable it... */
170 fbc_ctl = I915_READ(FBC_CONTROL);
171 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
172 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
Paulo Zanoni7733b492015-07-07 15:26:04 -0300173 if (IS_I945GM(dev_priv))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200174 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
175 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100176 fbc_ctl |= params->vma->fence->id;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200177 I915_WRITE(FBC_CONTROL, fbc_ctl);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200178}
179
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300180static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200181{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200182 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
183}
184
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200185static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200186{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200187 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200188 u32 dpfc_ctl;
189
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200190 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
191 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200192 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
193 else
194 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200195
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100196 if (params->vma->fence) {
197 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100198 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
199 } else {
200 I915_WRITE(DPFC_FENCE_YOFF, 0);
201 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200202
203 /* enable it... */
204 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200205}
206
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300207static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200208{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200209 u32 dpfc_ctl;
210
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200211 /* Disable compression */
212 dpfc_ctl = I915_READ(DPFC_CONTROL);
213 if (dpfc_ctl & DPFC_CTL_EN) {
214 dpfc_ctl &= ~DPFC_CTL_EN;
215 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200216 }
217}
218
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300219static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200220{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200221 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
222}
223
Paulo Zanonid5ce4162015-11-04 17:10:45 -0200224/* This function forces a CFB recompression through the nuke operation. */
225static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200226{
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200227 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
228 POSTING_READ(MSG_FBC_REND_STATE);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200229}
230
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200231static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200232{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200233 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200234 u32 dpfc_ctl;
Paulo Zanonice65e472015-06-30 10:53:05 -0300235 int threshold = dev_priv->fbc.threshold;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200236
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200237 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
238 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
Paulo Zanonice65e472015-06-30 10:53:05 -0300239 threshold++;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200240
Paulo Zanonice65e472015-06-30 10:53:05 -0300241 switch (threshold) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200242 case 4:
243 case 3:
244 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
245 break;
246 case 2:
247 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
248 break;
249 case 1:
250 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
251 break;
252 }
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100253
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100254 if (params->vma->fence) {
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100255 dpfc_ctl |= DPFC_CTL_FENCE_EN;
256 if (IS_GEN5(dev_priv))
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100257 dpfc_ctl |= params->vma->fence->id;
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100258 if (IS_GEN6(dev_priv)) {
259 I915_WRITE(SNB_DPFC_CTL_SA,
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100260 SNB_CPU_FENCE_ENABLE |
261 params->vma->fence->id);
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100262 I915_WRITE(DPFC_CPU_FENCE_OFFSET,
263 params->crtc.fence_y_offset);
264 }
265 } else {
266 if (IS_GEN6(dev_priv)) {
267 I915_WRITE(SNB_DPFC_CTL_SA, 0);
268 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
269 }
270 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200271
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200272 I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100273 I915_WRITE(ILK_FBC_RT_BASE,
274 i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200275 /* enable it... */
276 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
277
Paulo Zanonid5ce4162015-11-04 17:10:45 -0200278 intel_fbc_recompress(dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200279}
280
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300281static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200282{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200283 u32 dpfc_ctl;
284
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200285 /* Disable compression */
286 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
287 if (dpfc_ctl & DPFC_CTL_EN) {
288 dpfc_ctl &= ~DPFC_CTL_EN;
289 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200290 }
291}
292
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300293static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200294{
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200295 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
296}
297
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200298static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200299{
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200300 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200301 u32 dpfc_ctl;
Paulo Zanonice65e472015-06-30 10:53:05 -0300302 int threshold = dev_priv->fbc.threshold;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200303
Paulo Zanonid8514d62015-06-12 14:36:21 -0300304 dpfc_ctl = 0;
Paulo Zanoni7733b492015-07-07 15:26:04 -0300305 if (IS_IVYBRIDGE(dev_priv))
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200306 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
Paulo Zanonid8514d62015-06-12 14:36:21 -0300307
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200308 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
Paulo Zanonice65e472015-06-30 10:53:05 -0300309 threshold++;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200310
Paulo Zanonice65e472015-06-30 10:53:05 -0300311 switch (threshold) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200312 case 4:
313 case 3:
314 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
315 break;
316 case 2:
317 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
318 break;
319 case 1:
320 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
321 break;
322 }
323
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100324 if (params->vma->fence) {
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100325 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
326 I915_WRITE(SNB_DPFC_CTL_SA,
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100327 SNB_CPU_FENCE_ENABLE |
328 params->vma->fence->id);
Chris Wilson12ecf4b2016-08-19 16:54:24 +0100329 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
330 } else {
331 I915_WRITE(SNB_DPFC_CTL_SA,0);
332 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
333 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200334
335 if (dev_priv->fbc.false_color)
336 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
337
Paulo Zanoni7733b492015-07-07 15:26:04 -0300338 if (IS_IVYBRIDGE(dev_priv)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200339 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
340 I915_WRITE(ILK_DISPLAY_CHICKEN1,
341 I915_READ(ILK_DISPLAY_CHICKEN1) |
342 ILK_FBCQ_DIS);
Paulo Zanoni40f40222015-09-14 15:20:01 -0300343 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200344 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200345 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
346 I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200347 HSW_FBCQ_DIS);
348 }
349
Paulo Zanoni57012be92015-09-14 15:20:00 -0300350 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
351
Paulo Zanonid5ce4162015-11-04 17:10:45 -0200352 intel_fbc_recompress(dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200353}
354
Paulo Zanoni8c400742016-01-29 18:57:39 -0200355static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
356{
Paulo Zanoni5697d602016-11-11 14:57:41 -0200357 if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200358 return ilk_fbc_is_active(dev_priv);
359 else if (IS_GM45(dev_priv))
360 return g4x_fbc_is_active(dev_priv);
361 else
362 return i8xx_fbc_is_active(dev_priv);
363}
364
365static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
366{
Paulo Zanoni5375ce92016-01-29 18:57:40 -0200367 struct intel_fbc *fbc = &dev_priv->fbc;
368
369 fbc->active = true;
370
Paulo Zanoni5697d602016-11-11 14:57:41 -0200371 if (INTEL_GEN(dev_priv) >= 7)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200372 gen7_fbc_activate(dev_priv);
Paulo Zanoni5697d602016-11-11 14:57:41 -0200373 else if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200374 ilk_fbc_activate(dev_priv);
375 else if (IS_GM45(dev_priv))
376 g4x_fbc_activate(dev_priv);
377 else
378 i8xx_fbc_activate(dev_priv);
379}
380
381static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
382{
Paulo Zanoni5375ce92016-01-29 18:57:40 -0200383 struct intel_fbc *fbc = &dev_priv->fbc;
384
385 fbc->active = false;
386
Paulo Zanoni5697d602016-11-11 14:57:41 -0200387 if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200388 ilk_fbc_deactivate(dev_priv);
389 else if (IS_GM45(dev_priv))
390 g4x_fbc_deactivate(dev_priv);
391 else
392 i8xx_fbc_deactivate(dev_priv);
393}
394
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800395/**
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300396 * intel_fbc_is_active - Is FBC active?
Paulo Zanoni7733b492015-07-07 15:26:04 -0300397 * @dev_priv: i915 device instance
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800398 *
399 * This function is used to verify the current state of FBC.
Daniel Vetter2e7a5702016-06-01 23:40:36 +0200400 *
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800401 * FIXME: This should be tracked in the plane config eventually
Daniel Vetter2e7a5702016-06-01 23:40:36 +0200402 * instead of queried at runtime for most callers.
Rodrigo Vivi94b83952014-12-08 06:46:31 -0800403 */
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300404bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200405{
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300406 return dev_priv->fbc.active;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200407}
408
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200409static void intel_fbc_work_fn(struct work_struct *__work)
410{
Paulo Zanoni128d7352015-10-26 16:27:49 -0200411 struct drm_i915_private *dev_priv =
412 container_of(__work, struct drm_i915_private, fbc.work.work);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200413 struct intel_fbc *fbc = &dev_priv->fbc;
414 struct intel_fbc_work *work = &fbc->work;
415 struct intel_crtc *crtc = fbc->crtc;
Chris Wilson91c8a322016-07-05 10:40:23 +0100416 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
Paulo Zanonica18d512016-01-21 18:03:05 -0200417
418 if (drm_crtc_vblank_get(&crtc->base)) {
419 DRM_ERROR("vblank not available for FBC on pipe %c\n",
420 pipe_name(crtc->pipe));
421
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200422 mutex_lock(&fbc->lock);
Paulo Zanonica18d512016-01-21 18:03:05 -0200423 work->scheduled = false;
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200424 mutex_unlock(&fbc->lock);
Paulo Zanonica18d512016-01-21 18:03:05 -0200425 return;
426 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200427
Paulo Zanoni128d7352015-10-26 16:27:49 -0200428retry:
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200429 /* Delay the actual enabling to let pageflipping cease and the
430 * display to settle before starting the compression. Note that
431 * this delay also serves a second purpose: it allows for a
432 * vblank to pass after disabling the FBC before we attempt
433 * to modify the control registers.
434 *
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200435 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
Paulo Zanonica18d512016-01-21 18:03:05 -0200436 *
437 * It is also worth mentioning that since work->scheduled_vblank can be
438 * updated multiple times by the other threads, hitting the timeout is
439 * not an error condition. We'll just end up hitting the "goto retry"
440 * case below.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200441 */
Paulo Zanonica18d512016-01-21 18:03:05 -0200442 wait_event_timeout(vblank->queue,
443 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
444 msecs_to_jiffies(50));
Paulo Zanoni128d7352015-10-26 16:27:49 -0200445
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200446 mutex_lock(&fbc->lock);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200447
448 /* Were we cancelled? */
449 if (!work->scheduled)
450 goto out;
451
452 /* Were we delayed again while this function was sleeping? */
Paulo Zanonica18d512016-01-21 18:03:05 -0200453 if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200454 mutex_unlock(&fbc->lock);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200455 goto retry;
456 }
457
Paulo Zanoni8c400742016-01-29 18:57:39 -0200458 intel_fbc_hw_activate(dev_priv);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200459
460 work->scheduled = false;
461
462out:
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200463 mutex_unlock(&fbc->lock);
Paulo Zanonica18d512016-01-21 18:03:05 -0200464 drm_crtc_vblank_put(&crtc->base);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200465}
466
Paulo Zanoni128d7352015-10-26 16:27:49 -0200467static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
468{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100469 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200470 struct intel_fbc *fbc = &dev_priv->fbc;
471 struct intel_fbc_work *work = &fbc->work;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200472
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200473 WARN_ON(!mutex_is_locked(&fbc->lock));
Paulo Zanoni128d7352015-10-26 16:27:49 -0200474
Paulo Zanonica18d512016-01-21 18:03:05 -0200475 if (drm_crtc_vblank_get(&crtc->base)) {
476 DRM_ERROR("vblank not available for FBC on pipe %c\n",
477 pipe_name(crtc->pipe));
478 return;
479 }
480
Paulo Zanonie35be232016-01-18 15:56:58 -0200481 /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
482 * this function since we're not releasing fbc.lock, so it won't have an
483 * opportunity to grab it to discover that it was cancelled. So we just
484 * update the expected jiffy count. */
Paulo Zanoni128d7352015-10-26 16:27:49 -0200485 work->scheduled = true;
Paulo Zanonica18d512016-01-21 18:03:05 -0200486 work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
487 drm_crtc_vblank_put(&crtc->base);
Paulo Zanoni128d7352015-10-26 16:27:49 -0200488
489 schedule_work(&work->work);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200490}
491
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200492static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300493{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200494 struct intel_fbc *fbc = &dev_priv->fbc;
495
496 WARN_ON(!mutex_is_locked(&fbc->lock));
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300497
Paulo Zanonie35be232016-01-18 15:56:58 -0200498 /* Calling cancel_work() here won't help due to the fact that the work
499 * function grabs fbc->lock. Just set scheduled to false so the work
500 * function can know it was cancelled. */
501 fbc->work.scheduled = false;
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300502
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200503 if (fbc->active)
Paulo Zanoni8c400742016-01-29 18:57:39 -0200504 intel_fbc_hw_deactivate(dev_priv);
Paulo Zanoni754d1132015-10-13 19:13:25 -0300505}
506
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200507static bool multiple_pipes_ok(struct intel_crtc *crtc,
508 struct intel_plane_state *plane_state)
Paulo Zanoni232fd932015-07-07 15:26:07 -0300509{
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoni010cf732016-01-19 11:35:48 -0200511 struct intel_fbc *fbc = &dev_priv->fbc;
512 enum pipe pipe = crtc->pipe;
Paulo Zanoni232fd932015-07-07 15:26:07 -0300513
Paulo Zanoni010cf732016-01-19 11:35:48 -0200514 /* Don't even bother tracking anything we don't need. */
515 if (!no_fbc_on_multiple_pipes(dev_priv))
Paulo Zanoni232fd932015-07-07 15:26:07 -0300516 return true;
517
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300518 if (plane_state->base.visible)
Paulo Zanoni010cf732016-01-19 11:35:48 -0200519 fbc->visible_pipes_mask |= (1 << pipe);
520 else
521 fbc->visible_pipes_mask &= ~(1 << pipe);
Paulo Zanoni232fd932015-07-07 15:26:07 -0300522
Paulo Zanoni010cf732016-01-19 11:35:48 -0200523 return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
Paulo Zanoni232fd932015-07-07 15:26:07 -0300524}
525
Paulo Zanoni7733b492015-07-07 15:26:04 -0300526static int find_compression_threshold(struct drm_i915_private *dev_priv,
Paulo Zanonifc786722015-07-02 19:25:08 -0300527 struct drm_mm_node *node,
528 int size,
529 int fb_cpp)
530{
Joonas Lahtinen72e96d62016-03-30 16:57:10 +0300531 struct i915_ggtt *ggtt = &dev_priv->ggtt;
Paulo Zanonifc786722015-07-02 19:25:08 -0300532 int compression_threshold = 1;
533 int ret;
Paulo Zanonia9da5122015-09-14 15:19:57 -0300534 u64 end;
535
536 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
537 * reserved range size, so it always assumes the maximum (8mb) is used.
538 * If we enable FBC using a CFB on that memory range we'll get FIFO
539 * underruns, even if that range is not reserved by the BIOS. */
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700540 if (IS_BROADWELL(dev_priv) ||
541 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
Joonas Lahtinen72e96d62016-03-30 16:57:10 +0300542 end = ggtt->stolen_size - 8 * 1024 * 1024;
Paulo Zanonia9da5122015-09-14 15:19:57 -0300543 else
Joonas Lahtinen72e96d62016-03-30 16:57:10 +0300544 end = ggtt->stolen_usable_size;
Paulo Zanonifc786722015-07-02 19:25:08 -0300545
546 /* HACK: This code depends on what we will do in *_enable_fbc. If that
547 * code changes, this code needs to change as well.
548 *
549 * The enable_fbc code will attempt to use one of our 2 compression
550 * thresholds, therefore, in that case, we only have 1 resort.
551 */
552
553 /* Try to over-allocate to reduce reallocations and fragmentation. */
Paulo Zanonia9da5122015-09-14 15:19:57 -0300554 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
555 4096, 0, end);
Paulo Zanonifc786722015-07-02 19:25:08 -0300556 if (ret == 0)
557 return compression_threshold;
558
559again:
560 /* HW's ability to limit the CFB is 1:4 */
561 if (compression_threshold > 4 ||
562 (fb_cpp == 2 && compression_threshold == 2))
563 return 0;
564
Paulo Zanonia9da5122015-09-14 15:19:57 -0300565 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
566 4096, 0, end);
Paulo Zanoni5697d602016-11-11 14:57:41 -0200567 if (ret && INTEL_GEN(dev_priv) <= 4) {
Paulo Zanonifc786722015-07-02 19:25:08 -0300568 return 0;
569 } else if (ret) {
570 compression_threshold <<= 1;
571 goto again;
572 } else {
573 return compression_threshold;
574 }
575}
576
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300577static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
Paulo Zanonifc786722015-07-02 19:25:08 -0300578{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100579 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200580 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonifc786722015-07-02 19:25:08 -0300581 struct drm_mm_node *uninitialized_var(compressed_llb);
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300582 int size, fb_cpp, ret;
583
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200584 WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300585
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200586 size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
587 fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
Paulo Zanonifc786722015-07-02 19:25:08 -0300588
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200589 ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
Paulo Zanonifc786722015-07-02 19:25:08 -0300590 size, fb_cpp);
591 if (!ret)
592 goto err_llb;
593 else if (ret > 1) {
594 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
595
596 }
597
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200598 fbc->threshold = ret;
Paulo Zanonifc786722015-07-02 19:25:08 -0300599
Paulo Zanoni5697d602016-11-11 14:57:41 -0200600 if (INTEL_GEN(dev_priv) >= 5)
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200601 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
Paulo Zanoni7733b492015-07-07 15:26:04 -0300602 else if (IS_GM45(dev_priv)) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200603 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
Paulo Zanonifc786722015-07-02 19:25:08 -0300604 } else {
605 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
606 if (!compressed_llb)
607 goto err_fb;
608
609 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
610 4096, 4096);
611 if (ret)
612 goto err_fb;
613
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200614 fbc->compressed_llb = compressed_llb;
Paulo Zanonifc786722015-07-02 19:25:08 -0300615
616 I915_WRITE(FBC_CFB_BASE,
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200617 dev_priv->mm.stolen_base + fbc->compressed_fb.start);
Paulo Zanonifc786722015-07-02 19:25:08 -0300618 I915_WRITE(FBC_LL_BASE,
619 dev_priv->mm.stolen_base + compressed_llb->start);
620 }
621
Paulo Zanonib8bf5d72015-09-14 15:19:58 -0300622 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200623 fbc->compressed_fb.size, fbc->threshold);
Paulo Zanonifc786722015-07-02 19:25:08 -0300624
625 return 0;
626
627err_fb:
628 kfree(compressed_llb);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200629 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
Paulo Zanonifc786722015-07-02 19:25:08 -0300630err_llb:
631 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
632 return -ENOSPC;
633}
634
Paulo Zanoni7733b492015-07-07 15:26:04 -0300635static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
Paulo Zanonifc786722015-07-02 19:25:08 -0300636{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200637 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonifc786722015-07-02 19:25:08 -0300638
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200639 if (drm_mm_node_allocated(&fbc->compressed_fb))
640 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
641
642 if (fbc->compressed_llb) {
643 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
644 kfree(fbc->compressed_llb);
Paulo Zanonifc786722015-07-02 19:25:08 -0300645 }
Paulo Zanonifc786722015-07-02 19:25:08 -0300646}
647
Paulo Zanoni7733b492015-07-07 15:26:04 -0300648void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300649{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200650 struct intel_fbc *fbc = &dev_priv->fbc;
651
Paulo Zanoni9f218332015-09-23 12:52:27 -0300652 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -0300653 return;
654
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200655 mutex_lock(&fbc->lock);
Paulo Zanoni7733b492015-07-07 15:26:04 -0300656 __intel_fbc_cleanup_cfb(dev_priv);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200657 mutex_unlock(&fbc->lock);
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300658}
659
Paulo Zanoniadf70c62015-09-14 15:19:56 -0300660static bool stride_is_valid(struct drm_i915_private *dev_priv,
661 unsigned int stride)
662{
663 /* These should have been caught earlier. */
664 WARN_ON(stride < 512);
665 WARN_ON((stride & (64 - 1)) != 0);
666
667 /* Below are the additional FBC restrictions. */
668
669 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
670 return stride == 4096 || stride == 8192;
671
672 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
673 return false;
674
675 if (stride > 16384)
676 return false;
677
678 return true;
679}
680
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200681static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
682 uint32_t pixel_format)
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300683{
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200684 switch (pixel_format) {
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300685 case DRM_FORMAT_XRGB8888:
686 case DRM_FORMAT_XBGR8888:
687 return true;
688 case DRM_FORMAT_XRGB1555:
689 case DRM_FORMAT_RGB565:
690 /* 16bpp not supported on gen2 */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200691 if (IS_GEN2(dev_priv))
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300692 return false;
693 /* WaFbcOnly1to1Ratio:ctg */
694 if (IS_G4X(dev_priv))
695 return false;
696 return true;
697 default:
698 return false;
699 }
700}
701
Paulo Zanoni856312a2015-10-01 19:57:12 -0300702/*
703 * For some reason, the hardware tracking starts looking at whatever we
704 * programmed as the display plane base address register. It does not look at
705 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
706 * variables instead of just looking at the pipe/plane size.
707 */
708static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300709{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100710 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200711 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni856312a2015-10-01 19:57:12 -0300712 unsigned int effective_w, effective_h, max_w, max_h;
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300713
Paulo Zanoni5697d602016-11-11 14:57:41 -0200714 if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300715 max_w = 4096;
716 max_h = 4096;
Paulo Zanoni5697d602016-11-11 14:57:41 -0200717 } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300718 max_w = 4096;
719 max_h = 2048;
720 } else {
721 max_w = 2048;
722 max_h = 1536;
723 }
724
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200725 intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
726 &effective_h);
Paulo Zanoni856312a2015-10-01 19:57:12 -0300727 effective_w += crtc->adjusted_x;
728 effective_h += crtc->adjusted_y;
729
730 return effective_w <= max_w && effective_h <= max_h;
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300731}
732
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200733static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
734 struct intel_crtc_state *crtc_state,
735 struct intel_plane_state *plane_state)
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200736{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200738 struct intel_fbc *fbc = &dev_priv->fbc;
739 struct intel_fbc_state_cache *cache = &fbc->state_cache;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200740 struct drm_framebuffer *fb = plane_state->base.fb;
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100741
742 cache->vma = NULL;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200743
744 cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
745 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
746 cache->crtc.hsw_bdw_pixel_rate =
747 ilk_pipe_pixel_rate(crtc_state);
748
749 cache->plane.rotation = plane_state->base.rotation;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300750 cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
751 cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
752 cache->plane.visible = plane_state->base.visible;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200753
754 if (!cache->plane.visible)
755 return;
756
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200757 cache->fb.pixel_format = fb->pixel_format;
758 cache->fb.stride = fb->pitches[0];
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100759
760 cache->vma = plane_state->vma;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200761}
762
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200763static bool intel_fbc_can_activate(struct intel_crtc *crtc)
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200764{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200766 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200767 struct intel_fbc_state_cache *cache = &fbc->state_cache;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200768
Paulo Zanoni61a585d2016-09-13 10:38:57 -0300769 /* We don't need to use a state cache here since this information is
770 * global for all CRTC.
771 */
772 if (fbc->underrun_detected) {
773 fbc->no_fbc_reason = "underrun detected";
774 return false;
775 }
776
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100777 if (!cache->vma) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200778 fbc->no_fbc_reason = "primary plane not visible";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200779 return false;
780 }
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200781
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200782 if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
783 (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200784 fbc->no_fbc_reason = "incompatible mode";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200785 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200786 }
787
Paulo Zanoni45b32a22015-11-04 17:10:49 -0200788 if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200789 fbc->no_fbc_reason = "mode too large for compression";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200790 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200791 }
Paulo Zanoni3c5f1742015-09-23 12:52:24 -0300792
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200793 /* The use of a CPU fence is mandatory in order to detect writes
794 * by the CPU to the scanout and trigger updates to the FBC.
Chris Wilson2efb8132016-08-18 17:17:06 +0100795 *
796 * Note that is possible for a tiled surface to be unmappable (and
797 * so have no fence associated with it) due to aperture constaints
798 * at the time of pinning.
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200799 */
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100800 if (!cache->vma->fence) {
Chris Wilsonc82dd882016-08-24 19:00:53 +0100801 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
802 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200803 }
Paulo Zanoni5697d602016-11-11 14:57:41 -0200804 if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +0300805 cache->plane.rotation != DRM_ROTATE_0) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200806 fbc->no_fbc_reason = "rotation unsupported";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200807 return false;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200808 }
809
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200810 if (!stride_is_valid(dev_priv, cache->fb.stride)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200811 fbc->no_fbc_reason = "framebuffer stride not supported";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200812 return false;
Paulo Zanoniadf70c62015-09-14 15:19:56 -0300813 }
814
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200815 if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200816 fbc->no_fbc_reason = "pixel format is invalid";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200817 return false;
Paulo Zanonib9e831d2015-09-21 19:48:06 -0300818 }
819
Paulo Zanoni7b24c9a2015-09-14 15:19:59 -0300820 /* WaFbcExceedCdClockThreshold:hsw,bdw */
821 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200822 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200823 fbc->no_fbc_reason = "pixel rate is too big";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200824 return false;
Paulo Zanoni7b24c9a2015-09-14 15:19:59 -0300825 }
826
Paulo Zanonic5ecd462015-10-15 14:19:21 -0300827 /* It is possible for the required CFB size change without a
828 * crtc->disable + crtc->enable since it is possible to change the
829 * stride without triggering a full modeset. Since we try to
830 * over-allocate the CFB, there's a chance we may keep FBC enabled even
831 * if this happens, but if we exceed the current CFB size we'll have to
832 * disable FBC. Notice that it would be possible to disable FBC, wait
833 * for a frame, free the stolen node, then try to reenable FBC in case
834 * we didn't get any invalidate/deactivate calls, but this would require
835 * a lot of tracking just for a specific case. If we conclude it's an
836 * important case, we can implement it later. */
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200837 if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200838 fbc->compressed_fb.size * fbc->threshold) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200839 fbc->no_fbc_reason = "CFB requirements changed";
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200840 return false;
841 }
842
843 return true;
844}
845
Paulo Zanoniee2be302016-11-11 14:57:37 -0200846static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200847{
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200848 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200849
Chris Wilsonc0336662016-05-06 15:40:21 +0100850 if (intel_vgpu_active(dev_priv)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200851 fbc->no_fbc_reason = "VGPU is active";
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200852 return false;
853 }
854
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200855 if (!i915.enable_fbc) {
Paulo Zanoni80788a02016-04-13 16:01:09 -0300856 fbc->no_fbc_reason = "disabled per module param or by default";
Paulo Zanoni44a8a252016-01-19 11:35:36 -0200857 return false;
858 }
859
Paulo Zanoni61a585d2016-09-13 10:38:57 -0300860 if (fbc->underrun_detected) {
861 fbc->no_fbc_reason = "underrun detected";
862 return false;
863 }
864
Paulo Zanoniee2be302016-11-11 14:57:37 -0200865 return true;
866}
867
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200868static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
869 struct intel_fbc_reg_params *params)
870{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100871 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200872 struct intel_fbc *fbc = &dev_priv->fbc;
873 struct intel_fbc_state_cache *cache = &fbc->state_cache;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200874
875 /* Since all our fields are integer types, use memset here so the
876 * comparison function can rely on memcmp because the padding will be
877 * zero. */
878 memset(params, 0, sizeof(*params));
879
Chris Wilsone8fe4f42017-01-31 10:21:31 +0100880 params->vma = cache->vma;
881
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200882 params->crtc.pipe = crtc->pipe;
883 params->crtc.plane = crtc->plane;
884 params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
885
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200886 params->fb.pixel_format = cache->fb.pixel_format;
887 params->fb.stride = cache->fb.stride;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200888
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200889 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200890}
891
892static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
893 struct intel_fbc_reg_params *params2)
894{
895 /* We can use this since intel_fbc_get_reg_params() does a memset. */
896 return memcmp(params1, params2, sizeof(*params1)) == 0;
897}
898
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200899void intel_fbc_pre_update(struct intel_crtc *crtc,
900 struct intel_crtc_state *crtc_state,
901 struct intel_plane_state *plane_state)
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200902{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100903 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200904 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200905
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200906 if (!fbc_supported(dev_priv))
907 return;
908
909 mutex_lock(&fbc->lock);
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200910
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200911 if (!multiple_pipes_ok(crtc, plane_state)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -0200912 fbc->no_fbc_reason = "more than one pipe active";
Paulo Zanoni212890c2016-01-19 11:35:43 -0200913 goto deactivate;
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200914 }
915
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200916 if (!fbc->enabled || fbc->crtc != crtc)
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200917 goto unlock;
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200918
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +0200919 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200920
Paulo Zanoni212890c2016-01-19 11:35:43 -0200921deactivate:
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200922 intel_fbc_deactivate(dev_priv);
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200923unlock:
924 mutex_unlock(&fbc->lock);
Paulo Zanoni212890c2016-01-19 11:35:43 -0200925}
926
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200927static void __intel_fbc_post_update(struct intel_crtc *crtc)
Paulo Zanoni212890c2016-01-19 11:35:43 -0200928{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100929 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoni212890c2016-01-19 11:35:43 -0200930 struct intel_fbc *fbc = &dev_priv->fbc;
931 struct intel_fbc_reg_params old_params;
932
933 WARN_ON(!mutex_is_locked(&fbc->lock));
934
935 if (!fbc->enabled || fbc->crtc != crtc)
936 return;
937
938 if (!intel_fbc_can_activate(crtc)) {
939 WARN_ON(fbc->active);
940 return;
941 }
Paulo Zanoni615b40d72016-01-19 11:35:35 -0200942
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200943 old_params = fbc->params;
944 intel_fbc_get_reg_params(crtc, &fbc->params);
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200945
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200946 /* If the scanout has not changed, don't modify the FBC settings.
947 * Note that we make the fundamental assumption that the fb->obj
948 * cannot be unpinned (and have its GTT offset and fence revoked)
949 * without first being decoupled from the scanout and FBC disabled.
950 */
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200951 if (fbc->active &&
952 intel_fbc_reg_params_equal(&old_params, &fbc->params))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200953 return;
954
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200955 intel_fbc_deactivate(dev_priv);
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300956 intel_fbc_schedule_activation(crtc);
Paulo Zanoni212890c2016-01-19 11:35:43 -0200957 fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300958}
959
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200960void intel_fbc_post_update(struct intel_crtc *crtc)
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300961{
Chris Wilsonfac5e232016-07-04 11:34:36 +0100962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200963 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanoni754d1132015-10-13 19:13:25 -0300964
Paulo Zanoni9f218332015-09-23 12:52:27 -0300965 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -0300966 return;
967
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200968 mutex_lock(&fbc->lock);
Paulo Zanoni1eb52232016-01-19 11:35:44 -0200969 __intel_fbc_post_update(crtc);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200970 mutex_unlock(&fbc->lock);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -0200971}
972
Paulo Zanoni261fe992016-01-19 11:35:40 -0200973static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
974{
975 if (fbc->enabled)
976 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
977 else
978 return fbc->possible_framebuffer_bits;
979}
980
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200981void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
982 unsigned int frontbuffer_bits,
983 enum fb_op_origin origin)
984{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200985 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200986
Paulo Zanoni9f218332015-09-23 12:52:27 -0300987 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -0300988 return;
989
Paulo Zanoni0dd81542016-01-19 11:35:39 -0200990 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200991 return;
992
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200993 mutex_lock(&fbc->lock);
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300994
Paulo Zanoni261fe992016-01-19 11:35:40 -0200995 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200996
Paulo Zanoni5bc40472016-01-19 11:35:53 -0200997 if (fbc->enabled && fbc->busy_bits)
Paulo Zanoni60eb2cc2016-01-19 11:35:45 -0200998 intel_fbc_deactivate(dev_priv);
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300999
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001000 mutex_unlock(&fbc->lock);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001001}
1002
1003void intel_fbc_flush(struct drm_i915_private *dev_priv,
Paulo Zanoni6f4551f2015-07-14 16:29:10 -03001004 unsigned int frontbuffer_bits, enum fb_op_origin origin)
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001005{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001006 struct intel_fbc *fbc = &dev_priv->fbc;
1007
Paulo Zanoni9f218332015-09-23 12:52:27 -03001008 if (!fbc_supported(dev_priv))
Paulo Zanoni0bf73c32015-07-03 15:40:54 -03001009 return;
1010
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001011 mutex_lock(&fbc->lock);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001012
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001013 fbc->busy_bits &= ~frontbuffer_bits;
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001014
Paulo Zanoniab28a542016-04-04 18:17:15 -03001015 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1016 goto out;
1017
Paulo Zanoni261fe992016-01-19 11:35:40 -02001018 if (!fbc->busy_bits && fbc->enabled &&
1019 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
Paulo Zanoni0dd81542016-01-19 11:35:39 -02001020 if (fbc->active)
Paulo Zanoniee7d6cfa2015-11-11 14:46:22 -02001021 intel_fbc_recompress(dev_priv);
Paulo Zanoni0dd81542016-01-19 11:35:39 -02001022 else
Paulo Zanoni1eb52232016-01-19 11:35:44 -02001023 __intel_fbc_post_update(fbc->crtc);
Paulo Zanoni6f4551f2015-07-14 16:29:10 -03001024 }
Paulo Zanoni25ad93f2015-07-02 19:25:10 -03001025
Paulo Zanoniab28a542016-04-04 18:17:15 -03001026out:
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001027 mutex_unlock(&fbc->lock);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001028}
1029
Rodrigo Vivi94b83952014-12-08 06:46:31 -08001030/**
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001031 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1032 * @dev_priv: i915 device instance
1033 * @state: the atomic state structure
1034 *
1035 * This function looks at the proposed state for CRTCs and planes, then chooses
1036 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1037 * true.
1038 *
1039 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1040 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1041 */
1042void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1043 struct drm_atomic_state *state)
1044{
1045 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001046 struct drm_plane *plane;
1047 struct drm_plane_state *plane_state;
Paulo Zanoni4f8f2252016-11-11 14:57:39 -02001048 bool crtc_chosen = false;
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001049 int i;
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001050
1051 mutex_lock(&fbc->lock);
1052
Paulo Zanoni4f8f2252016-11-11 14:57:39 -02001053 /* Does this atomic commit involve the CRTC currently tied to FBC? */
1054 if (fbc->crtc &&
1055 !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001056 goto out;
1057
Paulo Zanoniee2be302016-11-11 14:57:37 -02001058 if (!intel_fbc_can_enable(dev_priv))
1059 goto out;
1060
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001061 /* Simply choose the first CRTC that is compatible and has a visible
1062 * plane. We could go for fancier schemes such as checking the plane
1063 * size, but this would just affect the few platforms that don't tie FBC
1064 * to pipe or plane A. */
1065 for_each_plane_in_state(state, plane, plane_state, i) {
1066 struct intel_plane_state *intel_plane_state =
1067 to_intel_plane_state(plane_state);
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001068 struct intel_crtc_state *intel_crtc_state;
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001069 struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001070
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001071 if (!intel_plane_state->base.visible)
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001072 continue;
1073
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001074 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1075 continue;
1076
1077 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
Paulo Zanoni03e39102016-11-11 14:57:35 -02001078 continue;
1079
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001080 intel_crtc_state = to_intel_crtc_state(
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001081 drm_atomic_get_existing_crtc_state(state, &crtc->base));
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001082
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001083 intel_crtc_state->enable_fbc = true;
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001084 crtc_chosen = true;
Paulo Zanoniba67fab2016-11-11 14:57:36 -02001085 break;
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001086 }
1087
Paulo Zanonif7e9b002016-11-11 14:57:38 -02001088 if (!crtc_chosen)
1089 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1090
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001091out:
1092 mutex_unlock(&fbc->lock);
1093}
1094
1095/**
Paulo Zanonid029bca2015-10-15 10:44:46 -03001096 * intel_fbc_enable: tries to enable FBC on the CRTC
1097 * @crtc: the CRTC
Daniel Vetter62f90b32016-07-15 21:48:07 +02001098 * @crtc_state: corresponding &drm_crtc_state for @crtc
1099 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
Paulo Zanonid029bca2015-10-15 10:44:46 -03001100 *
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001101 * This function checks if the given CRTC was chosen for FBC, then enables it if
Paulo Zanoni49227c42016-01-19 11:35:52 -02001102 * possible. Notice that it doesn't activate FBC. It is valid to call
1103 * intel_fbc_enable multiple times for the same pipe without an
1104 * intel_fbc_disable in the middle, as long as it is deactivated.
Paulo Zanonid029bca2015-10-15 10:44:46 -03001105 */
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001106void intel_fbc_enable(struct intel_crtc *crtc,
1107 struct intel_crtc_state *crtc_state,
1108 struct intel_plane_state *plane_state)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001109{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001110 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001111 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001112
1113 if (!fbc_supported(dev_priv))
1114 return;
1115
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001116 mutex_lock(&fbc->lock);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001117
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001118 if (fbc->enabled) {
Paulo Zanoni49227c42016-01-19 11:35:52 -02001119 WARN_ON(fbc->crtc == NULL);
1120 if (fbc->crtc == crtc) {
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001121 WARN_ON(!crtc_state->enable_fbc);
Paulo Zanoni49227c42016-01-19 11:35:52 -02001122 WARN_ON(fbc->active);
1123 }
Paulo Zanonid029bca2015-10-15 10:44:46 -03001124 goto out;
1125 }
1126
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001127 if (!crtc_state->enable_fbc)
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001128 goto out;
1129
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001130 WARN_ON(fbc->active);
1131 WARN_ON(fbc->crtc != NULL);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001132
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001133 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
Paulo Zanonic5ecd462015-10-15 14:19:21 -03001134 if (intel_fbc_alloc_cfb(crtc)) {
Paulo Zanoni913a3a62016-01-19 11:35:54 -02001135 fbc->no_fbc_reason = "not enough stolen memory";
Paulo Zanonic5ecd462015-10-15 14:19:21 -03001136 goto out;
1137 }
1138
Paulo Zanonid029bca2015-10-15 10:44:46 -03001139 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001140 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
Paulo Zanonid029bca2015-10-15 10:44:46 -03001141
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001142 fbc->enabled = true;
1143 fbc->crtc = crtc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001144out:
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001145 mutex_unlock(&fbc->lock);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001146}
1147
1148/**
1149 * __intel_fbc_disable - disable FBC
1150 * @dev_priv: i915 device instance
1151 *
1152 * This is the low level function that actually disables FBC. Callers should
1153 * grab the FBC lock.
1154 */
1155static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1156{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001157 struct intel_fbc *fbc = &dev_priv->fbc;
1158 struct intel_crtc *crtc = fbc->crtc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001159
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001160 WARN_ON(!mutex_is_locked(&fbc->lock));
1161 WARN_ON(!fbc->enabled);
1162 WARN_ON(fbc->active);
Paulo Zanoni58f9c0b2016-01-19 11:35:51 -02001163 WARN_ON(crtc->active);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001164
1165 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1166
Paulo Zanonic5ecd462015-10-15 14:19:21 -03001167 __intel_fbc_cleanup_cfb(dev_priv);
1168
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001169 fbc->enabled = false;
1170 fbc->crtc = NULL;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001171}
1172
1173/**
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001174 * intel_fbc_disable - disable FBC if it's associated with crtc
Paulo Zanonid029bca2015-10-15 10:44:46 -03001175 * @crtc: the CRTC
1176 *
1177 * This function disables FBC if it's associated with the provided CRTC.
1178 */
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001179void intel_fbc_disable(struct intel_crtc *crtc)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001180{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001181 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001182 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonid029bca2015-10-15 10:44:46 -03001183
1184 if (!fbc_supported(dev_priv))
1185 return;
1186
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001187 mutex_lock(&fbc->lock);
Matthew Auld4da45612016-07-05 10:28:34 +01001188 if (fbc->crtc == crtc)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001189 __intel_fbc_disable(dev_priv);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001190 mutex_unlock(&fbc->lock);
Paulo Zanoni65c76002016-01-19 11:35:47 -02001191
1192 cancel_work_sync(&fbc->work.work);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001193}
1194
1195/**
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001196 * intel_fbc_global_disable - globally disable FBC
Paulo Zanonid029bca2015-10-15 10:44:46 -03001197 * @dev_priv: i915 device instance
1198 *
1199 * This function disables FBC regardless of which CRTC is associated with it.
1200 */
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001201void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001202{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001203 struct intel_fbc *fbc = &dev_priv->fbc;
1204
Paulo Zanonid029bca2015-10-15 10:44:46 -03001205 if (!fbc_supported(dev_priv))
1206 return;
1207
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001208 mutex_lock(&fbc->lock);
1209 if (fbc->enabled)
Paulo Zanonid029bca2015-10-15 10:44:46 -03001210 __intel_fbc_disable(dev_priv);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001211 mutex_unlock(&fbc->lock);
Paulo Zanoni65c76002016-01-19 11:35:47 -02001212
1213 cancel_work_sync(&fbc->work.work);
Paulo Zanonid029bca2015-10-15 10:44:46 -03001214}
1215
Paulo Zanoni61a585d2016-09-13 10:38:57 -03001216static void intel_fbc_underrun_work_fn(struct work_struct *work)
1217{
1218 struct drm_i915_private *dev_priv =
1219 container_of(work, struct drm_i915_private, fbc.underrun_work);
1220 struct intel_fbc *fbc = &dev_priv->fbc;
1221
1222 mutex_lock(&fbc->lock);
1223
1224 /* Maybe we were scheduled twice. */
1225 if (fbc->underrun_detected)
1226 goto out;
1227
1228 DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1229 fbc->underrun_detected = true;
1230
1231 intel_fbc_deactivate(dev_priv);
1232out:
1233 mutex_unlock(&fbc->lock);
1234}
1235
1236/**
1237 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1238 * @dev_priv: i915 device instance
1239 *
1240 * Without FBC, most underruns are harmless and don't really cause too many
1241 * problems, except for an annoying message on dmesg. With FBC, underruns can
1242 * become black screens or even worse, especially when paired with bad
1243 * watermarks. So in order for us to be on the safe side, completely disable FBC
1244 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1245 * already suggests that watermarks may be bad, so try to be as safe as
1246 * possible.
1247 *
1248 * This function is called from the IRQ handler.
1249 */
1250void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1251{
1252 struct intel_fbc *fbc = &dev_priv->fbc;
1253
1254 if (!fbc_supported(dev_priv))
1255 return;
1256
1257 /* There's no guarantee that underrun_detected won't be set to true
1258 * right after this check and before the work is scheduled, but that's
1259 * not a problem since we'll check it again under the work function
1260 * while FBC is locked. This check here is just to prevent us from
1261 * unnecessarily scheduling the work, and it relies on the fact that we
1262 * never switch underrun_detect back to false after it's true. */
1263 if (READ_ONCE(fbc->underrun_detected))
1264 return;
1265
1266 schedule_work(&fbc->underrun_work);
1267}
1268
Paulo Zanonid029bca2015-10-15 10:44:46 -03001269/**
Paulo Zanoni010cf732016-01-19 11:35:48 -02001270 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1271 * @dev_priv: i915 device instance
1272 *
1273 * The FBC code needs to track CRTC visibility since the older platforms can't
1274 * have FBC enabled while multiple pipes are used. This function does the
1275 * initial setup at driver load to make sure FBC is matching the real hardware.
1276 */
1277void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1278{
1279 struct intel_crtc *crtc;
1280
1281 /* Don't even bother tracking anything if we don't need. */
1282 if (!no_fbc_on_multiple_pipes(dev_priv))
1283 return;
1284
Chris Wilson91c8a322016-07-05 10:40:23 +01001285 for_each_intel_crtc(&dev_priv->drm, crtc)
Ville Syrjälä525b9312016-10-31 22:37:02 +02001286 if (intel_crtc_active(crtc) &&
Ville Syrjälä936e71e2016-07-26 19:06:59 +03001287 to_intel_plane_state(crtc->base.primary->state)->base.visible)
Paulo Zanoni010cf732016-01-19 11:35:48 -02001288 dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1289}
1290
Paulo Zanoni80788a02016-04-13 16:01:09 -03001291/*
1292 * The DDX driver changes its behavior depending on the value it reads from
1293 * i915.enable_fbc, so sanitize it by translating the default value into either
1294 * 0 or 1 in order to allow it to know what's going on.
1295 *
1296 * Notice that this is done at driver initialization and we still allow user
1297 * space to change the value during runtime without sanitizing it again. IGT
1298 * relies on being able to change i915.enable_fbc at runtime.
1299 */
1300static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1301{
1302 if (i915.enable_fbc >= 0)
1303 return !!i915.enable_fbc;
1304
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001305 if (!HAS_FBC(dev_priv))
1306 return 0;
1307
Paulo Zanoni80788a02016-04-13 16:01:09 -03001308 if (IS_BROADWELL(dev_priv))
1309 return 1;
1310
1311 return 0;
1312}
1313
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001314static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1315{
1316#ifdef CONFIG_INTEL_IOMMU
1317 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1318 if (intel_iommu_gfx_mapped &&
1319 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1320 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1321 return true;
1322 }
1323#endif
1324
1325 return false;
1326}
1327
Paulo Zanoni010cf732016-01-19 11:35:48 -02001328/**
Rodrigo Vivi94b83952014-12-08 06:46:31 -08001329 * intel_fbc_init - Initialize FBC
1330 * @dev_priv: the i915 device
1331 *
1332 * This function might be called during PM init process.
1333 */
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001334void intel_fbc_init(struct drm_i915_private *dev_priv)
1335{
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001336 struct intel_fbc *fbc = &dev_priv->fbc;
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001337 enum pipe pipe;
1338
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001339 INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
Paulo Zanoni61a585d2016-09-13 10:38:57 -03001340 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001341 mutex_init(&fbc->lock);
1342 fbc->enabled = false;
1343 fbc->active = false;
1344 fbc->work.scheduled = false;
Paulo Zanoni25ad93f2015-07-02 19:25:10 -03001345
Chris Wilson36dbc4d2016-08-04 08:43:53 +01001346 if (need_fbc_vtd_wa(dev_priv))
1347 mkwrite_device_info(dev_priv)->has_fbc = false;
1348
Paulo Zanoni80788a02016-04-13 16:01:09 -03001349 i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1350 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1351
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001352 if (!HAS_FBC(dev_priv)) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001353 fbc->no_fbc_reason = "unsupported by this chipset";
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001354 return;
1355 }
1356
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001357 for_each_pipe(dev_priv, pipe) {
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001358 fbc->possible_framebuffer_bits |=
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001359 INTEL_FRONTBUFFER_PRIMARY(pipe);
1360
Paulo Zanoni57105022015-11-04 17:10:46 -02001361 if (fbc_on_pipe_a_only(dev_priv))
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001362 break;
1363 }
1364
Paulo Zanoni8c400742016-01-29 18:57:39 -02001365 /* This value was pulled out of someone's hat */
Paulo Zanoni5697d602016-11-11 14:57:41 -02001366 if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001367 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001368
Paulo Zanonib07ea0f2015-11-04 17:10:52 -02001369 /* We still don't have any sort of hardware state readout for FBC, so
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03001370 * deactivate it in case the BIOS activated it to make sure software
1371 * matches the hardware state. */
Paulo Zanoni8c400742016-01-29 18:57:39 -02001372 if (intel_fbc_hw_is_active(dev_priv))
1373 intel_fbc_hw_deactivate(dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001374}