blob: d5a6dd9084a81f3c230e7f4ae58bd45be7c1973f [file] [log] [blame]
Mischa Jonkera92a5d02013-04-18 11:40:39 +02001/*
2 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "skeleton.dtsi"
11
12/ {
13 compatible = "snps,nsimosci";
Mischa Jonker6eda4772013-05-16 19:36:08 +020014 clock-frequency = <20000000>; /* 20 MHZ */
Mischa Jonkera92a5d02013-04-18 11:40:39 +020015 #address-cells = <1>;
16 #size-cells = <1>;
Vineet Gupta9ba76482016-01-28 09:57:12 +053017 interrupt-parent = <&core_intc>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020018
19 chosen {
Vineet Gupta61fb4bf2014-04-05 15:30:22 +053020 /* this is for console on PGU */
21 /* bootargs = "console=tty0 consoleblank=0"; */
22 /* this is for console on serial */
Vineet Guptae8ef0602014-10-01 14:28:36 +053023 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug";
Mischa Jonkera92a5d02013-04-18 11:40:39 +020024 };
25
26 aliases {
27 serial0 = &uart0;
28 };
29
Mischa Jonkera92a5d02013-04-18 11:40:39 +020030 fpga {
31 compatible = "simple-bus";
32 #address-cells = <1>;
33 #size-cells = <1>;
34
35 /* child and parent address space 1:1 mapped */
36 ranges;
37
Vineet Gupta9ba76482016-01-28 09:57:12 +053038 core_intc: interrupt-controller {
Mischa Jonkera92a5d02013-04-18 11:40:39 +020039 compatible = "snps,arc700-intc";
40 interrupt-controller;
41 #interrupt-cells = <1>;
42 };
43
Vineet Guptae8ef0602014-10-01 14:28:36 +053044 uart0: serial@f0000000 {
Mischa Jonker6eda4772013-05-16 19:36:08 +020045 compatible = "ns8250";
Vineet Guptae8ef0602014-10-01 14:28:36 +053046 reg = <0xf0000000 0x2000>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020047 interrupts = <11>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020048 clock-frequency = <3686400>;
49 baud = <115200>;
50 reg-shift = <2>;
51 reg-io-width = <4>;
Mischa Jonker6eda4772013-05-16 19:36:08 +020052 no-loopback-test = <1>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020053 };
54
Vineet Guptae8ef0602014-10-01 14:28:36 +053055 pgu0: pgu@f9000000 {
Mischa Jonkera92a5d02013-04-18 11:40:39 +020056 compatible = "snps,arcpgufb";
Vineet Guptae8ef0602014-10-01 14:28:36 +053057 reg = <0xf9000000 0x400>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020058 };
59
Vineet Guptae8ef0602014-10-01 14:28:36 +053060 ps2: ps2@f9001000 {
Mischa Jonkera92a5d02013-04-18 11:40:39 +020061 compatible = "snps,arc_ps2";
Vineet Guptae8ef0602014-10-01 14:28:36 +053062 reg = <0xf9000400 0x14>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020063 interrupts = <13>;
64 interrupt-names = "arc_ps2_irq";
65 };
66
Vineet Guptae8ef0602014-10-01 14:28:36 +053067 eth0: ethernet@f0003000 {
Lada Trimasovadf420fd2016-03-14 17:11:57 +030068 compatible = "ezchip,nps-mgt-enet";
Vineet Guptae8ef0602014-10-01 14:28:36 +053069 reg = <0xf0003000 0x44>;
Lada Trimasovadf420fd2016-03-14 17:11:57 +030070 interrupts = <7>;
Mischa Jonkera92a5d02013-04-18 11:40:39 +020071 };
72 };
73};