blob: 7add88ea0e2e275e54322f9fba8c0101c2fe354c [file] [log] [blame]
Kalle Valo5e3dd152013-06-12 20:52:10 +03001/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
Michal Kazioredb82362013-07-05 16:15:14 +030018#include "core.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030019#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
Kalle Valoa9bf0502013-09-03 11:43:55 +030023#include "trace.h"
Michal Kazioraa5b4fb2014-07-23 12:20:33 +020024#include "mac.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030025
26#include <linux/log2.h>
27
28/* slightly larger than one large A-MPDU */
29#define HTT_RX_RING_SIZE_MIN 128
30
31/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
32#define HTT_RX_RING_SIZE_MAX 2048
33
34#define HTT_RX_AVG_FRM_BYTES 1000
35
36/* ms, very conservative */
37#define HTT_RX_HOST_LATENCY_MAX_MS 20
38
39/* ms, conservative */
40#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
41
42/* when under memory pressure rx ring refill may fail and needs a retry */
43#define HTT_RX_RING_REFILL_RETRY_MS 50
44
Michal Kaziorf6dc2092013-09-26 10:12:22 +030045static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
Michal Kazior6c5151a2014-02-27 18:50:04 +020046static void ath10k_htt_txrx_compl_task(unsigned long ptr);
Michal Kaziorf6dc2092013-09-26 10:12:22 +030047
Kalle Valo5e3dd152013-06-12 20:52:10 +030048static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
Kalle Valo8cc7f262014-09-14 12:50:39 +0300135 idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
Kalle Valo8cc7f262014-09-14 12:50:39 +0300173 *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
Michal Kazior6e712d42013-09-24 10:18:36 +0200185 int ret, num_deficit, num_to_fill;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300186
Michal Kazior6e712d42013-09-24 10:18:36 +0200187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300202 spin_lock_bh(&htt->rx_ring.lock);
Michal Kazior6e712d42013-09-24 10:18:36 +0200203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
Michal Kazior6e712d42013-09-24 10:18:36 +0200216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
Kalle Valoaf762c02014-09-14 12:50:17 +0300225
Kalle Valo5e3dd152013-06-12 20:52:10 +0300226 ath10k_htt_rx_msdu_buff_replenish(htt);
227}
228
Michal Kazior3e841fd2014-05-14 16:23:31 +0300229static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt)
230{
231 struct sk_buff *skb;
232 int i;
233
234 for (i = 0; i < htt->rx_ring.size; i++) {
235 skb = htt->rx_ring.netbufs_ring[i];
236 if (!skb)
237 continue;
238
239 dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr,
240 skb->len + skb_tailroom(skb),
241 DMA_FROM_DEVICE);
242 dev_kfree_skb_any(skb);
243 htt->rx_ring.netbufs_ring[i] = NULL;
244 }
245}
246
Michal Kazior95bf21f2014-05-16 17:15:39 +0300247void ath10k_htt_rx_free(struct ath10k_htt *htt)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300248{
Kalle Valo5e3dd152013-06-12 20:52:10 +0300249 del_timer_sync(&htt->rx_ring.refill_retry_timer);
Michal Kazior6e712d42013-09-24 10:18:36 +0200250 tasklet_kill(&htt->rx_replenish_task);
Michal Kazior6c5151a2014-02-27 18:50:04 +0200251 tasklet_kill(&htt->txrx_compl_task);
252
253 skb_queue_purge(&htt->tx_compl_q);
254 skb_queue_purge(&htt->rx_compl_q);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300255
Michal Kazior3e841fd2014-05-14 16:23:31 +0300256 ath10k_htt_rx_ring_clean_up(htt);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300257
258 dma_free_coherent(htt->ar->dev,
259 (htt->rx_ring.size *
260 sizeof(htt->rx_ring.paddrs_ring)),
261 htt->rx_ring.paddrs_ring,
262 htt->rx_ring.base_paddr);
263
264 dma_free_coherent(htt->ar->dev,
265 sizeof(*htt->rx_ring.alloc_idx.vaddr),
266 htt->rx_ring.alloc_idx.vaddr,
267 htt->rx_ring.alloc_idx.paddr);
268
269 kfree(htt->rx_ring.netbufs_ring);
270}
271
272static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
273{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200274 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300275 int idx;
276 struct sk_buff *msdu;
277
Michal Kazior45967082014-02-27 18:50:05 +0200278 lockdep_assert_held(&htt->rx_ring.lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300279
Michal Kazior8d60ee82014-02-27 18:50:05 +0200280 if (htt->rx_ring.fill_cnt == 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200281 ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n");
Michal Kazior8d60ee82014-02-27 18:50:05 +0200282 return NULL;
283 }
Kalle Valo5e3dd152013-06-12 20:52:10 +0300284
285 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
286 msdu = htt->rx_ring.netbufs_ring[idx];
Michal Kazior3e841fd2014-05-14 16:23:31 +0300287 htt->rx_ring.netbufs_ring[idx] = NULL;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300288
289 idx++;
290 idx &= htt->rx_ring.size_mask;
291 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
292 htt->rx_ring.fill_cnt--;
293
Kalle Valo5e3dd152013-06-12 20:52:10 +0300294 return msdu;
295}
296
297static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
298{
299 struct sk_buff *next;
300
301 while (skb) {
302 next = skb->next;
303 dev_kfree_skb_any(skb);
304 skb = next;
305 }
306}
307
Janusz Dziedzicd84dd602014-03-24 21:23:20 +0100308/* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300309static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
310 u8 **fw_desc, int *fw_desc_len,
311 struct sk_buff **head_msdu,
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +0300312 struct sk_buff **tail_msdu,
313 u32 *attention)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300314{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200315 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300316 int msdu_len, msdu_chaining = 0;
Kalle Valoaf762c02014-09-14 12:50:17 +0300317 struct sk_buff *msdu, *next;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300318 struct htt_rx_desc *rx_desc;
Rajkumar Manoharana0883cf2014-10-03 08:02:47 +0300319 u32 tsf;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300320
Michal Kazior45967082014-02-27 18:50:05 +0200321 lockdep_assert_held(&htt->rx_ring.lock);
322
Kalle Valo5e3dd152013-06-12 20:52:10 +0300323 if (htt->rx_confused) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200324 ath10k_warn(ar, "htt is confused. refusing rx\n");
Janusz Dziedzicd84dd602014-03-24 21:23:20 +0100325 return -1;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300326 }
327
328 msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
329 while (msdu) {
330 int last_msdu, msdu_len_invalid, msdu_chained;
331
332 dma_unmap_single(htt->ar->dev,
333 ATH10K_SKB_CB(msdu)->paddr,
334 msdu->len + skb_tailroom(msdu),
335 DMA_FROM_DEVICE);
336
Michal Kazior7aa7a722014-08-25 12:09:38 +0200337 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +0300338 msdu->data, msdu->len + skb_tailroom(msdu));
339
340 rx_desc = (struct htt_rx_desc *)msdu->data;
341
342 /* FIXME: we must report msdu payload since this is what caller
343 * expects now */
344 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
345 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
346
347 /*
348 * Sanity check - confirm the HW is finished filling in the
349 * rx data.
350 * If the HW and SW are working correctly, then it's guaranteed
351 * that the HW's MAC DMA is done before this point in the SW.
352 * To prevent the case that we handle a stale Rx descriptor,
353 * just assert for now until we have a way to recover.
354 */
355 if (!(__le32_to_cpu(rx_desc->attention.flags)
356 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
357 ath10k_htt_rx_free_msdu_chain(*head_msdu);
358 *head_msdu = NULL;
359 msdu = NULL;
Michal Kazior7aa7a722014-08-25 12:09:38 +0200360 ath10k_err(ar, "htt rx stopped. cannot recover\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +0300361 htt->rx_confused = true;
362 break;
363 }
364
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +0300365 *attention |= __le32_to_cpu(rx_desc->attention.flags) &
366 (RX_ATTENTION_FLAGS_TKIP_MIC_ERR |
367 RX_ATTENTION_FLAGS_DECRYPT_ERR |
368 RX_ATTENTION_FLAGS_FCS_ERR |
369 RX_ATTENTION_FLAGS_MGMT_TYPE);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300370 /*
371 * Copy the FW rx descriptor for this MSDU from the rx
372 * indication message into the MSDU's netbuf. HL uses the
373 * same rx indication message definition as LL, and simply
374 * appends new info (fields from the HW rx desc, and the
375 * MSDU payload itself). So, the offset into the rx
376 * indication message only has to account for the standard
377 * offset of the per-MSDU FW rx desc info within the
378 * message, and how many bytes of the per-MSDU FW rx desc
379 * info have already been consumed. (And the endianness of
380 * the host, since for a big-endian host, the rx ind
381 * message contents, including the per-MSDU rx desc bytes,
382 * were byteswapped during upload.)
383 */
384 if (*fw_desc_len > 0) {
385 rx_desc->fw_desc.info0 = **fw_desc;
386 /*
387 * The target is expected to only provide the basic
388 * per-MSDU rx descriptors. Just to be sure, verify
389 * that the target has not attached extension data
390 * (e.g. LRO flow ID).
391 */
392
393 /* or more, if there's extension data */
394 (*fw_desc)++;
395 (*fw_desc_len)--;
396 } else {
397 /*
398 * When an oversized AMSDU happened, FW will lost
399 * some of MSDU status - in this case, the FW
400 * descriptors provided will be less than the
401 * actual MSDUs inside this MPDU. Mark the FW
402 * descriptors so that it will still deliver to
403 * upper stack, if no CRC error for this MPDU.
404 *
405 * FIX THIS - the FW descriptors are actually for
406 * MSDUs in the end of this A-MSDU instead of the
407 * beginning.
408 */
409 rx_desc->fw_desc.info0 = 0;
410 }
411
412 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
413 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
414 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
415 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
416 RX_MSDU_START_INFO0_MSDU_LENGTH);
417 msdu_chained = rx_desc->frag_info.ring2_more_count;
418
419 if (msdu_len_invalid)
420 msdu_len = 0;
421
422 skb_trim(msdu, 0);
423 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
424 msdu_len -= msdu->len;
425
426 /* FIXME: Do chained buffers include htt_rx_desc or not? */
427 while (msdu_chained--) {
428 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
429
430 dma_unmap_single(htt->ar->dev,
431 ATH10K_SKB_CB(next)->paddr,
432 next->len + skb_tailroom(next),
433 DMA_FROM_DEVICE);
434
Michal Kazior7aa7a722014-08-25 12:09:38 +0200435 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL,
Ben Greear75fb2f92014-02-05 13:58:34 -0800436 "htt rx chained: ", next->data,
Kalle Valo5e3dd152013-06-12 20:52:10 +0300437 next->len + skb_tailroom(next));
438
439 skb_trim(next, 0);
440 skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
441 msdu_len -= next->len;
442
443 msdu->next = next;
444 msdu = next;
Michal Kaziorede9c8e2014-05-14 16:23:31 +0300445 msdu_chaining = 1;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300446 }
447
Kalle Valo5e3dd152013-06-12 20:52:10 +0300448 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
449 RX_MSDU_END_INFO0_LAST_MSDU;
450
Rajkumar Manoharana0883cf2014-10-03 08:02:47 +0300451 tsf = __le32_to_cpu(rx_desc->ppdu_end.tsf_timestamp);
452 trace_ath10k_htt_rx_desc(ar, tsf, &rx_desc->attention,
453 sizeof(*rx_desc) - sizeof(u32));
Kalle Valo5e3dd152013-06-12 20:52:10 +0300454 if (last_msdu) {
455 msdu->next = NULL;
456 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300457 }
Kalle Valod8bb26b2014-09-14 12:50:33 +0300458
459 next = ath10k_htt_rx_netbuf_pop(htt);
460 msdu->next = next;
461 msdu = next;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300462 }
463 *tail_msdu = msdu;
464
Janusz Dziedzicd84dd602014-03-24 21:23:20 +0100465 if (*head_msdu == NULL)
466 msdu_chaining = -1;
467
Kalle Valo5e3dd152013-06-12 20:52:10 +0300468 /*
469 * Don't refill the ring yet.
470 *
471 * First, the elements popped here are still in use - it is not
472 * safe to overwrite them until the matching call to
473 * mpdu_desc_list_next. Second, for efficiency it is preferable to
474 * refill the rx ring with 1 PPDU's worth of rx buffers (something
475 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
476 * (something like 3 buffers). Consequently, we'll rely on the txrx
477 * SW to tell us when it is done pulling all the PPDU's rx buffers
478 * out of the rx ring, and then refill it just once.
479 */
480
481 return msdu_chaining;
482}
483
Michal Kazior6e712d42013-09-24 10:18:36 +0200484static void ath10k_htt_rx_replenish_task(unsigned long ptr)
485{
486 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
Kalle Valoaf762c02014-09-14 12:50:17 +0300487
Michal Kazior6e712d42013-09-24 10:18:36 +0200488 ath10k_htt_rx_msdu_buff_replenish(htt);
489}
490
Michal Kazior95bf21f2014-05-16 17:15:39 +0300491int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300492{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200493 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300494 dma_addr_t paddr;
495 void *vaddr;
Kalle Valobd8bdbb2014-09-14 12:50:00 +0300496 size_t size;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300497 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
498
499 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
500 if (!is_power_of_2(htt->rx_ring.size)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200501 ath10k_warn(ar, "htt rx ring size is not power of 2\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +0300502 return -EINVAL;
503 }
504
505 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
506
507 /*
508 * Set the initial value for the level to which the rx ring
509 * should be filled, based on the max throughput and the
510 * worst likely latency for the host to fill the rx ring
511 * with new buffers. In theory, this fill level can be
512 * dynamically adjusted from the initial value set here, to
513 * reflect the actual host latency rather than a
514 * conservative assumption about the host latency.
515 */
516 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
517
518 htt->rx_ring.netbufs_ring =
Michal Kazior3e841fd2014-05-14 16:23:31 +0300519 kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
Kalle Valo5e3dd152013-06-12 20:52:10 +0300520 GFP_KERNEL);
521 if (!htt->rx_ring.netbufs_ring)
522 goto err_netbuf;
523
Kalle Valobd8bdbb2014-09-14 12:50:00 +0300524 size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring);
525
526 vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300527 if (!vaddr)
528 goto err_dma_ring;
529
530 htt->rx_ring.paddrs_ring = vaddr;
531 htt->rx_ring.base_paddr = paddr;
532
533 vaddr = dma_alloc_coherent(htt->ar->dev,
534 sizeof(*htt->rx_ring.alloc_idx.vaddr),
535 &paddr, GFP_DMA);
536 if (!vaddr)
537 goto err_dma_idx;
538
539 htt->rx_ring.alloc_idx.vaddr = vaddr;
540 htt->rx_ring.alloc_idx.paddr = paddr;
541 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
542 *htt->rx_ring.alloc_idx.vaddr = 0;
543
544 /* Initialize the Rx refill retry timer */
545 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
546
547 spin_lock_init(&htt->rx_ring.lock);
548
549 htt->rx_ring.fill_cnt = 0;
550 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
551 goto err_fill_ring;
552
Michal Kazior6e712d42013-09-24 10:18:36 +0200553 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
554 (unsigned long)htt);
555
Michal Kazior6c5151a2014-02-27 18:50:04 +0200556 skb_queue_head_init(&htt->tx_compl_q);
557 skb_queue_head_init(&htt->rx_compl_q);
558
559 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
560 (unsigned long)htt);
561
Michal Kazior7aa7a722014-08-25 12:09:38 +0200562 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +0300563 htt->rx_ring.size, htt->rx_ring.fill_level);
564 return 0;
565
566err_fill_ring:
567 ath10k_htt_rx_ring_free(htt);
568 dma_free_coherent(htt->ar->dev,
569 sizeof(*htt->rx_ring.alloc_idx.vaddr),
570 htt->rx_ring.alloc_idx.vaddr,
571 htt->rx_ring.alloc_idx.paddr);
572err_dma_idx:
573 dma_free_coherent(htt->ar->dev,
574 (htt->rx_ring.size *
575 sizeof(htt->rx_ring.paddrs_ring)),
576 htt->rx_ring.paddrs_ring,
577 htt->rx_ring.base_paddr);
578err_dma_ring:
579 kfree(htt->rx_ring.netbufs_ring);
580err_netbuf:
581 return -ENOMEM;
582}
583
Michal Kazior7aa7a722014-08-25 12:09:38 +0200584static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar,
585 enum htt_rx_mpdu_encrypt_type type)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300586{
587 switch (type) {
588 case HTT_RX_MPDU_ENCRYPT_WEP40:
589 case HTT_RX_MPDU_ENCRYPT_WEP104:
590 return 4;
591 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
592 case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */
593 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
594 case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */
595 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
596 return 8;
597 case HTT_RX_MPDU_ENCRYPT_NONE:
598 return 0;
599 }
600
Michal Kazior7aa7a722014-08-25 12:09:38 +0200601 ath10k_warn(ar, "unknown encryption type %d\n", type);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300602 return 0;
603}
604
Michal Kazior7aa7a722014-08-25 12:09:38 +0200605static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar,
606 enum htt_rx_mpdu_encrypt_type type)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300607{
608 switch (type) {
609 case HTT_RX_MPDU_ENCRYPT_NONE:
610 case HTT_RX_MPDU_ENCRYPT_WEP40:
611 case HTT_RX_MPDU_ENCRYPT_WEP104:
612 case HTT_RX_MPDU_ENCRYPT_WEP128:
613 case HTT_RX_MPDU_ENCRYPT_WAPI:
614 return 0;
615 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
616 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
617 return 4;
618 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
619 return 8;
620 }
621
Michal Kazior7aa7a722014-08-25 12:09:38 +0200622 ath10k_warn(ar, "unknown encryption type %d\n", type);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300623 return 0;
624}
625
626/* Applies for first msdu in chain, before altering it. */
627static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
628{
629 struct htt_rx_desc *rxd;
630 enum rx_msdu_decap_format fmt;
631
632 rxd = (void *)skb->data - sizeof(*rxd);
633 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Kalle Valo5b07e072014-09-14 12:50:06 +0300634 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300635
636 if (fmt == RX_MSDU_DECAP_RAW)
637 return (void *)skb->data;
Kalle Valod8bb26b2014-09-14 12:50:33 +0300638
639 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300640}
641
642/* This function only applies for first msdu in an msdu chain */
643static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
644{
Kalle Valoaf762c02014-09-14 12:50:17 +0300645 u8 *qc;
646
Kalle Valo5e3dd152013-06-12 20:52:10 +0300647 if (ieee80211_is_data_qos(hdr->frame_control)) {
Kalle Valoaf762c02014-09-14 12:50:17 +0300648 qc = ieee80211_get_qos_ctl(hdr);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300649 if (qc[0] & 0x80)
650 return true;
651 }
652 return false;
653}
654
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300655struct rfc1042_hdr {
656 u8 llc_dsap;
657 u8 llc_ssap;
658 u8 llc_ctrl;
659 u8 snap_oui[3];
660 __be16 snap_type;
661} __packed;
662
663struct amsdu_subframe_hdr {
664 u8 dst[ETH_ALEN];
665 u8 src[ETH_ALEN];
666 __be16 len;
667} __packed;
668
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100669static const u8 rx_legacy_rate_idx[] = {
670 3, /* 0x00 - 11Mbps */
671 2, /* 0x01 - 5.5Mbps */
672 1, /* 0x02 - 2Mbps */
673 0, /* 0x03 - 1Mbps */
674 3, /* 0x04 - 11Mbps */
675 2, /* 0x05 - 5.5Mbps */
676 1, /* 0x06 - 2Mbps */
677 0, /* 0x07 - 1Mbps */
678 10, /* 0x08 - 48Mbps */
679 8, /* 0x09 - 24Mbps */
680 6, /* 0x0A - 12Mbps */
681 4, /* 0x0B - 6Mbps */
682 11, /* 0x0C - 54Mbps */
683 9, /* 0x0D - 36Mbps */
684 7, /* 0x0E - 18Mbps */
685 5, /* 0x0F - 9Mbps */
686};
687
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100688static void ath10k_htt_rx_h_rates(struct ath10k *ar,
Janusz Dziedziccfadd9b2014-03-24 21:23:16 +0100689 enum ieee80211_band band,
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100690 u8 info0, u32 info1, u32 info2,
Janusz Dziedziccfadd9b2014-03-24 21:23:16 +0100691 struct ieee80211_rx_status *status)
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100692{
693 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100694 u8 preamble = 0;
695
696 /* Check if valid fields */
697 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
698 return;
699
700 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
701
702 switch (preamble) {
703 case HTT_RX_LEGACY:
704 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
705 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
706 rate_idx = 0;
707
708 if (rate < 0x08 || rate > 0x0F)
709 break;
710
711 switch (band) {
712 case IEEE80211_BAND_2GHZ:
713 if (cck)
714 rate &= ~BIT(3);
715 rate_idx = rx_legacy_rate_idx[rate];
716 break;
717 case IEEE80211_BAND_5GHZ:
718 rate_idx = rx_legacy_rate_idx[rate];
719 /* We are using same rate table registering
720 HW - ath10k_rates[]. In case of 5GHz skip
721 CCK rates, so -4 here */
722 rate_idx -= 4;
723 break;
724 default:
725 break;
726 }
727
728 status->rate_idx = rate_idx;
729 break;
730 case HTT_RX_HT:
731 case HTT_RX_HT_WITH_TXBF:
732 /* HT-SIG - Table 20-11 in info1 and info2 */
733 mcs = info1 & 0x1F;
734 nss = mcs >> 3;
735 bw = (info1 >> 7) & 1;
736 sgi = (info2 >> 7) & 1;
737
738 status->rate_idx = mcs;
739 status->flag |= RX_FLAG_HT;
740 if (sgi)
741 status->flag |= RX_FLAG_SHORT_GI;
742 if (bw)
743 status->flag |= RX_FLAG_40MHZ;
744 break;
745 case HTT_RX_VHT:
746 case HTT_RX_VHT_WITH_TXBF:
747 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
748 TODO check this */
749 mcs = (info2 >> 4) & 0x0F;
750 nss = ((info1 >> 10) & 0x07) + 1;
751 bw = info1 & 3;
752 sgi = info2 & 1;
753
754 status->rate_idx = mcs;
755 status->vht_nss = nss;
756
757 if (sgi)
758 status->flag |= RX_FLAG_SHORT_GI;
759
760 switch (bw) {
761 /* 20MHZ */
762 case 0:
763 break;
764 /* 40MHZ */
765 case 1:
766 status->flag |= RX_FLAG_40MHZ;
767 break;
768 /* 80MHZ */
769 case 2:
770 status->vht_flag |= RX_VHT_FLAG_80MHZ;
771 }
772
773 status->flag |= RX_FLAG_VHT;
774 break;
775 default:
776 break;
777 }
778}
779
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100780static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100781 struct ieee80211_rx_status *rx_status,
782 struct sk_buff *skb,
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300783 enum htt_rx_mpdu_encrypt_type enctype,
784 enum rx_msdu_decap_format fmt,
785 bool dot11frag)
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100786{
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100787 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100788
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300789 rx_status->flag &= ~(RX_FLAG_DECRYPTED |
790 RX_FLAG_IV_STRIPPED |
791 RX_FLAG_MMIC_STRIPPED);
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100792
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300793 if (enctype == HTT_RX_MPDU_ENCRYPT_NONE)
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100794 return;
Michal Kaziorc071dcb2014-05-23 11:33:18 +0300795
796 /*
797 * There's no explicit rx descriptor flag to indicate whether a given
798 * frame has been decrypted or not. We're forced to use the decap
799 * format as an implicit indication. However fragmentation rx is always
800 * raw and it probably never reports undecrypted raws.
801 *
802 * This makes sure sniffed frames are reported as-is without stripping
803 * the protected flag.
804 */
805 if (fmt == RX_MSDU_DECAP_RAW && !dot11frag)
806 return;
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100807
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100808 rx_status->flag |= RX_FLAG_DECRYPTED |
809 RX_FLAG_IV_STRIPPED |
810 RX_FLAG_MMIC_STRIPPED;
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100811 hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
812 ~IEEE80211_FCTL_PROTECTED);
813}
814
Janusz Dziedzic36653f02014-03-24 21:23:18 +0100815static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
816 struct ieee80211_rx_status *status)
817{
818 struct ieee80211_channel *ch;
819
820 spin_lock_bh(&ar->data_lock);
821 ch = ar->scan_channel;
822 if (!ch)
823 ch = ar->rx_channel;
824 spin_unlock_bh(&ar->data_lock);
825
826 if (!ch)
827 return false;
828
829 status->band = ch->band;
830 status->freq = ch->center_freq;
831
832 return true;
833}
834
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300835static const char * const tid_to_ac[] = {
836 "BE",
837 "BK",
838 "BK",
839 "BE",
840 "VI",
841 "VI",
842 "VO",
843 "VO",
844};
845
846static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size)
847{
848 u8 *qc;
849 int tid;
850
851 if (!ieee80211_is_data_qos(hdr->frame_control))
852 return "";
853
854 qc = ieee80211_get_qos_ctl(hdr);
855 tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
856 if (tid < 8)
857 snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]);
858 else
859 snprintf(out, size, "tid %d", tid);
860
861 return out;
862}
863
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100864static void ath10k_process_rx(struct ath10k *ar,
865 struct ieee80211_rx_status *rx_status,
866 struct sk_buff *skb)
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100867{
868 struct ieee80211_rx_status *status;
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300869 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
870 char tid[32];
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100871
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100872 status = IEEE80211_SKB_RXCB(skb);
873 *status = *rx_status;
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100874
Michal Kazior7aa7a722014-08-25 12:09:38 +0200875 ath10k_dbg(ar, ATH10K_DBG_DATA,
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300876 "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100877 skb,
878 skb->len,
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300879 ieee80211_get_SA(hdr),
880 ath10k_get_tid(hdr, tid, sizeof(tid)),
881 is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
882 "mcast" : "ucast",
883 (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100884 status->flag == 0 ? "legacy" : "",
885 status->flag & RX_FLAG_HT ? "ht" : "",
886 status->flag & RX_FLAG_VHT ? "vht" : "",
887 status->flag & RX_FLAG_40MHZ ? "40" : "",
888 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
889 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
890 status->rate_idx,
891 status->vht_nss,
892 status->freq,
Janusz Dziedzic87326c92014-03-24 21:23:19 +0100893 status->band, status->flag,
Janusz Dziedzic78433f92014-03-24 21:23:21 +0100894 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
Janusz Dziedzic76f53292014-07-28 23:59:43 +0300895 !!(status->flag & RX_FLAG_MMIC_ERROR),
896 !!(status->flag & RX_FLAG_AMSDU_MORE));
Michal Kazior7aa7a722014-08-25 12:09:38 +0200897 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100898 skb->data, skb->len);
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100899
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100900 ieee80211_rx(ar->hw, skb);
Janusz Dziedzic73539b42014-03-24 21:23:15 +0100901}
902
Michal Kaziord960c362014-02-25 09:29:57 +0200903static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
904{
905 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
906 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
907}
908
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300909static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100910 struct ieee80211_rx_status *rx_status,
911 struct sk_buff *skb_in)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300912{
Michal Kazior7aa7a722014-08-25 12:09:38 +0200913 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300914 struct htt_rx_desc *rxd;
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +0100915 struct sk_buff *skb = skb_in;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300916 struct sk_buff *first;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300917 enum rx_msdu_decap_format fmt;
918 enum htt_rx_mpdu_encrypt_type enctype;
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300919 struct ieee80211_hdr *hdr;
Michal Kazior72bdeb82014-07-28 23:59:42 +0300920 u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300921 unsigned int hdr_len;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300922
923 rxd = (void *)skb->data - sizeof(*rxd);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300924 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
Kalle Valo5b07e072014-09-14 12:50:06 +0300925 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300926
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300927 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
928 hdr_len = ieee80211_hdrlen(hdr->frame_control);
929 memcpy(hdr_buf, hdr, hdr_len);
930 hdr = (struct ieee80211_hdr *)hdr_buf;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300931
Kalle Valo5e3dd152013-06-12 20:52:10 +0300932 first = skb;
933 while (skb) {
934 void *decap_hdr;
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300935 int len;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300936
937 rxd = (void *)skb->data - sizeof(*rxd);
938 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300939 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300940 decap_hdr = (void *)rxd->rx_hdr_status;
941
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300942 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
943
944 /* First frame in an A-MSDU chain has more decapped data. */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300945 if (skb == first) {
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300946 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
Michal Kazior7aa7a722014-08-25 12:09:38 +0200947 len += round_up(ath10k_htt_rx_crypto_param_len(ar,
948 enctype), 4);
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300949 decap_hdr += len;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300950 }
951
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300952 switch (fmt) {
953 case RX_MSDU_DECAP_RAW:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +0300954 /* remove trailing FCS */
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300955 skb_trim(skb, skb->len - FCS_LEN);
956 break;
957 case RX_MSDU_DECAP_NATIVE_WIFI:
Michal Kazior72bdeb82014-07-28 23:59:42 +0300958 /* pull decapped header and copy SA & DA */
Michal Kazior784f69d2013-09-26 10:12:23 +0300959 hdr = (struct ieee80211_hdr *)skb->data;
Michal Kaziord960c362014-02-25 09:29:57 +0200960 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
Kalle Valob25f32c2014-09-14 12:50:49 +0300961 ether_addr_copy(da, ieee80211_get_DA(hdr));
962 ether_addr_copy(sa, ieee80211_get_SA(hdr));
Michal Kazior784f69d2013-09-26 10:12:23 +0300963 skb_pull(skb, hdr_len);
964
965 /* push original 802.11 header */
966 hdr = (struct ieee80211_hdr *)hdr_buf;
967 hdr_len = ieee80211_hdrlen(hdr->frame_control);
968 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
969
970 /* original A-MSDU header has the bit set but we're
971 * not including A-MSDU subframe header */
972 hdr = (struct ieee80211_hdr *)skb->data;
973 qos = ieee80211_get_qos_ctl(hdr);
974 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
975
Michal Kazior72bdeb82014-07-28 23:59:42 +0300976 /* original 802.11 header has a different DA and in
977 * case of 4addr it may also have different SA
978 */
Kalle Valob25f32c2014-09-14 12:50:49 +0300979 ether_addr_copy(ieee80211_get_DA(hdr), da);
980 ether_addr_copy(ieee80211_get_SA(hdr), sa);
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300981 break;
982 case RX_MSDU_DECAP_ETHERNET2_DIX:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +0300983 /* strip ethernet header and insert decapped 802.11
984 * header, amsdu subframe header and rfc1042 header */
985
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300986 len = 0;
987 len += sizeof(struct rfc1042_hdr);
988 len += sizeof(struct amsdu_subframe_hdr);
Michal Kaziordfa95b52013-08-13 07:59:37 +0200989
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300990 skb_pull(skb, sizeof(struct ethhdr));
991 memcpy(skb_push(skb, len), decap_hdr, len);
992 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
993 break;
994 case RX_MSDU_DECAP_8023_SNAP_LLC:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +0300995 /* insert decapped 802.11 header making a singly
996 * A-MSDU */
Michal Kaziorf6dc2092013-09-26 10:12:22 +0300997 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
998 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300999 }
1000
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001001 skb_in = skb;
Michal Kaziorc071dcb2014-05-23 11:33:18 +03001002 ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype, fmt,
1003 false);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001004 skb = skb->next;
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001005 skb_in->next = NULL;
Michal Kaziorf6dc2092013-09-26 10:12:22 +03001006
Kalle Valo652de352013-11-13 15:23:30 +02001007 if (skb)
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001008 rx_status->flag |= RX_FLAG_AMSDU_MORE;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001009 else
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001010 rx_status->flag &= ~RX_FLAG_AMSDU_MORE;
Kalle Valo652de352013-11-13 15:23:30 +02001011
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001012 ath10k_process_rx(htt->ar, rx_status, skb_in);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001013 }
1014
Michal Kaziorf6dc2092013-09-26 10:12:22 +03001015 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
1016 * monitor interface active for sniffing purposes. */
Kalle Valo5e3dd152013-06-12 20:52:10 +03001017}
1018
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001019static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
1020 struct ieee80211_rx_status *rx_status,
1021 struct sk_buff *skb)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001022{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001023 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001024 struct htt_rx_desc *rxd;
1025 struct ieee80211_hdr *hdr;
1026 enum rx_msdu_decap_format fmt;
1027 enum htt_rx_mpdu_encrypt_type enctype;
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001028 int hdr_len;
1029 void *rfc1042;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001030
1031 /* This shouldn't happen. If it does than it may be a FW bug. */
1032 if (skb->next) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001033 ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001034 ath10k_htt_rx_free_msdu_chain(skb->next);
1035 skb->next = NULL;
1036 }
1037
1038 rxd = (void *)skb->data - sizeof(*rxd);
1039 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Kalle Valo5b07e072014-09-14 12:50:06 +03001040 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001041 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
Kalle Valo5b07e072014-09-14 12:50:06 +03001042 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001043 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1044 hdr_len = ieee80211_hdrlen(hdr->frame_control);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001045
Michal Kaziorf6dc2092013-09-26 10:12:22 +03001046 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
1047
Kalle Valo5e3dd152013-06-12 20:52:10 +03001048 switch (fmt) {
1049 case RX_MSDU_DECAP_RAW:
1050 /* remove trailing FCS */
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001051 skb_trim(skb, skb->len - FCS_LEN);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001052 break;
1053 case RX_MSDU_DECAP_NATIVE_WIFI:
Michal Kazior784f69d2013-09-26 10:12:23 +03001054 /* Pull decapped header */
1055 hdr = (struct ieee80211_hdr *)skb->data;
Michal Kaziord960c362014-02-25 09:29:57 +02001056 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
Michal Kazior784f69d2013-09-26 10:12:23 +03001057 skb_pull(skb, hdr_len);
1058
1059 /* Push original header */
1060 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1061 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1062 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001063 break;
1064 case RX_MSDU_DECAP_ETHERNET2_DIX:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001065 /* strip ethernet header and insert decapped 802.11 header and
1066 * rfc1042 header */
1067
1068 rfc1042 = hdr;
1069 rfc1042 += roundup(hdr_len, 4);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001070 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar,
1071 enctype), 4);
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001072
1073 skb_pull(skb, sizeof(struct ethhdr));
1074 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
1075 rfc1042, sizeof(struct rfc1042_hdr));
1076 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001077 break;
1078 case RX_MSDU_DECAP_8023_SNAP_LLC:
Michal Kaziore3fbf8d2013-09-26 10:12:23 +03001079 /* remove A-MSDU subframe header and insert
1080 * decapped 802.11 header. rfc1042 header is already there */
1081
1082 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
1083 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001084 break;
1085 }
1086
Michal Kaziorc071dcb2014-05-23 11:33:18 +03001087 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false);
Michal Kaziorf6dc2092013-09-26 10:12:22 +03001088
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001089 ath10k_process_rx(htt->ar, rx_status, skb);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001090}
1091
Michal Kazior605f81a2013-07-31 10:47:56 +02001092static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1093{
1094 struct htt_rx_desc *rxd;
1095 u32 flags, info;
1096 bool is_ip4, is_ip6;
1097 bool is_tcp, is_udp;
1098 bool ip_csum_ok, tcpudp_csum_ok;
1099
1100 rxd = (void *)skb->data - sizeof(*rxd);
1101 flags = __le32_to_cpu(rxd->attention.flags);
1102 info = __le32_to_cpu(rxd->msdu_start.info1);
1103
1104 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1105 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1106 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1107 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1108 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1109 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1110
1111 if (!is_ip4 && !is_ip6)
1112 return CHECKSUM_NONE;
1113 if (!is_tcp && !is_udp)
1114 return CHECKSUM_NONE;
1115 if (!ip_csum_ok)
1116 return CHECKSUM_NONE;
1117 if (!tcpudp_csum_ok)
1118 return CHECKSUM_NONE;
1119
1120 return CHECKSUM_UNNECESSARY;
1121}
1122
Ben Greearbfa35362014-03-03 14:07:09 -08001123static int ath10k_unchain_msdu(struct sk_buff *msdu_head)
1124{
1125 struct sk_buff *next = msdu_head->next;
1126 struct sk_buff *to_free = next;
1127 int space;
1128 int total_len = 0;
1129
1130 /* TODO: Might could optimize this by using
1131 * skb_try_coalesce or similar method to
1132 * decrease copying, or maybe get mac80211 to
1133 * provide a way to just receive a list of
1134 * skb?
1135 */
1136
1137 msdu_head->next = NULL;
1138
1139 /* Allocate total length all at once. */
1140 while (next) {
1141 total_len += next->len;
1142 next = next->next;
1143 }
1144
1145 space = total_len - skb_tailroom(msdu_head);
1146 if ((space > 0) &&
1147 (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) {
1148 /* TODO: bump some rx-oom error stat */
1149 /* put it back together so we can free the
1150 * whole list at once.
1151 */
1152 msdu_head->next = to_free;
1153 return -1;
1154 }
1155
1156 /* Walk list again, copying contents into
1157 * msdu_head
1158 */
1159 next = to_free;
1160 while (next) {
1161 skb_copy_from_linear_data(next, skb_put(msdu_head, next->len),
1162 next->len);
1163 next = next->next;
1164 }
1165
1166 /* If here, we have consolidated skb. Free the
1167 * fragments and pass the main skb on up the
1168 * stack.
1169 */
1170 ath10k_htt_rx_free_msdu_chain(to_free);
1171 return 0;
1172}
1173
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001174static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1175 struct sk_buff *head,
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001176 enum htt_rx_mpdu_status status,
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001177 bool channel_set,
1178 u32 attention)
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001179{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001180 struct ath10k *ar = htt->ar;
1181
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001182 if (head->len == 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001183 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001184 "htt rx dropping due to zero-len\n");
1185 return false;
1186 }
1187
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001188 if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001189 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001190 "htt rx dropping due to decrypt-err\n");
1191 return false;
1192 }
1193
Janusz Dziedzic36653f02014-03-24 21:23:18 +01001194 if (!channel_set) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001195 ath10k_warn(ar, "no channel configured; ignoring frame!\n");
Janusz Dziedzic36653f02014-03-24 21:23:18 +01001196 return false;
1197 }
1198
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001199 /* Skip mgmt frames while we handle this in WMI */
1200 if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL ||
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001201 attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001202 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001203 return false;
1204 }
1205
1206 if (status != HTT_RX_IND_MPDU_STATUS_OK &&
1207 status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
1208 status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER &&
Michal Kazior1bbc0972014-04-08 09:45:47 +03001209 !htt->ar->monitor_started) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001210 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001211 "htt rx ignoring frame w/ status %d\n",
1212 status);
1213 return false;
1214 }
1215
1216 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001217 ath10k_dbg(ar, ATH10K_DBG_HTT,
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001218 "htt rx CAC running\n");
1219 return false;
1220 }
1221
1222 return true;
1223}
1224
Kalle Valo5e3dd152013-06-12 20:52:10 +03001225static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1226 struct htt_rx_indication *rx)
1227{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001228 struct ath10k *ar = htt->ar;
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001229 struct ieee80211_rx_status *rx_status = &htt->rx_status;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001230 struct htt_rx_indication_mpdu_range *mpdu_ranges;
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001231 struct htt_rx_desc *rxd;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001232 enum htt_rx_mpdu_status status;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001233 struct ieee80211_hdr *hdr;
1234 int num_mpdu_ranges;
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001235 u32 attention;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001236 int fw_desc_len;
1237 u8 *fw_desc;
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001238 bool channel_set;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001239 int i, j;
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001240 int ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001241
Michal Kazior45967082014-02-27 18:50:05 +02001242 lockdep_assert_held(&htt->rx_ring.lock);
1243
Kalle Valo5e3dd152013-06-12 20:52:10 +03001244 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1245 fw_desc = (u8 *)&rx->fw_desc;
1246
1247 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1248 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1249 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1250
Janusz Dziedzice8dc1a92014-03-19 07:09:41 +01001251 /* Fill this once, while this is per-ppdu */
Janusz Dziedzic22891882014-03-24 21:24:58 +01001252 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) {
1253 memset(rx_status, 0, sizeof(*rx_status));
1254 rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR +
1255 rx->ppdu.combined_rssi;
1256 }
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001257
1258 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
1259 /* TSF available only in 32-bit */
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001260 rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
1261 rx_status->flag |= RX_FLAG_MACTIME_END;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001262 }
Janusz Dziedzice8dc1a92014-03-19 07:09:41 +01001263
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001264 channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status);
Janusz Dziedzic36653f02014-03-24 21:23:18 +01001265
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001266 if (channel_set) {
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001267 ath10k_htt_rx_h_rates(htt->ar, rx_status->band,
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001268 rx->ppdu.info0,
1269 __le32_to_cpu(rx->ppdu.info1),
1270 __le32_to_cpu(rx->ppdu.info2),
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001271 rx_status);
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001272 }
Janusz Dziedzice8dc1a92014-03-19 07:09:41 +01001273
Michal Kazior7aa7a722014-08-25 12:09:38 +02001274 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001275 rx, sizeof(*rx) +
1276 (sizeof(struct htt_rx_indication_mpdu_range) *
1277 num_mpdu_ranges));
1278
1279 for (i = 0; i < num_mpdu_ranges; i++) {
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001280 status = mpdu_ranges[i].mpdu_range_status;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001281
1282 for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
1283 struct sk_buff *msdu_head, *msdu_tail;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001284
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001285 attention = 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001286 msdu_head = NULL;
1287 msdu_tail = NULL;
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001288 ret = ath10k_htt_rx_amsdu_pop(htt,
1289 &fw_desc,
1290 &fw_desc_len,
1291 &msdu_head,
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001292 &msdu_tail,
1293 &attention);
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001294
1295 if (ret < 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001296 ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n",
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001297 ret);
1298 ath10k_htt_rx_free_msdu_chain(msdu_head);
1299 continue;
1300 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03001301
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001302 rxd = container_of((void *)msdu_head->data,
1303 struct htt_rx_desc,
1304 msdu_payload);
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001305
Janusz Dziedzic2acc4eb2014-03-19 07:09:40 +01001306 if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head,
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001307 status,
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001308 channel_set,
1309 attention)) {
Marek Puzyniake8a50f82013-11-20 09:59:47 +02001310 ath10k_htt_rx_free_msdu_chain(msdu_head);
1311 continue;
1312 }
1313
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001314 if (ret > 0 &&
1315 ath10k_unchain_msdu(msdu_head) < 0) {
Kalle Valo5e3dd152013-06-12 20:52:10 +03001316 ath10k_htt_rx_free_msdu_chain(msdu_head);
1317 continue;
1318 }
1319
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001320 if (attention & RX_ATTENTION_FLAGS_FCS_ERR)
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001321 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001322 else
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001323 rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001324
Janusz Dziedzic78433f92014-03-24 21:23:21 +01001325 if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001326 rx_status->flag |= RX_FLAG_MMIC_ERROR;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001327 else
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001328 rx_status->flag &= ~RX_FLAG_MMIC_ERROR;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001329
Kalle Valo5e3dd152013-06-12 20:52:10 +03001330 hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
1331
1332 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001333 ath10k_htt_rx_amsdu(htt, rx_status, msdu_head);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001334 else
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001335 ath10k_htt_rx_msdu(htt, rx_status, msdu_head);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001336 }
1337 }
1338
Michal Kazior6e712d42013-09-24 10:18:36 +02001339 tasklet_schedule(&htt->rx_replenish_task);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001340}
1341
1342static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
Kalle Valo5b07e072014-09-14 12:50:06 +03001343 struct htt_rx_fragment_indication *frag)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001344{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001345 struct ath10k *ar = htt->ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001346 struct sk_buff *msdu_head, *msdu_tail;
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001347 enum htt_rx_mpdu_encrypt_type enctype;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001348 struct htt_rx_desc *rxd;
1349 enum rx_msdu_decap_format fmt;
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001350 struct ieee80211_rx_status *rx_status = &htt->rx_status;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001351 struct ieee80211_hdr *hdr;
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001352 int ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001353 bool tkip_mic_err;
1354 bool decrypt_err;
1355 u8 *fw_desc;
1356 int fw_desc_len, hdrlen, paramlen;
1357 int trim;
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001358 u32 attention = 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001359
1360 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1361 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1362
1363 msdu_head = NULL;
1364 msdu_tail = NULL;
Michal Kazior45967082014-02-27 18:50:05 +02001365
1366 spin_lock_bh(&htt->rx_ring.lock);
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001367 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001368 &msdu_head, &msdu_tail,
1369 &attention);
Michal Kazior45967082014-02-27 18:50:05 +02001370 spin_unlock_bh(&htt->rx_ring.lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001371
Michal Kazior7aa7a722014-08-25 12:09:38 +02001372 ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001373
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001374 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001375 ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n",
Janusz Dziedzicd84dd602014-03-24 21:23:20 +01001376 ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001377 ath10k_htt_rx_free_msdu_chain(msdu_head);
1378 return;
1379 }
1380
1381 /* FIXME: implement signal strength */
Ben Greear4b81d172014-05-26 12:46:04 +03001382 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001383
1384 hdr = (struct ieee80211_hdr *)msdu_head->data;
1385 rxd = (void *)msdu_head->data - sizeof(*rxd);
Janusz Dziedzic0ccb7a32014-07-25 11:28:50 +03001386 tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1387 decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001388 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
Kalle Valo5b07e072014-09-14 12:50:06 +03001389 RX_MSDU_START_INFO1_DECAP_FORMAT);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001390
1391 if (fmt != RX_MSDU_DECAP_RAW) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001392 ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001393 dev_kfree_skb_any(msdu_head);
1394 goto end;
1395 }
1396
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001397 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1398 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
Michal Kaziorc071dcb2014-05-23 11:33:18 +03001399 ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype, fmt,
1400 true);
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001401 msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001402
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001403 if (tkip_mic_err)
Michal Kazior7aa7a722014-08-25 12:09:38 +02001404 ath10k_warn(ar, "tkip mic error\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001405
1406 if (decrypt_err) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001407 ath10k_warn(ar, "decryption err in fragmented rx\n");
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001408 dev_kfree_skb_any(msdu_head);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001409 goto end;
1410 }
1411
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001412 if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
Kalle Valo5e3dd152013-06-12 20:52:10 +03001413 hdrlen = ieee80211_hdrlen(hdr->frame_control);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001414 paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001415
1416 /* It is more efficient to move the header than the payload */
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001417 memmove((void *)msdu_head->data + paramlen,
1418 (void *)msdu_head->data,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001419 hdrlen);
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001420 skb_pull(msdu_head, paramlen);
1421 hdr = (struct ieee80211_hdr *)msdu_head->data;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001422 }
1423
1424 /* remove trailing FCS */
1425 trim = 4;
1426
1427 /* remove crypto trailer */
Michal Kazior7aa7a722014-08-25 12:09:38 +02001428 trim += ath10k_htt_rx_crypto_tail_len(ar, enctype);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001429
1430 /* last fragment of TKIP frags has MIC */
1431 if (!ieee80211_has_morefrags(hdr->frame_control) &&
Janusz Dziedzic87326c92014-03-24 21:23:19 +01001432 enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001433 trim += 8;
1434
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001435 if (trim > msdu_head->len) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001436 ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n");
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001437 dev_kfree_skb_any(msdu_head);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001438 goto end;
1439 }
1440
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001441 skb_trim(msdu_head, msdu_head->len - trim);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001442
Michal Kazior7aa7a722014-08-25 12:09:38 +02001443 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
Janusz Dziedzic85f6d7c2014-03-24 21:23:22 +01001444 msdu_head->data, msdu_head->len);
Janusz Dziedzic6df92a32014-03-24 21:24:57 +01001445 ath10k_process_rx(htt->ar, rx_status, msdu_head);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001446
1447end:
1448 if (fw_desc_len > 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001449 ath10k_dbg(ar, ATH10K_DBG_HTT,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001450 "expecting more fragmented rx in one indication %d\n",
1451 fw_desc_len);
1452 }
1453}
1454
Michal Kazior6c5151a2014-02-27 18:50:04 +02001455static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1456 struct sk_buff *skb)
1457{
1458 struct ath10k_htt *htt = &ar->htt;
1459 struct htt_resp *resp = (struct htt_resp *)skb->data;
1460 struct htt_tx_done tx_done = {};
1461 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1462 __le16 msdu_id;
1463 int i;
1464
Michal Kazior45967082014-02-27 18:50:05 +02001465 lockdep_assert_held(&htt->tx_lock);
1466
Michal Kazior6c5151a2014-02-27 18:50:04 +02001467 switch (status) {
1468 case HTT_DATA_TX_STATUS_NO_ACK:
1469 tx_done.no_ack = true;
1470 break;
1471 case HTT_DATA_TX_STATUS_OK:
1472 break;
1473 case HTT_DATA_TX_STATUS_DISCARD:
1474 case HTT_DATA_TX_STATUS_POSTPONE:
1475 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1476 tx_done.discard = true;
1477 break;
1478 default:
Michal Kazior7aa7a722014-08-25 12:09:38 +02001479 ath10k_warn(ar, "unhandled tx completion status %d\n", status);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001480 tx_done.discard = true;
1481 break;
1482 }
1483
Michal Kazior7aa7a722014-08-25 12:09:38 +02001484 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
Michal Kazior6c5151a2014-02-27 18:50:04 +02001485 resp->data_tx_completion.num_msdus);
1486
1487 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1488 msdu_id = resp->data_tx_completion.msdus[i];
1489 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1490 ath10k_txrx_tx_unref(htt, &tx_done);
1491 }
1492}
1493
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001494static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
1495{
1496 struct htt_rx_addba *ev = &resp->rx_addba;
1497 struct ath10k_peer *peer;
1498 struct ath10k_vif *arvif;
1499 u16 info0, tid, peer_id;
1500
1501 info0 = __le16_to_cpu(ev->info0);
1502 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1503 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1504
Michal Kazior7aa7a722014-08-25 12:09:38 +02001505 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001506 "htt rx addba tid %hu peer_id %hu size %hhu\n",
1507 tid, peer_id, ev->window_size);
1508
1509 spin_lock_bh(&ar->data_lock);
1510 peer = ath10k_peer_find_by_id(ar, peer_id);
1511 if (!peer) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001512 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001513 peer_id);
1514 spin_unlock_bh(&ar->data_lock);
1515 return;
1516 }
1517
1518 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1519 if (!arvif) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001520 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001521 peer->vdev_id);
1522 spin_unlock_bh(&ar->data_lock);
1523 return;
1524 }
1525
Michal Kazior7aa7a722014-08-25 12:09:38 +02001526 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001527 "htt rx start rx ba session sta %pM tid %hu size %hhu\n",
1528 peer->addr, tid, ev->window_size);
1529
1530 ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1531 spin_unlock_bh(&ar->data_lock);
1532}
1533
1534static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
1535{
1536 struct htt_rx_delba *ev = &resp->rx_delba;
1537 struct ath10k_peer *peer;
1538 struct ath10k_vif *arvif;
1539 u16 info0, tid, peer_id;
1540
1541 info0 = __le16_to_cpu(ev->info0);
1542 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1543 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1544
Michal Kazior7aa7a722014-08-25 12:09:38 +02001545 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001546 "htt rx delba tid %hu peer_id %hu\n",
1547 tid, peer_id);
1548
1549 spin_lock_bh(&ar->data_lock);
1550 peer = ath10k_peer_find_by_id(ar, peer_id);
1551 if (!peer) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001552 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001553 peer_id);
1554 spin_unlock_bh(&ar->data_lock);
1555 return;
1556 }
1557
1558 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1559 if (!arvif) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001560 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001561 peer->vdev_id);
1562 spin_unlock_bh(&ar->data_lock);
1563 return;
1564 }
1565
Michal Kazior7aa7a722014-08-25 12:09:38 +02001566 ath10k_dbg(ar, ATH10K_DBG_HTT,
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001567 "htt rx stop rx ba session sta %pM tid %hu\n",
1568 peer->addr, tid);
1569
1570 ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1571 spin_unlock_bh(&ar->data_lock);
1572}
1573
Kalle Valo5e3dd152013-06-12 20:52:10 +03001574void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1575{
Michal Kazioredb82362013-07-05 16:15:14 +03001576 struct ath10k_htt *htt = &ar->htt;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001577 struct htt_resp *resp = (struct htt_resp *)skb->data;
1578
1579 /* confirm alignment */
1580 if (!IS_ALIGNED((unsigned long)skb->data, 4))
Michal Kazior7aa7a722014-08-25 12:09:38 +02001581 ath10k_warn(ar, "unaligned htt message, expect trouble\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001582
Michal Kazior7aa7a722014-08-25 12:09:38 +02001583 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001584 resp->hdr.msg_type);
1585 switch (resp->hdr.msg_type) {
1586 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1587 htt->target_version_major = resp->ver_resp.major;
1588 htt->target_version_minor = resp->ver_resp.minor;
1589 complete(&htt->target_version_received);
1590 break;
1591 }
Michal Kazior6c5151a2014-02-27 18:50:04 +02001592 case HTT_T2H_MSG_TYPE_RX_IND:
Michal Kazior45967082014-02-27 18:50:05 +02001593 spin_lock_bh(&htt->rx_ring.lock);
1594 __skb_queue_tail(&htt->rx_compl_q, skb);
1595 spin_unlock_bh(&htt->rx_ring.lock);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001596 tasklet_schedule(&htt->txrx_compl_task);
1597 return;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001598 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1599 struct htt_peer_map_event ev = {
1600 .vdev_id = resp->peer_map.vdev_id,
1601 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1602 };
1603 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1604 ath10k_peer_map_event(htt, &ev);
1605 break;
1606 }
1607 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1608 struct htt_peer_unmap_event ev = {
1609 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1610 };
1611 ath10k_peer_unmap_event(htt, &ev);
1612 break;
1613 }
1614 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1615 struct htt_tx_done tx_done = {};
1616 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1617
1618 tx_done.msdu_id =
1619 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1620
1621 switch (status) {
1622 case HTT_MGMT_TX_STATUS_OK:
1623 break;
1624 case HTT_MGMT_TX_STATUS_RETRY:
1625 tx_done.no_ack = true;
1626 break;
1627 case HTT_MGMT_TX_STATUS_DROP:
1628 tx_done.discard = true;
1629 break;
1630 }
1631
Michal Kazior6c5151a2014-02-27 18:50:04 +02001632 spin_lock_bh(&htt->tx_lock);
Michal Kazior0a89f8a2013-09-18 14:43:20 +02001633 ath10k_txrx_tx_unref(htt, &tx_done);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001634 spin_unlock_bh(&htt->tx_lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001635 break;
1636 }
Michal Kazior6c5151a2014-02-27 18:50:04 +02001637 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1638 spin_lock_bh(&htt->tx_lock);
1639 __skb_queue_tail(&htt->tx_compl_q, skb);
1640 spin_unlock_bh(&htt->tx_lock);
1641 tasklet_schedule(&htt->txrx_compl_task);
1642 return;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001643 case HTT_T2H_MSG_TYPE_SEC_IND: {
1644 struct ath10k *ar = htt->ar;
1645 struct htt_security_indication *ev = &resp->security_indication;
1646
Michal Kazior7aa7a722014-08-25 12:09:38 +02001647 ath10k_dbg(ar, ATH10K_DBG_HTT,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001648 "sec ind peer_id %d unicast %d type %d\n",
1649 __le16_to_cpu(ev->peer_id),
1650 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1651 MS(ev->flags, HTT_SECURITY_TYPE));
1652 complete(&ar->install_key_done);
1653 break;
1654 }
1655 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001656 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001657 skb->data, skb->len);
1658 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1659 break;
1660 }
1661 case HTT_T2H_MSG_TYPE_TEST:
1662 /* FIX THIS */
1663 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001664 case HTT_T2H_MSG_TYPE_STATS_CONF:
Michal Kaziord35a6c12014-09-02 11:00:21 +03001665 trace_ath10k_htt_stats(ar, skb->data, skb->len);
Kalle Valoa9bf0502013-09-03 11:43:55 +03001666 break;
1667 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
Michal Kazior708b9bd2014-07-21 20:52:59 +03001668 /* Firmware can return tx frames if it's unable to fully
1669 * process them and suspects host may be able to fix it. ath10k
1670 * sends all tx frames as already inspected so this shouldn't
1671 * happen unless fw has a bug.
1672 */
Michal Kazior7aa7a722014-08-25 12:09:38 +02001673 ath10k_warn(ar, "received an unexpected htt tx inspect event\n");
Michal Kazior708b9bd2014-07-21 20:52:59 +03001674 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001675 case HTT_T2H_MSG_TYPE_RX_ADDBA:
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001676 ath10k_htt_rx_addba(ar, resp);
1677 break;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001678 case HTT_T2H_MSG_TYPE_RX_DELBA:
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001679 ath10k_htt_rx_delba(ar, resp);
1680 break;
Rajkumar Manoharanbfdd7932014-10-03 08:02:40 +03001681 case HTT_T2H_MSG_TYPE_PKTLOG: {
1682 struct ath10k_pktlog_hdr *hdr =
1683 (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload;
1684
1685 trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload,
1686 sizeof(*hdr) +
1687 __le16_to_cpu(hdr->size));
1688 break;
1689 }
Michal Kazioraa5b4fb2014-07-23 12:20:33 +02001690 case HTT_T2H_MSG_TYPE_RX_FLUSH: {
1691 /* Ignore this event because mac80211 takes care of Rx
1692 * aggregation reordering.
1693 */
1694 break;
1695 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03001696 default:
Michal Kazior7aa7a722014-08-25 12:09:38 +02001697 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt event (%d) not handled\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001698 resp->hdr.msg_type);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001699 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
Kalle Valo5e3dd152013-06-12 20:52:10 +03001700 skb->data, skb->len);
1701 break;
1702 };
1703
1704 /* Free the indication buffer */
1705 dev_kfree_skb_any(skb);
1706}
Michal Kazior6c5151a2014-02-27 18:50:04 +02001707
1708static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1709{
1710 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1711 struct htt_resp *resp;
1712 struct sk_buff *skb;
1713
Michal Kazior45967082014-02-27 18:50:05 +02001714 spin_lock_bh(&htt->tx_lock);
1715 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
Michal Kazior6c5151a2014-02-27 18:50:04 +02001716 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1717 dev_kfree_skb_any(skb);
1718 }
Michal Kazior45967082014-02-27 18:50:05 +02001719 spin_unlock_bh(&htt->tx_lock);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001720
Michal Kazior45967082014-02-27 18:50:05 +02001721 spin_lock_bh(&htt->rx_ring.lock);
1722 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
Michal Kazior6c5151a2014-02-27 18:50:04 +02001723 resp = (struct htt_resp *)skb->data;
1724 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1725 dev_kfree_skb_any(skb);
1726 }
Michal Kazior45967082014-02-27 18:50:05 +02001727 spin_unlock_bh(&htt->rx_ring.lock);
Michal Kazior6c5151a2014-02-27 18:50:04 +02001728}