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Chunfeng Yundf2069a2016-10-19 10:28:23 +08001/*
2 * Copyright (C) 2016 MediaTek Inc.
3 *
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clk.h>
18#include <linux/dma-mapping.h>
19#include <linux/iopoll.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080024#include <linux/pinctrl/consumer.h>
Chunfeng Yundf2069a2016-10-19 10:28:23 +080025#include <linux/platform_device.h>
26
27#include "mtu3.h"
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080028#include "mtu3_dr.h"
Chunfeng Yundf2069a2016-10-19 10:28:23 +080029
30/* u2-port0 should be powered on and enabled; */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080031int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
Chunfeng Yundf2069a2016-10-19 10:28:23 +080032{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080033 void __iomem *ibase = ssusb->ippc_base;
Chunfeng Yundf2069a2016-10-19 10:28:23 +080034 u32 value, check_val;
35 int ret;
36
37 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
38 SSUSB_REF_RST_B_STS;
39
40 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
41 (check_val == (value & check_val)), 100, 20000);
42 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080043 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080044 return ret;
45 }
46
47 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
48 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
49 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080050 dev_err(ssusb->dev, "mac2 clock is not stable\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080051 return ret;
52 }
53
54 return 0;
55}
56
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080057static int ssusb_phy_init(struct ssusb_mtk *ssusb)
58{
59 int i;
60 int ret;
61
62 for (i = 0; i < ssusb->num_phys; i++) {
63 ret = phy_init(ssusb->phys[i]);
64 if (ret)
65 goto exit_phy;
66 }
67 return 0;
68
69exit_phy:
70 for (; i > 0; i--)
71 phy_exit(ssusb->phys[i - 1]);
72
73 return ret;
74}
75
76static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
77{
78 int i;
79
80 for (i = 0; i < ssusb->num_phys; i++)
81 phy_exit(ssusb->phys[i]);
82
83 return 0;
84}
85
86static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
87{
88 int i;
89 int ret;
90
91 for (i = 0; i < ssusb->num_phys; i++) {
92 ret = phy_power_on(ssusb->phys[i]);
93 if (ret)
94 goto power_off_phy;
95 }
96 return 0;
97
98power_off_phy:
99 for (; i > 0; i--)
100 phy_power_off(ssusb->phys[i - 1]);
101
102 return ret;
103}
104
105static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
106{
107 unsigned int i;
108
109 for (i = 0; i < ssusb->num_phys; i++)
110 phy_power_off(ssusb->phys[i]);
111}
112
Chunfeng Yuna316da82017-10-13 17:10:40 +0800113static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800114{
Chunfeng Yuna316da82017-10-13 17:10:40 +0800115 int ret;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800116
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800117 ret = clk_prepare_enable(ssusb->sys_clk);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800118 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800119 dev_err(ssusb->dev, "failed to enable sys_clk\n");
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800120 goto sys_clk_err;
121 }
122
123 ret = clk_prepare_enable(ssusb->ref_clk);
124 if (ret) {
125 dev_err(ssusb->dev, "failed to enable ref_clk\n");
126 goto ref_clk_err;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800127 }
128
Chunfeng Yuna316da82017-10-13 17:10:40 +0800129 ret = clk_prepare_enable(ssusb->mcu_clk);
130 if (ret) {
131 dev_err(ssusb->dev, "failed to enable mcu_clk\n");
132 goto mcu_clk_err;
133 }
134
135 ret = clk_prepare_enable(ssusb->dma_clk);
136 if (ret) {
137 dev_err(ssusb->dev, "failed to enable dma_clk\n");
138 goto dma_clk_err;
139 }
140
141 return 0;
142
143dma_clk_err:
144 clk_disable_unprepare(ssusb->mcu_clk);
145mcu_clk_err:
146 clk_disable_unprepare(ssusb->ref_clk);
147ref_clk_err:
148 clk_disable_unprepare(ssusb->sys_clk);
149sys_clk_err:
150 return ret;
151}
152
153static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
154{
155 clk_disable_unprepare(ssusb->dma_clk);
156 clk_disable_unprepare(ssusb->mcu_clk);
157 clk_disable_unprepare(ssusb->ref_clk);
158 clk_disable_unprepare(ssusb->sys_clk);
159}
160
161static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
162{
163 int ret = 0;
164
165 ret = regulator_enable(ssusb->vusb33);
166 if (ret) {
167 dev_err(ssusb->dev, "failed to enable vusb33\n");
168 goto vusb33_err;
169 }
170
171 ret = ssusb_clks_enable(ssusb);
172 if (ret)
173 goto clks_err;
174
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800175 ret = ssusb_phy_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800176 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800177 dev_err(ssusb->dev, "failed to init phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800178 goto phy_init_err;
179 }
180
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800181 ret = ssusb_phy_power_on(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800182 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800183 dev_err(ssusb->dev, "failed to power on phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800184 goto phy_err;
185 }
186
187 return 0;
188
189phy_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800190 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800191phy_init_err:
Chunfeng Yuna316da82017-10-13 17:10:40 +0800192 ssusb_clks_disable(ssusb);
193clks_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800194 regulator_disable(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800195vusb33_err:
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800196 return ret;
197}
198
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800199static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800200{
Chunfeng Yuna316da82017-10-13 17:10:40 +0800201 ssusb_clks_disable(ssusb);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800202 regulator_disable(ssusb->vusb33);
203 ssusb_phy_power_off(ssusb);
204 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800205}
206
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800207static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800208{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800209 /* reset whole ip (xhci & u3d) */
210 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800211 udelay(1);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800212 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800213}
214
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800215static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
216{
217 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
218
219 otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev);
220 if (IS_ERR(otg_sx->id_pinctrl)) {
221 dev_err(ssusb->dev, "Cannot find id pinctrl!\n");
222 return PTR_ERR(otg_sx->id_pinctrl);
223 }
224
225 otg_sx->id_float =
226 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float");
227 if (IS_ERR(otg_sx->id_float)) {
228 dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n");
229 return PTR_ERR(otg_sx->id_float);
230 }
231
232 otg_sx->id_ground =
233 pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground");
234 if (IS_ERR(otg_sx->id_ground)) {
235 dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n");
236 return PTR_ERR(otg_sx->id_ground);
237 }
238
239 return 0;
240}
241
Chunfeng Yuna316da82017-10-13 17:10:40 +0800242/* ignore the error if the clock does not exist */
243static struct clk *get_optional_clk(struct device *dev, const char *id)
244{
245 struct clk *opt_clk;
246
247 opt_clk = devm_clk_get(dev, id);
248 /* ignore error number except EPROBE_DEFER */
249 if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
250 opt_clk = NULL;
251
252 return opt_clk;
253}
254
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800255static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800256{
257 struct device_node *node = pdev->dev.of_node;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800258 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800259 struct device *dev = &pdev->dev;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800260 struct regulator *vbus;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800261 struct resource *res;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800262 int i;
263 int ret;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800264
Chunfeng Yun5cbf2d62017-01-18 14:08:22 +0800265 ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
266 if (IS_ERR(ssusb->vusb33)) {
267 dev_err(dev, "failed to get vusb33\n");
268 return PTR_ERR(ssusb->vusb33);
269 }
270
271 ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
272 if (IS_ERR(ssusb->sys_clk)) {
273 dev_err(dev, "failed to get sys clock\n");
274 return PTR_ERR(ssusb->sys_clk);
275 }
276
Chunfeng Yuna316da82017-10-13 17:10:40 +0800277 ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
278 if (IS_ERR(ssusb->ref_clk))
279 return PTR_ERR(ssusb->ref_clk);
Chunfeng Yunca12cb72017-02-07 14:13:32 +0800280
Chunfeng Yuna316da82017-10-13 17:10:40 +0800281 ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
282 if (IS_ERR(ssusb->mcu_clk))
283 return PTR_ERR(ssusb->mcu_clk);
284
285 ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
286 if (IS_ERR(ssusb->dma_clk))
287 return PTR_ERR(ssusb->dma_clk);
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800288
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800289 ssusb->num_phys = of_count_phandle_with_args(node,
290 "phys", "#phy-cells");
291 if (ssusb->num_phys > 0) {
292 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
293 sizeof(*ssusb->phys), GFP_KERNEL);
294 if (!ssusb->phys)
295 return -ENOMEM;
296 } else {
297 ssusb->num_phys = 0;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800298 }
299
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800300 for (i = 0; i < ssusb->num_phys; i++) {
301 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
302 if (IS_ERR(ssusb->phys[i])) {
303 dev_err(dev, "failed to get phy-%d\n", i);
304 return PTR_ERR(ssusb->phys[i]);
305 }
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800306 }
307
308 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800309 ssusb->ippc_base = devm_ioremap_resource(dev, res);
Wei Yongjunb7ecfe72017-02-05 16:25:38 +0000310 if (IS_ERR(ssusb->ippc_base))
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800311 return PTR_ERR(ssusb->ippc_base);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800312
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800313 ssusb->dr_mode = usb_get_dr_mode(dev);
314 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
315 dev_err(dev, "dr_mode is error\n");
316 return -EINVAL;
317 }
318
319 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
320 return 0;
321
322 /* if host role is supported */
323 ret = ssusb_wakeup_of_property_parse(ssusb, node);
324 if (ret)
325 return ret;
326
Chunfeng Yun076f1a82017-10-13 17:10:38 +0800327 /* optional property, ignore the error if it does not exist */
328 of_property_read_u32(node, "mediatek,u3p-dis-msk",
329 &ssusb->u3p_dis_msk);
330
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800331 if (ssusb->dr_mode != USB_DR_MODE_OTG)
332 return 0;
333
334 /* if dual-role mode is supported */
335 vbus = devm_regulator_get(&pdev->dev, "vbus");
336 if (IS_ERR(vbus)) {
337 dev_err(dev, "failed to get vbus\n");
338 return PTR_ERR(vbus);
339 }
340 otg_sx->vbus = vbus;
341
342 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
343 otg_sx->manual_drd_enabled =
344 of_property_read_bool(node, "enable-manual-drd");
345
346 if (of_property_read_bool(node, "extcon")) {
347 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
348 if (IS_ERR(otg_sx->edev)) {
349 dev_err(ssusb->dev, "couldn't get extcon device\n");
350 return -EPROBE_DEFER;
351 }
352 if (otg_sx->manual_drd_enabled) {
353 ret = get_iddig_pinctrl(ssusb);
354 if (ret)
355 return ret;
356 }
357 }
358
Chunfeng Yun076f1a82017-10-13 17:10:38 +0800359 dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n",
360 ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk);
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800361
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800362 return 0;
363}
364
365static int mtu3_probe(struct platform_device *pdev)
366{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800367 struct device_node *node = pdev->dev.of_node;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800368 struct device *dev = &pdev->dev;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800369 struct ssusb_mtk *ssusb;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800370 int ret = -ENOMEM;
371
372 /* all elements are set to ZERO as default value */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800373 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
374 if (!ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800375 return -ENOMEM;
376
377 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
378 if (ret) {
379 dev_err(dev, "No suitable DMA config available\n");
380 return -ENOTSUPP;
381 }
382
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800383 platform_set_drvdata(pdev, ssusb);
384 ssusb->dev = dev;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800385
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800386 ret = get_ssusb_rscs(pdev, ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800387 if (ret)
388 return ret;
389
390 /* enable power domain */
391 pm_runtime_enable(dev);
392 pm_runtime_get_sync(dev);
393 device_enable_async_suspend(dev);
394
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800395 ret = ssusb_rscs_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800396 if (ret)
397 goto comm_init_err;
398
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800399 ssusb_ip_sw_reset(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800400
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800401 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
402 ssusb->dr_mode = USB_DR_MODE_HOST;
403 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
404 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
405
406 /* default as host */
407 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
408
409 switch (ssusb->dr_mode) {
410 case USB_DR_MODE_PERIPHERAL:
411 ret = ssusb_gadget_init(ssusb);
412 if (ret) {
413 dev_err(dev, "failed to initialize gadget\n");
414 goto comm_exit;
415 }
416 break;
417 case USB_DR_MODE_HOST:
418 ret = ssusb_host_init(ssusb, node);
419 if (ret) {
420 dev_err(dev, "failed to initialize host\n");
421 goto comm_exit;
422 }
423 break;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800424 case USB_DR_MODE_OTG:
425 ret = ssusb_gadget_init(ssusb);
426 if (ret) {
427 dev_err(dev, "failed to initialize gadget\n");
428 goto comm_exit;
429 }
430
431 ret = ssusb_host_init(ssusb, node);
432 if (ret) {
433 dev_err(dev, "failed to initialize host\n");
434 goto gadget_exit;
435 }
436
437 ssusb_otg_switch_init(ssusb);
438 break;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800439 default:
440 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
441 ret = -EINVAL;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800442 goto comm_exit;
443 }
444
445 return 0;
446
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800447gadget_exit:
448 ssusb_gadget_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800449comm_exit:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800450 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800451comm_init_err:
452 pm_runtime_put_sync(dev);
453 pm_runtime_disable(dev);
454
455 return ret;
456}
457
458static int mtu3_remove(struct platform_device *pdev)
459{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800460 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800461
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800462 switch (ssusb->dr_mode) {
463 case USB_DR_MODE_PERIPHERAL:
464 ssusb_gadget_exit(ssusb);
465 break;
466 case USB_DR_MODE_HOST:
467 ssusb_host_exit(ssusb);
468 break;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800469 case USB_DR_MODE_OTG:
470 ssusb_otg_switch_exit(ssusb);
471 ssusb_gadget_exit(ssusb);
472 ssusb_host_exit(ssusb);
473 break;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800474 default:
475 return -EINVAL;
476 }
477
478 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800479 pm_runtime_put_sync(&pdev->dev);
480 pm_runtime_disable(&pdev->dev);
481
482 return 0;
483}
484
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800485/*
486 * when support dual-role mode, we reject suspend when
487 * it works as device mode;
488 */
489static int __maybe_unused mtu3_suspend(struct device *dev)
490{
491 struct platform_device *pdev = to_platform_device(dev);
492 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
493
494 dev_dbg(dev, "%s\n", __func__);
495
496 /* REVISIT: disconnect it for only device mode? */
497 if (!ssusb->is_host)
498 return 0;
499
500 ssusb_host_disable(ssusb, true);
501 ssusb_phy_power_off(ssusb);
Chunfeng Yuna316da82017-10-13 17:10:40 +0800502 ssusb_clks_disable(ssusb);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800503 ssusb_wakeup_enable(ssusb);
504
505 return 0;
506}
507
508static int __maybe_unused mtu3_resume(struct device *dev)
509{
510 struct platform_device *pdev = to_platform_device(dev);
511 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530512 int ret;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800513
514 dev_dbg(dev, "%s\n", __func__);
515
516 if (!ssusb->is_host)
517 return 0;
518
519 ssusb_wakeup_disable(ssusb);
Chunfeng Yuna316da82017-10-13 17:10:40 +0800520 ret = ssusb_clks_enable(ssusb);
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530521 if (ret)
Chunfeng Yuna316da82017-10-13 17:10:40 +0800522 goto clks_err;
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530523
524 ret = ssusb_phy_power_on(ssusb);
525 if (ret)
Chunfeng Yuna316da82017-10-13 17:10:40 +0800526 goto phy_err;
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530527
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800528 ssusb_host_enable(ssusb);
529
530 return 0;
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530531
Chunfeng Yuna316da82017-10-13 17:10:40 +0800532phy_err:
533 ssusb_clks_disable(ssusb);
534clks_err:
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530535 return ret;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800536}
537
538static const struct dev_pm_ops mtu3_pm_ops = {
539 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
540};
541
542#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
543
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800544#ifdef CONFIG_OF
545
546static const struct of_device_id mtu3_of_match[] = {
547 {.compatible = "mediatek,mt8173-mtu3",},
Chunfeng Yundfcdcba2017-08-08 13:42:49 +0800548 {.compatible = "mediatek,mtu3",},
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800549 {},
550};
551
552MODULE_DEVICE_TABLE(of, mtu3_of_match);
553
554#endif
555
556static struct platform_driver mtu3_driver = {
557 .probe = mtu3_probe,
558 .remove = mtu3_remove,
559 .driver = {
560 .name = MTU3_DRIVER_NAME,
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800561 .pm = DEV_PM_OPS,
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800562 .of_match_table = of_match_ptr(mtu3_of_match),
563 },
564};
565module_platform_driver(mtu3_driver);
566
567MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
568MODULE_LICENSE("GPL v2");
569MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");