blob: 7e8562a8507ddba70a7d19f937d54e538284227e [file] [log] [blame]
Bryan Wud7df69f2013-01-02 15:53:51 -08001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra30.dtsi"
Bryan Wud7df69f2013-01-02 15:53:51 -08004
5/ {
6 model = "NVIDIA Tegra30 Beaver evaluation board";
7 compatible = "nvidia,beaver", "nvidia,tegra30";
8
9 memory {
Stephen Warren30022bb2013-05-13 09:47:31 +000010 reg = <0x80000000 0x7ff00000>;
Bryan Wud7df69f2013-01-02 15:53:51 -080011 };
12
Stephen Warren58ecb232013-11-25 17:53:16 -070013 pcie-controller@00003000 {
Thierry Redingbb034cb2013-08-09 16:49:28 +020014 status = "okay";
15 pex-clk-supply = <&sys_3v3_pexs_reg>;
16 vdd-supply = <&ldo1_reg>;
17 avdd-supply = <&ldo2_reg>;
18
19 pci@1,0 {
20 status = "okay";
Stephen Warren44fefab2013-08-09 16:49:29 +020021 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020022 };
23
24 pci@2,0 {
Stephen Warren44fefab2013-08-09 16:49:29 +020025 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020026 };
27
28 pci@3,0 {
Stephen Warren44fefab2013-08-09 16:49:29 +020029 status = "okay";
30 nvidia,num-lanes = <2>;
Thierry Redingbb034cb2013-08-09 16:49:28 +020031 };
32 };
33
Stephen Warren58ecb232013-11-25 17:53:16 -070034 host1x@50000000 {
35 hdmi@54280000 {
Thierry Reding9bd80b42013-08-12 17:49:03 +020036 status = "okay";
37
38 vdd-supply = <&sys_3v3_reg>;
39 pll-supply = <&vio_reg>;
40
41 nvidia,hpd-gpio =
42 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
43 nvidia,ddc-i2c-bus = <&hdmiddc>;
44 };
45 };
46
Stephen Warren58ecb232013-11-25 17:53:16 -070047 pinmux@70000868 {
Bryan Wud7df69f2013-01-02 15:53:51 -080048 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>;
50
51 state_default: pinmux {
52 sdmmc1_clk_pz0 {
53 nvidia,pins = "sdmmc1_clk_pz0";
54 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +053055 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
56 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080057 };
58 sdmmc1_cmd_pz1 {
59 nvidia,pins = "sdmmc1_cmd_pz1",
60 "sdmmc1_dat0_py7",
61 "sdmmc1_dat1_py6",
62 "sdmmc1_dat2_py5",
63 "sdmmc1_dat3_py4";
64 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +053065 nvidia,pull = <TEGRA_PIN_PULL_UP>;
66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080067 };
68 sdmmc3_clk_pa6 {
69 nvidia,pins = "sdmmc3_clk_pa6";
70 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +053071 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080073 };
74 sdmmc3_cmd_pa7 {
75 nvidia,pins = "sdmmc3_cmd_pa7",
76 "sdmmc3_dat0_pb7",
77 "sdmmc3_dat1_pb6",
78 "sdmmc3_dat2_pb5",
79 "sdmmc3_dat3_pb4";
80 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +053081 nvidia,pull = <TEGRA_PIN_PULL_UP>;
82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080083 };
84 sdmmc4_clk_pcc4 {
85 nvidia,pins = "sdmmc4_clk_pcc4",
86 "sdmmc4_rst_n_pcc3";
87 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +053088 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
89 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -080090 };
91 sdmmc4_dat0_paa0 {
92 nvidia,pins = "sdmmc4_dat0_paa0",
93 "sdmmc4_dat1_paa1",
94 "sdmmc4_dat2_paa2",
95 "sdmmc4_dat3_paa3",
96 "sdmmc4_dat4_paa4",
97 "sdmmc4_dat5_paa5",
98 "sdmmc4_dat6_paa6",
99 "sdmmc4_dat7_paa7";
100 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800103 };
104 dap2_fs_pa2 {
105 nvidia,pins = "dap2_fs_pa2",
106 "dap2_sclk_pa3",
107 "dap2_din_pa4",
108 "dap2_dout_pa5";
109 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800112 };
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300113 pex_l1_prsnt_n_pdd4 {
114 nvidia,pins = "pex_l1_prsnt_n_pdd4",
115 "pex_l1_clkreq_n_pdd6";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530116 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300117 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800118 sdio3 {
119 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530120 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
121 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800122 nvidia,pull-down-strength = <46>;
123 nvidia,pull-up-strength = <42>;
124 nvidia,slew-rate-rising = <1>;
125 nvidia,slew-rate-falling = <1>;
126 };
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300127 gpv {
128 nvidia,pins = "drive_gpv";
129 nvidia,pull-up-strength = <16>;
130 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800131 };
132 };
133
134 serial@70006000 {
135 status = "okay";
Bryan Wud7df69f2013-01-02 15:53:51 -0800136 };
137
138 i2c@7000c000 {
139 status = "okay";
140 clock-frequency = <100000>;
141 };
142
143 i2c@7000c400 {
144 status = "okay";
145 clock-frequency = <100000>;
146 };
147
148 i2c@7000c500 {
149 status = "okay";
150 clock-frequency = <100000>;
151 };
152
Thierry Reding9bd80b42013-08-12 17:49:03 +0200153 hdmiddc: i2c@7000c700 {
Bryan Wud7df69f2013-01-02 15:53:51 -0800154 status = "okay";
155 clock-frequency = <100000>;
156 };
157
158 i2c@7000d000 {
159 status = "okay";
160 clock-frequency = <100000>;
161
Stephen Warren58ecb232013-11-25 17:53:16 -0700162 rt5640: rt5640@1c {
Stephen Warren23037bb2013-03-27 16:53:20 -0600163 compatible = "realtek,rt5640";
164 reg = <0x1c>;
165 interrupt-parent = <&gpio>;
166 interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
167 realtek,ldo1-en-gpios =
168 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
169 };
170
Bryan Wud7df69f2013-01-02 15:53:51 -0800171 pmic: tps65911@2d {
172 compatible = "ti,tps65911";
173 reg = <0x2d>;
174
Stephen Warren6cecf912013-02-13 12:51:51 -0700175 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800176 #interrupt-cells = <2>;
177 interrupt-controller;
178
179 ti,system-power-controller;
180
181 #gpio-cells = <2>;
182 gpio-controller;
183
184 vcc1-supply = <&vdd_5v_in_reg>;
185 vcc2-supply = <&vdd_5v_in_reg>;
186 vcc3-supply = <&vio_reg>;
187 vcc4-supply = <&vdd_5v_in_reg>;
188 vcc5-supply = <&vdd_5v_in_reg>;
189 vcc6-supply = <&vdd2_reg>;
190 vcc7-supply = <&vdd_5v_in_reg>;
191 vccio-supply = <&vdd_5v_in_reg>;
192
193 regulators {
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 vdd1_reg: vdd1 {
198 regulator-name = "vddio_ddr_1v2";
199 regulator-min-microvolt = <1200000>;
200 regulator-max-microvolt = <1200000>;
201 regulator-always-on;
202 };
203
204 vdd2_reg: vdd2 {
205 regulator-name = "vdd_1v5_gen";
206 regulator-min-microvolt = <1500000>;
207 regulator-max-microvolt = <1500000>;
208 regulator-always-on;
209 };
210
211 vddctrl_reg: vddctrl {
212 regulator-name = "vdd_cpu,vdd_sys";
213 regulator-min-microvolt = <1000000>;
214 regulator-max-microvolt = <1000000>;
215 regulator-always-on;
216 };
217
218 vio_reg: vio {
219 regulator-name = "vdd_1v8_gen";
220 regulator-min-microvolt = <1800000>;
221 regulator-max-microvolt = <1800000>;
222 regulator-always-on;
223 };
224
225 ldo1_reg: ldo1 {
226 regulator-name = "vdd_pexa,vdd_pexb";
227 regulator-min-microvolt = <1050000>;
228 regulator-max-microvolt = <1050000>;
229 };
230
231 ldo2_reg: ldo2 {
232 regulator-name = "vdd_sata,avdd_plle";
233 regulator-min-microvolt = <1050000>;
234 regulator-max-microvolt = <1050000>;
235 };
236
237 /* LDO3 is not connected to anything */
238
239 ldo4_reg: ldo4 {
240 regulator-name = "vdd_rtc";
241 regulator-min-microvolt = <1200000>;
242 regulator-max-microvolt = <1200000>;
243 regulator-always-on;
244 };
245
246 ldo5_reg: ldo5 {
247 regulator-name = "vddio_sdmmc,avdd_vdac";
248 regulator-min-microvolt = <3300000>;
249 regulator-max-microvolt = <3300000>;
250 regulator-always-on;
251 };
252
253 ldo6_reg: ldo6 {
254 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
255 regulator-min-microvolt = <1200000>;
256 regulator-max-microvolt = <1200000>;
257 };
258
259 ldo7_reg: ldo7 {
260 regulator-name = "vdd_pllm,x,u,a_p_c_s";
261 regulator-min-microvolt = <1200000>;
262 regulator-max-microvolt = <1200000>;
263 regulator-always-on;
264 };
265
266 ldo8_reg: ldo8 {
267 regulator-name = "vdd_ddr_hs";
268 regulator-min-microvolt = <1000000>;
269 regulator-max-microvolt = <1000000>;
270 regulator-always-on;
271 };
272 };
273 };
Stephen Warren57899052013-11-26 14:43:45 -0700274
275 tps62361@60 {
276 compatible = "ti,tps62361";
277 reg = <0x60>;
278
279 regulator-name = "tps62361-vout";
280 regulator-min-microvolt = <500000>;
281 regulator-max-microvolt = <1500000>;
282 regulator-boot-on;
283 regulator-always-on;
284 ti,vsel0-state-high;
285 ti,vsel1-state-high;
286 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800287 };
288
289 spi@7000da00 {
290 status = "okay";
291 spi-max-frequency = <25000000>;
292 spi-flash@1 {
293 compatible = "winbond,w25q32";
294 reg = <1>;
295 spi-max-frequency = <20000000>;
296 };
297 };
298
Stephen Warren58ecb232013-11-25 17:53:16 -0700299 pmc@7000e400 {
Bryan Wud7df69f2013-01-02 15:53:51 -0800300 status = "okay";
301 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800302 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800303 nvidia,cpu-pwr-good-time = <2000>;
304 nvidia,cpu-pwr-off-time = <200>;
305 nvidia,core-pwr-good-time = <3845 3845>;
306 nvidia,core-pwr-off-time = <0>;
307 nvidia,core-power-req-active-high;
308 nvidia,sys-clock-req-active-high;
Bryan Wud7df69f2013-01-02 15:53:51 -0800309 };
310
Stephen Warren57899052013-11-26 14:43:45 -0700311 ahub@70080000 {
312 i2s@70080400 {
313 status = "okay";
314 };
315 };
316
Bryan Wud7df69f2013-01-02 15:53:51 -0800317 sdhci@78000000 {
318 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700319 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
320 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
321 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800322 bus-width = <4>;
323 };
324
325 sdhci@78000600 {
326 status = "okay";
327 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600328 non-removable;
Bryan Wud7df69f2013-01-02 15:53:51 -0800329 };
330
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300331 usb@7d008000 {
332 status = "okay";
333 };
334
335 usb-phy@7d008000 {
336 vbus-supply = <&usb3_vbus_reg>;
337 status = "okay";
338 };
339
Joseph Lo7021d122013-04-03 19:31:27 +0800340 clocks {
341 compatible = "simple-bus";
342 #address-cells = <1>;
343 #size-cells = <0>;
344
Stephen Warren58ecb232013-11-25 17:53:16 -0700345 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800346 compatible = "fixed-clock";
347 reg=<0>;
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 };
351 };
352
Stephen Warren57899052013-11-26 14:43:45 -0700353 gpio-leds {
354 compatible = "gpio-leds";
355
356 gpled1 {
357 label = "LED1"; /* CR5A1 (blue) */
358 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
359 };
360 gpled2 {
361 label = "LED2"; /* CR4A2 (green) */
362 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
363 };
364 };
365
Bryan Wud7df69f2013-01-02 15:53:51 -0800366 regulators {
367 compatible = "simple-bus";
368 #address-cells = <1>;
369 #size-cells = <0>;
370
371 vdd_5v_in_reg: regulator@0 {
372 compatible = "regulator-fixed";
373 reg = <0>;
374 regulator-name = "vdd_5v_in";
375 regulator-min-microvolt = <5000000>;
376 regulator-max-microvolt = <5000000>;
377 regulator-always-on;
378 };
379
380 chargepump_5v_reg: regulator@1 {
381 compatible = "regulator-fixed";
382 reg = <1>;
383 regulator-name = "chargepump_5v";
384 regulator-min-microvolt = <5000000>;
385 regulator-max-microvolt = <5000000>;
386 regulator-boot-on;
387 regulator-always-on;
388 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700389 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800390 };
391
392 ddr_reg: regulator@2 {
393 compatible = "regulator-fixed";
394 reg = <2>;
395 regulator-name = "vdd_ddr";
396 regulator-min-microvolt = <1500000>;
397 regulator-max-microvolt = <1500000>;
398 regulator-always-on;
399 regulator-boot-on;
400 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700401 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800402 vin-supply = <&vdd_5v_in_reg>;
403 };
404
405 vdd_5v_sata_reg: regulator@3 {
406 compatible = "regulator-fixed";
407 reg = <3>;
408 regulator-name = "vdd_5v_sata";
409 regulator-min-microvolt = <5000000>;
410 regulator-max-microvolt = <5000000>;
411 regulator-always-on;
412 regulator-boot-on;
413 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700414 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800415 vin-supply = <&vdd_5v_in_reg>;
416 };
417
418 usb1_vbus_reg: regulator@4 {
419 compatible = "regulator-fixed";
420 reg = <4>;
421 regulator-name = "usb1_vbus";
422 regulator-min-microvolt = <5000000>;
423 regulator-max-microvolt = <5000000>;
424 enable-active-high;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300425 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800426 gpio-open-drain;
427 vin-supply = <&vdd_5v_in_reg>;
428 };
429
430 usb3_vbus_reg: regulator@5 {
431 compatible = "regulator-fixed";
432 reg = <5>;
433 regulator-name = "usb3_vbus";
434 regulator-min-microvolt = <5000000>;
435 regulator-max-microvolt = <5000000>;
436 enable-active-high;
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300437 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800438 gpio-open-drain;
439 vin-supply = <&vdd_5v_in_reg>;
440 };
441
442 sys_3v3_reg: regulator@6 {
443 compatible = "regulator-fixed";
444 reg = <6>;
445 regulator-name = "sys_3v3,vdd_3v3_alw";
446 regulator-min-microvolt = <3300000>;
447 regulator-max-microvolt = <3300000>;
448 regulator-always-on;
449 regulator-boot-on;
450 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700451 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800452 vin-supply = <&vdd_5v_in_reg>;
453 };
454
455 sys_3v3_pexs_reg: regulator@7 {
456 compatible = "regulator-fixed";
457 reg = <7>;
458 regulator-name = "sys_3v3_pexs";
459 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>;
461 regulator-always-on;
462 regulator-boot-on;
463 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700464 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Bryan Wud7df69f2013-01-02 15:53:51 -0800465 vin-supply = <&sys_3v3_reg>;
466 };
467 };
Eric Browerb4dd3e02013-05-10 14:40:29 +0000468
Stephen Warren23037bb2013-03-27 16:53:20 -0600469 sound {
470 compatible = "nvidia,tegra-audio-rt5640-beaver",
471 "nvidia,tegra-audio-rt5640";
472 nvidia,model = "NVIDIA Tegra Beaver";
473
474 nvidia,audio-routing =
475 "Headphones", "HPOR",
Stephen Warrenac472282013-08-14 13:54:24 -0600476 "Headphones", "HPOL",
477 "Mic Jack", "MICBIAS1",
478 "IN2P", "Mic Jack";
Stephen Warren23037bb2013-03-27 16:53:20 -0600479
480 nvidia,i2s-controller = <&tegra_i2s1>;
481 nvidia,audio-codec = <&rt5640>;
482
483 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
484
485 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
486 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
487 <&tegra_car TEGRA30_CLK_EXTERN1>;
488 clock-names = "pll_a", "pll_a_out0", "mclk";
489 };
Bryan Wud7df69f2013-01-02 15:53:51 -0800490};