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Sean Wangf4ff2572017-07-31 15:36:42 +08001/*
2 * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7/dts-v1/;
8#include <dt-bindings/input/input.h>
9#include "mt7623.dtsi"
10#include "mt6323.dtsi"
11
12/ {
13 model = "Bananapi BPI-R2";
14 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
15
16 aliases {
17 serial2 = &uart2;
18 };
19
20 chosen {
21 stdout-path = "serial2:115200n8";
22 };
23
24 cpus {
25 cpu@0 {
26 proc-supply = <&mt6323_vproc_reg>;
27 };
28
29 cpu@1 {
30 proc-supply = <&mt6323_vproc_reg>;
31 };
32
33 cpu@2 {
34 proc-supply = <&mt6323_vproc_reg>;
35 };
36
37 cpu@3 {
38 proc-supply = <&mt6323_vproc_reg>;
39 };
40 };
41
Sean Wang528a97e2018-02-23 18:16:27 +080042 reg_1p8v: regulator-1p8v {
43 compatible = "regulator-fixed";
44 regulator-name = "fixed-1.8V";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 regulator-boot-on;
48 regulator-always-on;
49 };
50
Sean Wang0629a012018-02-23 18:16:26 +080051 reg_3p3v: regulator-3p3v {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-3.3V";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
60 reg_5v: regulator-5v {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-5V";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
65 regulator-boot-on;
66 regulator-always-on;
67 };
68
Sean Wang58b36962018-02-23 18:16:31 +080069 gpio-keys {
Sean Wangf4ff2572017-07-31 15:36:42 +080070 compatible = "gpio-keys";
71 pinctrl-names = "default";
72 pinctrl-0 = <&key_pins_a>;
73
74 factory {
75 label = "factory";
76 linux,code = <BTN_0>;
77 gpios = <&pio 256 GPIO_ACTIVE_LOW>;
78 };
79
80 wps {
81 label = "wps";
82 linux,code = <KEY_WPS_BUTTON>;
83 gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
84 };
85 };
86
87 leds {
88 compatible = "gpio-leds";
89 pinctrl-names = "default";
90 pinctrl-0 = <&led_pins_a>;
91
Ryder Leedfff5692017-08-04 11:59:35 +080092 blue {
93 label = "bpi-r2:pio:blue";
94 gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
Sean Wangf4ff2572017-07-31 15:36:42 +080095 default-state = "off";
96 };
97
98 green {
99 label = "bpi-r2:pio:green";
100 gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
101 default-state = "off";
102 };
103
Ryder Leedfff5692017-08-04 11:59:35 +0800104 red {
105 label = "bpi-r2:pio:red";
106 gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800107 default-state = "off";
108 };
109 };
110
111 memory@80000000 {
Sean Wangc0b0d542018-04-11 16:53:56 +0800112 device_type = "memory";
Sean Wangacf09962018-04-11 16:53:57 +0800113 reg = <0 0x80000000 0 0x80000000>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800114 };
115};
116
117&cir {
118 pinctrl-names = "default";
119 pinctrl-0 = <&cir_pins_a>;
120 status = "okay";
121};
122
123&crypto {
124 status = "okay";
125};
126
127&eth {
128 status = "okay";
Ryder Leedfff5692017-08-04 11:59:35 +0800129
Sean Wangf4ff2572017-07-31 15:36:42 +0800130 gmac0: mac@0 {
131 compatible = "mediatek,eth-mac";
132 reg = <0>;
133 phy-mode = "trgmii";
Ryder Leedfff5692017-08-04 11:59:35 +0800134
Sean Wangf4ff2572017-07-31 15:36:42 +0800135 fixed-link {
136 speed = <1000>;
137 full-duplex;
138 pause;
139 };
140 };
141
142 mdio: mdio-bus {
143 #address-cells = <1>;
144 #size-cells = <0>;
Ryder Leedfff5692017-08-04 11:59:35 +0800145
Sean Wangf4ff2572017-07-31 15:36:42 +0800146 switch@0 {
147 compatible = "mediatek,mt7530";
Sean Wangf4ff2572017-07-31 15:36:42 +0800148 reg = <0>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800149 reset-gpios = <&pio 33 0>;
150 core-supply = <&mt6323_vpa_reg>;
151 io-supply = <&mt6323_vemc3v3_reg>;
152
153 ports {
154 #address-cells = <1>;
155 #size-cells = <0>;
Ryder Leedfff5692017-08-04 11:59:35 +0800156
Sean Wangf4ff2572017-07-31 15:36:42 +0800157 port@0 {
158 reg = <0>;
159 label = "wan";
160 };
161
162 port@1 {
163 reg = <1>;
164 label = "lan0";
165 };
166
167 port@2 {
168 reg = <2>;
169 label = "lan1";
170 };
171
172 port@3 {
173 reg = <3>;
174 label = "lan2";
175 };
176
177 port@4 {
178 reg = <4>;
179 label = "lan3";
180 };
181
182 port@6 {
183 reg = <6>;
184 label = "cpu";
185 ethernet = <&gmac0>;
186 phy-mode = "trgmii";
Ryder Leedfff5692017-08-04 11:59:35 +0800187
Sean Wangf4ff2572017-07-31 15:36:42 +0800188 fixed-link {
189 speed = <1000>;
190 full-duplex;
191 };
192 };
193 };
194 };
195 };
196};
197
198&i2c0 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&i2c0_pins_a>;
201 status = "okay";
202};
203
204&i2c1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&i2c1_pins_a>;
207 status = "okay";
208};
209
Sean Wang0eed8d02017-08-04 11:59:34 +0800210&mmc0 {
211 pinctrl-names = "default", "state_uhs";
212 pinctrl-0 = <&mmc0_pins_default>;
213 pinctrl-1 = <&mmc0_pins_uhs>;
214 status = "okay";
215 bus-width = <8>;
216 max-frequency = <50000000>;
217 cap-mmc-highspeed;
Sean Wang528a97e2018-02-23 18:16:27 +0800218 vmmc-supply = <&reg_3p3v>;
219 vqmmc-supply = <&reg_1p8v>;
Sean Wang0eed8d02017-08-04 11:59:34 +0800220 non-removable;
221};
222
223&mmc1 {
224 pinctrl-names = "default", "state_uhs";
225 pinctrl-0 = <&mmc1_pins_default>;
226 pinctrl-1 = <&mmc1_pins_uhs>;
227 status = "okay";
228 bus-width = <4>;
229 max-frequency = <50000000>;
230 cap-sd-highspeed;
Sean Wangb96a6962017-12-07 14:43:24 +0800231 cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
Sean Wang528a97e2018-02-23 18:16:27 +0800232 vmmc-supply = <&reg_3p3v>;
233 vqmmc-supply = <&reg_3p3v>;
Sean Wang0eed8d02017-08-04 11:59:34 +0800234};
235
Ryder Leec10a98c2018-02-14 11:27:34 +0800236&pcie {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pcie_default>;
239 status = "okay";
240
241 pcie@0,0 {
242 status = "okay";
243 };
244
245 pcie@1,0 {
246 status = "okay";
247 };
248};
249
250&pcie0_phy {
251 status = "okay";
252};
253
254&pcie1_phy {
255 status = "okay";
256};
257
Sean Wangf4ff2572017-07-31 15:36:42 +0800258&pio {
Sean Wang1c8fadd2018-04-11 16:53:58 +0800259 cir_pins_a:cir-default {
Sean Wang58b36962018-02-23 18:16:31 +0800260 pins-cir {
Sean Wangf4ff2572017-07-31 15:36:42 +0800261 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
262 bias-disable;
263 };
264 };
265
Sean Wang1c8fadd2018-04-11 16:53:58 +0800266 i2c0_pins_a: i2c0-default {
Sean Wang58b36962018-02-23 18:16:31 +0800267 pins-i2c0 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800268 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
269 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
270 bias-disable;
271 };
272 };
273
Sean Wang1c8fadd2018-04-11 16:53:58 +0800274 i2c1_pins_a: i2c1-default {
Sean Wang58b36962018-02-23 18:16:31 +0800275 pin-i2c1 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800276 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
277 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
278 bias-disable;
279 };
280 };
281
Sean Wang1c8fadd2018-04-11 16:53:58 +0800282 i2s0_pins_a: i2s0-default {
Sean Wang58b36962018-02-23 18:16:31 +0800283 pin-i2s0 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800284 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
285 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
286 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
287 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
288 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
289 drive-strength = <MTK_DRIVE_12mA>;
290 bias-pull-down;
291 };
292 };
293
Sean Wang1c8fadd2018-04-11 16:53:58 +0800294 i2s1_pins_a: i2s1-default {
Sean Wang58b36962018-02-23 18:16:31 +0800295 pin-i2s1 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800296 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
297 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
298 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
299 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
300 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
301 drive-strength = <MTK_DRIVE_12mA>;
302 bias-pull-down;
303 };
304 };
305
Sean Wang1c8fadd2018-04-11 16:53:58 +0800306 key_pins_a: keys-alt {
Sean Wang58b36962018-02-23 18:16:31 +0800307 pins-keys {
Sean Wangf4ff2572017-07-31 15:36:42 +0800308 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
309 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
310 input-enable;
311 };
312 };
313
Sean Wang1c8fadd2018-04-11 16:53:58 +0800314 led_pins_a: leds-alt {
Sean Wang58b36962018-02-23 18:16:31 +0800315 pins-leds {
Sean Wangf4ff2572017-07-31 15:36:42 +0800316 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
317 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
318 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
319 };
320 };
321
322 mmc0_pins_default: mmc0default {
Sean Wang58b36962018-02-23 18:16:31 +0800323 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800324 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
325 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
326 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
327 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
328 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
329 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
330 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
331 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
332 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
333 input-enable;
334 bias-pull-up;
335 };
336
Sean Wang58b36962018-02-23 18:16:31 +0800337 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800338 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
339 bias-pull-down;
340 };
341
Sean Wang58b36962018-02-23 18:16:31 +0800342 pins-rst {
Sean Wangf4ff2572017-07-31 15:36:42 +0800343 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
344 bias-pull-up;
345 };
346 };
347
348 mmc0_pins_uhs: mmc0 {
Sean Wang58b36962018-02-23 18:16:31 +0800349 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800350 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
351 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
352 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
353 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
354 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
355 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
356 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
357 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
358 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
359 input-enable;
360 drive-strength = <MTK_DRIVE_2mA>;
361 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
362 };
363
Sean Wang58b36962018-02-23 18:16:31 +0800364 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800365 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
366 drive-strength = <MTK_DRIVE_2mA>;
367 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
368 };
369
Sean Wang58b36962018-02-23 18:16:31 +0800370 pins-rst {
Sean Wangf4ff2572017-07-31 15:36:42 +0800371 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
372 bias-pull-up;
373 };
374 };
375
376 mmc1_pins_default: mmc1default {
Sean Wang58b36962018-02-23 18:16:31 +0800377 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800378 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
379 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
380 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
381 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
382 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
383 input-enable;
384 drive-strength = <MTK_DRIVE_4mA>;
385 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
386 };
387
Sean Wang58b36962018-02-23 18:16:31 +0800388 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800389 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
390 bias-pull-down;
391 drive-strength = <MTK_DRIVE_4mA>;
392 };
Sean Wang0eed8d02017-08-04 11:59:34 +0800393
Sean Wang58b36962018-02-23 18:16:31 +0800394 pins-wp {
Sean Wang0eed8d02017-08-04 11:59:34 +0800395 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
396 input-enable;
397 bias-pull-up;
398 };
399
Sean Wang58b36962018-02-23 18:16:31 +0800400 pins-insert {
Sean Wang0eed8d02017-08-04 11:59:34 +0800401 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
402 bias-pull-up;
403 };
Sean Wangf4ff2572017-07-31 15:36:42 +0800404 };
405
406 mmc1_pins_uhs: mmc1 {
Sean Wang58b36962018-02-23 18:16:31 +0800407 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800408 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
409 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
410 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
411 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
412 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
413 input-enable;
414 drive-strength = <MTK_DRIVE_4mA>;
415 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
416 };
417
Sean Wang58b36962018-02-23 18:16:31 +0800418 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800419 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
420 drive-strength = <MTK_DRIVE_4mA>;
421 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
422 };
423 };
424
Ryder Leec10a98c2018-02-14 11:27:34 +0800425 pcie_default: pcie_pin_default {
426 pins_cmd_dat {
427 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
428 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
429 bias-disable;
430 };
431 };
432
Sean Wang1c8fadd2018-04-11 16:53:58 +0800433 pwm_pins_a: pwm-default {
Sean Wang58b36962018-02-23 18:16:31 +0800434 pins-pwm {
Sean Wangf4ff2572017-07-31 15:36:42 +0800435 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
436 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
437 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
438 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
439 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
440 };
441 };
442
Sean Wang1c8fadd2018-04-11 16:53:58 +0800443 spi0_pins_a: spi0-default {
Sean Wang58b36962018-02-23 18:16:31 +0800444 pins-spi {
Ryder Leedfff5692017-08-04 11:59:35 +0800445 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
446 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
447 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
448 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
449 bias-disable;
450 };
451 };
452
Sean Wang1c8fadd2018-04-11 16:53:58 +0800453 uart0_pins_a: uart0-default {
Sean Wang58b36962018-02-23 18:16:31 +0800454 pins-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800455 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
456 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
457 };
458 };
459
Sean Wang1c8fadd2018-04-11 16:53:58 +0800460 uart1_pins_a: uart1-default {
Sean Wang58b36962018-02-23 18:16:31 +0800461 pins-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800462 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
463 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
464 };
465 };
Sean Wangcc2f6522018-02-23 18:16:28 +0800466
Sean Wang1c8fadd2018-04-11 16:53:58 +0800467 uart2_pins_a: uart2-default {
Sean Wang58b36962018-02-23 18:16:31 +0800468 pins-dat {
Sean Wangcc2f6522018-02-23 18:16:28 +0800469 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
470 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
471 };
472 };
Sean Wangf4ff2572017-07-31 15:36:42 +0800473};
474
475&pwm {
476 pinctrl-names = "default";
477 pinctrl-0 = <&pwm_pins_a>;
478 status = "okay";
479};
480
481&pwrap {
482 mt6323 {
483 mt6323led: led {
484 compatible = "mediatek,mt6323-led";
485 #address-cells = <1>;
486 #size-cells = <0>;
487
488 led@0 {
489 reg = <0>;
490 label = "bpi-r2:isink:green";
491 default-state = "off";
492 };
Ryder Leedfff5692017-08-04 11:59:35 +0800493
Sean Wangf4ff2572017-07-31 15:36:42 +0800494 led@1 {
495 reg = <1>;
496 label = "bpi-r2:isink:red";
497 default-state = "off";
498 };
Ryder Leedfff5692017-08-04 11:59:35 +0800499
Sean Wangf4ff2572017-07-31 15:36:42 +0800500 led@2 {
501 reg = <2>;
502 label = "bpi-r2:isink:blue";
503 default-state = "off";
504 };
505 };
506 };
507};
508
509&spi0 {
510 pinctrl-names = "default";
511 pinctrl-0 = <&spi0_pins_a>;
512 status = "okay";
513};
514
515&uart0 {
516 pinctrl-names = "default";
517 pinctrl-0 = <&uart0_pins_a>;
Sean Wangcc2f6522018-02-23 18:16:28 +0800518 status = "okay";
Sean Wangf4ff2572017-07-31 15:36:42 +0800519};
520
Sean Wangf4ff2572017-07-31 15:36:42 +0800521&uart1 {
522 pinctrl-names = "default";
523 pinctrl-0 = <&uart1_pins_a>;
Sean Wangcc2f6522018-02-23 18:16:28 +0800524 status = "okay";
Sean Wangf4ff2572017-07-31 15:36:42 +0800525};
526
527&uart2 {
Sean Wangcc2f6522018-02-23 18:16:28 +0800528 pinctrl-names = "default";
529 pinctrl-0 = <&uart2_pins_a>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800530 status = "okay";
531};
532
533&usb1 {
Sean Wang0629a012018-02-23 18:16:26 +0800534 vusb33-supply = <&reg_3p3v>;
535 vbus-supply = <&reg_5v>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800536 status = "okay";
537};
538
539&usb2 {
Sean Wang0629a012018-02-23 18:16:26 +0800540 vusb33-supply = <&reg_3p3v>;
541 vbus-supply = <&reg_5v>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800542 status = "okay";
543};
Ryder Leedfff5692017-08-04 11:59:35 +0800544
545&u3phy1 {
546 status = "okay";
547};
548
549&u3phy2 {
550 status = "okay";
551};
552