blob: d2a354e0b9a65b8c5c150ed2f3d43b20fe70f205 [file] [log] [blame]
Sean Wangf4ff2572017-07-31 15:36:42 +08001/*
2 * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7/dts-v1/;
8#include <dt-bindings/input/input.h>
9#include "mt7623.dtsi"
10#include "mt6323.dtsi"
11
12/ {
13 model = "Bananapi BPI-R2";
14 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
15
16 aliases {
17 serial2 = &uart2;
18 };
19
20 chosen {
21 stdout-path = "serial2:115200n8";
22 };
23
24 cpus {
25 cpu@0 {
26 proc-supply = <&mt6323_vproc_reg>;
27 };
28
29 cpu@1 {
30 proc-supply = <&mt6323_vproc_reg>;
31 };
32
33 cpu@2 {
34 proc-supply = <&mt6323_vproc_reg>;
35 };
36
37 cpu@3 {
38 proc-supply = <&mt6323_vproc_reg>;
39 };
40 };
41
Sean Wang528a97e2018-02-23 18:16:27 +080042 reg_1p8v: regulator-1p8v {
43 compatible = "regulator-fixed";
44 regulator-name = "fixed-1.8V";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 regulator-boot-on;
48 regulator-always-on;
49 };
50
Sean Wang0629a012018-02-23 18:16:26 +080051 reg_3p3v: regulator-3p3v {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-3.3V";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
60 reg_5v: regulator-5v {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-5V";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
65 regulator-boot-on;
66 regulator-always-on;
67 };
68
Sean Wang58b36962018-02-23 18:16:31 +080069 gpio-keys {
Sean Wangf4ff2572017-07-31 15:36:42 +080070 compatible = "gpio-keys";
71 pinctrl-names = "default";
72 pinctrl-0 = <&key_pins_a>;
73
74 factory {
75 label = "factory";
76 linux,code = <BTN_0>;
77 gpios = <&pio 256 GPIO_ACTIVE_LOW>;
78 };
79
80 wps {
81 label = "wps";
82 linux,code = <KEY_WPS_BUTTON>;
83 gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
84 };
85 };
86
87 leds {
88 compatible = "gpio-leds";
89 pinctrl-names = "default";
90 pinctrl-0 = <&led_pins_a>;
91
Ryder Leedfff5692017-08-04 11:59:35 +080092 blue {
93 label = "bpi-r2:pio:blue";
94 gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
Sean Wangf4ff2572017-07-31 15:36:42 +080095 default-state = "off";
96 };
97
98 green {
99 label = "bpi-r2:pio:green";
100 gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
101 default-state = "off";
102 };
103
Ryder Leedfff5692017-08-04 11:59:35 +0800104 red {
105 label = "bpi-r2:pio:red";
106 gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800107 default-state = "off";
108 };
109 };
110
111 memory@80000000 {
Sean Wangc0b0d542018-04-11 16:53:56 +0800112 device_type = "memory";
Sean Wangacf09962018-04-11 16:53:57 +0800113 reg = <0 0x80000000 0 0x80000000>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800114 };
115};
116
117&cir {
118 pinctrl-names = "default";
119 pinctrl-0 = <&cir_pins_a>;
120 status = "okay";
121};
122
123&crypto {
124 status = "okay";
125};
126
127&eth {
128 status = "okay";
Ryder Leedfff5692017-08-04 11:59:35 +0800129
Sean Wangf4ff2572017-07-31 15:36:42 +0800130 gmac0: mac@0 {
131 compatible = "mediatek,eth-mac";
132 reg = <0>;
133 phy-mode = "trgmii";
Ryder Leedfff5692017-08-04 11:59:35 +0800134
Sean Wangf4ff2572017-07-31 15:36:42 +0800135 fixed-link {
136 speed = <1000>;
137 full-duplex;
138 pause;
139 };
140 };
141
142 mdio: mdio-bus {
143 #address-cells = <1>;
144 #size-cells = <0>;
Ryder Leedfff5692017-08-04 11:59:35 +0800145
Sean Wangf4ff2572017-07-31 15:36:42 +0800146 switch@0 {
147 compatible = "mediatek,mt7530";
148 #address-cells = <1>;
149 #size-cells = <0>;
150 reg = <0>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800151 reset-gpios = <&pio 33 0>;
152 core-supply = <&mt6323_vpa_reg>;
153 io-supply = <&mt6323_vemc3v3_reg>;
154
155 ports {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0>;
Ryder Leedfff5692017-08-04 11:59:35 +0800159
Sean Wangf4ff2572017-07-31 15:36:42 +0800160 port@0 {
161 reg = <0>;
162 label = "wan";
163 };
164
165 port@1 {
166 reg = <1>;
167 label = "lan0";
168 };
169
170 port@2 {
171 reg = <2>;
172 label = "lan1";
173 };
174
175 port@3 {
176 reg = <3>;
177 label = "lan2";
178 };
179
180 port@4 {
181 reg = <4>;
182 label = "lan3";
183 };
184
185 port@6 {
186 reg = <6>;
187 label = "cpu";
188 ethernet = <&gmac0>;
189 phy-mode = "trgmii";
Ryder Leedfff5692017-08-04 11:59:35 +0800190
Sean Wangf4ff2572017-07-31 15:36:42 +0800191 fixed-link {
192 speed = <1000>;
193 full-duplex;
194 };
195 };
196 };
197 };
198 };
199};
200
201&i2c0 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&i2c0_pins_a>;
204 status = "okay";
205};
206
207&i2c1 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c1_pins_a>;
210 status = "okay";
211};
212
Sean Wang0eed8d02017-08-04 11:59:34 +0800213&mmc0 {
214 pinctrl-names = "default", "state_uhs";
215 pinctrl-0 = <&mmc0_pins_default>;
216 pinctrl-1 = <&mmc0_pins_uhs>;
217 status = "okay";
218 bus-width = <8>;
219 max-frequency = <50000000>;
220 cap-mmc-highspeed;
Sean Wang528a97e2018-02-23 18:16:27 +0800221 vmmc-supply = <&reg_3p3v>;
222 vqmmc-supply = <&reg_1p8v>;
Sean Wang0eed8d02017-08-04 11:59:34 +0800223 non-removable;
224};
225
226&mmc1 {
227 pinctrl-names = "default", "state_uhs";
228 pinctrl-0 = <&mmc1_pins_default>;
229 pinctrl-1 = <&mmc1_pins_uhs>;
230 status = "okay";
231 bus-width = <4>;
232 max-frequency = <50000000>;
233 cap-sd-highspeed;
Sean Wangb96a6962017-12-07 14:43:24 +0800234 cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
Sean Wang528a97e2018-02-23 18:16:27 +0800235 vmmc-supply = <&reg_3p3v>;
236 vqmmc-supply = <&reg_3p3v>;
Sean Wang0eed8d02017-08-04 11:59:34 +0800237};
238
Ryder Leec10a98c2018-02-14 11:27:34 +0800239&pcie {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pcie_default>;
242 status = "okay";
243
244 pcie@0,0 {
245 status = "okay";
246 };
247
248 pcie@1,0 {
249 status = "okay";
250 };
251};
252
253&pcie0_phy {
254 status = "okay";
255};
256
257&pcie1_phy {
258 status = "okay";
259};
260
Sean Wangf4ff2572017-07-31 15:36:42 +0800261&pio {
262 cir_pins_a:cir@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800263 pins-cir {
Sean Wangf4ff2572017-07-31 15:36:42 +0800264 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
265 bias-disable;
266 };
267 };
268
269 i2c0_pins_a: i2c@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800270 pins-i2c0 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800271 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
272 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
273 bias-disable;
274 };
275 };
276
277 i2c1_pins_a: i2c@1 {
Sean Wang58b36962018-02-23 18:16:31 +0800278 pin-i2c1 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800279 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
280 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
281 bias-disable;
282 };
283 };
284
285 i2s0_pins_a: i2s@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800286 pin-i2s0 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800287 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
288 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
289 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
290 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
291 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
292 drive-strength = <MTK_DRIVE_12mA>;
293 bias-pull-down;
294 };
295 };
296
297 i2s1_pins_a: i2s@1 {
Sean Wang58b36962018-02-23 18:16:31 +0800298 pin-i2s1 {
Sean Wangf4ff2572017-07-31 15:36:42 +0800299 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
300 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
301 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
302 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
303 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
304 drive-strength = <MTK_DRIVE_12mA>;
305 bias-pull-down;
306 };
307 };
308
309 key_pins_a: keys@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800310 pins-keys {
Sean Wangf4ff2572017-07-31 15:36:42 +0800311 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
312 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
313 input-enable;
314 };
315 };
316
317 led_pins_a: leds@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800318 pins-leds {
Sean Wangf4ff2572017-07-31 15:36:42 +0800319 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
320 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
321 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
322 };
323 };
324
325 mmc0_pins_default: mmc0default {
Sean Wang58b36962018-02-23 18:16:31 +0800326 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800327 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
328 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
329 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
330 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
331 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
332 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
333 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
334 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
335 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
336 input-enable;
337 bias-pull-up;
338 };
339
Sean Wang58b36962018-02-23 18:16:31 +0800340 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800341 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
342 bias-pull-down;
343 };
344
Sean Wang58b36962018-02-23 18:16:31 +0800345 pins-rst {
Sean Wangf4ff2572017-07-31 15:36:42 +0800346 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
347 bias-pull-up;
348 };
349 };
350
351 mmc0_pins_uhs: mmc0 {
Sean Wang58b36962018-02-23 18:16:31 +0800352 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800353 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
354 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
355 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
356 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
357 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
358 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
359 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
360 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
361 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
362 input-enable;
363 drive-strength = <MTK_DRIVE_2mA>;
364 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
365 };
366
Sean Wang58b36962018-02-23 18:16:31 +0800367 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800368 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
369 drive-strength = <MTK_DRIVE_2mA>;
370 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
371 };
372
Sean Wang58b36962018-02-23 18:16:31 +0800373 pins-rst {
Sean Wangf4ff2572017-07-31 15:36:42 +0800374 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
375 bias-pull-up;
376 };
377 };
378
379 mmc1_pins_default: mmc1default {
Sean Wang58b36962018-02-23 18:16:31 +0800380 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800381 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
382 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
383 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
384 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
385 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
386 input-enable;
387 drive-strength = <MTK_DRIVE_4mA>;
388 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
389 };
390
Sean Wang58b36962018-02-23 18:16:31 +0800391 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800392 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
393 bias-pull-down;
394 drive-strength = <MTK_DRIVE_4mA>;
395 };
Sean Wang0eed8d02017-08-04 11:59:34 +0800396
Sean Wang58b36962018-02-23 18:16:31 +0800397 pins-wp {
Sean Wang0eed8d02017-08-04 11:59:34 +0800398 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
399 input-enable;
400 bias-pull-up;
401 };
402
Sean Wang58b36962018-02-23 18:16:31 +0800403 pins-insert {
Sean Wang0eed8d02017-08-04 11:59:34 +0800404 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
405 bias-pull-up;
406 };
Sean Wangf4ff2572017-07-31 15:36:42 +0800407 };
408
409 mmc1_pins_uhs: mmc1 {
Sean Wang58b36962018-02-23 18:16:31 +0800410 pins-cmd-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800411 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
412 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
413 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
414 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
415 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
416 input-enable;
417 drive-strength = <MTK_DRIVE_4mA>;
418 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
419 };
420
Sean Wang58b36962018-02-23 18:16:31 +0800421 pins-clk {
Sean Wangf4ff2572017-07-31 15:36:42 +0800422 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
423 drive-strength = <MTK_DRIVE_4mA>;
424 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
425 };
426 };
427
Ryder Leec10a98c2018-02-14 11:27:34 +0800428 pcie_default: pcie_pin_default {
429 pins_cmd_dat {
430 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
431 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
432 bias-disable;
433 };
434 };
435
Sean Wangf4ff2572017-07-31 15:36:42 +0800436 pwm_pins_a: pwm@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800437 pins-pwm {
Sean Wangf4ff2572017-07-31 15:36:42 +0800438 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
439 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
440 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
441 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
442 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
443 };
444 };
445
Ryder Leedfff5692017-08-04 11:59:35 +0800446 spi0_pins_a: spi@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800447 pins-spi {
Ryder Leedfff5692017-08-04 11:59:35 +0800448 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
449 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
450 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
451 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
452 bias-disable;
453 };
454 };
455
Sean Wangf4ff2572017-07-31 15:36:42 +0800456 uart0_pins_a: uart@0 {
Sean Wang58b36962018-02-23 18:16:31 +0800457 pins-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800458 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
459 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
460 };
461 };
462
463 uart1_pins_a: uart@1 {
Sean Wang58b36962018-02-23 18:16:31 +0800464 pins-dat {
Sean Wangf4ff2572017-07-31 15:36:42 +0800465 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
466 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
467 };
468 };
Sean Wangcc2f6522018-02-23 18:16:28 +0800469
470 uart2_pins_a: uart@2 {
Sean Wang58b36962018-02-23 18:16:31 +0800471 pins-dat {
Sean Wangcc2f6522018-02-23 18:16:28 +0800472 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
473 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
474 };
475 };
Sean Wangf4ff2572017-07-31 15:36:42 +0800476};
477
478&pwm {
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm_pins_a>;
481 status = "okay";
482};
483
484&pwrap {
485 mt6323 {
486 mt6323led: led {
487 compatible = "mediatek,mt6323-led";
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 led@0 {
492 reg = <0>;
493 label = "bpi-r2:isink:green";
494 default-state = "off";
495 };
Ryder Leedfff5692017-08-04 11:59:35 +0800496
Sean Wangf4ff2572017-07-31 15:36:42 +0800497 led@1 {
498 reg = <1>;
499 label = "bpi-r2:isink:red";
500 default-state = "off";
501 };
Ryder Leedfff5692017-08-04 11:59:35 +0800502
Sean Wangf4ff2572017-07-31 15:36:42 +0800503 led@2 {
504 reg = <2>;
505 label = "bpi-r2:isink:blue";
506 default-state = "off";
507 };
508 };
509 };
510};
511
512&spi0 {
513 pinctrl-names = "default";
514 pinctrl-0 = <&spi0_pins_a>;
515 status = "okay";
516};
517
518&uart0 {
519 pinctrl-names = "default";
520 pinctrl-0 = <&uart0_pins_a>;
Sean Wangcc2f6522018-02-23 18:16:28 +0800521 status = "okay";
Sean Wangf4ff2572017-07-31 15:36:42 +0800522};
523
Sean Wangf4ff2572017-07-31 15:36:42 +0800524&uart1 {
525 pinctrl-names = "default";
526 pinctrl-0 = <&uart1_pins_a>;
Sean Wangcc2f6522018-02-23 18:16:28 +0800527 status = "okay";
Sean Wangf4ff2572017-07-31 15:36:42 +0800528};
529
530&uart2 {
Sean Wangcc2f6522018-02-23 18:16:28 +0800531 pinctrl-names = "default";
532 pinctrl-0 = <&uart2_pins_a>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800533 status = "okay";
534};
535
536&usb1 {
Sean Wang0629a012018-02-23 18:16:26 +0800537 vusb33-supply = <&reg_3p3v>;
538 vbus-supply = <&reg_5v>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800539 status = "okay";
540};
541
542&usb2 {
Sean Wang0629a012018-02-23 18:16:26 +0800543 vusb33-supply = <&reg_3p3v>;
544 vbus-supply = <&reg_5v>;
Sean Wangf4ff2572017-07-31 15:36:42 +0800545 status = "okay";
546};
Ryder Leedfff5692017-08-04 11:59:35 +0800547
548&u3phy1 {
549 status = "okay";
550};
551
552&u3phy2 {
553 status = "okay";
554};
555