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gerrit-public.fairphone.software / kernel / msm-5.4 / ba4104e79470ae848a9f38029fe1371790dc0df9 / . / arch / arm / boot / dts / tegra20-harmony.dts
blob: b02653da8bd7ea1ac36f875be84b38ac29877073 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]3#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]4#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]5
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +0000[diff] [blame]7 model = "NVIDIA Tegra20 Harmony evaluation board";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]8 compatible = "nvidia,harmony", "nvidia,tegra20";
9
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]10 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]11 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]12 };
13
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]14 host1x@50000000 {
15 hdmi@54280000 {
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]16 status = "okay";
17
18 vdd-supply = <&hdmi_vdd_reg>;
19 pll-supply = <&hdmi_pll_reg>;
20
21 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]22 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 GPIO_ACTIVE_HIGH>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]24 };
25 };
26
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]27 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 ata {
33 nvidia,pins = "ata";
34 nvidia,function = "ide";
35 };
36 atb {
37 nvidia,pins = "atb", "gma", "gme";
38 nvidia,function = "sdio4";
39 };
40 atc {
41 nvidia,pins = "atc";
42 nvidia,function = "nand";
43 };
44 atd {
45 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
46 "spia", "spib", "spic";
47 nvidia,function = "gmi";
48 };
49 cdev1 {
50 nvidia,pins = "cdev1";
51 nvidia,function = "plla_out";
52 };
53 cdev2 {
54 nvidia,pins = "cdev2";
55 nvidia,function = "pllp_out4";
56 };
57 crtp {
58 nvidia,pins = "crtp";
59 nvidia,function = "crt";
60 };
61 csus {
62 nvidia,pins = "csus";
63 nvidia,function = "vi_sensor_clk";
64 };
65 dap1 {
66 nvidia,pins = "dap1";
67 nvidia,function = "dap1";
68 };
69 dap2 {
70 nvidia,pins = "dap2";
71 nvidia,function = "dap2";
72 };
73 dap3 {
74 nvidia,pins = "dap3";
75 nvidia,function = "dap3";
76 };
77 dap4 {
78 nvidia,pins = "dap4";
79 nvidia,function = "dap4";
80 };
81 ddc {
82 nvidia,pins = "ddc";
83 nvidia,function = "i2c2";
84 };
85 dta {
86 nvidia,pins = "dta", "dtd";
87 nvidia,function = "sdio2";
88 };
89 dtb {
90 nvidia,pins = "dtb", "dtc", "dte";
91 nvidia,function = "rsvd1";
92 };
93 dtf {
94 nvidia,pins = "dtf";
95 nvidia,function = "i2c3";
96 };
97 gmc {
98 nvidia,pins = "gmc";
99 nvidia,function = "uartd";
100 };
101 gpu7 {
102 nvidia,pins = "gpu7";
103 nvidia,function = "rtck";
104 };
105 gpv {
106 nvidia,pins = "gpv", "slxa", "slxk";
107 nvidia,function = "pcie";
108 };
109 hdint {
110 nvidia,pins = "hdint", "pta";
111 nvidia,function = "hdmi";
112 };
113 i2cp {
114 nvidia,pins = "i2cp";
115 nvidia,function = "i2cp";
116 };
117 irrx {
118 nvidia,pins = "irrx", "irtx";
119 nvidia,function = "uarta";
120 };
121 kbca {
122 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
123 "kbce", "kbcf";
124 nvidia,function = "kbc";
125 };
126 lcsn {
127 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
128 "ld3", "ld4", "ld5", "ld6", "ld7",
129 "ld8", "ld9", "ld10", "ld11", "ld12",
130 "ld13", "ld14", "ld15", "ld16", "ld17",
131 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
132 "lhs", "lm0", "lm1", "lpp", "lpw0",
133 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
134 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
135 "lvs";
136 nvidia,function = "displaya";
137 };
138 owc {
139 nvidia,pins = "owc", "spdi", "spdo", "uac";
140 nvidia,function = "rsvd2";
141 };
142 pmc {
143 nvidia,pins = "pmc";
144 nvidia,function = "pwr_on";
145 };
146 rm {
147 nvidia,pins = "rm";
148 nvidia,function = "i2c1";
149 };
150 sdb {
151 nvidia,pins = "sdb", "sdc", "sdd";
152 nvidia,function = "pwm";
153 };
154 sdio1 {
155 nvidia,pins = "sdio1";
156 nvidia,function = "sdio1";
157 };
158 slxc {
159 nvidia,pins = "slxc", "slxd";
160 nvidia,function = "spdif";
161 };
162 spid {
163 nvidia,pins = "spid", "spie", "spif";
164 nvidia,function = "spi1";
165 };
166 spig {
167 nvidia,pins = "spig", "spih";
168 nvidia,function = "spi2_alt";
169 };
170 uaa {
171 nvidia,pins = "uaa", "uab", "uda";
172 nvidia,function = "ulpi";
173 };
174 uad {
175 nvidia,pins = "uad";
176 nvidia,function = "irda";
177 };
178 uca {
179 nvidia,pins = "uca", "ucb";
180 nvidia,function = "uartc";
181 };
182 conf_ata {
183 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]184 "cdev1", "cdev2", "dap1", "dtb", "gma",
185 "gmb", "gmc", "gmd", "gme", "gpu7",
186 "gpv", "i2cp", "pta", "rm", "slxa",
187 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]188 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
189 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]190 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]191 conf_ck32 {
192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]194 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]195 };
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]196 conf_csus {
197 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]198 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]200 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]201 conf_crtp {
202 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
203 "dtc", "dte", "dtf", "gpu", "sdio1",
204 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]205 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]208 };
209 conf_ddc {
210 nvidia,pins = "ddc", "dta", "dtd", "kbca",
211 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
212 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]213 nvidia,pull = <TEGRA_PIN_PULL_UP>;
214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]215 };
216 conf_hdint {
217 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
218 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
219 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]221 };
222 conf_irrx {
223 nvidia,pins = "irrx", "irtx", "sdd", "spic",
224 "spie", "spih", "uaa", "uab", "uad",
225 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
227 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]228 };
229 conf_lc {
230 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]232 };
233 conf_ld0 {
234 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
235 "ld5", "ld6", "ld7", "ld8", "ld9",
236 "ld10", "ld11", "ld12", "ld13", "ld14",
237 "ld15", "ld16", "ld17", "ldi", "lhp0",
238 "lhp1", "lhp2", "lhs", "lm0", "lpp",
239 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
240 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]242 };
243 conf_ld17_0 {
244 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
245 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame^]246 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]247 };
248 };
249 };
250
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]251 i2s@70002800 {
252 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]253 };
254
255 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]256 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]257 };
258
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]259 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]260 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]261 clock-frequency = <400000>;
262
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]263 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]264 compatible = "wlf,wm8903";
265 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]266 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]267 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]268
269 gpio-controller;
270 #gpio-cells = <2>;
271
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]272 micdet-cfg = <0>;
273 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]274 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]275 };
276 };
277
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]278 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]279 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]280 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]281 };
282
283 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]284 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]285 clock-frequency = <400000>;
286 };
287
288 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]289 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]290 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]291
292 pmic: tps6586x@34 {
293 compatible = "ti,tps6586x";
294 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]295 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]296
Stephen Warrenbe972c32012-09-11 11:40:04 -0600[diff] [blame]297 ti,system-power-controller;
298
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]299 #gpio-cells = <2>;
300 gpio-controller;
301
302 sys-supply = <&vdd_5v0_reg>;
303 vin-sm0-supply = <&sys_reg>;
304 vin-sm1-supply = <&sys_reg>;
305 vin-sm2-supply = <&sys_reg>;
306 vinldo01-supply = <&sm2_reg>;
307 vinldo23-supply = <&sm2_reg>;
308 vinldo4-supply = <&sm2_reg>;
309 vinldo678-supply = <&sm2_reg>;
310 vinldo9-supply = <&sm2_reg>;
311
312 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]313 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]314 regulator-name = "vdd_sys";
315 regulator-always-on;
316 };
317
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]318 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]319 regulator-name = "vdd_sm0,vdd_core";
320 regulator-min-microvolt = <1200000>;
321 regulator-max-microvolt = <1200000>;
322 regulator-always-on;
323 };
324
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]325 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]326 regulator-name = "vdd_sm1,vdd_cpu";
327 regulator-min-microvolt = <1000000>;
328 regulator-max-microvolt = <1000000>;
329 regulator-always-on;
330 };
331
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]332 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]333 regulator-name = "vdd_sm2,vin_ldo*";
334 regulator-min-microvolt = <3700000>;
335 regulator-max-microvolt = <3700000>;
336 regulator-always-on;
337 };
338
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]339 pci_clk_reg: ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]340 regulator-name = "vdd_ldo0,vddio_pex_clk";
341 regulator-min-microvolt = <3300000>;
342 regulator-max-microvolt = <3300000>;
343 };
344
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]345 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]346 regulator-name = "vdd_ldo1,avdd_pll*";
347 regulator-min-microvolt = <1100000>;
348 regulator-max-microvolt = <1100000>;
349 regulator-always-on;
350 };
351
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]352 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]353 regulator-name = "vdd_ldo2,vdd_rtc";
354 regulator-min-microvolt = <1200000>;
355 regulator-max-microvolt = <1200000>;
356 };
357
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]358 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]359 regulator-name = "vdd_ldo3,avdd_usb*";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 regulator-always-on;
363 };
364
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]365 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]366 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
367 regulator-min-microvolt = <1800000>;
368 regulator-max-microvolt = <1800000>;
369 regulator-always-on;
370 };
371
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]372 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]373 regulator-name = "vdd_ldo5,vcore_mmc";
374 regulator-min-microvolt = <2850000>;
375 regulator-max-microvolt = <2850000>;
376 regulator-always-on;
377 };
378
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]379 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]380 regulator-name = "vdd_ldo6,avdd_vdac";
381 regulator-min-microvolt = <1800000>;
382 regulator-max-microvolt = <1800000>;
383 };
384
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]385 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600[diff] [blame]386 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]387 regulator-min-microvolt = <3300000>;
388 regulator-max-microvolt = <3300000>;
389 };
390
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]391 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]392 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
393 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <1800000>;
395 };
396
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]397 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]398 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
399 regulator-min-microvolt = <2850000>;
400 regulator-max-microvolt = <2850000>;
401 regulator-always-on;
402 };
403
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]404 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]405 regulator-name = "vdd_rtc_out,vdd_cell";
406 regulator-min-microvolt = <3300000>;
407 regulator-max-microvolt = <3300000>;
408 regulator-always-on;
409 };
410 };
411 };
Thierry Reding42d25342012-11-09 22:58:43 +0100[diff] [blame]412
413 temperature-sensor@4c {
414 compatible = "adi,adt7461";
415 reg = <0x4c>;
416 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]417 };
418
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]419 kbc@7000e200 {
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]420 status = "okay";
421 nvidia,debounce-delay-ms = <2>;
422 nvidia,repeat-delay-ms = <160>;
423 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
424 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]425 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
426 MATRIX_KEY(0x00, 0x03, KEY_S)
427 MATRIX_KEY(0x00, 0x04, KEY_A)
428 MATRIX_KEY(0x00, 0x05, KEY_Z)
429 MATRIX_KEY(0x00, 0x07, KEY_FN)
430 MATRIX_KEY(0x01, 0x07, KEY_MENU)
431 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
432 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
433 MATRIX_KEY(0x03, 0x00, KEY_5)
434 MATRIX_KEY(0x03, 0x01, KEY_4)
435 MATRIX_KEY(0x03, 0x02, KEY_R)
436 MATRIX_KEY(0x03, 0x03, KEY_E)
437 MATRIX_KEY(0x03, 0x04, KEY_F)
438 MATRIX_KEY(0x03, 0x05, KEY_D)
439 MATRIX_KEY(0x03, 0x06, KEY_X)
440 MATRIX_KEY(0x04, 0x00, KEY_7)
441 MATRIX_KEY(0x04, 0x01, KEY_6)
442 MATRIX_KEY(0x04, 0x02, KEY_T)
443 MATRIX_KEY(0x04, 0x03, KEY_H)
444 MATRIX_KEY(0x04, 0x04, KEY_G)
445 MATRIX_KEY(0x04, 0x05, KEY_V)
446 MATRIX_KEY(0x04, 0x06, KEY_C)
447 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
448 MATRIX_KEY(0x05, 0x00, KEY_9)
449 MATRIX_KEY(0x05, 0x01, KEY_8)
450 MATRIX_KEY(0x05, 0x02, KEY_U)
451 MATRIX_KEY(0x05, 0x03, KEY_Y)
452 MATRIX_KEY(0x05, 0x04, KEY_J)
453 MATRIX_KEY(0x05, 0x05, KEY_N)
454 MATRIX_KEY(0x05, 0x06, KEY_B)
455 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
456 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
457 MATRIX_KEY(0x06, 0x01, KEY_0)
458 MATRIX_KEY(0x06, 0x02, KEY_O)
459 MATRIX_KEY(0x06, 0x03, KEY_I)
460 MATRIX_KEY(0x06, 0x04, KEY_L)
461 MATRIX_KEY(0x06, 0x05, KEY_K)
462 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
463 MATRIX_KEY(0x06, 0x07, KEY_M)
464 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
465 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
466 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
467 MATRIX_KEY(0x07, 0x07, KEY_MENU)
468 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
469 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
470 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
471 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
472 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
473 MATRIX_KEY(0x0B, 0x01, KEY_P)
474 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
475 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
476 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
477 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
478 MATRIX_KEY(0x0C, 0x00, KEY_F10)
479 MATRIX_KEY(0x0C, 0x01, KEY_F9)
480 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
481 MATRIX_KEY(0x0C, 0x03, KEY_3)
482 MATRIX_KEY(0x0C, 0x04, KEY_2)
483 MATRIX_KEY(0x0C, 0x05, KEY_UP)
484 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
485 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
486 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
487 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
488 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
489 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
490 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
491 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
492 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
493 MATRIX_KEY(0x0E, 0x00, KEY_F11)
494 MATRIX_KEY(0x0E, 0x01, KEY_F12)
495 MATRIX_KEY(0x0E, 0x02, KEY_F8)
496 MATRIX_KEY(0x0E, 0x03, KEY_Q)
497 MATRIX_KEY(0x0E, 0x04, KEY_F4)
498 MATRIX_KEY(0x0E, 0x05, KEY_F3)
499 MATRIX_KEY(0x0E, 0x06, KEY_1)
500 MATRIX_KEY(0x0E, 0x07, KEY_F7)
501 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
502 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
503 MATRIX_KEY(0x0F, 0x02, KEY_F5)
504 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
505 MATRIX_KEY(0x0F, 0x04, KEY_F1)
506 MATRIX_KEY(0x0F, 0x05, KEY_F2)
507 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
508 MATRIX_KEY(0x0F, 0x07, KEY_F6)
509 MATRIX_KEY(0x14, 0x00, KEY_KP7)
510 MATRIX_KEY(0x15, 0x00, KEY_KP9)
511 MATRIX_KEY(0x15, 0x01, KEY_KP8)
512 MATRIX_KEY(0x15, 0x02, KEY_KP4)
513 MATRIX_KEY(0x15, 0x04, KEY_KP1)
514 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
515 MATRIX_KEY(0x16, 0x02, KEY_KP6)
516 MATRIX_KEY(0x16, 0x03, KEY_KP5)
517 MATRIX_KEY(0x16, 0x04, KEY_KP3)
518 MATRIX_KEY(0x16, 0x05, KEY_KP2)
519 MATRIX_KEY(0x16, 0x07, KEY_KP0)
520 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
521 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
522 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
523 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
524 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
525 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
526 MATRIX_KEY(0x1D, 0x04, KEY_END)
527 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
528 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
529 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
530 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
531 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
532 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
533 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]534 };
535
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]536 pmc@7000e400 {
537 nvidia,invert-interrupt;
538 nvidia,suspend-mode = <1>;
539 nvidia,cpu-pwr-good-time = <5000>;
540 nvidia,cpu-pwr-off-time = <5000>;
541 nvidia,core-pwr-good-time = <3845 3845>;
542 nvidia,core-pwr-off-time = <3875>;
543 nvidia,sys-clock-req-active-high;
544 };
545
546 pcie-controller@80003000 {
547 pex-clk-supply = <&pci_clk_reg>;
548 vdd-supply = <&pci_vdd_reg>;
549 status = "okay";
550
551 pci@1,0 {
552 status = "okay";
553 };
554
555 pci@2,0 {
556 status = "okay";
557 };
558 };
559
560 usb@c5000000 {
561 status = "okay";
562 };
563
564 usb-phy@c5000000 {
565 status = "okay";
566 };
567
568 usb@c5004000 {
569 status = "okay";
570 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
571 GPIO_ACTIVE_LOW>;
572 };
573
574 usb-phy@c5004000 {
575 status = "okay";
576 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
577 GPIO_ACTIVE_LOW>;
578 };
579
580 usb@c5008000 {
581 status = "okay";
582 };
583
584 usb-phy@c5008000 {
585 status = "okay";
586 };
587
588 sdhci@c8000200 {
589 status = "okay";
590 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
591 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
592 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
593 bus-width = <4>;
594 };
595
596 sdhci@c8000600 {
597 status = "okay";
598 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
599 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
600 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
601 bus-width = <8>;
602 };
603
604 clocks {
605 compatible = "simple-bus";
606 #address-cells = <1>;
607 #size-cells = <0>;
608
609 clk32k_in: clock@0 {
610 compatible = "fixed-clock";
611 reg=<0>;
612 #clock-cells = <0>;
613 clock-frequency = <32768>;
614 };
615 };
616
617 gpio-keys {
618 compatible = "gpio-keys";
619
620 power {
621 label = "Power";
622 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]623 linux,code = <KEY_POWER>;
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]624 gpio-key,wakeup;
625 };
626 };
627
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]628 regulators {
629 compatible = "simple-bus";
630 #address-cells = <1>;
631 #size-cells = <0>;
632
633 vdd_5v0_reg: regulator@0 {
634 compatible = "regulator-fixed";
635 reg = <0>;
636 regulator-name = "vdd_5v0";
637 regulator-min-microvolt = <5000000>;
638 regulator-max-microvolt = <5000000>;
639 regulator-always-on;
640 };
641
642 regulator@1 {
643 compatible = "regulator-fixed";
644 reg = <1>;
645 regulator-name = "vdd_1v5";
646 regulator-min-microvolt = <1500000>;
647 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]648 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]649 };
650
651 regulator@2 {
652 compatible = "regulator-fixed";
653 reg = <2>;
654 regulator-name = "vdd_1v2";
655 regulator-min-microvolt = <1200000>;
656 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]657 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]658 enable-active-high;
659 };
660
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]661 pci_vdd_reg: regulator@3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]662 compatible = "regulator-fixed";
663 reg = <3>;
664 regulator-name = "vdd_1v05";
665 regulator-min-microvolt = <1050000>;
666 regulator-max-microvolt = <1050000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]667 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]668 enable-active-high;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]669 };
670
671 regulator@4 {
672 compatible = "regulator-fixed";
673 reg = <4>;
674 regulator-name = "vdd_pnl";
675 regulator-min-microvolt = <2800000>;
676 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]677 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]678 enable-active-high;
679 };
680
681 regulator@5 {
682 compatible = "regulator-fixed";
683 reg = <5>;
684 regulator-name = "vdd_bl";
685 regulator-min-microvolt = <2800000>;
686 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]687 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]688 enable-active-high;
689 };
690 };
691
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]692 sound {
693 compatible = "nvidia,tegra-audio-wm8903-harmony",
694 "nvidia,tegra-audio-wm8903";
695 nvidia,model = "NVIDIA Tegra Harmony";
696
697 nvidia,audio-routing =
698 "Headphone Jack", "HPOUTR",
699 "Headphone Jack", "HPOUTL",
700 "Int Spk", "ROP",
701 "Int Spk", "RON",
702 "Int Spk", "LOP",
703 "Int Spk", "LON",
704 "Mic Jack", "MICBIAS",
705 "IN1L", "Mic Jack";
706
707 nvidia,i2s-controller = <&tegra_i2s1>;
708 nvidia,audio-codec = <&wm8903>;
709
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]710 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
711 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
712 GPIO_ACTIVE_HIGH>;
713 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
714 GPIO_ACTIVE_HIGH>;
715 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
716 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]717
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]718 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
719 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
720 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]721 clock-names = "pll_a", "pll_a_out0", "mclk";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]722 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]723};