blob: cc62d4c64fb5888a3085f996201b93dcd0f833c5 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020052#include <linux/dcbnl.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020053#include <net/switchdev.h>
54#include <generated/utsrelease.h>
55
56#include "spectrum.h"
57#include "core.h"
58#include "reg.h"
59#include "port.h"
60#include "trap.h"
61#include "txheader.h"
62
63static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
64static const char mlxsw_sp_driver_version[] = "1.0";
65
66/* tx_hdr_version
67 * Tx header version.
68 * Must be set to 1.
69 */
70MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
71
72/* tx_hdr_ctl
73 * Packet control type.
74 * 0 - Ethernet control (e.g. EMADs, LACP)
75 * 1 - Ethernet data
76 */
77MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
78
79/* tx_hdr_proto
80 * Packet protocol type. Must be set to 1 (Ethernet).
81 */
82MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
83
84/* tx_hdr_rx_is_router
85 * Packet is sent from the router. Valid for data packets only.
86 */
87MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
88
89/* tx_hdr_fid_valid
90 * Indicates if the 'fid' field is valid and should be used for
91 * forwarding lookup. Valid for data packets only.
92 */
93MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
94
95/* tx_hdr_swid
96 * Switch partition ID. Must be set to 0.
97 */
98MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
99
100/* tx_hdr_control_tclass
101 * Indicates if the packet should use the control TClass and not one
102 * of the data TClasses.
103 */
104MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
105
106/* tx_hdr_etclass
107 * Egress TClass to be used on the egress device on the egress port.
108 */
109MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
110
111/* tx_hdr_port_mid
112 * Destination local port for unicast packets.
113 * Destination multicast ID for multicast packets.
114 *
115 * Control packets are directed to a specific egress port, while data
116 * packets are transmitted through the CPU port (0) into the switch partition,
117 * where forwarding rules are applied.
118 */
119MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
120
121/* tx_hdr_fid
122 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
123 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
124 * Valid for data packets only.
125 */
126MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
127
128/* tx_hdr_type
129 * 0 - Data packets
130 * 6 - Control packets
131 */
132MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
133
134static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
135 const struct mlxsw_tx_info *tx_info)
136{
137 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
138
139 memset(txhdr, 0, MLXSW_TXHDR_LEN);
140
141 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
142 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
143 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
144 mlxsw_tx_hdr_swid_set(txhdr, 0);
145 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
146 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
147 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
148}
149
150static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
151{
152 char spad_pl[MLXSW_REG_SPAD_LEN];
153 int err;
154
155 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
156 if (err)
157 return err;
158 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
159 return 0;
160}
161
162static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
163 bool is_up)
164{
165 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
166 char paos_pl[MLXSW_REG_PAOS_LEN];
167
168 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
169 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
170 MLXSW_PORT_ADMIN_STATUS_DOWN);
171 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
172}
173
174static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
175 bool *p_is_up)
176{
177 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
178 char paos_pl[MLXSW_REG_PAOS_LEN];
179 u8 oper_status;
180 int err;
181
182 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
183 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
184 if (err)
185 return err;
186 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
187 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
188 return 0;
189}
190
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200191static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
192 unsigned char *addr)
193{
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
195 char ppad_pl[MLXSW_REG_PPAD_LEN];
196
197 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
198 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
199 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
200}
201
202static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
203{
204 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
205 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
206
207 ether_addr_copy(addr, mlxsw_sp->base_mac);
208 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
209 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
210}
211
212static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
213 u16 vid, enum mlxsw_reg_spms_state state)
214{
215 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
216 char *spms_pl;
217 int err;
218
219 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
220 if (!spms_pl)
221 return -ENOMEM;
222 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
223 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
224 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
225 kfree(spms_pl);
226 return err;
227}
228
229static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
230{
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
232 char pmtu_pl[MLXSW_REG_PMTU_LEN];
233 int max_mtu;
234 int err;
235
236 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
237 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
238 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
239 if (err)
240 return err;
241 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
242
243 if (mtu > max_mtu)
244 return -EINVAL;
245
246 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
247 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
248}
249
Ido Schimmelbe945352016-06-09 09:51:39 +0200250static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
251 u8 swid)
252{
253 char pspa_pl[MLXSW_REG_PSPA_LEN];
254
255 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
256 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
257}
258
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200259static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
260{
261 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200262
Ido Schimmelbe945352016-06-09 09:51:39 +0200263 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
264 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200265}
266
267static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
268 bool enable)
269{
270 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
271 char svpe_pl[MLXSW_REG_SVPE_LEN];
272
273 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
274 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
275}
276
277int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
278 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
279 u16 vid)
280{
281 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
282 char svfa_pl[MLXSW_REG_SVFA_LEN];
283
284 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
285 fid, vid);
286 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
287}
288
289static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
290 u16 vid, bool learn_enable)
291{
292 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
293 char *spvmlr_pl;
294 int err;
295
296 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
297 if (!spvmlr_pl)
298 return -ENOMEM;
299 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
300 learn_enable);
301 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
302 kfree(spvmlr_pl);
303 return err;
304}
305
306static int
307mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
308{
309 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
310 char sspr_pl[MLXSW_REG_SSPR_LEN];
311
312 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
313 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
314}
315
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200316static int __mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
317 u8 local_port, u8 *p_module,
318 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200319{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200320 char pmlp_pl[MLXSW_REG_PMLP_LEN];
321 int err;
322
Ido Schimmel558c2d52016-02-26 17:32:29 +0100323 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200324 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
325 if (err)
326 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100327 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
328 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200329 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200330 return 0;
331}
332
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200333static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
334 u8 local_port, u8 *p_module,
335 u8 *p_width)
336{
337 u8 lane;
338
339 return __mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, p_module,
340 p_width, &lane);
341}
342
Ido Schimmel18f1e702016-02-26 17:32:31 +0100343static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
344 u8 module, u8 width, u8 lane)
345{
346 char pmlp_pl[MLXSW_REG_PMLP_LEN];
347 int i;
348
349 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
350 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
351 for (i = 0; i < width; i++) {
352 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
353 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
354 }
355
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100359static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
360{
361 char pmlp_pl[MLXSW_REG_PMLP_LEN];
362
363 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
364 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
365 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
366}
367
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200368static int mlxsw_sp_port_open(struct net_device *dev)
369{
370 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
371 int err;
372
373 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
374 if (err)
375 return err;
376 netif_start_queue(dev);
377 return 0;
378}
379
380static int mlxsw_sp_port_stop(struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383
384 netif_stop_queue(dev);
385 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
386}
387
388static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
389 struct net_device *dev)
390{
391 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
392 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
393 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
394 const struct mlxsw_tx_info tx_info = {
395 .local_port = mlxsw_sp_port->local_port,
396 .is_emad = false,
397 };
398 u64 len;
399 int err;
400
Jiri Pirko307c2432016-04-08 19:11:22 +0200401 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200402 return NETDEV_TX_BUSY;
403
404 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
405 struct sk_buff *skb_orig = skb;
406
407 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
408 if (!skb) {
409 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
410 dev_kfree_skb_any(skb_orig);
411 return NETDEV_TX_OK;
412 }
413 }
414
415 if (eth_skb_pad(skb)) {
416 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
417 return NETDEV_TX_OK;
418 }
419
420 mlxsw_sp_txhdr_construct(skb, &tx_info);
421 len = skb->len;
422 /* Due to a race we might fail here because of a full queue. In that
423 * unlikely case we simply drop the packet.
424 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200425 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200426
427 if (!err) {
428 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
429 u64_stats_update_begin(&pcpu_stats->syncp);
430 pcpu_stats->tx_packets++;
431 pcpu_stats->tx_bytes += len;
432 u64_stats_update_end(&pcpu_stats->syncp);
433 } else {
434 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
435 dev_kfree_skb_any(skb);
436 }
437 return NETDEV_TX_OK;
438}
439
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100440static void mlxsw_sp_set_rx_mode(struct net_device *dev)
441{
442}
443
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200444static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
445{
446 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
447 struct sockaddr *addr = p;
448 int err;
449
450 if (!is_valid_ether_addr(addr->sa_data))
451 return -EADDRNOTAVAIL;
452
453 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
454 if (err)
455 return err;
456 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
457 return 0;
458}
459
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200460static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200461 bool pause_en, bool pfc_en, u16 delay)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200462{
463 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
464
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200465 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
466 MLXSW_SP_PAUSE_DELAY;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200467
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200468 if (pause_en || pfc_en)
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200469 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200470 pg_size + delay, pg_size);
471 else
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200472 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200473}
474
475int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200476 u8 *prio_tc, bool pause_en,
477 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200478{
479 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200480 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
481 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200482 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200483 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200484
485 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
486 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
487 if (err)
488 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200489
490 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
491 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200492 bool pfc = false;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200493
494 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
495 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200496 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200497 configure = true;
498 break;
499 }
500 }
501
502 if (!configure)
503 continue;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200504 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200505 }
506
Ido Schimmelff6551e2016-04-06 17:10:03 +0200507 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
508}
509
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200510static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200511 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200512{
513 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
514 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200515 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200516 u8 *prio_tc;
517
518 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200519 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200520
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200521 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200522 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200523}
524
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200525static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
526{
527 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200528 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200529 int err;
530
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200531 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200532 if (err)
533 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200534 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
535 if (err)
536 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200537 dev->mtu = mtu;
538 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200539
540err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200541 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200542 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200543}
544
545static struct rtnl_link_stats64 *
546mlxsw_sp_port_get_stats64(struct net_device *dev,
547 struct rtnl_link_stats64 *stats)
548{
549 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
550 struct mlxsw_sp_port_pcpu_stats *p;
551 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
552 u32 tx_dropped = 0;
553 unsigned int start;
554 int i;
555
556 for_each_possible_cpu(i) {
557 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
558 do {
559 start = u64_stats_fetch_begin_irq(&p->syncp);
560 rx_packets = p->rx_packets;
561 rx_bytes = p->rx_bytes;
562 tx_packets = p->tx_packets;
563 tx_bytes = p->tx_bytes;
564 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
565
566 stats->rx_packets += rx_packets;
567 stats->rx_bytes += rx_bytes;
568 stats->tx_packets += tx_packets;
569 stats->tx_bytes += tx_bytes;
570 /* tx_dropped is u32, updated without syncp protection. */
571 tx_dropped += p->tx_dropped;
572 }
573 stats->tx_dropped = tx_dropped;
574 return stats;
575}
576
577int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
578 u16 vid_end, bool is_member, bool untagged)
579{
580 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
581 char *spvm_pl;
582 int err;
583
584 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
585 if (!spvm_pl)
586 return -ENOMEM;
587
588 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
589 vid_end, is_member, untagged);
590 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
591 kfree(spvm_pl);
592 return err;
593}
594
595static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
596{
597 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
598 u16 vid, last_visited_vid;
599 int err;
600
601 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
602 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
603 vid);
604 if (err) {
605 last_visited_vid = vid;
606 goto err_port_vid_to_fid_set;
607 }
608 }
609
610 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
611 if (err) {
612 last_visited_vid = VLAN_N_VID;
613 goto err_port_vid_to_fid_set;
614 }
615
616 return 0;
617
618err_port_vid_to_fid_set:
619 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
620 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
621 vid);
622 return err;
623}
624
625static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
626{
627 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
628 u16 vid;
629 int err;
630
631 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
632 if (err)
633 return err;
634
635 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
636 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
637 vid, vid);
638 if (err)
639 return err;
640 }
641
642 return 0;
643}
644
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100645static struct mlxsw_sp_vfid *
646mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
647{
648 struct mlxsw_sp_vfid *vfid;
649
650 list_for_each_entry(vfid, &mlxsw_sp->port_vfids.list, list) {
651 if (vfid->vid == vid)
652 return vfid;
653 }
654
655 return NULL;
656}
657
658static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
659{
660 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
661 MLXSW_SP_VFID_PORT_MAX);
662}
663
664static int __mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp, u16 vfid)
665{
666 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
667 char sfmr_pl[MLXSW_REG_SFMR_LEN];
668
669 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, 0);
670 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
671}
672
673static void __mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp, u16 vfid)
674{
675 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
676 char sfmr_pl[MLXSW_REG_SFMR_LEN];
677
678 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID, fid, 0);
679 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
680}
681
682static struct mlxsw_sp_vfid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
683 u16 vid)
684{
685 struct device *dev = mlxsw_sp->bus_info->dev;
686 struct mlxsw_sp_vfid *vfid;
687 u16 n_vfid;
688 int err;
689
690 n_vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
691 if (n_vfid == MLXSW_SP_VFID_PORT_MAX) {
692 dev_err(dev, "No available vFIDs\n");
693 return ERR_PTR(-ERANGE);
694 }
695
696 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
697 if (err) {
698 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
699 return ERR_PTR(err);
700 }
701
702 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
703 if (!vfid)
704 goto err_allocate_vfid;
705
706 vfid->vfid = n_vfid;
707 vfid->vid = vid;
708
709 list_add(&vfid->list, &mlxsw_sp->port_vfids.list);
710 set_bit(n_vfid, mlxsw_sp->port_vfids.mapped);
711
712 return vfid;
713
714err_allocate_vfid:
715 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
716 return ERR_PTR(-ENOMEM);
717}
718
719static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
720 struct mlxsw_sp_vfid *vfid)
721{
722 clear_bit(vfid->vfid, mlxsw_sp->port_vfids.mapped);
723 list_del(&vfid->list);
724
725 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
726
727 kfree(vfid);
728}
729
730static struct mlxsw_sp_port *
731mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port,
732 struct mlxsw_sp_vfid *vfid)
733{
734 struct mlxsw_sp_port *mlxsw_sp_vport;
735
736 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
737 if (!mlxsw_sp_vport)
738 return NULL;
739
740 /* dev will be set correctly after the VLAN device is linked
741 * with the real device. In case of bridge SELF invocation, dev
742 * will remain as is.
743 */
744 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
745 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
746 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
747 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100748 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
749 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100750 mlxsw_sp_vport->vport.vfid = vfid;
751 mlxsw_sp_vport->vport.vid = vfid->vid;
752
753 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
754
755 return mlxsw_sp_vport;
756}
757
758static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
759{
760 list_del(&mlxsw_sp_vport->vport.list);
761 kfree(mlxsw_sp_vport);
762}
763
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200764int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
765 u16 vid)
766{
767 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
768 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100769 struct mlxsw_sp_port *mlxsw_sp_vport;
770 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200771 int err;
772
773 /* VLAN 0 is added to HW filter when device goes up, but it is
774 * reserved in our case, so simply return.
775 */
776 if (!vid)
777 return 0;
778
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100779 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200780 netdev_warn(dev, "VID=%d already configured\n", vid);
781 return 0;
782 }
783
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100784 vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
785 if (!vfid) {
786 vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
787 if (IS_ERR(vfid)) {
788 netdev_err(dev, "Failed to create vFID for VID=%d\n",
789 vid);
790 return PTR_ERR(vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200791 }
792 }
793
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100794 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vfid);
795 if (!mlxsw_sp_vport) {
796 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
797 err = -ENOMEM;
798 goto err_port_vport_create;
799 }
800
801 if (!vfid->nr_vports) {
802 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100803 true, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100804 if (err) {
805 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
806 vfid->vfid);
807 goto err_vport_flood_set;
808 }
809 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200810
811 /* When adding the first VLAN interface on a bridged port we need to
812 * transition all the active 802.1Q bridge VLANs to use explicit
813 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
814 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100815 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200816 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
817 if (err) {
818 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100819 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200820 }
821 }
822
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100823 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200824 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100825 true,
826 mlxsw_sp_vfid_to_fid(vfid->vfid),
827 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200828 if (err) {
829 netdev_err(dev, "Failed to map {Port, VID=%d} to vFID=%d\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100830 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200831 goto err_port_vid_to_fid_set;
832 }
833
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100834 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200835 if (err) {
836 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
837 goto err_port_vid_learning_set;
838 }
839
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100840 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200841 if (err) {
842 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
843 vid);
844 goto err_port_add_vid;
845 }
846
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100847 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848 MLXSW_REG_SPMS_STATE_FORWARDING);
849 if (err) {
850 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
851 goto err_port_stp_state_set;
852 }
853
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100854 vfid->nr_vports++;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200855
856 return 0;
857
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200858err_port_stp_state_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100859 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200860err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100861 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200862err_port_vid_learning_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100863 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200864 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100865 mlxsw_sp_vfid_to_fid(vfid->vfid), vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200866err_port_vid_to_fid_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100867 if (list_is_singular(&mlxsw_sp_port->vports_list))
868 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
869err_port_vp_mode_trans:
870 if (!vfid->nr_vports)
Ido Schimmel19ae6122015-12-15 16:03:39 +0100871 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
872 false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100873err_vport_flood_set:
874 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
875err_port_vport_create:
876 if (!vfid->nr_vports)
877 mlxsw_sp_vfid_destroy(mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200878 return err;
879}
880
881int mlxsw_sp_port_kill_vid(struct net_device *dev,
882 __be16 __always_unused proto, u16 vid)
883{
884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100885 struct mlxsw_sp_port *mlxsw_sp_vport;
886 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200887 int err;
888
889 /* VLAN 0 is removed from HW filter when device goes down, but
890 * it is reserved in our case, so simply return.
891 */
892 if (!vid)
893 return 0;
894
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100895 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
896 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897 netdev_warn(dev, "VID=%d does not exist\n", vid);
898 return 0;
899 }
900
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100901 vfid = mlxsw_sp_vport->vport.vfid;
902
903 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200904 MLXSW_REG_SPMS_STATE_DISCARDING);
905 if (err) {
906 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
907 return err;
908 }
909
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100910 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200911 if (err) {
912 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
913 vid);
914 return err;
915 }
916
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100917 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200918 if (err) {
919 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
920 return err;
921 }
922
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100923 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200924 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100925 false,
926 mlxsw_sp_vfid_to_fid(vfid->vfid),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200927 vid);
928 if (err) {
929 netdev_err(dev, "Failed to invalidate {Port, VID=%d} to vFID=%d mapping\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100930 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200931 return err;
932 }
933
934 /* When removing the last VLAN interface on a bridged port we need to
935 * transition all active 802.1Q bridge VLANs to use VID to FID
936 * mappings and set port's mode to VLAN mode.
937 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100938 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200939 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
940 if (err) {
941 netdev_err(dev, "Failed to set to VLAN mode\n");
942 return err;
943 }
944 }
945
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100946 vfid->nr_vports--;
947 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
948
949 /* Destroy the vFID if no vPorts are assigned to it anymore. */
950 if (!vfid->nr_vports)
951 mlxsw_sp_vfid_destroy(mlxsw_sp_port->mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200952
953 return 0;
954}
955
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200956static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
957 size_t len)
958{
959 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
960 u8 module, width, lane;
961 int err;
962
963 err = __mlxsw_sp_port_module_info_get(mlxsw_sp_port->mlxsw_sp,
964 mlxsw_sp_port->local_port,
965 &module, &width, &lane);
966 if (err) {
967 netdev_err(dev, "Failed to retrieve module information\n");
968 return err;
969 }
970
971 if (!mlxsw_sp_port->split)
972 err = snprintf(name, len, "p%d", module + 1);
973 else
974 err = snprintf(name, len, "p%ds%d", module + 1,
975 lane / width);
976
977 if (err >= len)
978 return -EINVAL;
979
980 return 0;
981}
982
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200983static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
984 .ndo_open = mlxsw_sp_port_open,
985 .ndo_stop = mlxsw_sp_port_stop,
986 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100987 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200988 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
989 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
990 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
991 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
992 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
993 .ndo_fdb_add = switchdev_port_fdb_add,
994 .ndo_fdb_del = switchdev_port_fdb_del,
995 .ndo_fdb_dump = switchdev_port_fdb_dump,
996 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
997 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
998 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200999 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001000};
1001
1002static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1003 struct ethtool_drvinfo *drvinfo)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1007
1008 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1009 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1010 sizeof(drvinfo->version));
1011 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1012 "%d.%d.%d",
1013 mlxsw_sp->bus_info->fw_rev.major,
1014 mlxsw_sp->bus_info->fw_rev.minor,
1015 mlxsw_sp->bus_info->fw_rev.subminor);
1016 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1017 sizeof(drvinfo->bus_info));
1018}
1019
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001020static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1021 struct ethtool_pauseparam *pause)
1022{
1023 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1024
1025 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1026 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1027}
1028
1029static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1030 struct ethtool_pauseparam *pause)
1031{
1032 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1033
1034 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1035 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1036 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1037
1038 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1039 pfcc_pl);
1040}
1041
1042static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1043 struct ethtool_pauseparam *pause)
1044{
1045 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1046 bool pause_en = pause->tx_pause || pause->rx_pause;
1047 int err;
1048
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001049 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1050 netdev_err(dev, "PFC already enabled on port\n");
1051 return -EINVAL;
1052 }
1053
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001054 if (pause->autoneg) {
1055 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1056 return -EINVAL;
1057 }
1058
1059 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1060 if (err) {
1061 netdev_err(dev, "Failed to configure port's headroom\n");
1062 return err;
1063 }
1064
1065 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1066 if (err) {
1067 netdev_err(dev, "Failed to set PAUSE parameters\n");
1068 goto err_port_pause_configure;
1069 }
1070
1071 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1072 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1073
1074 return 0;
1075
1076err_port_pause_configure:
1077 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1078 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1079 return err;
1080}
1081
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001082struct mlxsw_sp_port_hw_stats {
1083 char str[ETH_GSTRING_LEN];
1084 u64 (*getter)(char *payload);
1085};
1086
1087static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1088 {
1089 .str = "a_frames_transmitted_ok",
1090 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1091 },
1092 {
1093 .str = "a_frames_received_ok",
1094 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1095 },
1096 {
1097 .str = "a_frame_check_sequence_errors",
1098 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1099 },
1100 {
1101 .str = "a_alignment_errors",
1102 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1103 },
1104 {
1105 .str = "a_octets_transmitted_ok",
1106 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1107 },
1108 {
1109 .str = "a_octets_received_ok",
1110 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1111 },
1112 {
1113 .str = "a_multicast_frames_xmitted_ok",
1114 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1115 },
1116 {
1117 .str = "a_broadcast_frames_xmitted_ok",
1118 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1119 },
1120 {
1121 .str = "a_multicast_frames_received_ok",
1122 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1123 },
1124 {
1125 .str = "a_broadcast_frames_received_ok",
1126 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1127 },
1128 {
1129 .str = "a_in_range_length_errors",
1130 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1131 },
1132 {
1133 .str = "a_out_of_range_length_field",
1134 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1135 },
1136 {
1137 .str = "a_frame_too_long_errors",
1138 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1139 },
1140 {
1141 .str = "a_symbol_error_during_carrier",
1142 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1143 },
1144 {
1145 .str = "a_mac_control_frames_transmitted",
1146 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1147 },
1148 {
1149 .str = "a_mac_control_frames_received",
1150 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1151 },
1152 {
1153 .str = "a_unsupported_opcodes_received",
1154 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1155 },
1156 {
1157 .str = "a_pause_mac_ctrl_frames_received",
1158 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1159 },
1160 {
1161 .str = "a_pause_mac_ctrl_frames_xmitted",
1162 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1163 },
1164};
1165
1166#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1167
1168static void mlxsw_sp_port_get_strings(struct net_device *dev,
1169 u32 stringset, u8 *data)
1170{
1171 u8 *p = data;
1172 int i;
1173
1174 switch (stringset) {
1175 case ETH_SS_STATS:
1176 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1177 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1178 ETH_GSTRING_LEN);
1179 p += ETH_GSTRING_LEN;
1180 }
1181 break;
1182 }
1183}
1184
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001185static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1186 enum ethtool_phys_id_state state)
1187{
1188 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1189 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1190 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1191 bool active;
1192
1193 switch (state) {
1194 case ETHTOOL_ID_ACTIVE:
1195 active = true;
1196 break;
1197 case ETHTOOL_ID_INACTIVE:
1198 active = false;
1199 break;
1200 default:
1201 return -EOPNOTSUPP;
1202 }
1203
1204 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1205 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1206}
1207
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001208static void mlxsw_sp_port_get_stats(struct net_device *dev,
1209 struct ethtool_stats *stats, u64 *data)
1210{
1211 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1212 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1213 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1214 int i;
1215 int err;
1216
Ido Schimmel34dba0a2016-04-06 17:10:15 +02001217 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1218 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001219 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1220 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1221 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1222}
1223
1224static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1225{
1226 switch (sset) {
1227 case ETH_SS_STATS:
1228 return MLXSW_SP_PORT_HW_STATS_LEN;
1229 default:
1230 return -EOPNOTSUPP;
1231 }
1232}
1233
1234struct mlxsw_sp_port_link_mode {
1235 u32 mask;
1236 u32 supported;
1237 u32 advertised;
1238 u32 speed;
1239};
1240
1241static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1242 {
1243 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1244 .supported = SUPPORTED_100baseT_Full,
1245 .advertised = ADVERTISED_100baseT_Full,
1246 .speed = 100,
1247 },
1248 {
1249 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1250 .speed = 100,
1251 },
1252 {
1253 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1254 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1255 .supported = SUPPORTED_1000baseKX_Full,
1256 .advertised = ADVERTISED_1000baseKX_Full,
1257 .speed = 1000,
1258 },
1259 {
1260 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1261 .supported = SUPPORTED_10000baseT_Full,
1262 .advertised = ADVERTISED_10000baseT_Full,
1263 .speed = 10000,
1264 },
1265 {
1266 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1267 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1268 .supported = SUPPORTED_10000baseKX4_Full,
1269 .advertised = ADVERTISED_10000baseKX4_Full,
1270 .speed = 10000,
1271 },
1272 {
1273 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1274 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1275 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1276 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1277 .supported = SUPPORTED_10000baseKR_Full,
1278 .advertised = ADVERTISED_10000baseKR_Full,
1279 .speed = 10000,
1280 },
1281 {
1282 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1283 .supported = SUPPORTED_20000baseKR2_Full,
1284 .advertised = ADVERTISED_20000baseKR2_Full,
1285 .speed = 20000,
1286 },
1287 {
1288 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1289 .supported = SUPPORTED_40000baseCR4_Full,
1290 .advertised = ADVERTISED_40000baseCR4_Full,
1291 .speed = 40000,
1292 },
1293 {
1294 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1295 .supported = SUPPORTED_40000baseKR4_Full,
1296 .advertised = ADVERTISED_40000baseKR4_Full,
1297 .speed = 40000,
1298 },
1299 {
1300 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1301 .supported = SUPPORTED_40000baseSR4_Full,
1302 .advertised = ADVERTISED_40000baseSR4_Full,
1303 .speed = 40000,
1304 },
1305 {
1306 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1307 .supported = SUPPORTED_40000baseLR4_Full,
1308 .advertised = ADVERTISED_40000baseLR4_Full,
1309 .speed = 40000,
1310 },
1311 {
1312 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1313 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1314 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1315 .speed = 25000,
1316 },
1317 {
1318 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1319 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1320 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1321 .speed = 50000,
1322 },
1323 {
1324 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1325 .supported = SUPPORTED_56000baseKR4_Full,
1326 .advertised = ADVERTISED_56000baseKR4_Full,
1327 .speed = 56000,
1328 },
1329 {
1330 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1331 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1332 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1333 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1334 .speed = 100000,
1335 },
1336};
1337
1338#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1339
1340static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1341{
1342 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1343 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1344 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1345 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1346 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1347 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1348 return SUPPORTED_FIBRE;
1349
1350 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1351 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1352 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1353 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1354 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1355 return SUPPORTED_Backplane;
1356 return 0;
1357}
1358
1359static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1360{
1361 u32 modes = 0;
1362 int i;
1363
1364 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1365 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1366 modes |= mlxsw_sp_port_link_mode[i].supported;
1367 }
1368 return modes;
1369}
1370
1371static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1372{
1373 u32 modes = 0;
1374 int i;
1375
1376 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1377 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1378 modes |= mlxsw_sp_port_link_mode[i].advertised;
1379 }
1380 return modes;
1381}
1382
1383static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1384 struct ethtool_cmd *cmd)
1385{
1386 u32 speed = SPEED_UNKNOWN;
1387 u8 duplex = DUPLEX_UNKNOWN;
1388 int i;
1389
1390 if (!carrier_ok)
1391 goto out;
1392
1393 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1394 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1395 speed = mlxsw_sp_port_link_mode[i].speed;
1396 duplex = DUPLEX_FULL;
1397 break;
1398 }
1399 }
1400out:
1401 ethtool_cmd_speed_set(cmd, speed);
1402 cmd->duplex = duplex;
1403}
1404
1405static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1406{
1407 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1408 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1409 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1410 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1411 return PORT_FIBRE;
1412
1413 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1414 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1415 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1416 return PORT_DA;
1417
1418 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1419 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1420 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1421 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1422 return PORT_NONE;
1423
1424 return PORT_OTHER;
1425}
1426
1427static int mlxsw_sp_port_get_settings(struct net_device *dev,
1428 struct ethtool_cmd *cmd)
1429{
1430 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1431 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1432 char ptys_pl[MLXSW_REG_PTYS_LEN];
1433 u32 eth_proto_cap;
1434 u32 eth_proto_admin;
1435 u32 eth_proto_oper;
1436 int err;
1437
1438 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1439 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1440 if (err) {
1441 netdev_err(dev, "Failed to get proto");
1442 return err;
1443 }
1444 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1445 &eth_proto_admin, &eth_proto_oper);
1446
1447 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1448 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1449 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1450 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1451 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1452 eth_proto_oper, cmd);
1453
1454 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1455 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1456 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1457
1458 cmd->transceiver = XCVR_INTERNAL;
1459 return 0;
1460}
1461
1462static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1463{
1464 u32 ptys_proto = 0;
1465 int i;
1466
1467 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1468 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1469 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1470 }
1471 return ptys_proto;
1472}
1473
1474static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1475{
1476 u32 ptys_proto = 0;
1477 int i;
1478
1479 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1480 if (speed == mlxsw_sp_port_link_mode[i].speed)
1481 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1482 }
1483 return ptys_proto;
1484}
1485
Ido Schimmel18f1e702016-02-26 17:32:31 +01001486static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1487{
1488 u32 ptys_proto = 0;
1489 int i;
1490
1491 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1492 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1493 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1494 }
1495 return ptys_proto;
1496}
1497
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001498static int mlxsw_sp_port_set_settings(struct net_device *dev,
1499 struct ethtool_cmd *cmd)
1500{
1501 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1502 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1503 char ptys_pl[MLXSW_REG_PTYS_LEN];
1504 u32 speed;
1505 u32 eth_proto_new;
1506 u32 eth_proto_cap;
1507 u32 eth_proto_admin;
1508 bool is_up;
1509 int err;
1510
1511 speed = ethtool_cmd_speed(cmd);
1512
1513 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1514 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1515 mlxsw_sp_to_ptys_speed(speed);
1516
1517 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1518 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1519 if (err) {
1520 netdev_err(dev, "Failed to get proto");
1521 return err;
1522 }
1523 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1524
1525 eth_proto_new = eth_proto_new & eth_proto_cap;
1526 if (!eth_proto_new) {
1527 netdev_err(dev, "Not supported proto admin requested");
1528 return -EINVAL;
1529 }
1530 if (eth_proto_new == eth_proto_admin)
1531 return 0;
1532
1533 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1534 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1535 if (err) {
1536 netdev_err(dev, "Failed to set proto admin");
1537 return err;
1538 }
1539
1540 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1541 if (err) {
1542 netdev_err(dev, "Failed to get oper status");
1543 return err;
1544 }
1545 if (!is_up)
1546 return 0;
1547
1548 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1549 if (err) {
1550 netdev_err(dev, "Failed to set admin status");
1551 return err;
1552 }
1553
1554 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1555 if (err) {
1556 netdev_err(dev, "Failed to set admin status");
1557 return err;
1558 }
1559
1560 return 0;
1561}
1562
1563static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1564 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1565 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001566 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1567 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001568 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001569 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001570 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1571 .get_sset_count = mlxsw_sp_port_get_sset_count,
1572 .get_settings = mlxsw_sp_port_get_settings,
1573 .set_settings = mlxsw_sp_port_set_settings,
1574};
1575
Ido Schimmel18f1e702016-02-26 17:32:31 +01001576static int
1577mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1578{
1579 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1580 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1581 char ptys_pl[MLXSW_REG_PTYS_LEN];
1582 u32 eth_proto_admin;
1583
1584 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1585 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1586 eth_proto_admin);
1587 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1588}
1589
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001590int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1591 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1592 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001593{
1594 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1595 char qeec_pl[MLXSW_REG_QEEC_LEN];
1596
1597 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1598 next_index);
1599 mlxsw_reg_qeec_de_set(qeec_pl, true);
1600 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1601 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1602 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1603}
1604
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001605int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1606 enum mlxsw_reg_qeec_hr hr, u8 index,
1607 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001608{
1609 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1610 char qeec_pl[MLXSW_REG_QEEC_LEN];
1611
1612 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1613 next_index);
1614 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1615 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1616 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1617}
1618
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001619int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1620 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001621{
1622 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1623 char qtct_pl[MLXSW_REG_QTCT_LEN];
1624
1625 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1626 tclass);
1627 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1628}
1629
1630static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1631{
1632 int err, i;
1633
1634 /* Setup the elements hierarcy, so that each TC is linked to
1635 * one subgroup, which are all member in the same group.
1636 */
1637 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1638 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1639 0);
1640 if (err)
1641 return err;
1642 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1643 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1644 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1645 0, false, 0);
1646 if (err)
1647 return err;
1648 }
1649 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1650 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1651 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1652 false, 0);
1653 if (err)
1654 return err;
1655 }
1656
1657 /* Make sure the max shaper is disabled in all hierarcies that
1658 * support it.
1659 */
1660 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1661 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1662 MLXSW_REG_QEEC_MAS_DIS);
1663 if (err)
1664 return err;
1665 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1666 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1667 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1668 i, 0,
1669 MLXSW_REG_QEEC_MAS_DIS);
1670 if (err)
1671 return err;
1672 }
1673 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1674 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1675 MLXSW_REG_QEEC_HIERARCY_TC,
1676 i, i,
1677 MLXSW_REG_QEEC_MAS_DIS);
1678 if (err)
1679 return err;
1680 }
1681
1682 /* Map all priorities to traffic class 0. */
1683 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1684 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1685 if (err)
1686 return err;
1687 }
1688
1689 return 0;
1690}
1691
Ido Schimmelbe945352016-06-09 09:51:39 +02001692static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1693 bool split, u8 module, u8 width)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001694{
1695 struct mlxsw_sp_port *mlxsw_sp_port;
1696 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001697 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001698 int err;
1699
1700 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1701 if (!dev)
1702 return -ENOMEM;
1703 mlxsw_sp_port = netdev_priv(dev);
1704 mlxsw_sp_port->dev = dev;
1705 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1706 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001707 mlxsw_sp_port->split = split;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001708 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1709 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1710 if (!mlxsw_sp_port->active_vlans) {
1711 err = -ENOMEM;
1712 goto err_port_active_vlans_alloc;
1713 }
Elad Razfc1273a2016-01-06 13:01:11 +01001714 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1715 if (!mlxsw_sp_port->untagged_vlans) {
1716 err = -ENOMEM;
1717 goto err_port_untagged_vlans_alloc;
1718 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001719 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001720
1721 mlxsw_sp_port->pcpu_stats =
1722 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1723 if (!mlxsw_sp_port->pcpu_stats) {
1724 err = -ENOMEM;
1725 goto err_alloc_stats;
1726 }
1727
1728 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1729 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1730
1731 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1732 if (err) {
1733 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1734 mlxsw_sp_port->local_port);
1735 goto err_dev_addr_init;
1736 }
1737
1738 netif_carrier_off(dev);
1739
1740 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1741 NETIF_F_HW_VLAN_CTAG_FILTER;
1742
1743 /* Each packet needs to have a Tx header (metadata) on top all other
1744 * headers.
1745 */
1746 dev->hard_header_len += MLXSW_TXHDR_LEN;
1747
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001748 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1749 if (err) {
1750 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1751 mlxsw_sp_port->local_port);
1752 goto err_port_system_port_mapping_set;
1753 }
1754
1755 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1756 if (err) {
1757 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1758 mlxsw_sp_port->local_port);
1759 goto err_port_swid_set;
1760 }
1761
Ido Schimmel18f1e702016-02-26 17:32:31 +01001762 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1763 if (err) {
1764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1765 mlxsw_sp_port->local_port);
1766 goto err_port_speed_by_width_set;
1767 }
1768
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001769 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1770 if (err) {
1771 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1772 mlxsw_sp_port->local_port);
1773 goto err_port_mtu_set;
1774 }
1775
1776 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1777 if (err)
1778 goto err_port_admin_status_set;
1779
1780 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1781 if (err) {
1782 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1783 mlxsw_sp_port->local_port);
1784 goto err_port_buffers_init;
1785 }
1786
Ido Schimmel90183b92016-04-06 17:10:08 +02001787 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1788 if (err) {
1789 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1790 mlxsw_sp_port->local_port);
1791 goto err_port_ets_init;
1792 }
1793
Ido Schimmelf00817d2016-04-06 17:10:09 +02001794 /* ETS and buffers must be initialized before DCB. */
1795 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1796 if (err) {
1797 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1798 mlxsw_sp_port->local_port);
1799 goto err_port_dcb_init;
1800 }
1801
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001802 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1803 err = register_netdev(dev);
1804 if (err) {
1805 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1806 mlxsw_sp_port->local_port);
1807 goto err_register_netdev;
1808 }
1809
Jiri Pirko932762b2016-04-08 19:11:21 +02001810 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1811 mlxsw_sp_port->local_port, dev,
1812 mlxsw_sp_port->split, module);
1813 if (err) {
1814 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1815 mlxsw_sp_port->local_port);
1816 goto err_core_port_init;
1817 }
Jiri Pirkoc4745502016-02-26 17:32:26 +01001818
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001819 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1820 if (err)
1821 goto err_port_vlan_init;
1822
1823 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1824 return 0;
1825
1826err_port_vlan_init:
Jiri Pirko932762b2016-04-08 19:11:21 +02001827 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1828err_core_port_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001829 unregister_netdev(dev);
1830err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001831err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001832err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001833err_port_buffers_init:
1834err_port_admin_status_set:
1835err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001836err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001837err_port_swid_set:
1838err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001839err_dev_addr_init:
1840 free_percpu(mlxsw_sp_port->pcpu_stats);
1841err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001842 kfree(mlxsw_sp_port->untagged_vlans);
1843err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001844 kfree(mlxsw_sp_port->active_vlans);
1845err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001846 free_netdev(dev);
1847 return err;
1848}
1849
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001850static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001851{
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001852 struct net_device *dev = mlxsw_sp_port->dev;
1853 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001854
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001855 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1856 &mlxsw_sp_port->vports_list, vport.list) {
1857 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1858
1859 /* vPorts created for VLAN devices should already be gone
1860 * by now, since we unregistered the port netdev.
1861 */
1862 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1863 mlxsw_sp_port_kill_vid(dev, 0, vid);
1864 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001865}
1866
1867static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1868{
1869 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1870
1871 if (!mlxsw_sp_port)
1872 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001873 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirko932762b2016-04-08 19:11:21 +02001874 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001875 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001876 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001877 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001878 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001879 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1880 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001881 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001882 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001883 kfree(mlxsw_sp_port->active_vlans);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001884 free_netdev(mlxsw_sp_port->dev);
1885}
1886
1887static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1888{
1889 int i;
1890
1891 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1892 mlxsw_sp_port_remove(mlxsw_sp, i);
1893 kfree(mlxsw_sp->ports);
1894}
1895
1896static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1897{
1898 size_t alloc_size;
Ido Schimmel558c2d52016-02-26 17:32:29 +01001899 u8 module, width;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001900 int i;
1901 int err;
1902
1903 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1904 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1905 if (!mlxsw_sp->ports)
1906 return -ENOMEM;
1907
1908 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001909 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
1910 &width);
1911 if (err)
1912 goto err_port_module_info_get;
1913 if (!width)
1914 continue;
1915 mlxsw_sp->port_to_module[i] = module;
Ido Schimmelbe945352016-06-09 09:51:39 +02001916 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001917 if (err)
1918 goto err_port_create;
1919 }
1920 return 0;
1921
1922err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001923err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001924 for (i--; i >= 1; i--)
1925 mlxsw_sp_port_remove(mlxsw_sp, i);
1926 kfree(mlxsw_sp->ports);
1927 return err;
1928}
1929
Ido Schimmel18f1e702016-02-26 17:32:31 +01001930static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1931{
1932 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1933
1934 return local_port - offset;
1935}
1936
Ido Schimmelbe945352016-06-09 09:51:39 +02001937static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1938 u8 module, unsigned int count)
1939{
1940 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1941 int err, i;
1942
1943 for (i = 0; i < count; i++) {
1944 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1945 width, i * width);
1946 if (err)
1947 goto err_port_module_map;
1948 }
1949
1950 for (i = 0; i < count; i++) {
1951 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1952 if (err)
1953 goto err_port_swid_set;
1954 }
1955
1956 for (i = 0; i < count; i++) {
1957 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
1958 module, width);
1959 if (err)
1960 goto err_port_create;
1961 }
1962
1963 return 0;
1964
1965err_port_create:
1966 for (i--; i >= 0; i--)
1967 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1968 i = count;
1969err_port_swid_set:
1970 for (i--; i >= 0; i--)
1971 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1972 MLXSW_PORT_SWID_DISABLED_PORT);
1973 i = count;
1974err_port_module_map:
1975 for (i--; i >= 0; i--)
1976 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1977 return err;
1978}
1979
1980static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1981 u8 base_port, unsigned int count)
1982{
1983 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1984 int i;
1985
1986 /* Split by four means we need to re-create two ports, otherwise
1987 * only one.
1988 */
1989 count = count / 2;
1990
1991 for (i = 0; i < count; i++) {
1992 local_port = base_port + i * 2;
1993 module = mlxsw_sp->port_to_module[local_port];
1994
1995 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1996 0);
1997 }
1998
1999 for (i = 0; i < count; i++)
2000 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2001
2002 for (i = 0; i < count; i++) {
2003 local_port = base_port + i * 2;
2004 module = mlxsw_sp->port_to_module[local_port];
2005
2006 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
2007 width);
2008 }
2009}
2010
Jiri Pirkob2f10572016-04-08 19:11:23 +02002011static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2012 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002013{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002014 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002015 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002016 u8 module, cur_width, base_port;
2017 int i;
2018 int err;
2019
2020 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2021 if (!mlxsw_sp_port) {
2022 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2023 local_port);
2024 return -EINVAL;
2025 }
2026
2027 if (count != 2 && count != 4) {
2028 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2029 return -EINVAL;
2030 }
2031
2032 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
2033 &cur_width);
2034 if (err) {
2035 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
2036 return err;
2037 }
2038
2039 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2040 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2041 return -EINVAL;
2042 }
2043
2044 /* Make sure we have enough slave (even) ports for the split. */
2045 if (count == 2) {
2046 base_port = local_port;
2047 if (mlxsw_sp->ports[base_port + 1]) {
2048 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2049 return -EINVAL;
2050 }
2051 } else {
2052 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2053 if (mlxsw_sp->ports[base_port + 1] ||
2054 mlxsw_sp->ports[base_port + 3]) {
2055 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2056 return -EINVAL;
2057 }
2058 }
2059
2060 for (i = 0; i < count; i++)
2061 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2062
Ido Schimmelbe945352016-06-09 09:51:39 +02002063 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2064 if (err) {
2065 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2066 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002067 }
2068
2069 return 0;
2070
Ido Schimmelbe945352016-06-09 09:51:39 +02002071err_port_split_create:
2072 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002073 return err;
2074}
2075
Jiri Pirkob2f10572016-04-08 19:11:23 +02002076static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002077{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002078 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002079 struct mlxsw_sp_port *mlxsw_sp_port;
2080 u8 module, cur_width, base_port;
2081 unsigned int count;
2082 int i;
2083 int err;
2084
2085 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2086 if (!mlxsw_sp_port) {
2087 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2088 local_port);
2089 return -EINVAL;
2090 }
2091
2092 if (!mlxsw_sp_port->split) {
2093 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2094 return -EINVAL;
2095 }
2096
2097 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
2098 &cur_width);
2099 if (err) {
2100 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
2101 return err;
2102 }
2103 count = cur_width == 1 ? 4 : 2;
2104
2105 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2106
2107 /* Determine which ports to remove. */
2108 if (count == 2 && local_port >= base_port + 2)
2109 base_port = base_port + 2;
2110
2111 for (i = 0; i < count; i++)
2112 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2113
Ido Schimmelbe945352016-06-09 09:51:39 +02002114 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002115
2116 return 0;
2117}
2118
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002119static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2120 char *pude_pl, void *priv)
2121{
2122 struct mlxsw_sp *mlxsw_sp = priv;
2123 struct mlxsw_sp_port *mlxsw_sp_port;
2124 enum mlxsw_reg_pude_oper_status status;
2125 u8 local_port;
2126
2127 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2128 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2129 if (!mlxsw_sp_port) {
2130 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2131 local_port);
2132 return;
2133 }
2134
2135 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2136 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2137 netdev_info(mlxsw_sp_port->dev, "link up\n");
2138 netif_carrier_on(mlxsw_sp_port->dev);
2139 } else {
2140 netdev_info(mlxsw_sp_port->dev, "link down\n");
2141 netif_carrier_off(mlxsw_sp_port->dev);
2142 }
2143}
2144
2145static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2146 .func = mlxsw_sp_pude_event_func,
2147 .trap_id = MLXSW_TRAP_ID_PUDE,
2148};
2149
2150static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2151 enum mlxsw_event_trap_id trap_id)
2152{
2153 struct mlxsw_event_listener *el;
2154 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2155 int err;
2156
2157 switch (trap_id) {
2158 case MLXSW_TRAP_ID_PUDE:
2159 el = &mlxsw_sp_pude_event;
2160 break;
2161 }
2162 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2163 if (err)
2164 return err;
2165
2166 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2167 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2168 if (err)
2169 goto err_event_trap_set;
2170
2171 return 0;
2172
2173err_event_trap_set:
2174 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2175 return err;
2176}
2177
2178static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2179 enum mlxsw_event_trap_id trap_id)
2180{
2181 struct mlxsw_event_listener *el;
2182
2183 switch (trap_id) {
2184 case MLXSW_TRAP_ID_PUDE:
2185 el = &mlxsw_sp_pude_event;
2186 break;
2187 }
2188 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2189}
2190
2191static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2192 void *priv)
2193{
2194 struct mlxsw_sp *mlxsw_sp = priv;
2195 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2196 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2197
2198 if (unlikely(!mlxsw_sp_port)) {
2199 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2200 local_port);
2201 return;
2202 }
2203
2204 skb->dev = mlxsw_sp_port->dev;
2205
2206 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2207 u64_stats_update_begin(&pcpu_stats->syncp);
2208 pcpu_stats->rx_packets++;
2209 pcpu_stats->rx_bytes += skb->len;
2210 u64_stats_update_end(&pcpu_stats->syncp);
2211
2212 skb->protocol = eth_type_trans(skb, skb->dev);
2213 netif_receive_skb(skb);
2214}
2215
2216static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2217 {
2218 .func = mlxsw_sp_rx_listener_func,
2219 .local_port = MLXSW_PORT_DONT_CARE,
2220 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2221 },
2222 /* Traps for specific L2 packet types, not trapped as FDB MC */
2223 {
2224 .func = mlxsw_sp_rx_listener_func,
2225 .local_port = MLXSW_PORT_DONT_CARE,
2226 .trap_id = MLXSW_TRAP_ID_STP,
2227 },
2228 {
2229 .func = mlxsw_sp_rx_listener_func,
2230 .local_port = MLXSW_PORT_DONT_CARE,
2231 .trap_id = MLXSW_TRAP_ID_LACP,
2232 },
2233 {
2234 .func = mlxsw_sp_rx_listener_func,
2235 .local_port = MLXSW_PORT_DONT_CARE,
2236 .trap_id = MLXSW_TRAP_ID_EAPOL,
2237 },
2238 {
2239 .func = mlxsw_sp_rx_listener_func,
2240 .local_port = MLXSW_PORT_DONT_CARE,
2241 .trap_id = MLXSW_TRAP_ID_LLDP,
2242 },
2243 {
2244 .func = mlxsw_sp_rx_listener_func,
2245 .local_port = MLXSW_PORT_DONT_CARE,
2246 .trap_id = MLXSW_TRAP_ID_MMRP,
2247 },
2248 {
2249 .func = mlxsw_sp_rx_listener_func,
2250 .local_port = MLXSW_PORT_DONT_CARE,
2251 .trap_id = MLXSW_TRAP_ID_MVRP,
2252 },
2253 {
2254 .func = mlxsw_sp_rx_listener_func,
2255 .local_port = MLXSW_PORT_DONT_CARE,
2256 .trap_id = MLXSW_TRAP_ID_RPVST,
2257 },
2258 {
2259 .func = mlxsw_sp_rx_listener_func,
2260 .local_port = MLXSW_PORT_DONT_CARE,
2261 .trap_id = MLXSW_TRAP_ID_DHCP,
2262 },
2263 {
2264 .func = mlxsw_sp_rx_listener_func,
2265 .local_port = MLXSW_PORT_DONT_CARE,
2266 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2267 },
2268 {
2269 .func = mlxsw_sp_rx_listener_func,
2270 .local_port = MLXSW_PORT_DONT_CARE,
2271 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2272 },
2273 {
2274 .func = mlxsw_sp_rx_listener_func,
2275 .local_port = MLXSW_PORT_DONT_CARE,
2276 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2277 },
2278 {
2279 .func = mlxsw_sp_rx_listener_func,
2280 .local_port = MLXSW_PORT_DONT_CARE,
2281 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2282 },
2283 {
2284 .func = mlxsw_sp_rx_listener_func,
2285 .local_port = MLXSW_PORT_DONT_CARE,
2286 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2287 },
2288};
2289
2290static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2291{
2292 char htgt_pl[MLXSW_REG_HTGT_LEN];
2293 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2294 int i;
2295 int err;
2296
2297 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2298 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2299 if (err)
2300 return err;
2301
2302 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2303 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2304 if (err)
2305 return err;
2306
2307 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2308 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2309 &mlxsw_sp_rx_listener[i],
2310 mlxsw_sp);
2311 if (err)
2312 goto err_rx_listener_register;
2313
2314 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2315 mlxsw_sp_rx_listener[i].trap_id);
2316 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2317 if (err)
2318 goto err_rx_trap_set;
2319 }
2320 return 0;
2321
2322err_rx_trap_set:
2323 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2324 &mlxsw_sp_rx_listener[i],
2325 mlxsw_sp);
2326err_rx_listener_register:
2327 for (i--; i >= 0; i--) {
2328 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2329 mlxsw_sp_rx_listener[i].trap_id);
2330 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2331
2332 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2333 &mlxsw_sp_rx_listener[i],
2334 mlxsw_sp);
2335 }
2336 return err;
2337}
2338
2339static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2340{
2341 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2342 int i;
2343
2344 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2345 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2346 mlxsw_sp_rx_listener[i].trap_id);
2347 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2348
2349 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2350 &mlxsw_sp_rx_listener[i],
2351 mlxsw_sp);
2352 }
2353}
2354
2355static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2356 enum mlxsw_reg_sfgc_type type,
2357 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2358{
2359 enum mlxsw_flood_table_type table_type;
2360 enum mlxsw_sp_flood_table flood_table;
2361 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2362
Ido Schimmel19ae6122015-12-15 16:03:39 +01002363 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002364 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002365 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002366 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002367
2368 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2369 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2370 else
2371 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002372
2373 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2374 flood_table);
2375 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2376}
2377
2378static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2379{
2380 int type, err;
2381
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002382 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2383 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2384 continue;
2385
2386 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2387 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2388 if (err)
2389 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002390
2391 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2392 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2393 if (err)
2394 return err;
2395 }
2396
2397 return 0;
2398}
2399
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002400static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2401{
2402 char slcr_pl[MLXSW_REG_SLCR_LEN];
2403
2404 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2405 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2407 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2408 MLXSW_REG_SLCR_LAG_HASH_SIP |
2409 MLXSW_REG_SLCR_LAG_HASH_DIP |
2410 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2411 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2412 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2413 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2414}
2415
Jiri Pirkob2f10572016-04-08 19:11:23 +02002416static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002417 const struct mlxsw_bus_info *mlxsw_bus_info)
2418{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002419 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002420 int err;
2421
2422 mlxsw_sp->core = mlxsw_core;
2423 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002424 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002425 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002426 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002427
2428 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2429 if (err) {
2430 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2431 return err;
2432 }
2433
2434 err = mlxsw_sp_ports_create(mlxsw_sp);
2435 if (err) {
2436 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002437 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002438 }
2439
2440 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2441 if (err) {
2442 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2443 goto err_event_register;
2444 }
2445
2446 err = mlxsw_sp_traps_init(mlxsw_sp);
2447 if (err) {
2448 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2449 goto err_rx_listener_register;
2450 }
2451
2452 err = mlxsw_sp_flood_init(mlxsw_sp);
2453 if (err) {
2454 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2455 goto err_flood_init;
2456 }
2457
2458 err = mlxsw_sp_buffers_init(mlxsw_sp);
2459 if (err) {
2460 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2461 goto err_buffers_init;
2462 }
2463
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002464 err = mlxsw_sp_lag_init(mlxsw_sp);
2465 if (err) {
2466 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2467 goto err_lag_init;
2468 }
2469
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002470 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2471 if (err) {
2472 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2473 goto err_switchdev_init;
2474 }
2475
2476 return 0;
2477
2478err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002479err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02002480 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002481err_buffers_init:
2482err_flood_init:
2483 mlxsw_sp_traps_fini(mlxsw_sp);
2484err_rx_listener_register:
2485 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2486err_event_register:
2487 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002488 return err;
2489}
2490
Jiri Pirkob2f10572016-04-08 19:11:23 +02002491static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002492{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002493 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002494
2495 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02002496 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002497 mlxsw_sp_traps_fini(mlxsw_sp);
2498 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2499 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002500}
2501
2502static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2503 .used_max_vepa_channels = 1,
2504 .max_vepa_channels = 0,
2505 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002506 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002507 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002508 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002509 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002510 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002511 .used_max_pgt = 1,
2512 .max_pgt = 0,
2513 .used_max_system_port = 1,
2514 .max_system_port = 64,
2515 .used_max_vlan_groups = 1,
2516 .max_vlan_groups = 127,
2517 .used_max_regions = 1,
2518 .max_regions = 400,
2519 .used_flood_tables = 1,
2520 .used_flood_mode = 1,
2521 .flood_mode = 3,
2522 .max_fid_offset_flood_tables = 2,
2523 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002524 .max_fid_flood_tables = 2,
2525 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002526 .used_max_ib_mc = 1,
2527 .max_ib_mc = 0,
2528 .used_max_pkey = 1,
2529 .max_pkey = 0,
2530 .swid_config = {
2531 {
2532 .used_type = 1,
2533 .type = MLXSW_PORT_SWID_TYPE_ETH,
2534 }
2535 },
2536};
2537
2538static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko2d0ed392016-04-14 18:19:30 +02002539 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2540 .owner = THIS_MODULE,
2541 .priv_size = sizeof(struct mlxsw_sp),
2542 .init = mlxsw_sp_init,
2543 .fini = mlxsw_sp_fini,
2544 .port_split = mlxsw_sp_port_split,
2545 .port_unsplit = mlxsw_sp_port_unsplit,
2546 .sb_pool_get = mlxsw_sp_sb_pool_get,
2547 .sb_pool_set = mlxsw_sp_sb_pool_set,
2548 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2549 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2550 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2551 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2552 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2553 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2554 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2555 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2556 .txhdr_construct = mlxsw_sp_txhdr_construct,
2557 .txhdr_len = MLXSW_TXHDR_LEN,
2558 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002559};
2560
Ido Schimmel039c49a2016-01-27 15:20:18 +01002561static int
2562mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2563{
2564 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2565 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2566
2567 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2568 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2569
2570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2571}
2572
2573static int
2574mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2575 u16 fid)
2576{
2577 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2578 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2579
2580 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2581 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2582 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2583 mlxsw_sp_port->local_port);
2584
2585 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2586}
2587
2588static int
2589mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2590{
2591 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2592 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2593
2594 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2595 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2596
2597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2598}
2599
2600static int
2601mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2602 u16 fid)
2603{
2604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2605 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2606
2607 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2608 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2609 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2610
2611 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2612}
2613
2614static int
2615__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2616{
2617 int err, last_err = 0;
2618 u16 vid;
2619
2620 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2621 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2622 if (err)
2623 last_err = err;
2624 }
2625
2626 return last_err;
2627}
2628
2629static int
2630__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2631{
2632 int err, last_err = 0;
2633 u16 vid;
2634
2635 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2636 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2637 if (err)
2638 last_err = err;
2639 }
2640
2641 return last_err;
2642}
2643
2644static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2645{
2646 if (!list_empty(&mlxsw_sp_port->vports_list))
2647 if (mlxsw_sp_port->lagged)
2648 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2649 else
2650 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2651 else
2652 if (mlxsw_sp_port->lagged)
2653 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2654 else
2655 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2656}
2657
2658static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport)
2659{
2660 u16 vfid = mlxsw_sp_vport_vfid_get(mlxsw_sp_vport);
2661 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
2662
2663 if (mlxsw_sp_vport->lagged)
2664 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2665 fid);
2666 else
2667 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport, fid);
2668}
2669
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002670static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2671{
2672 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2673}
2674
2675static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port)
2676{
2677 struct net_device *dev = mlxsw_sp_port->dev;
2678 int err;
2679
2680 /* When port is not bridged untagged packets are tagged with
2681 * PVID=VID=1, thereby creating an implicit VLAN interface in
2682 * the device. Remove it and let bridge code take care of its
2683 * own VLANs.
2684 */
2685 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002686 if (err)
2687 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002688
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002689 mlxsw_sp_port->learning = 1;
2690 mlxsw_sp_port->learning_sync = 1;
2691 mlxsw_sp_port->uc_flood = 1;
2692 mlxsw_sp_port->bridged = 1;
2693
2694 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002695}
2696
Ido Schimmel039c49a2016-01-27 15:20:18 +01002697static int mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2698 bool flush_fdb)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002699{
2700 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002701
Ido Schimmel039c49a2016-01-27 15:20:18 +01002702 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2703 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2704
Ido Schimmel28a01d22016-02-18 11:30:02 +01002705 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2706
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002707 mlxsw_sp_port->learning = 0;
2708 mlxsw_sp_port->learning_sync = 0;
2709 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002710 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002711
2712 /* Add implicit VLAN interface in the device, so that untagged
2713 * packets will be classified to the default vFID.
2714 */
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002715 return mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002716}
2717
2718static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2719 struct net_device *br_dev)
2720{
2721 return !mlxsw_sp->master_bridge.dev ||
2722 mlxsw_sp->master_bridge.dev == br_dev;
2723}
2724
2725static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2726 struct net_device *br_dev)
2727{
2728 mlxsw_sp->master_bridge.dev = br_dev;
2729 mlxsw_sp->master_bridge.ref_count++;
2730}
2731
2732static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp,
2733 struct net_device *br_dev)
2734{
2735 if (--mlxsw_sp->master_bridge.ref_count == 0)
2736 mlxsw_sp->master_bridge.dev = NULL;
2737}
2738
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002739static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002740{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002741 char sldr_pl[MLXSW_REG_SLDR_LEN];
2742
2743 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2744 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2745}
2746
2747static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2748{
2749 char sldr_pl[MLXSW_REG_SLDR_LEN];
2750
2751 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2752 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2753}
2754
2755static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2756 u16 lag_id, u8 port_index)
2757{
2758 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2759 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2760
2761 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2762 lag_id, port_index);
2763 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2764}
2765
2766static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2767 u16 lag_id)
2768{
2769 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2770 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2771
2772 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2773 lag_id);
2774 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2775}
2776
2777static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2778 u16 lag_id)
2779{
2780 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2781 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2782
2783 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2784 lag_id);
2785 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2786}
2787
2788static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2789 u16 lag_id)
2790{
2791 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2792 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2793
2794 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2795 lag_id);
2796 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2797}
2798
2799static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2800 struct net_device *lag_dev,
2801 u16 *p_lag_id)
2802{
2803 struct mlxsw_sp_upper *lag;
2804 int free_lag_id = -1;
2805 int i;
2806
2807 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2808 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2809 if (lag->ref_count) {
2810 if (lag->dev == lag_dev) {
2811 *p_lag_id = i;
2812 return 0;
2813 }
2814 } else if (free_lag_id < 0) {
2815 free_lag_id = i;
2816 }
2817 }
2818 if (free_lag_id < 0)
2819 return -EBUSY;
2820 *p_lag_id = free_lag_id;
2821 return 0;
2822}
2823
2824static bool
2825mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2826 struct net_device *lag_dev,
2827 struct netdev_lag_upper_info *lag_upper_info)
2828{
2829 u16 lag_id;
2830
2831 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2832 return false;
2833 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2834 return false;
2835 return true;
2836}
2837
2838static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2839 u16 lag_id, u8 *p_port_index)
2840{
2841 int i;
2842
2843 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2844 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2845 *p_port_index = i;
2846 return 0;
2847 }
2848 }
2849 return -EBUSY;
2850}
2851
2852static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2853 struct net_device *lag_dev)
2854{
2855 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2856 struct mlxsw_sp_upper *lag;
2857 u16 lag_id;
2858 u8 port_index;
2859 int err;
2860
2861 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2862 if (err)
2863 return err;
2864 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2865 if (!lag->ref_count) {
2866 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2867 if (err)
2868 return err;
2869 lag->dev = lag_dev;
2870 }
2871
2872 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2873 if (err)
2874 return err;
2875 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2876 if (err)
2877 goto err_col_port_add;
2878 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2879 if (err)
2880 goto err_col_port_enable;
2881
2882 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2883 mlxsw_sp_port->local_port);
2884 mlxsw_sp_port->lag_id = lag_id;
2885 mlxsw_sp_port->lagged = 1;
2886 lag->ref_count++;
2887 return 0;
2888
Ido Schimmel51554db2016-05-06 22:18:39 +02002889err_col_port_enable:
2890 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002891err_col_port_add:
2892 if (!lag->ref_count)
2893 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002894 return err;
2895}
2896
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002897static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01002898 struct net_device *br_dev,
2899 bool flush_fdb);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002900
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002901static int mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2902 struct net_device *lag_dev)
2903{
2904 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002905 struct mlxsw_sp_port *mlxsw_sp_vport;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002906 struct mlxsw_sp_upper *lag;
2907 u16 lag_id = mlxsw_sp_port->lag_id;
2908 int err;
2909
2910 if (!mlxsw_sp_port->lagged)
2911 return 0;
2912 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2913 WARN_ON(lag->ref_count == 0);
2914
2915 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2916 if (err)
2917 return err;
Dan Carpenter82a06422015-12-09 13:33:51 +03002918 err = mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002919 if (err)
2920 return err;
2921
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002922 /* In case we leave a LAG device that has bridges built on top,
2923 * then their teardown sequence is never issued and we need to
2924 * invoke the necessary cleanup routines ourselves.
2925 */
2926 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2927 vport.list) {
2928 struct net_device *br_dev;
2929
2930 if (!mlxsw_sp_vport->bridged)
2931 continue;
2932
2933 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002934 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002935 }
2936
2937 if (mlxsw_sp_port->bridged) {
2938 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002939 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
Ido Schimmel912b1c82016-03-07 15:15:29 +01002940 mlxsw_sp_master_bridge_dec(mlxsw_sp, NULL);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002941 }
2942
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002943 if (lag->ref_count == 1) {
Ido Schimmel039c49a2016-01-27 15:20:18 +01002944 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2945 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002946 err = mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2947 if (err)
2948 return err;
2949 }
2950
2951 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2952 mlxsw_sp_port->local_port);
2953 mlxsw_sp_port->lagged = 0;
2954 lag->ref_count--;
2955 return 0;
2956}
2957
Jiri Pirko74581202015-12-03 12:12:30 +01002958static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2959 u16 lag_id)
2960{
2961 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2962 char sldr_pl[MLXSW_REG_SLDR_LEN];
2963
2964 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2965 mlxsw_sp_port->local_port);
2966 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2967}
2968
2969static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2970 u16 lag_id)
2971{
2972 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2973 char sldr_pl[MLXSW_REG_SLDR_LEN];
2974
2975 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2976 mlxsw_sp_port->local_port);
2977 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2978}
2979
2980static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2981 bool lag_tx_enabled)
2982{
2983 if (lag_tx_enabled)
2984 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2985 mlxsw_sp_port->lag_id);
2986 else
2987 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2988 mlxsw_sp_port->lag_id);
2989}
2990
2991static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2992 struct netdev_lag_lower_state_info *info)
2993{
2994 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2995}
2996
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002997static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2998 struct net_device *vlan_dev)
2999{
3000 struct mlxsw_sp_port *mlxsw_sp_vport;
3001 u16 vid = vlan_dev_vlan_id(vlan_dev);
3002
3003 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3004 if (!mlxsw_sp_vport) {
3005 WARN_ON(!mlxsw_sp_vport);
3006 return -EINVAL;
3007 }
3008
3009 mlxsw_sp_vport->dev = vlan_dev;
3010
3011 return 0;
3012}
3013
3014static int mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
3015 struct net_device *vlan_dev)
3016{
3017 struct mlxsw_sp_port *mlxsw_sp_vport;
3018 u16 vid = vlan_dev_vlan_id(vlan_dev);
3019
3020 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3021 if (!mlxsw_sp_vport) {
3022 WARN_ON(!mlxsw_sp_vport);
3023 return -EINVAL;
3024 }
3025
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003026 /* When removing a VLAN device while still bridged we should first
3027 * remove it from the bridge, as we receive the bridge's notification
3028 * when the vPort is already gone.
3029 */
3030 if (mlxsw_sp_vport->bridged) {
3031 struct net_device *br_dev;
3032
3033 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003034 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003035 }
3036
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003037 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
3038
3039 return 0;
3040}
3041
Jiri Pirko74581202015-12-03 12:12:30 +01003042static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3043 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003044{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003045 struct netdev_notifier_changeupper_info *info;
3046 struct mlxsw_sp_port *mlxsw_sp_port;
3047 struct net_device *upper_dev;
3048 struct mlxsw_sp *mlxsw_sp;
3049 int err;
3050
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003051 mlxsw_sp_port = netdev_priv(dev);
3052 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3053 info = ptr;
3054
3055 switch (event) {
3056 case NETDEV_PRECHANGEUPPER:
3057 upper_dev = info->upper_dev;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003058 if (!info->master || !info->linking)
3059 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003060 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003061 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003062 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
3063 return NOTIFY_BAD;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003064 if (netif_is_lag_master(upper_dev) &&
3065 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3066 info->upper_info))
3067 return NOTIFY_BAD;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003068 break;
3069 case NETDEV_CHANGEUPPER:
3070 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003071 if (is_vlan_dev(upper_dev)) {
3072 if (info->linking) {
3073 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3074 upper_dev);
3075 if (err) {
3076 netdev_err(dev, "Failed to link VLAN device\n");
3077 return NOTIFY_BAD;
3078 }
3079 } else {
3080 err = mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3081 upper_dev);
3082 if (err) {
3083 netdev_err(dev, "Failed to unlink VLAN device\n");
3084 return NOTIFY_BAD;
3085 }
3086 }
3087 } else if (netif_is_bridge_master(upper_dev)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003088 if (info->linking) {
3089 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port);
Ido Schimmel78124072016-01-04 10:42:24 +01003090 if (err) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003091 netdev_err(dev, "Failed to join bridge\n");
Ido Schimmel78124072016-01-04 10:42:24 +01003092 return NOTIFY_BAD;
3093 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003094 mlxsw_sp_master_bridge_inc(mlxsw_sp, upper_dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003095 } else {
Ido Schimmel039c49a2016-01-27 15:20:18 +01003096 err = mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
3097 true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003098 mlxsw_sp_master_bridge_dec(mlxsw_sp, upper_dev);
Ido Schimmel78124072016-01-04 10:42:24 +01003099 if (err) {
3100 netdev_err(dev, "Failed to leave bridge\n");
3101 return NOTIFY_BAD;
3102 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003103 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003104 } else if (netif_is_lag_master(upper_dev)) {
3105 if (info->linking) {
3106 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3107 upper_dev);
3108 if (err) {
3109 netdev_err(dev, "Failed to join link aggregation\n");
3110 return NOTIFY_BAD;
3111 }
3112 } else {
3113 err = mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3114 upper_dev);
3115 if (err) {
3116 netdev_err(dev, "Failed to leave link aggregation\n");
3117 return NOTIFY_BAD;
3118 }
3119 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003120 }
3121 break;
3122 }
3123
3124 return NOTIFY_DONE;
3125}
3126
Jiri Pirko74581202015-12-03 12:12:30 +01003127static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3128 unsigned long event, void *ptr)
3129{
3130 struct netdev_notifier_changelowerstate_info *info;
3131 struct mlxsw_sp_port *mlxsw_sp_port;
3132 int err;
3133
3134 mlxsw_sp_port = netdev_priv(dev);
3135 info = ptr;
3136
3137 switch (event) {
3138 case NETDEV_CHANGELOWERSTATE:
3139 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3140 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3141 info->lower_state_info);
3142 if (err)
3143 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3144 }
3145 break;
3146 }
3147
3148 return NOTIFY_DONE;
3149}
3150
3151static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3152 unsigned long event, void *ptr)
3153{
3154 switch (event) {
3155 case NETDEV_PRECHANGEUPPER:
3156 case NETDEV_CHANGEUPPER:
3157 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3158 case NETDEV_CHANGELOWERSTATE:
3159 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3160 }
3161
3162 return NOTIFY_DONE;
3163}
3164
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003165static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3166 unsigned long event, void *ptr)
3167{
3168 struct net_device *dev;
3169 struct list_head *iter;
3170 int ret;
3171
3172 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3173 if (mlxsw_sp_port_dev_check(dev)) {
3174 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3175 if (ret == NOTIFY_BAD)
3176 return ret;
3177 }
3178 }
3179
3180 return NOTIFY_DONE;
3181}
3182
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003183static struct mlxsw_sp_vfid *
3184mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3185 const struct net_device *br_dev)
3186{
3187 struct mlxsw_sp_vfid *vfid;
3188
3189 list_for_each_entry(vfid, &mlxsw_sp->br_vfids.list, list) {
3190 if (vfid->br_dev == br_dev)
3191 return vfid;
3192 }
3193
3194 return NULL;
3195}
3196
3197static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3198{
3199 return vfid - MLXSW_SP_VFID_PORT_MAX;
3200}
3201
3202static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3203{
3204 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3205}
3206
3207static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3208{
3209 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3210 MLXSW_SP_VFID_BR_MAX);
3211}
3212
3213static struct mlxsw_sp_vfid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3214 struct net_device *br_dev)
3215{
3216 struct device *dev = mlxsw_sp->bus_info->dev;
3217 struct mlxsw_sp_vfid *vfid;
3218 u16 n_vfid;
3219 int err;
3220
3221 n_vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3222 if (n_vfid == MLXSW_SP_VFID_MAX) {
3223 dev_err(dev, "No available vFIDs\n");
3224 return ERR_PTR(-ERANGE);
3225 }
3226
3227 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
3228 if (err) {
3229 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
3230 return ERR_PTR(err);
3231 }
3232
3233 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
3234 if (!vfid)
3235 goto err_allocate_vfid;
3236
3237 vfid->vfid = n_vfid;
3238 vfid->br_dev = br_dev;
3239
3240 list_add(&vfid->list, &mlxsw_sp->br_vfids.list);
3241 set_bit(mlxsw_sp_vfid_to_br_vfid(n_vfid), mlxsw_sp->br_vfids.mapped);
3242
3243 return vfid;
3244
3245err_allocate_vfid:
3246 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
3247 return ERR_PTR(-ENOMEM);
3248}
3249
3250static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3251 struct mlxsw_sp_vfid *vfid)
3252{
3253 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid->vfid);
3254
3255 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3256 list_del(&vfid->list);
3257
3258 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
3259
3260 kfree(vfid);
3261}
3262
3263static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003264 struct net_device *br_dev,
3265 bool flush_fdb)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003266{
3267 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3268 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3269 struct net_device *dev = mlxsw_sp_vport->dev;
3270 struct mlxsw_sp_vfid *vfid, *new_vfid;
3271 int err;
3272
3273 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3274 if (!vfid) {
3275 WARN_ON(!vfid);
3276 return -EINVAL;
3277 }
3278
3279 /* We need a vFID to go back to after leaving the bridge's vFID. */
3280 new_vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
3281 if (!new_vfid) {
3282 new_vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
3283 if (IS_ERR(new_vfid)) {
3284 netdev_err(dev, "Failed to create vFID for VID=%d\n",
3285 vid);
3286 return PTR_ERR(new_vfid);
3287 }
3288 }
3289
3290 /* Invalidate existing {Port, VID} to vFID mapping and create a new
3291 * one for the new vFID.
3292 */
3293 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3294 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3295 false,
3296 mlxsw_sp_vfid_to_fid(vfid->vfid),
3297 vid);
3298 if (err) {
3299 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3300 vfid->vfid);
3301 goto err_port_vid_to_fid_invalidate;
3302 }
3303
3304 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3305 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3306 true,
3307 mlxsw_sp_vfid_to_fid(new_vfid->vfid),
3308 vid);
3309 if (err) {
3310 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3311 new_vfid->vfid);
3312 goto err_port_vid_to_fid_validate;
3313 }
3314
3315 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3316 if (err) {
3317 netdev_err(dev, "Failed to disable learning\n");
3318 goto err_port_vid_learning_set;
3319 }
3320
3321 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
3322 false);
3323 if (err) {
3324 netdev_err(dev, "Failed clear to clear flooding\n");
3325 goto err_vport_flood_set;
3326 }
3327
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003328 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3329 MLXSW_REG_SPMS_STATE_FORWARDING);
3330 if (err) {
3331 netdev_err(dev, "Failed to set STP state\n");
3332 goto err_port_stp_state_set;
3333 }
3334
Ido Schimmel039c49a2016-01-27 15:20:18 +01003335 if (flush_fdb && mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport))
3336 netdev_err(dev, "Failed to flush FDB\n");
3337
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003338 /* Switch between the vFIDs and destroy the old one if needed. */
3339 new_vfid->nr_vports++;
3340 mlxsw_sp_vport->vport.vfid = new_vfid;
3341 vfid->nr_vports--;
3342 if (!vfid->nr_vports)
3343 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3344
3345 mlxsw_sp_vport->learning = 0;
3346 mlxsw_sp_vport->learning_sync = 0;
3347 mlxsw_sp_vport->uc_flood = 0;
3348 mlxsw_sp_vport->bridged = 0;
3349
3350 return 0;
3351
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003352err_port_stp_state_set:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003353err_vport_flood_set:
3354err_port_vid_learning_set:
3355err_port_vid_to_fid_validate:
3356err_port_vid_to_fid_invalidate:
3357 /* Rollback vFID only if new. */
3358 if (!new_vfid->nr_vports)
3359 mlxsw_sp_vfid_destroy(mlxsw_sp, new_vfid);
3360 return err;
3361}
3362
3363static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3364 struct net_device *br_dev)
3365{
3366 struct mlxsw_sp_vfid *old_vfid = mlxsw_sp_vport->vport.vfid;
3367 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3368 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3369 struct net_device *dev = mlxsw_sp_vport->dev;
3370 struct mlxsw_sp_vfid *vfid;
3371 int err;
3372
3373 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3374 if (!vfid) {
3375 vfid = mlxsw_sp_br_vfid_create(mlxsw_sp, br_dev);
3376 if (IS_ERR(vfid)) {
3377 netdev_err(dev, "Failed to create bridge vFID\n");
3378 return PTR_ERR(vfid);
3379 }
3380 }
3381
3382 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, true, false);
3383 if (err) {
3384 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
3385 vfid->vfid);
3386 goto err_port_flood_set;
3387 }
3388
3389 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3390 if (err) {
3391 netdev_err(dev, "Failed to enable learning\n");
3392 goto err_port_vid_learning_set;
3393 }
3394
3395 /* We need to invalidate existing {Port, VID} to vFID mapping and
3396 * create a new one for the bridge's vFID.
3397 */
3398 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3399 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3400 false,
3401 mlxsw_sp_vfid_to_fid(old_vfid->vfid),
3402 vid);
3403 if (err) {
3404 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3405 old_vfid->vfid);
3406 goto err_port_vid_to_fid_invalidate;
3407 }
3408
3409 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3410 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3411 true,
3412 mlxsw_sp_vfid_to_fid(vfid->vfid),
3413 vid);
3414 if (err) {
3415 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3416 vfid->vfid);
3417 goto err_port_vid_to_fid_validate;
3418 }
3419
3420 /* Switch between the vFIDs and destroy the old one if needed. */
3421 vfid->nr_vports++;
3422 mlxsw_sp_vport->vport.vfid = vfid;
3423 old_vfid->nr_vports--;
3424 if (!old_vfid->nr_vports)
3425 mlxsw_sp_vfid_destroy(mlxsw_sp, old_vfid);
3426
3427 mlxsw_sp_vport->learning = 1;
3428 mlxsw_sp_vport->learning_sync = 1;
3429 mlxsw_sp_vport->uc_flood = 1;
3430 mlxsw_sp_vport->bridged = 1;
3431
3432 return 0;
3433
3434err_port_vid_to_fid_validate:
3435 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3436 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
3437 mlxsw_sp_vfid_to_fid(old_vfid->vfid), vid);
3438err_port_vid_to_fid_invalidate:
3439 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3440err_port_vid_learning_set:
3441 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false, false);
3442err_port_flood_set:
3443 if (!vfid->nr_vports)
3444 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3445 return err;
3446}
3447
3448static bool
3449mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3450 const struct net_device *br_dev)
3451{
3452 struct mlxsw_sp_port *mlxsw_sp_vport;
3453
3454 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3455 vport.list) {
3456 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3457 return false;
3458 }
3459
3460 return true;
3461}
3462
3463static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3464 unsigned long event, void *ptr,
3465 u16 vid)
3466{
3467 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3468 struct netdev_notifier_changeupper_info *info = ptr;
3469 struct mlxsw_sp_port *mlxsw_sp_vport;
3470 struct net_device *upper_dev;
3471 int err;
3472
3473 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3474
3475 switch (event) {
3476 case NETDEV_PRECHANGEUPPER:
3477 upper_dev = info->upper_dev;
3478 if (!info->master || !info->linking)
3479 break;
3480 if (!netif_is_bridge_master(upper_dev))
3481 return NOTIFY_BAD;
3482 /* We can't have multiple VLAN interfaces configured on
3483 * the same port and being members in the same bridge.
3484 */
3485 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3486 upper_dev))
3487 return NOTIFY_BAD;
3488 break;
3489 case NETDEV_CHANGEUPPER:
3490 upper_dev = info->upper_dev;
3491 if (!info->master)
3492 break;
3493 if (info->linking) {
3494 if (!mlxsw_sp_vport) {
3495 WARN_ON(!mlxsw_sp_vport);
3496 return NOTIFY_BAD;
3497 }
3498 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3499 upper_dev);
3500 if (err) {
3501 netdev_err(dev, "Failed to join bridge\n");
3502 return NOTIFY_BAD;
3503 }
3504 } else {
3505 /* We ignore bridge's unlinking notifications if vPort
3506 * is gone, since we already left the bridge when the
3507 * VLAN device was unlinked from the real device.
3508 */
3509 if (!mlxsw_sp_vport)
3510 return NOTIFY_DONE;
3511 err = mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003512 upper_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003513 if (err) {
3514 netdev_err(dev, "Failed to leave bridge\n");
3515 return NOTIFY_BAD;
3516 }
3517 }
3518 }
3519
3520 return NOTIFY_DONE;
3521}
3522
Ido Schimmel272c4472015-12-15 16:03:47 +01003523static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3524 unsigned long event, void *ptr,
3525 u16 vid)
3526{
3527 struct net_device *dev;
3528 struct list_head *iter;
3529 int ret;
3530
3531 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3532 if (mlxsw_sp_port_dev_check(dev)) {
3533 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3534 vid);
3535 if (ret == NOTIFY_BAD)
3536 return ret;
3537 }
3538 }
3539
3540 return NOTIFY_DONE;
3541}
3542
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003543static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3544 unsigned long event, void *ptr)
3545{
3546 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3547 u16 vid = vlan_dev_vlan_id(vlan_dev);
3548
Ido Schimmel272c4472015-12-15 16:03:47 +01003549 if (mlxsw_sp_port_dev_check(real_dev))
3550 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3551 vid);
3552 else if (netif_is_lag_master(real_dev))
3553 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3554 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003555
Ido Schimmel272c4472015-12-15 16:03:47 +01003556 return NOTIFY_DONE;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003557}
3558
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003559static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3560 unsigned long event, void *ptr)
3561{
3562 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3563
3564 if (mlxsw_sp_port_dev_check(dev))
3565 return mlxsw_sp_netdevice_port_event(dev, event, ptr);
3566
3567 if (netif_is_lag_master(dev))
3568 return mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3569
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003570 if (is_vlan_dev(dev))
3571 return mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
3572
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003573 return NOTIFY_DONE;
3574}
3575
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003576static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3577 .notifier_call = mlxsw_sp_netdevice_event,
3578};
3579
3580static int __init mlxsw_sp_module_init(void)
3581{
3582 int err;
3583
3584 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3585 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3586 if (err)
3587 goto err_core_driver_register;
3588 return 0;
3589
3590err_core_driver_register:
3591 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3592 return err;
3593}
3594
3595static void __exit mlxsw_sp_module_exit(void)
3596{
3597 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3598 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3599}
3600
3601module_init(mlxsw_sp_module_init);
3602module_exit(mlxsw_sp_module_exit);
3603
3604MODULE_LICENSE("Dual BSD/GPL");
3605MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3606MODULE_DESCRIPTION("Mellanox Spectrum driver");
3607MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);