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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -070012#undef DEBUG
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
Sudhakar Mamillapalli0ad372b2012-04-10 14:10:58 -070020#include <linux/serial_reg.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
Andy Shevchenko21947ba2015-03-13 18:51:12 +020024#include <linux/rational.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
Andy Shevchenko9a1870c2014-08-19 20:29:22 +030029#include <linux/dmaengine.h>
30#include <linux/platform_data/dma-dw.h>
Andy Shevchenkof549e942015-02-23 16:24:43 +020031#include <linux/platform_data/dma-hsu.h>
Andy Shevchenko9a1870c2014-08-19 20:29:22 +030032
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include "8250.h"
34
Linus Torvalds1da177e2005-04-16 15:20:36 -070035/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
Frédéric Brière5bf8f502011-05-29 15:08:03 -040046 int (*probe)(struct pci_dev *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 int (*init)(struct pci_dev *dev);
Russell King975a1a72009-01-02 13:44:27 +000048 int (*setup)(struct serial_private *,
49 const struct pciserial_board *,
Alan Cox2655a2c2012-07-12 12:59:50 +010050 struct uart_8250_port *, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 void (*exit)(struct pci_dev *dev);
52};
53
54#define PCI_NUM_BAR_RESOURCES 6
55
56struct serial_private {
Russell King70db3d92005-07-27 11:34:27 +010057 struct pci_dev *dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 unsigned int nr;
59 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
60 struct pci_serial_quirk *quirk;
61 int line[0];
62};
63
Nicos Gollan7808edc2011-05-05 21:00:37 +020064static int pci_default_setup(struct serial_private*,
Alan Cox2655a2c2012-07-12 12:59:50 +010065 const struct pciserial_board*, struct uart_8250_port *, int);
Nicos Gollan7808edc2011-05-05 21:00:37 +020066
Linus Torvalds1da177e2005-04-16 15:20:36 -070067static void moan_device(const char *str, struct pci_dev *dev)
68{
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -070069 dev_err(&dev->dev,
Joe Perchesad361c92009-07-06 13:05:40 -070070 "%s: %s\n"
71 "Please send the output of lspci -vv, this\n"
72 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
73 "manufacturer and name of serial board or\n"
Russell Kingf2e0ea82015-03-06 10:49:21 +000074 "modem board to <linux-serial@vger.kernel.org>.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 pci_name(dev), str, dev->vendor, dev->device,
76 dev->subsystem_vendor, dev->subsystem_device);
77}
78
79static int
Alan Cox2655a2c2012-07-12 12:59:50 +010080setup_port(struct serial_private *priv, struct uart_8250_port *port,
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 int bar, int offset, int regshift)
82{
Russell King70db3d92005-07-27 11:34:27 +010083 struct pci_dev *dev = priv->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -070084
85 if (bar >= PCI_NUM_BAR_RESOURCES)
86 return -EINVAL;
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 if (!priv->remapped_bar[bar])
Aaron Sierra398a9db2014-10-30 19:49:45 -050090 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
Alan Cox2655a2c2012-07-12 12:59:50 +010094 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
Aaron Sierra398a9db2014-10-30 19:49:45 -050096 port->port.mapbase = pci_resource_start(dev, bar) + offset;
Alan Cox2655a2c2012-07-12 12:59:50 +010097 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 } else {
Alan Cox2655a2c2012-07-12 12:59:50 +0100100 port->port.iotype = UPIO_PORT;
Aaron Sierra398a9db2014-10-30 19:49:45 -0500101 port->port.iobase = pci_resource_start(dev, bar) + offset;
Alan Cox2655a2c2012-07-12 12:59:50 +0100102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 }
106 return 0;
107}
108
109/*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +0000113 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100114 struct uart_8250_port *port, int idx)
Krauth.Julien02c9b5c2008-02-04 22:27:49 -0800115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
135/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
Russell King975a1a72009-01-02 13:44:27 +0000140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100141 struct uart_8250_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142{
143 unsigned int bar, offset = board->first_offset;
Alan Cox5756ee92008-02-08 04:18:51 -0800144
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
Russell King70db3d92005-07-27 11:34:27 +0100153 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
Russell King61a116e2006-07-03 15:22:35 +0100163static int pci_hp_diva_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
Justin Chen551f8f02005-10-24 22:16:38 +0100181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
Russell King975a1a72009-01-02 13:44:27 +0000194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100196 struct uart_8250_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
Russell King70db3d92005-07-27 11:34:27 +0100201 switch (priv->dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
Russell King70db3d92005-07-27 11:34:27 +0100218 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
Russell King61a116e2006-07-03 15:22:35 +0100224static int pci_inteli960ni_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225{
Heikki Krogerus0a0d4122015-01-12 13:47:46 +0200226 u32 oldval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
Heikki Krogerus0a0d4122015-01-12 13:47:46 +0200232 pci_read_config_dword(dev, 0x44, &oldval);
Alan Cox5756ee92008-02-08 04:18:51 -0800233 if (oldval == 0x00001000L) { /* RESET value */
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -0700234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
Russell King61a116e2006-07-03 15:22:35 +0100246static int pci_plx9050_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
Bjorn Helgaasadd7b582005-10-24 22:11:57 +0100257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
Alan Cox5756ee92008-02-08 04:18:51 -0800258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 irq_config = 0x43;
Alan Cox5756ee92008-02-08 04:18:51 -0800260
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
Alan Cox5756ee92008-02-08 04:18:51 -0800262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 /*
273 * enable/disable interrupts
274 */
Alan Cox6f441fe2008-05-01 04:34:59 -0700275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500289static void pci_plx9050_exit(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
Alan Cox6f441fe2008-05-01 04:34:59 -0700299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
Will Page04bf7e72009-04-06 17:32:15 +0100311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500314static void pci_ni8420_exit(struct pci_dev *dev)
Will Page04bf7e72009-04-06 17:32:15 +0100315{
316 void __iomem *p;
Will Page04bf7e72009-04-06 17:32:15 +0100317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
Aaron Sierra398a9db2014-10-30 19:49:45 -0500324 p = pci_ioremap_bar(dev, bar);
Will Page04bf7e72009-04-06 17:32:15 +0100325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332}
333
334
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100335/* MITE registers */
336#define MITE_IOWBSR1 0xc4
337#define MITE_IOWCR1 0xf4
338#define MITE_LCIMR1 0x08
339#define MITE_LCIMR2 0x10
340
341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500343static void pci_ni8430_exit(struct pci_dev *dev)
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100344{
345 void __iomem *p;
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100346 unsigned int bar = 0;
347
348 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
349 moan_device("no memory in bar", dev);
350 return;
351 }
352
Aaron Sierra398a9db2014-10-30 19:49:45 -0500353 p = pci_ioremap_bar(dev, bar);
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100354 if (p == NULL)
355 return;
356
357 /* Disable the CPU Interrupt */
358 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
359 iounmap(p);
360}
361
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363static int
Russell King975a1a72009-01-02 13:44:27 +0000364sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100365 struct uart_8250_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366{
367 unsigned int bar, offset = board->first_offset;
368
369 bar = 0;
370
371 if (idx < 4) {
372 /* first four channels map to 0, 0x100, 0x200, 0x300 */
373 offset += idx * board->uart_offset;
374 } else if (idx < 8) {
375 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
376 offset += idx * board->uart_offset + 0xC00;
377 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return 1;
379
Russell King70db3d92005-07-27 11:34:27 +0100380 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381}
382
383/*
384* This does initialization for PMC OCTALPRO cards:
385* maps the device memory, resets the UARTs (needed, bc
386* if the module is removed and inserted again, the card
387* is in the sleep mode) and enables global interrupt.
388*/
389
390/* global control register offset for SBS PMC-OctalPro */
391#define OCT_REG_CR_OFF 0x500
392
Russell King61a116e2006-07-03 15:22:35 +0100393static int sbs_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394{
395 u8 __iomem *p;
396
Arjan van de Ven24ed3ab2009-06-24 18:34:58 +0100397 p = pci_ioremap_bar(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398
399 if (p == NULL)
400 return -ENOMEM;
401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
Alan Cox5756ee92008-02-08 04:18:51 -0800402 writeb(0x10, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 udelay(50);
Alan Cox5756ee92008-02-08 04:18:51 -0800404 writeb(0x0, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
406 /* Set bit-2 (INTENABLE) of Control Register */
407 writeb(0x4, p + OCT_REG_CR_OFF);
408 iounmap(p);
409
410 return 0;
411}
412
413/*
414 * Disables the global interrupt of PMC-OctalPro
415 */
416
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500417static void sbs_exit(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418{
419 u8 __iomem *p;
420
Arjan van de Ven24ed3ab2009-06-24 18:34:58 +0100421 p = pci_ioremap_bar(dev, 0);
Alan Cox5756ee92008-02-08 04:18:51 -0800422 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 if (p != NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 writeb(0, p + OCT_REG_CR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 iounmap(p);
426}
427
428/*
429 * SIIG serial cards have an PCI interface chip which also controls
430 * the UART clocking frequency. Each UART can be clocked independently
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300431 * (except cards equipped with 4 UARTs) and initial clocking settings
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432 * are stored in the EEPROM chip. It can cause problems because this
433 * version of serial driver doesn't support differently clocked UART's
434 * on single PCI card. To prevent this, initialization functions set
435 * high frequency clocking for all UART's on given card. It is safe (I
436 * hope) because it doesn't touch EEPROM settings to prevent conflicts
437 * with other OSes (like M$ DOS).
438 *
439 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
Alan Cox5756ee92008-02-08 04:18:51 -0800440 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 * There is two family of SIIG serial cards with different PCI
442 * interface chip and different configuration methods:
443 * - 10x cards have control registers in IO and/or memory space;
444 * - 20x cards have control registers in standard PCI configuration space.
445 *
Russell King67d74b82005-07-27 11:33:03 +0100446 * Note: all 10x cards have PCI device ids 0x10..
447 * all 20x cards have PCI device ids 0x20..
448 *
Andrey Paninfbc0dc02005-07-18 11:38:09 +0100449 * There are also Quartet Serial cards which use Oxford Semiconductor
450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 * Note: some SIIG cards are probed by the parport_serial object.
453 */
454
455#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
456#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457
458static int pci_siig10x_init(struct pci_dev *dev)
459{
460 u16 data;
461 void __iomem *p;
462
463 switch (dev->device & 0xfff8) {
464 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 data = 0xffdf;
466 break;
467 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 data = 0xf7ff;
469 break;
470 default: /* 1S1P, 4S */
471 data = 0xfffb;
472 break;
473 }
474
Alan Cox6f441fe2008-05-01 04:34:59 -0700475 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476 if (p == NULL)
477 return -ENOMEM;
478
479 writew(readw(p + 0x28) & data, p + 0x28);
480 readw(p + 0x28);
481 iounmap(p);
482 return 0;
483}
484
485#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
486#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487
488static int pci_siig20x_init(struct pci_dev *dev)
489{
490 u8 data;
491
492 /* Change clock frequency for the first UART. */
493 pci_read_config_byte(dev, 0x6f, &data);
494 pci_write_config_byte(dev, 0x6f, data & 0xef);
495
496 /* If this card has 2 UART, we have to do the same with second UART. */
497 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
498 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
499 pci_read_config_byte(dev, 0x73, &data);
500 pci_write_config_byte(dev, 0x73, data & 0xef);
501 }
502 return 0;
503}
504
Russell King67d74b82005-07-27 11:33:03 +0100505static int pci_siig_init(struct pci_dev *dev)
506{
507 unsigned int type = dev->device & 0xff00;
508
509 if (type == 0x1000)
510 return pci_siig10x_init(dev);
511 else if (type == 0x2000)
512 return pci_siig20x_init(dev);
513
514 moan_device("Unknown SIIG card", dev);
515 return -ENODEV;
516}
517
Andrey Panin3ec9c592006-02-02 20:15:09 +0000518static int pci_siig_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +0000519 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100520 struct uart_8250_port *port, int idx)
Andrey Panin3ec9c592006-02-02 20:15:09 +0000521{
522 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
523
524 if (idx > 3) {
525 bar = 4;
526 offset = (idx - 4) * 8;
527 }
528
529 return setup_port(priv, port, bar, offset, 0);
530}
531
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532/*
533 * Timedia has an explosion of boards, and to avoid the PCI table from
534 * growing *huge*, we use this function to collapse some 70 entries
535 * in the PCI table into one, for sanity's and compactness's sake.
536 */
Helge Dellere9422e02006-08-29 21:57:29 +0200537static const unsigned short timedia_single_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539};
540
Helge Dellere9422e02006-08-29 21:57:29 +0200541static const unsigned short timedia_dual_port[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
Alan Cox5756ee92008-02-08 04:18:51 -0800543 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
544 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
546 0xD079, 0
547};
548
Helge Dellere9422e02006-08-29 21:57:29 +0200549static const unsigned short timedia_quad_port[] = {
Alan Cox5756ee92008-02-08 04:18:51 -0800550 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
551 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
553 0xB157, 0
554};
555
Helge Dellere9422e02006-08-29 21:57:29 +0200556static const unsigned short timedia_eight_port[] = {
Alan Cox5756ee92008-02-08 04:18:51 -0800557 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559};
560
Arjan van de Vencb3592b2005-11-28 21:04:11 +0000561static const struct timedia_struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 int num;
Helge Dellere9422e02006-08-29 21:57:29 +0200563 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564} timedia_data[] = {
565 { 1, timedia_single_port },
566 { 2, timedia_dual_port },
567 { 4, timedia_quad_port },
Helge Dellere9422e02006-08-29 21:57:29 +0200568 { 8, timedia_eight_port }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569};
570
Frédéric Brièreb9b24552011-05-29 15:08:04 -0400571/*
572 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
573 * listing them individually, this driver merely grabs them all with
574 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
575 * and should be left free to be claimed by parport_serial instead.
576 */
577static int pci_timedia_probe(struct pci_dev *dev)
578{
579 /*
580 * Check the third digit of the subdevice ID
581 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 */
583 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 dev_info(&dev->dev,
585 "ignoring Timedia subdevice %04x for parport_serial\n",
586 dev->subsystem_device);
587 return -ENODEV;
588 }
589
590 return 0;
591}
592
Russell King61a116e2006-07-03 15:22:35 +0100593static int pci_timedia_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594{
Helge Dellere9422e02006-08-29 21:57:29 +0200595 const unsigned short *ids;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 int i, j;
597
Helge Dellere9422e02006-08-29 21:57:29 +0200598 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 ids = timedia_data[i].ids;
600 for (j = 0; ids[j]; j++)
601 if (dev->subsystem_device == ids[j])
602 return timedia_data[i].num;
603 }
604 return 0;
605}
606
607/*
608 * Timedia/SUNIX uses a mixture of BARs and offsets
609 * Ugh, this is ugly as all hell --- TYT
610 */
611static int
Russell King975a1a72009-01-02 13:44:27 +0000612pci_timedia_setup(struct serial_private *priv,
613 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100614 struct uart_8250_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615{
616 unsigned int bar = 0, offset = board->first_offset;
617
618 switch (idx) {
619 case 0:
620 bar = 0;
621 break;
622 case 1:
623 offset = board->uart_offset;
624 bar = 0;
625 break;
626 case 2:
627 bar = 1;
628 break;
629 case 3:
630 offset = board->uart_offset;
Dave Jonesc2cd6d32005-12-07 18:11:26 +0000631 /* FALLTHROUGH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632 case 4: /* BAR 2 */
633 case 5: /* BAR 3 */
634 case 6: /* BAR 4 */
635 case 7: /* BAR 5 */
636 bar = idx - 2;
637 }
638
Russell King70db3d92005-07-27 11:34:27 +0100639 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640}
641
642/*
643 * Some Titan cards are also a little weird
644 */
645static int
Russell King70db3d92005-07-27 11:34:27 +0100646titan_400l_800l_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +0000647 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100648 struct uart_8250_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649{
650 unsigned int bar, offset = board->first_offset;
651
652 switch (idx) {
653 case 0:
654 bar = 1;
655 break;
656 case 1:
657 bar = 2;
658 break;
659 default:
660 bar = 4;
661 offset = (idx - 2) * board->uart_offset;
662 }
663
Russell King70db3d92005-07-27 11:34:27 +0100664 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665}
666
Russell King61a116e2006-07-03 15:22:35 +0100667static int pci_xircom_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668{
669 msleep(100);
670 return 0;
671}
672
Will Page04bf7e72009-04-06 17:32:15 +0100673static int pci_ni8420_init(struct pci_dev *dev)
674{
675 void __iomem *p;
Will Page04bf7e72009-04-06 17:32:15 +0100676 unsigned int bar = 0;
677
678 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
679 moan_device("no memory in bar", dev);
680 return 0;
681 }
682
Aaron Sierra398a9db2014-10-30 19:49:45 -0500683 p = pci_ioremap_bar(dev, bar);
Will Page04bf7e72009-04-06 17:32:15 +0100684 if (p == NULL)
685 return -ENOMEM;
686
687 /* Enable CPU Interrupt */
688 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
689 p + NI8420_INT_ENABLE_REG);
690
691 iounmap(p);
692 return 0;
693}
694
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100695#define MITE_IOWBSR1_WSIZE 0xa
696#define MITE_IOWBSR1_WIN_OFFSET 0x800
697#define MITE_IOWBSR1_WENAB (1 << 7)
698#define MITE_LCIMR1_IO_IE_0 (1 << 24)
699#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
700#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701
702static int pci_ni8430_init(struct pci_dev *dev)
703{
704 void __iomem *p;
Aaron Sierra398a9db2014-10-30 19:49:45 -0500705 struct pci_bus_region region;
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100706 u32 device_window;
707 unsigned int bar = 0;
708
709 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
710 moan_device("no memory in bar", dev);
711 return 0;
712 }
713
Aaron Sierra398a9db2014-10-30 19:49:45 -0500714 p = pci_ioremap_bar(dev, bar);
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100715 if (p == NULL)
716 return -ENOMEM;
717
Aaron Sierra398a9db2014-10-30 19:49:45 -0500718 /*
719 * Set device window address and size in BAR0, while acknowledging that
720 * the resource structure may contain a translated address that differs
721 * from the address the device responds to.
722 */
723 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
724 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100725 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
726 writel(device_window, p + MITE_IOWBSR1);
727
728 /* Set window access to go to RAMSEL IO address space */
729 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 p + MITE_IOWCR1);
731
732 /* Enable IO Bus Interrupt 0 */
733 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734
735 /* Enable CPU Interrupt */
736 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
737
738 iounmap(p);
739 return 0;
740}
741
742/* UART Port Control Register */
743#define NI8430_PORTCON 0x0f
744#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745
746static int
Alan Coxbf538fe2009-04-06 17:35:42 +0100747pci_ni8430_setup(struct serial_private *priv,
748 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100749 struct uart_8250_port *port, int idx)
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100750{
Aaron Sierra398a9db2014-10-30 19:49:45 -0500751 struct pci_dev *dev = priv->dev;
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100752 void __iomem *p;
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100753 unsigned int bar, offset = board->first_offset;
754
755 if (idx >= board->num_ports)
756 return 1;
757
758 bar = FL_GET_BASE(board->flags);
759 offset += idx * board->uart_offset;
760
Aaron Sierra398a9db2014-10-30 19:49:45 -0500761 p = pci_ioremap_bar(dev, bar);
Aaron Sierra5d14bba2014-10-30 19:49:52 -0500762 if (!p)
763 return -ENOMEM;
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100764
Joe Perches7c9d4402011-06-23 11:39:20 -0700765 /* enable the transceiver */
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100766 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
767 p + offset + NI8430_PORTCON);
768
769 iounmap(p);
770
771 return setup_port(priv, port, bar, offset, board->reg_shift);
772}
773
Nicos Gollan7808edc2011-05-05 21:00:37 +0200774static int pci_netmos_9900_setup(struct serial_private *priv,
775 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +0100776 struct uart_8250_port *port, int idx)
Nicos Gollan7808edc2011-05-05 21:00:37 +0200777{
778 unsigned int bar;
779
Dmitry Eremin-Solenikov333c0852014-02-11 14:18:13 +0400780 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
781 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
Nicos Gollan7808edc2011-05-05 21:00:37 +0200782 /* netmos apparently orders BARs by datasheet layout, so serial
783 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
784 */
785 bar = 3 * idx;
786
787 return setup_port(priv, port, bar, 0, board->reg_shift);
788 } else {
789 return pci_default_setup(priv, board, port, idx);
790 }
791}
792
793/* the 99xx series comes with a range of device IDs and a variety
794 * of capabilities:
795 *
796 * 9900 has varying capabilities and can cascade to sub-controllers
797 * (cascading should be purely internal)
798 * 9904 is hardwired with 4 serial ports
799 * 9912 and 9922 are hardwired with 2 serial ports
800 */
801static int pci_netmos_9900_numports(struct pci_dev *dev)
802{
803 unsigned int c = dev->class;
804 unsigned int pi;
805 unsigned short sub_serports;
806
807 pi = (c & 0xff);
808
809 if (pi == 2) {
810 return 1;
811 } else if ((pi == 0) &&
812 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
813 /* two possibilities: 0x30ps encodes number of parallel and
814 * serial ports, or 0x1000 indicates *something*. This is not
815 * immediately obvious, since the 2s1p+4s configuration seems
816 * to offer all functionality on functions 0..2, while still
817 * advertising the same function 3 as the 4s+2s1p config.
818 */
819 sub_serports = dev->subsystem_device & 0xf;
820 if (sub_serports > 0) {
821 return sub_serports;
822 } else {
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -0700823 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
Nicos Gollan7808edc2011-05-05 21:00:37 +0200824 return 0;
825 }
826 }
827
828 moan_device("unknown NetMos/Mostech program interface", dev);
829 return 0;
830}
Shawn Bohrer46a0fac2009-04-06 17:32:07 +0100831
Russell King61a116e2006-07-03 15:22:35 +0100832static int pci_netmos_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833{
834 /* subdevice 0x00PS means <P> parallel, <S> serial */
835 unsigned int num_serial = dev->subsystem_device & 0xf;
836
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -0800837 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
838 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
Michael Bueschc4285b42009-06-30 11:41:21 -0700839 return 0;
Nicos Gollan7808edc2011-05-05 21:00:37 +0200840
Jiri Slaby25cf9bc2009-01-15 13:30:34 +0000841 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
842 dev->subsystem_device == 0x0299)
843 return 0;
844
Nicos Gollan7808edc2011-05-05 21:00:37 +0200845 switch (dev->device) { /* FALLTHROUGH on all */
846 case PCI_DEVICE_ID_NETMOS_9904:
847 case PCI_DEVICE_ID_NETMOS_9912:
848 case PCI_DEVICE_ID_NETMOS_9922:
849 case PCI_DEVICE_ID_NETMOS_9900:
850 num_serial = pci_netmos_9900_numports(dev);
851 break;
852
853 default:
854 if (num_serial == 0 ) {
855 moan_device("unknown NetMos/Mostech device", dev);
856 }
857 }
858
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 if (num_serial == 0)
860 return -ENODEV;
Nicos Gollan7808edc2011-05-05 21:00:37 +0200861
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 return num_serial;
863}
864
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700865/*
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700866 * These chips are available with optionally one parallel port and up to
867 * two serial ports. Unfortunately they all have the same product id.
868 *
869 * Basic configuration is done over a region of 32 I/O ports. The base
870 * ioport is called INTA or INTC, depending on docs/other drivers.
871 *
872 * The region of the 32 I/O ports is configured in POSIO0R...
873 */
874
875/* registers */
876#define ITE_887x_MISCR 0x9c
877#define ITE_887x_INTCBAR 0x78
878#define ITE_887x_UARTBAR 0x7c
879#define ITE_887x_PS0BAR 0x10
880#define ITE_887x_POSIO0 0x60
881
882/* I/O space size */
883#define ITE_887x_IOSIZE 32
884/* I/O space size (bits 26-24; 8 bytes = 011b) */
885#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
886/* I/O space size (bits 26-24; 32 bytes = 101b) */
887#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
888/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
889#define ITE_887x_POSIO_SPEED (3 << 29)
890/* enable IO_Space bit */
891#define ITE_887x_POSIO_ENABLE (1 << 31)
892
Ralf Baechlef79abb82007-08-30 23:56:31 -0700893static int pci_ite887x_init(struct pci_dev *dev)
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700894{
895 /* inta_addr are the configuration addresses of the ITE */
896 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 0x200, 0x280, 0 };
898 int ret, i, type;
899 struct resource *iobase = NULL;
900 u32 miscr, uartbar, ioport;
901
902 /* search for the base-ioport */
903 i = 0;
904 while (inta_addr[i] && iobase == NULL) {
905 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 "ite887x");
907 if (iobase != NULL) {
908 /* write POSIO0R - speed | size | ioport */
909 pci_write_config_dword(dev, ITE_887x_POSIO0,
910 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
911 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
912 /* write INTCBAR - ioport */
Alan Cox5756ee92008-02-08 04:18:51 -0800913 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 inta_addr[i]);
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700915 ret = inb(inta_addr[i]);
916 if (ret != 0xff) {
917 /* ioport connected */
918 break;
919 }
920 release_region(iobase->start, ITE_887x_IOSIZE);
921 iobase = NULL;
922 }
923 i++;
924 }
925
926 if (!inta_addr[i]) {
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -0700927 dev_err(&dev->dev, "ite887x: could not find iobase\n");
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985}
986
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500987static void pci_ite887x_exit(struct pci_dev *dev)
Niels de Vos84f8c6f2007-08-22 14:01:14 -0700988{
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994}
995
Russell King9f2a0362009-01-02 13:44:20 +0000996/*
Mike Skoog1bc8cde2014-10-16 13:10:01 -0700997 * EndRun Technologies.
998 * Determine the number of ports available on the device.
999 */
1000#define PCI_VENDOR_ID_ENDRUN 0x7401
1001#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
1003static int pci_endrun_init(struct pci_dev *dev)
1004{
1005 u8 __iomem *p;
1006 unsigned long deviceID;
1007 unsigned int number_uarts = 0;
1008
1009 /* EndRun device is all 0xexxx */
1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011 (dev->device & 0xf000) != 0xe000)
1012 return 0;
1013
1014 p = pci_iomap(dev, 0, 5);
1015 if (p == NULL)
1016 return -ENOMEM;
1017
1018 deviceID = ioread32(p);
1019 /* EndRun device */
1020 if (deviceID == 0x07000200) {
1021 number_uarts = ioread8(p + 4);
1022 dev_dbg(&dev->dev,
1023 "%d ports detected on EndRun PCI Express device\n",
1024 number_uarts);
1025 }
1026 pci_iounmap(dev, p);
1027 return number_uarts;
1028}
1029
1030/*
Russell King9f2a0362009-01-02 13:44:20 +00001031 * Oxford Semiconductor Inc.
1032 * Check that device is part of the Tornado range of devices, then determine
1033 * the number of ports available on the device.
1034 */
1035static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036{
1037 u8 __iomem *p;
1038 unsigned long deviceID;
1039 unsigned int number_uarts = 0;
1040
1041 /* OxSemi Tornado devices are all 0xCxxx */
1042 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043 (dev->device & 0xF000) != 0xC000)
1044 return 0;
1045
1046 p = pci_iomap(dev, 0, 5);
1047 if (p == NULL)
1048 return -ENOMEM;
1049
1050 deviceID = ioread32(p);
1051 /* Tornado device */
1052 if (deviceID == 0x07000200) {
1053 number_uarts = ioread8(p + 4);
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -07001054 dev_dbg(&dev->dev,
Russell King9f2a0362009-01-02 13:44:20 +00001055 "%d ports detected on Oxford PCI Express device\n",
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -07001056 number_uarts);
Russell King9f2a0362009-01-02 13:44:20 +00001057 }
1058 pci_iounmap(dev, p);
1059 return number_uarts;
1060}
1061
Alan Coxeb26dfe2012-07-12 13:00:31 +01001062static int pci_asix_setup(struct serial_private *priv,
Russell King975a1a72009-01-02 13:44:27 +00001063 const struct pciserial_board *board,
Alan Coxeb26dfe2012-07-12 13:00:31 +01001064 struct uart_8250_port *port, int idx)
1065{
1066 port->bugs |= UART_BUG_PARITY;
1067 return pci_default_setup(priv, board, port, idx);
1068}
1069
Alan Cox55c7c0f2012-11-29 09:03:00 +10301070/* Quatech devices have their own extra interface features */
1071
1072struct quatech_feature {
1073 u16 devid;
1074 bool amcc;
1075};
1076
1077#define QPCR_TEST_FOR1 0x3F
1078#define QPCR_TEST_GET1 0x00
1079#define QPCR_TEST_FOR2 0x40
1080#define QPCR_TEST_GET2 0x40
1081#define QPCR_TEST_FOR3 0x80
1082#define QPCR_TEST_GET3 0x40
1083#define QPCR_TEST_FOR4 0xC0
1084#define QPCR_TEST_GET4 0x80
1085
1086#define QOPR_CLOCK_X1 0x0000
1087#define QOPR_CLOCK_X2 0x0001
1088#define QOPR_CLOCK_X4 0x0002
1089#define QOPR_CLOCK_X8 0x0003
1090#define QOPR_CLOCK_RATE_MASK 0x0003
1091
1092
1093static struct quatech_feature quatech_cards[] = {
1094 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1100 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113 { 0, }
1114};
1115
1116static int pci_quatech_amcc(u16 devid)
1117{
1118 struct quatech_feature *qf = &quatech_cards[0];
1119 while (qf->devid) {
1120 if (qf->devid == devid)
1121 return qf->amcc;
1122 qf++;
1123 }
1124 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125 return 0;
1126};
1127
1128static int pci_quatech_rqopr(struct uart_8250_port *port)
1129{
1130 unsigned long base = port->port.iobase;
1131 u8 LCR, val;
1132
1133 LCR = inb(base + UART_LCR);
1134 outb(0xBF, base + UART_LCR);
1135 val = inb(base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137 return val;
1138}
1139
1140static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(qopr, base + UART_SCR);
1149 outb(LCR, base + UART_LCR);
1150}
1151
1152static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153{
1154 unsigned long base = port->port.iobase;
1155 u8 LCR, val, qmcr;
1156
1157 LCR = inb(base + UART_LCR);
1158 outb(0xBF, base + UART_LCR);
1159 val = inb(base + UART_SCR);
1160 outb(val | 0x10, base + UART_SCR);
1161 qmcr = inb(base + UART_MCR);
1162 outb(val, base + UART_SCR);
1163 outb(LCR, base + UART_LCR);
1164
1165 return qmcr;
1166}
1167
1168static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169{
1170 unsigned long base = port->port.iobase;
1171 u8 LCR, val;
1172
1173 LCR = inb(base + UART_LCR);
1174 outb(0xBF, base + UART_LCR);
1175 val = inb(base + UART_SCR);
1176 outb(val | 0x10, base + UART_SCR);
1177 outb(qmcr, base + UART_MCR);
1178 outb(val, base + UART_SCR);
1179 outb(LCR, base + UART_LCR);
1180}
1181
1182static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183{
1184 unsigned long base = port->port.iobase;
1185 u8 LCR, val;
1186
1187 LCR = inb(base + UART_LCR);
1188 outb(0xBF, base + UART_LCR);
1189 val = inb(base + UART_SCR);
1190 if (val & 0x20) {
1191 outb(0x80, UART_LCR);
1192 if (!(inb(UART_SCR) & 0x20)) {
1193 outb(LCR, base + UART_LCR);
1194 return 1;
1195 }
1196 }
1197 return 0;
1198}
1199
1200static int pci_quatech_test(struct uart_8250_port *port)
1201{
1202 u8 reg;
1203 u8 qopr = pci_quatech_rqopr(port);
1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205 reg = pci_quatech_rqopr(port) & 0xC0;
1206 if (reg != QPCR_TEST_GET1)
1207 return -EINVAL;
1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209 reg = pci_quatech_rqopr(port) & 0xC0;
1210 if (reg != QPCR_TEST_GET2)
1211 return -EINVAL;
1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET3)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET4)
1219 return -EINVAL;
1220
1221 pci_quatech_wqopr(port, qopr);
1222 return 0;
1223}
1224
1225static int pci_quatech_clock(struct uart_8250_port *port)
1226{
1227 u8 qopr, reg, set;
1228 unsigned long clock;
1229
1230 if (pci_quatech_test(port) < 0)
1231 return 1843200;
1232
1233 qopr = pci_quatech_rqopr(port);
1234
1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (reg & QOPR_CLOCK_X8) {
1238 clock = 1843200;
1239 goto out;
1240 }
1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (!(reg & QOPR_CLOCK_X8)) {
1244 clock = 1843200;
1245 goto out;
1246 }
1247 reg &= QOPR_CLOCK_X8;
1248 if (reg == QOPR_CLOCK_X2) {
1249 clock = 3685400;
1250 set = QOPR_CLOCK_X2;
1251 } else if (reg == QOPR_CLOCK_X4) {
1252 clock = 7372800;
1253 set = QOPR_CLOCK_X4;
1254 } else if (reg == QOPR_CLOCK_X8) {
1255 clock = 14745600;
1256 set = QOPR_CLOCK_X8;
1257 } else {
1258 clock = 1843200;
1259 set = QOPR_CLOCK_X1;
1260 }
1261 qopr &= ~QOPR_CLOCK_RATE_MASK;
1262 qopr |= set;
1263
1264out:
1265 pci_quatech_wqopr(port, qopr);
1266 return clock;
1267}
1268
1269static int pci_quatech_rs422(struct uart_8250_port *port)
1270{
1271 u8 qmcr;
1272 int rs422 = 0;
1273
1274 if (!pci_quatech_has_qmcr(port))
1275 return 0;
1276 qmcr = pci_quatech_rqmcr(port);
1277 pci_quatech_wqmcr(port, 0xFF);
1278 if (pci_quatech_rqmcr(port))
1279 rs422 = 1;
1280 pci_quatech_wqmcr(port, qmcr);
1281 return rs422;
1282}
1283
1284static int pci_quatech_init(struct pci_dev *dev)
1285{
1286 if (pci_quatech_amcc(dev->device)) {
1287 unsigned long base = pci_resource_start(dev, 0);
1288 if (base) {
1289 u32 tmp;
Jonathan Woithe9c5320f2013-12-09 16:33:08 +10301290 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
Alan Cox55c7c0f2012-11-29 09:03:00 +10301291 tmp = inl(base + 0x3c);
1292 outl(tmp | 0x01000000, base + 0x3c);
Jonathan Woithe9c5320f2013-12-09 16:33:08 +10301293 outl(tmp &= ~0x01000000, base + 0x3c);
Alan Cox55c7c0f2012-11-29 09:03:00 +10301294 }
1295 }
1296 return 0;
1297}
1298
1299static int pci_quatech_setup(struct serial_private *priv,
1300 const struct pciserial_board *board,
1301 struct uart_8250_port *port, int idx)
1302{
1303 /* Needed by pci_quatech calls below */
1304 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305 /* Set up the clocking */
1306 port->port.uartclk = pci_quatech_clock(port);
1307 /* For now just warn about RS422 */
1308 if (pci_quatech_rs422(port))
1309 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310 return pci_default_setup(priv, board, port, idx);
1311}
1312
Greg Kroah-Hartmand73dfc62013-01-15 22:44:48 -08001313static void pci_quatech_exit(struct pci_dev *dev)
Alan Cox55c7c0f2012-11-29 09:03:00 +10301314{
1315}
1316
Alan Coxeb26dfe2012-07-12 13:00:31 +01001317static int pci_default_setup(struct serial_private *priv,
Russell King70db3d92005-07-27 11:34:27 +01001318 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +01001319 struct uart_8250_port *port, int idx)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320{
1321 unsigned int bar, offset = board->first_offset, maxnr;
1322
1323 bar = FL_GET_BASE(board->flags);
1324 if (board->flags & FL_BASE_BARS)
1325 bar += idx;
1326 else
1327 offset += idx * board->uart_offset;
1328
Greg Kroah-Hartman2427ddd2006-06-12 17:07:52 -07001329 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330 (board->reg_shift + 3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001331
1332 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return 1;
Alan Cox5756ee92008-02-08 04:18:51 -08001334
Russell King70db3d92005-07-27 11:34:27 +01001335 return setup_port(priv, port, bar, offset, board->reg_shift);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336}
1337
Angelo Butti94341472013-10-15 22:41:10 +03001338static int pci_pericom_setup(struct serial_private *priv,
1339 const struct pciserial_board *board,
1340 struct uart_8250_port *port, int idx)
1341{
1342 unsigned int bar, offset = board->first_offset, maxnr;
1343
1344 bar = FL_GET_BASE(board->flags);
1345 if (board->flags & FL_BASE_BARS)
1346 bar += idx;
1347 else
1348 offset += idx * board->uart_offset;
1349
1350 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351 (board->reg_shift + 3);
1352
1353 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return 1;
1355
1356 port->port.uartclk = 14745600;
1357
1358 return setup_port(priv, port, bar, offset, board->reg_shift);
1359}
1360
Dirk Brandewie095e24b2010-11-17 07:35:20 -08001361static int
1362ce4100_serial_setup(struct serial_private *priv,
1363 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +01001364 struct uart_8250_port *port, int idx)
Dirk Brandewie095e24b2010-11-17 07:35:20 -08001365{
1366 int ret;
1367
Maxime Bizon08ec2122012-10-19 10:45:07 +02001368 ret = setup_port(priv, port, idx, 0, board->reg_shift);
Alan Cox2655a2c2012-07-12 12:59:50 +01001369 port->port.iotype = UPIO_MEM32;
1370 port->port.type = PORT_XSCALE;
1371 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372 port->port.regshift = 2;
Dirk Brandewie095e24b2010-11-17 07:35:20 -08001373
1374 return ret;
1375}
1376
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001377#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1378#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379
Alan Cox29897082014-08-19 20:29:23 +03001380#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1381#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001383#define BYT_PRV_CLK 0x800
1384#define BYT_PRV_CLK_EN (1 << 0)
1385#define BYT_PRV_CLK_M_VAL_SHIFT 1
1386#define BYT_PRV_CLK_N_VAL_SHIFT 16
1387#define BYT_PRV_CLK_UPDATE (1 << 31)
1388
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001389#define BYT_TX_OVF_INT 0x820
1390#define BYT_TX_OVF_INT_MASK (1 << 1)
1391
1392static void
1393byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394 struct ktermios *old)
1395{
1396 unsigned int baud = tty_termios_baud_rate(termios);
Andy Shevchenko21947ba2015-03-13 18:51:12 +02001397 unsigned long fref = 100000000, fuart = baud * 16;
1398 unsigned long w = BIT(15) - 1;
1399 unsigned long m, n;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001400 u32 reg;
1401
Andy Shevchenko21947ba2015-03-13 18:51:12 +02001402 /* Get Fuart closer to Fref */
1403 fuart *= rounddown_pow_of_two(fref / fuart);
1404
Aaron Sierra50825c52014-03-03 19:54:29 -06001405 /*
1406 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407 * dividers must be adjusted.
1408 *
1409 * uartclk = (m / n) * 100 MHz, where m <= n
1410 */
Andy Shevchenko21947ba2015-03-13 18:51:12 +02001411 rational_best_approximation(fuart, fref, w, w, &m, &n);
1412 p->uartclk = fuart;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001413
1414 /* Reset the clock */
1415 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416 writel(reg, p->membase + BYT_PRV_CLK);
1417 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001420 serial8250_do_set_termios(p, termios, old);
1421}
1422
1423static bool byt_dma_filter(struct dma_chan *chan, void *param)
1424{
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001425 struct dw_dma_slave *dws = param;
1426
1427 if (dws->dma_dev != chan->device->dev)
1428 return false;
1429
1430 chan->private = dws;
1431 return true;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001432}
1433
1434static int
1435byt_serial_setup(struct serial_private *priv,
1436 const struct pciserial_board *board,
1437 struct uart_8250_port *port, int idx)
1438{
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001439 struct pci_dev *pdev = priv->dev;
1440 struct device *dev = port->port.dev;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001441 struct uart_8250_dma *dma;
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001442 struct dw_dma_slave *tx_param, *rx_param;
1443 struct pci_dev *dma_dev;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001444 int ret;
1445
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001446 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001447 if (!dma)
1448 return -ENOMEM;
1449
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001450 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1451 if (!tx_param)
1452 return -ENOMEM;
1453
1454 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1455 if (!rx_param)
1456 return -ENOMEM;
1457
1458 switch (pdev->device) {
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001459 case PCI_DEVICE_ID_INTEL_BYT_UART1:
Alan Cox29897082014-08-19 20:29:23 +03001460 case PCI_DEVICE_ID_INTEL_BSW_UART1:
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001461 rx_param->src_id = 3;
1462 tx_param->dst_id = 2;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001463 break;
1464 case PCI_DEVICE_ID_INTEL_BYT_UART2:
Alan Cox29897082014-08-19 20:29:23 +03001465 case PCI_DEVICE_ID_INTEL_BSW_UART2:
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001466 rx_param->src_id = 5;
1467 tx_param->dst_id = 4;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001468 break;
1469 default:
1470 return -EINVAL;
1471 }
1472
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001473 rx_param->src_master = 1;
1474 rx_param->dst_master = 0;
1475
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001476 dma->rxconf.src_maxburst = 16;
1477
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001478 tx_param->src_master = 1;
1479 tx_param->dst_master = 0;
1480
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001481 dma->txconf.dst_maxburst = 16;
1482
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001483 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1484 rx_param->dma_dev = &dma_dev->dev;
1485 tx_param->dma_dev = &dma_dev->dev;
1486
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001487 dma->fn = byt_dma_filter;
Andy Shevchenko9a1870c2014-08-19 20:29:22 +03001488 dma->rx_param = rx_param;
1489 dma->tx_param = tx_param;
Heikki Krogerusb15e5692013-09-27 10:52:59 +03001490
1491 ret = pci_default_setup(priv, board, port, idx);
1492 port->port.iotype = UPIO_MEM;
1493 port->port.type = PORT_16550A;
1494 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1495 port->port.set_termios = byt_set_termios;
1496 port->port.fifosize = 64;
1497 port->tx_loadsz = 64;
1498 port->dma = dma;
1499 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1500
1501 /* Disable Tx counter interrupts */
1502 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1503
1504 return ret;
1505}
1506
Andy Shevchenkof549e942015-02-23 16:24:43 +02001507#define INTEL_MID_UART_PS 0x30
1508#define INTEL_MID_UART_MUL 0x34
1509
1510static void intel_mid_set_termios_50M(struct uart_port *p,
1511 struct ktermios *termios,
1512 struct ktermios *old)
1513{
1514 unsigned int baud = tty_termios_baud_rate(termios);
1515 u32 ps, mul;
1516
1517 /*
1518 * The uart clk is 50Mhz, and the baud rate come from:
1519 * baud = 50M * MUL / (DIV * PS * DLAB)
1520 *
1521 * For those basic low baud rate we can get the direct
1522 * scalar from 2746800, like 115200 = 2746800/24. For those
1523 * higher baud rate, we handle them case by case, mainly by
1524 * adjusting the MUL/PS registers, and DIV register is kept
1525 * as default value 0x3d09 to make things simple.
1526 */
1527
1528 ps = 0x10;
1529
1530 switch (baud) {
1531 case 500000:
1532 case 1000000:
1533 case 1500000:
1534 case 3000000:
1535 mul = 0x3a98;
1536 p->uartclk = 48000000;
1537 break;
1538 case 2000000:
1539 case 4000000:
1540 mul = 0x2710;
1541 ps = 0x08;
1542 p->uartclk = 64000000;
1543 break;
1544 case 2500000:
1545 mul = 0x30d4;
1546 p->uartclk = 40000000;
1547 break;
1548 case 3500000:
1549 mul = 0x3345;
1550 ps = 0x0c;
1551 p->uartclk = 56000000;
1552 break;
1553 default:
1554 mul = 0x2400;
1555 p->uartclk = 29491200;
1556 }
1557
1558 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
1559 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
1560
1561 serial8250_do_set_termios(p, termios, old);
1562}
1563
1564static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1565{
1566 struct hsu_dma_slave *s = param;
1567
1568 if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1569 return false;
1570
1571 chan->private = s;
1572 return true;
1573}
1574
1575static int intel_mid_serial_setup(struct serial_private *priv,
1576 const struct pciserial_board *board,
1577 struct uart_8250_port *port, int idx,
1578 int index, struct pci_dev *dma_dev)
1579{
1580 struct device *dev = port->port.dev;
1581 struct uart_8250_dma *dma;
1582 struct hsu_dma_slave *tx_param, *rx_param;
1583
1584 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1585 if (!dma)
1586 return -ENOMEM;
1587
1588 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1589 if (!tx_param)
1590 return -ENOMEM;
1591
1592 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1593 if (!rx_param)
1594 return -ENOMEM;
1595
1596 rx_param->chan_id = index * 2 + 1;
1597 tx_param->chan_id = index * 2;
1598
1599 dma->rxconf.src_maxburst = 64;
1600 dma->txconf.dst_maxburst = 64;
1601
1602 rx_param->dma_dev = &dma_dev->dev;
1603 tx_param->dma_dev = &dma_dev->dev;
1604
1605 dma->fn = intel_mid_dma_filter;
1606 dma->rx_param = rx_param;
1607 dma->tx_param = tx_param;
1608
1609 port->port.type = PORT_16750;
1610 port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1611 port->dma = dma;
1612
1613 return pci_default_setup(priv, board, port, idx);
1614}
1615
1616#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
1617#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
1618#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
1619
1620static int pnw_serial_setup(struct serial_private *priv,
1621 const struct pciserial_board *board,
1622 struct uart_8250_port *port, int idx)
1623{
1624 struct pci_dev *pdev = priv->dev;
1625 struct pci_dev *dma_dev;
1626 int index;
1627
1628 switch (pdev->device) {
1629 case PCI_DEVICE_ID_INTEL_PNW_UART1:
1630 index = 0;
1631 break;
1632 case PCI_DEVICE_ID_INTEL_PNW_UART2:
1633 index = 1;
1634 break;
1635 case PCI_DEVICE_ID_INTEL_PNW_UART3:
1636 index = 2;
1637 break;
1638 default:
1639 return -EINVAL;
1640 }
1641
1642 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1643
1644 port->port.set_termios = intel_mid_set_termios_50M;
1645
1646 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1647}
1648
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04001649static int
1650pci_omegapci_setup(struct serial_private *priv,
Alan Cox1798ca12011-05-24 12:35:48 +01001651 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +01001652 struct uart_8250_port *port, int idx)
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04001653{
1654 return setup_port(priv, port, 2, idx * 8, 0);
1655}
1656
Stephen Hurdebebd492013-01-17 14:14:53 -08001657static int
1658pci_brcm_trumanage_setup(struct serial_private *priv,
1659 const struct pciserial_board *board,
1660 struct uart_8250_port *port, int idx)
1661{
1662 int ret = pci_default_setup(priv, board, port, idx);
1663
1664 port->port.type = PORT_BRCM_TRUMANAGE;
1665 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1666 return ret;
1667}
1668
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001669static int pci_fintek_setup(struct serial_private *priv,
1670 const struct pciserial_board *board,
1671 struct uart_8250_port *port, int idx)
1672{
1673 struct pci_dev *pdev = priv->dev;
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001674 unsigned long iobase;
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001675 u8 config_base;
Peter Hungcb8ee9f2014-11-19 13:22:27 +08001676 u32 bar_data[3];
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001677
1678 /*
Peter Hungcb8ee9f2014-11-19 13:22:27 +08001679 * Find each UARTs offset in PCI configuraion space
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001680 */
1681 switch (idx) {
Peter Hungcb8ee9f2014-11-19 13:22:27 +08001682 case 0:
1683 config_base = 0x40;
1684 break;
1685 case 1:
1686 config_base = 0x48;
1687 break;
1688 case 2:
1689 config_base = 0x50;
1690 break;
1691 case 3:
1692 config_base = 0x58;
1693 break;
1694 case 4:
1695 config_base = 0x60;
1696 break;
1697 case 5:
1698 config_base = 0x68;
1699 break;
1700 case 6:
1701 config_base = 0x70;
1702 break;
1703 case 7:
1704 config_base = 0x78;
1705 break;
1706 case 8:
1707 config_base = 0x80;
1708 break;
1709 case 9:
1710 config_base = 0x88;
1711 break;
1712 case 10:
1713 config_base = 0x90;
1714 break;
1715 case 11:
1716 config_base = 0x98;
1717 break;
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001718 default:
1719 /* Unknown number of ports, get out of here */
1720 return -EINVAL;
1721 }
1722
Peter Hungcb8ee9f2014-11-19 13:22:27 +08001723 /* Get the io address dispatch from the BIOS */
1724 pci_read_config_dword(pdev, 0x24, &bar_data[0]);
1725 pci_read_config_dword(pdev, 0x20, &bar_data[1]);
1726 pci_read_config_dword(pdev, 0x1c, &bar_data[2]);
1727
1728 /* Calculate Real IO Port */
1729 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8;
1730
Peter Hung77002c62015-03-17 18:02:14 +08001731 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx config_base=0x%2x\n",
1732 __func__, idx, iobase, config_base);
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07001733
1734 /* Enable UART I/O port */
1735 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1736
1737 /* Select 128-byte FIFO and 8x FIFO threshold */
1738 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1739
1740 /* LSB UART */
1741 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1742
1743 /* MSB UART */
1744 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1745
1746 /* irq number, this usually fails, but the spec says to do it anyway. */
1747 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1748
1749 port->port.iotype = UPIO_PORT;
1750 port->port.iobase = iobase;
1751 port->port.mapbase = 0;
1752 port->port.membase = NULL;
1753 port->port.regshift = 0;
1754
1755 return 0;
1756}
1757
Mauro Carvalho Chehabb6adea32009-02-20 15:38:52 -08001758static int skip_tx_en_setup(struct serial_private *priv,
1759 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +01001760 struct uart_8250_port *port, int idx)
Mauro Carvalho Chehabb6adea32009-02-20 15:38:52 -08001761{
Alan Cox2655a2c2012-07-12 12:59:50 +01001762 port->port.flags |= UPF_NO_TXEN_TEST;
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -07001763 dev_dbg(&priv->dev->dev,
1764 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1765 priv->dev->vendor, priv->dev->device,
1766 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
Mauro Carvalho Chehabb6adea32009-02-20 15:38:52 -08001767
1768 return pci_default_setup(priv, board, port, idx);
1769}
1770
Sudhakar Mamillapalli0ad372b2012-04-10 14:10:58 -07001771static void kt_handle_break(struct uart_port *p)
1772{
Andy Shevchenkob1261c82014-07-14 14:26:14 +03001773 struct uart_8250_port *up = up_to_u8250p(p);
Sudhakar Mamillapalli0ad372b2012-04-10 14:10:58 -07001774 /*
1775 * On receipt of a BI, serial device in Intel ME (Intel
1776 * management engine) needs to have its fifos cleared for sane
1777 * SOL (Serial Over Lan) output.
1778 */
1779 serial8250_clear_and_reinit_fifos(up);
1780}
1781
1782static unsigned int kt_serial_in(struct uart_port *p, int offset)
1783{
Andy Shevchenkob1261c82014-07-14 14:26:14 +03001784 struct uart_8250_port *up = up_to_u8250p(p);
Sudhakar Mamillapalli0ad372b2012-04-10 14:10:58 -07001785 unsigned int val;
1786
1787 /*
1788 * When the Intel ME (management engine) gets reset its serial
1789 * port registers could return 0 momentarily. Functions like
1790 * serial8250_console_write, read and save the IER, perform
1791 * some operation and then restore it. In order to avoid
1792 * setting IER register inadvertently to 0, if the value read
1793 * is 0, double check with ier value in uart_8250_port and use
1794 * that instead. up->ier should be the same value as what is
1795 * currently configured.
1796 */
1797 val = inb(p->iobase + offset);
1798 if (offset == UART_IER) {
1799 if (val == 0)
1800 val = up->ier;
1801 }
1802 return val;
1803}
1804
Dan Williamsbc02d152012-04-06 11:49:50 -07001805static int kt_serial_setup(struct serial_private *priv,
1806 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +01001807 struct uart_8250_port *port, int idx)
Dan Williamsbc02d152012-04-06 11:49:50 -07001808{
Alan Cox2655a2c2012-07-12 12:59:50 +01001809 port->port.flags |= UPF_BUG_THRE;
1810 port->port.serial_in = kt_serial_in;
1811 port->port.handle_break = kt_handle_break;
Dan Williamsbc02d152012-04-06 11:49:50 -07001812 return skip_tx_en_setup(priv, board, port, idx);
1813}
1814
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09001815static int pci_eg20t_init(struct pci_dev *dev)
1816{
1817#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1818 return -ENODEV;
1819#else
1820 return 0;
1821#endif
1822}
1823
Søren Holm06315342011-09-02 22:55:37 +02001824static int
1825pci_xr17c154_setup(struct serial_private *priv,
1826 const struct pciserial_board *board,
Alan Cox2655a2c2012-07-12 12:59:50 +01001827 struct uart_8250_port *port, int idx)
Søren Holm06315342011-09-02 22:55:37 +02001828{
Alan Cox2655a2c2012-07-12 12:59:50 +01001829 port->port.flags |= UPF_EXAR_EFR;
Søren Holm06315342011-09-02 22:55:37 +02001830 return pci_default_setup(priv, board, port, idx);
1831}
1832
Guainluca Anzolin6971c632012-09-04 15:56:12 +01001833static int
Matt Schultedc96efb2012-11-19 09:12:04 -06001834pci_xr17v35x_setup(struct serial_private *priv,
1835 const struct pciserial_board *board,
1836 struct uart_8250_port *port, int idx)
1837{
1838 u8 __iomem *p;
1839
1840 p = pci_ioremap_bar(priv->dev, 0);
Matt Schulte13c32372012-11-21 10:39:18 -06001841 if (p == NULL)
1842 return -ENOMEM;
Matt Schultedc96efb2012-11-19 09:12:04 -06001843
1844 port->port.flags |= UPF_EXAR_EFR;
1845
1846 /*
1847 * Setup Multipurpose Input/Output pins.
1848 */
1849 if (idx == 0) {
1850 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1851 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1852 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1853 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1854 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1855 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1856 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1857 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1858 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1859 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1860 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1861 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1862 }
Matt Schultef965b9c2012-11-20 11:25:40 -06001863 writeb(0x00, p + UART_EXAR_8XMODE);
1864 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1865 writeb(128, p + UART_EXAR_TXTRG);
1866 writeb(128, p + UART_EXAR_RXTRG);
Matt Schultedc96efb2012-11-19 09:12:04 -06001867 iounmap(p);
1868
1869 return pci_default_setup(priv, board, port, idx);
1870}
1871
Matt Schulte14faa8c2012-11-21 10:35:15 -06001872#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1873#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1874#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1875#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1876
1877static int
1878pci_fastcom335_setup(struct serial_private *priv,
1879 const struct pciserial_board *board,
1880 struct uart_8250_port *port, int idx)
1881{
1882 u8 __iomem *p;
1883
1884 p = pci_ioremap_bar(priv->dev, 0);
1885 if (p == NULL)
1886 return -ENOMEM;
1887
1888 port->port.flags |= UPF_EXAR_EFR;
1889
1890 /*
1891 * Setup Multipurpose Input/Output pins.
1892 */
1893 if (idx == 0) {
1894 switch (priv->dev->device) {
1895 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1896 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1897 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1898 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1899 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1900 break;
1901 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1902 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1903 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1904 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1905 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1906 break;
1907 }
1908 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1909 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1910 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1911 }
1912 writeb(0x00, p + UART_EXAR_8XMODE);
1913 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1914 writeb(32, p + UART_EXAR_TXTRG);
1915 writeb(32, p + UART_EXAR_RXTRG);
1916 iounmap(p);
1917
1918 return pci_default_setup(priv, board, port, idx);
1919}
1920
Matt Schultedc96efb2012-11-19 09:12:04 -06001921static int
Guainluca Anzolin6971c632012-09-04 15:56:12 +01001922pci_wch_ch353_setup(struct serial_private *priv,
1923 const struct pciserial_board *board,
1924 struct uart_8250_port *port, int idx)
1925{
1926 port->port.flags |= UPF_FIXED_TYPE;
1927 port->port.type = PORT_16550A;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001928 return pci_default_setup(priv, board, port, idx);
1929}
1930
Sergej Pupykin2fdd8c82014-11-06 14:36:31 +03001931static int
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03001932pci_wch_ch38x_setup(struct serial_private *priv,
Sergej Pupykin2fdd8c82014-11-06 14:36:31 +03001933 const struct pciserial_board *board,
1934 struct uart_8250_port *port, int idx)
1935{
1936 port->port.flags |= UPF_FIXED_TYPE;
1937 port->port.type = PORT_16850;
1938 return pci_default_setup(priv, board, port, idx);
1939}
1940
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1942#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1943#define PCI_DEVICE_ID_OCTPRO 0x0001
1944#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1945#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1946#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1947#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
Flavio Leitner26e82202012-09-21 21:04:34 -03001948#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1949#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
Michael Bramer78d70d42009-01-27 11:51:16 +00001950#define PCI_VENDOR_ID_ADVANTECH 0x13fe
Dirk Brandewie095e24b2010-11-17 07:35:20 -08001951#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
Michael Bramer78d70d42009-01-27 11:51:16 +00001952#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
Thomee Wright0c6d7742014-05-19 20:30:51 +00001953#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1954#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
Yegor Yefremov66169ad2010-06-04 09:58:18 +02001955#define PCI_DEVICE_ID_TITAN_200I 0x8028
1956#define PCI_DEVICE_ID_TITAN_400I 0x8048
1957#define PCI_DEVICE_ID_TITAN_800I 0x8088
1958#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1959#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1960#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1961#define PCI_DEVICE_ID_TITAN_100E 0xA010
1962#define PCI_DEVICE_ID_TITAN_200E 0xA012
1963#define PCI_DEVICE_ID_TITAN_400E 0xA013
1964#define PCI_DEVICE_ID_TITAN_800E 0xA014
1965#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1966#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
Yegor Yefremov48c02472013-12-09 12:11:15 +01001967#define PCI_DEVICE_ID_TITAN_200V3 0xA306
Yegor Yefremov1e9deb12011-12-27 15:47:37 +01001968#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1969#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1970#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1971#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
Lytochkin Borise8470032010-07-26 10:02:26 +04001972#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
Scott Kilauaa273ae2011-05-11 15:41:59 -05001973#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04001974#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
Dan Williamsbc02d152012-04-06 11:49:50 -07001975#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
Alan Cox27788c52012-09-04 16:21:06 +01001976#define PCI_VENDOR_ID_WCH 0x4348
Wang YanQing8b5c9132013-03-05 23:16:48 +08001977#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
Alan Cox27788c52012-09-04 16:21:06 +01001978#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1979#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
Ezequiel Garciafeb58142014-05-24 15:24:51 -03001980#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
Alan Cox27788c52012-09-04 16:21:06 +01001981#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
Alan Cox66835492012-08-16 12:01:33 +01001982#define PCI_VENDOR_ID_AGESTAR 0x5372
1983#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
Alan Coxeb26dfe2012-07-12 13:00:31 +01001984#define PCI_VENDOR_ID_ASIX 0x9710
Matt Schulte14faa8c2012-11-21 10:35:15 -06001985#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1986#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
Matt Schulteb7b90412012-12-06 22:19:59 -06001987#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
Stephen Hurdebebd492013-01-17 14:14:53 -08001988#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
Ian Abbott57c1f0e2013-07-16 16:14:40 +01001989#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
Bryan O'Donoghue1ede7dc2014-09-23 01:21:11 +01001990#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
Matt Schulte14faa8c2012-11-21 10:35:15 -06001991
Stephen Chiversabd7bac2013-01-28 19:49:20 +11001992#define PCI_VENDOR_ID_SUNIX 0x1fd4
1993#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1994
Sergej Pupykin2fdd8c82014-11-06 14:36:31 +03001995#define PCIE_VENDOR_ID_WCH 0x1c00
1996#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03001997#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998
Catalin(ux) M BOIEb76c5a02008-07-23 21:29:46 -07001999/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2000#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
Scott Ashcroftd13402a2013-03-03 21:35:06 +00002001#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
Catalin(ux) M BOIEb76c5a02008-07-23 21:29:46 -07002002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002003/*
2004 * Master list of serial port init/setup/exit quirks.
2005 * This does not describe the general nature of the port.
2006 * (ie, baud base, number and location of ports, etc)
2007 *
2008 * This list is ordered alphabetically by vendor then device.
2009 * Specific entries must come before more generic entries.
2010 */
Sam Ravnborg7a63ce52008-04-28 02:14:02 -07002011static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002012 /*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08002013 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2014 */
2015 {
Ian Abbott086231f2013-07-16 16:14:39 +01002016 .vendor = PCI_VENDOR_ID_AMCC,
Ian Abbott57c1f0e2013-07-16 16:14:40 +01002017 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08002018 .subvendor = PCI_ANY_ID,
2019 .subdevice = PCI_ANY_ID,
2020 .setup = addidata_apci7800_setup,
2021 },
2022 /*
Russell King61a116e2006-07-03 15:22:35 +01002023 * AFAVLAB cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07002024 * It is not clear whether this applies to all products.
2025 */
2026 {
2027 .vendor = PCI_VENDOR_ID_AFAVLAB,
2028 .device = PCI_ANY_ID,
2029 .subvendor = PCI_ANY_ID,
2030 .subdevice = PCI_ANY_ID,
2031 .setup = afavlab_setup,
2032 },
2033 /*
2034 * HP Diva
2035 */
2036 {
2037 .vendor = PCI_VENDOR_ID_HP,
2038 .device = PCI_DEVICE_ID_HP_DIVA,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .init = pci_hp_diva_init,
2042 .setup = pci_hp_diva_setup,
2043 },
2044 /*
2045 * Intel
2046 */
2047 {
2048 .vendor = PCI_VENDOR_ID_INTEL,
2049 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2050 .subvendor = 0xe4bf,
2051 .subdevice = PCI_ANY_ID,
2052 .init = pci_inteli960ni_init,
2053 .setup = pci_default_setup,
2054 },
Mauro Carvalho Chehabb6adea32009-02-20 15:38:52 -08002055 {
2056 .vendor = PCI_VENDOR_ID_INTEL,
2057 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2058 .subvendor = PCI_ANY_ID,
2059 .subdevice = PCI_ANY_ID,
2060 .setup = skip_tx_en_setup,
2061 },
2062 {
2063 .vendor = PCI_VENDOR_ID_INTEL,
2064 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2065 .subvendor = PCI_ANY_ID,
2066 .subdevice = PCI_ANY_ID,
2067 .setup = skip_tx_en_setup,
2068 },
2069 {
2070 .vendor = PCI_VENDOR_ID_INTEL,
2071 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2072 .subvendor = PCI_ANY_ID,
2073 .subdevice = PCI_ANY_ID,
2074 .setup = skip_tx_en_setup,
2075 },
Dirk Brandewie095e24b2010-11-17 07:35:20 -08002076 {
2077 .vendor = PCI_VENDOR_ID_INTEL,
2078 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2079 .subvendor = PCI_ANY_ID,
2080 .subdevice = PCI_ANY_ID,
2081 .setup = ce4100_serial_setup,
2082 },
Dan Williamsbc02d152012-04-06 11:49:50 -07002083 {
2084 .vendor = PCI_VENDOR_ID_INTEL,
2085 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2086 .subvendor = PCI_ANY_ID,
2087 .subdevice = PCI_ANY_ID,
2088 .setup = kt_serial_setup,
2089 },
Heikki Krogerusb15e5692013-09-27 10:52:59 +03002090 {
2091 .vendor = PCI_VENDOR_ID_INTEL,
2092 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2093 .subvendor = PCI_ANY_ID,
2094 .subdevice = PCI_ANY_ID,
2095 .setup = byt_serial_setup,
2096 },
2097 {
2098 .vendor = PCI_VENDOR_ID_INTEL,
2099 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .setup = byt_serial_setup,
2103 },
Bryan O'Donoghue1ede7dc2014-09-23 01:21:11 +01002104 {
2105 .vendor = PCI_VENDOR_ID_INTEL,
Andy Shevchenkof549e942015-02-23 16:24:43 +02002106 .device = PCI_DEVICE_ID_INTEL_PNW_UART1,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .setup = pnw_serial_setup,
2110 },
2111 {
2112 .vendor = PCI_VENDOR_ID_INTEL,
2113 .device = PCI_DEVICE_ID_INTEL_PNW_UART2,
2114 .subvendor = PCI_ANY_ID,
2115 .subdevice = PCI_ANY_ID,
2116 .setup = pnw_serial_setup,
2117 },
2118 {
2119 .vendor = PCI_VENDOR_ID_INTEL,
2120 .device = PCI_DEVICE_ID_INTEL_PNW_UART3,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = pnw_serial_setup,
2124 },
2125 {
2126 .vendor = PCI_VENDOR_ID_INTEL,
Alan Cox29897082014-08-19 20:29:23 +03002127 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2128 .subvendor = PCI_ANY_ID,
2129 .subdevice = PCI_ANY_ID,
2130 .setup = byt_serial_setup,
2131 },
2132 {
2133 .vendor = PCI_VENDOR_ID_INTEL,
2134 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2135 .subvendor = PCI_ANY_ID,
2136 .subdevice = PCI_ANY_ID,
2137 .setup = byt_serial_setup,
2138 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139 /*
Niels de Vos84f8c6f2007-08-22 14:01:14 -07002140 * ITE
2141 */
2142 {
2143 .vendor = PCI_VENDOR_ID_ITE,
2144 .device = PCI_DEVICE_ID_ITE_8872,
2145 .subvendor = PCI_ANY_ID,
2146 .subdevice = PCI_ANY_ID,
2147 .init = pci_ite887x_init,
2148 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002149 .exit = pci_ite887x_exit,
Niels de Vos84f8c6f2007-08-22 14:01:14 -07002150 },
2151 /*
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01002152 * National Instruments
2153 */
2154 {
2155 .vendor = PCI_VENDOR_ID_NI,
Will Page04bf7e72009-04-06 17:32:15 +01002156 .device = PCI_DEVICE_ID_NI_PCI23216,
2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
2159 .init = pci_ni8420_init,
2160 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002161 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002162 },
2163 {
2164 .vendor = PCI_VENDOR_ID_NI,
2165 .device = PCI_DEVICE_ID_NI_PCI2328,
2166 .subvendor = PCI_ANY_ID,
2167 .subdevice = PCI_ANY_ID,
2168 .init = pci_ni8420_init,
2169 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002170 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002171 },
2172 {
2173 .vendor = PCI_VENDOR_ID_NI,
2174 .device = PCI_DEVICE_ID_NI_PCI2324,
2175 .subvendor = PCI_ANY_ID,
2176 .subdevice = PCI_ANY_ID,
2177 .init = pci_ni8420_init,
2178 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002179 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002180 },
2181 {
2182 .vendor = PCI_VENDOR_ID_NI,
2183 .device = PCI_DEVICE_ID_NI_PCI2322,
2184 .subvendor = PCI_ANY_ID,
2185 .subdevice = PCI_ANY_ID,
2186 .init = pci_ni8420_init,
2187 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002188 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002189 },
2190 {
2191 .vendor = PCI_VENDOR_ID_NI,
2192 .device = PCI_DEVICE_ID_NI_PCI2324I,
2193 .subvendor = PCI_ANY_ID,
2194 .subdevice = PCI_ANY_ID,
2195 .init = pci_ni8420_init,
2196 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002197 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002198 },
2199 {
2200 .vendor = PCI_VENDOR_ID_NI,
2201 .device = PCI_DEVICE_ID_NI_PCI2322I,
2202 .subvendor = PCI_ANY_ID,
2203 .subdevice = PCI_ANY_ID,
2204 .init = pci_ni8420_init,
2205 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002206 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002207 },
2208 {
2209 .vendor = PCI_VENDOR_ID_NI,
2210 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2211 .subvendor = PCI_ANY_ID,
2212 .subdevice = PCI_ANY_ID,
2213 .init = pci_ni8420_init,
2214 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002215 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002216 },
2217 {
2218 .vendor = PCI_VENDOR_ID_NI,
2219 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .init = pci_ni8420_init,
2223 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002224 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002225 },
2226 {
2227 .vendor = PCI_VENDOR_ID_NI,
2228 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .init = pci_ni8420_init,
2232 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002233 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002234 },
2235 {
2236 .vendor = PCI_VENDOR_ID_NI,
2237 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2238 .subvendor = PCI_ANY_ID,
2239 .subdevice = PCI_ANY_ID,
2240 .init = pci_ni8420_init,
2241 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002242 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002243 },
2244 {
2245 .vendor = PCI_VENDOR_ID_NI,
2246 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2247 .subvendor = PCI_ANY_ID,
2248 .subdevice = PCI_ANY_ID,
2249 .init = pci_ni8420_init,
2250 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002251 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002252 },
2253 {
2254 .vendor = PCI_VENDOR_ID_NI,
2255 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2256 .subvendor = PCI_ANY_ID,
2257 .subdevice = PCI_ANY_ID,
2258 .init = pci_ni8420_init,
2259 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002260 .exit = pci_ni8420_exit,
Will Page04bf7e72009-04-06 17:32:15 +01002261 },
2262 {
2263 .vendor = PCI_VENDOR_ID_NI,
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01002264 .device = PCI_ANY_ID,
2265 .subvendor = PCI_ANY_ID,
2266 .subdevice = PCI_ANY_ID,
2267 .init = pci_ni8430_init,
2268 .setup = pci_ni8430_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002269 .exit = pci_ni8430_exit,
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01002270 },
Alan Cox55c7c0f2012-11-29 09:03:00 +10302271 /* Quatech */
2272 {
2273 .vendor = PCI_VENDOR_ID_QUATECH,
2274 .device = PCI_ANY_ID,
2275 .subvendor = PCI_ANY_ID,
2276 .subdevice = PCI_ANY_ID,
2277 .init = pci_quatech_init,
2278 .setup = pci_quatech_setup,
Greg Kroah-Hartmand73dfc62013-01-15 22:44:48 -08002279 .exit = pci_quatech_exit,
Alan Cox55c7c0f2012-11-29 09:03:00 +10302280 },
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01002281 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282 * Panacom
2283 */
2284 {
2285 .vendor = PCI_VENDOR_ID_PANACOM,
2286 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2287 .subvendor = PCI_ANY_ID,
2288 .subdevice = PCI_ANY_ID,
2289 .init = pci_plx9050_init,
2290 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002291 .exit = pci_plx9050_exit,
Alan Cox5756ee92008-02-08 04:18:51 -08002292 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002293 {
2294 .vendor = PCI_VENDOR_ID_PANACOM,
2295 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .init = pci_plx9050_init,
2299 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002300 .exit = pci_plx9050_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002301 },
2302 /*
Angelo Butti94341472013-10-15 22:41:10 +03002303 * Pericom
2304 */
2305 {
2306 .vendor = 0x12d8,
2307 .device = 0x7952,
2308 .subvendor = PCI_ANY_ID,
2309 .subdevice = PCI_ANY_ID,
2310 .setup = pci_pericom_setup,
2311 },
2312 {
2313 .vendor = 0x12d8,
2314 .device = 0x7954,
2315 .subvendor = PCI_ANY_ID,
2316 .subdevice = PCI_ANY_ID,
2317 .setup = pci_pericom_setup,
2318 },
2319 {
2320 .vendor = 0x12d8,
2321 .device = 0x7958,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .setup = pci_pericom_setup,
2325 },
2326
2327 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002328 * PLX
2329 */
2330 {
2331 .vendor = PCI_VENDOR_ID_PLX,
2332 .device = PCI_DEVICE_ID_PLX_9050,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01002333 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2334 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2335 .init = pci_plx9050_init,
2336 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002337 .exit = pci_plx9050_exit,
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01002338 },
2339 {
2340 .vendor = PCI_VENDOR_ID_PLX,
2341 .device = PCI_DEVICE_ID_PLX_9050,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002342 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2343 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2344 .init = pci_plx9050_init,
2345 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002346 .exit = pci_plx9050_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002347 },
2348 {
2349 .vendor = PCI_VENDOR_ID_PLX,
2350 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2351 .subvendor = PCI_VENDOR_ID_PLX,
2352 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2353 .init = pci_plx9050_init,
2354 .setup = pci_default_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002355 .exit = pci_plx9050_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002356 },
2357 /*
2358 * SBS Technologies, Inc., PMC-OCTALPRO 232
2359 */
2360 {
2361 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2362 .device = PCI_DEVICE_ID_OCTPRO,
2363 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2364 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2365 .init = sbs_init,
2366 .setup = sbs_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002367 .exit = sbs_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368 },
2369 /*
2370 * SBS Technologies, Inc., PMC-OCTALPRO 422
2371 */
2372 {
2373 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2374 .device = PCI_DEVICE_ID_OCTPRO,
2375 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2376 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2377 .init = sbs_init,
2378 .setup = sbs_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002379 .exit = sbs_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002380 },
2381 /*
2382 * SBS Technologies, Inc., P-Octal 232
2383 */
2384 {
2385 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2386 .device = PCI_DEVICE_ID_OCTPRO,
2387 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2388 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2389 .init = sbs_init,
2390 .setup = sbs_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002391 .exit = sbs_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002392 },
2393 /*
2394 * SBS Technologies, Inc., P-Octal 422
2395 */
2396 {
2397 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2398 .device = PCI_DEVICE_ID_OCTPRO,
2399 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2400 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2401 .init = sbs_init,
2402 .setup = sbs_setup,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002403 .exit = sbs_exit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002405 /*
Russell King61a116e2006-07-03 15:22:35 +01002406 * SIIG cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407 */
2408 {
2409 .vendor = PCI_VENDOR_ID_SIIG,
Russell King67d74b82005-07-27 11:33:03 +01002410 .device = PCI_ANY_ID,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
Russell King67d74b82005-07-27 11:33:03 +01002413 .init = pci_siig_init,
Andrey Panin3ec9c592006-02-02 20:15:09 +00002414 .setup = pci_siig_setup,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002415 },
2416 /*
2417 * Titan cards
2418 */
2419 {
2420 .vendor = PCI_VENDOR_ID_TITAN,
2421 .device = PCI_DEVICE_ID_TITAN_400L,
2422 .subvendor = PCI_ANY_ID,
2423 .subdevice = PCI_ANY_ID,
2424 .setup = titan_400l_800l_setup,
2425 },
2426 {
2427 .vendor = PCI_VENDOR_ID_TITAN,
2428 .device = PCI_DEVICE_ID_TITAN_800L,
2429 .subvendor = PCI_ANY_ID,
2430 .subdevice = PCI_ANY_ID,
2431 .setup = titan_400l_800l_setup,
2432 },
2433 /*
2434 * Timedia cards
2435 */
2436 {
2437 .vendor = PCI_VENDOR_ID_TIMEDIA,
2438 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2439 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2440 .subdevice = PCI_ANY_ID,
Frédéric Brièreb9b24552011-05-29 15:08:04 -04002441 .probe = pci_timedia_probe,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002442 .init = pci_timedia_init,
2443 .setup = pci_timedia_setup,
2444 },
2445 {
2446 .vendor = PCI_VENDOR_ID_TIMEDIA,
2447 .device = PCI_ANY_ID,
2448 .subvendor = PCI_ANY_ID,
2449 .subdevice = PCI_ANY_ID,
2450 .setup = pci_timedia_setup,
2451 },
2452 /*
Stephen Chiversabd7bac2013-01-28 19:49:20 +11002453 * SUNIX (Timedia) cards
2454 * Do not "probe" for these cards as there is at least one combination
2455 * card that should be handled by parport_pc that doesn't match the
2456 * rule in pci_timedia_probe.
2457 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2458 * There are some boards with part number SER5037AL that report
2459 * subdevice ID 0x0002.
2460 */
2461 {
2462 .vendor = PCI_VENDOR_ID_SUNIX,
2463 .device = PCI_DEVICE_ID_SUNIX_1999,
2464 .subvendor = PCI_VENDOR_ID_SUNIX,
2465 .subdevice = PCI_ANY_ID,
2466 .init = pci_timedia_init,
2467 .setup = pci_timedia_setup,
2468 },
2469 /*
Søren Holm06315342011-09-02 22:55:37 +02002470 * Exar cards
2471 */
2472 {
2473 .vendor = PCI_VENDOR_ID_EXAR,
2474 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2475 .subvendor = PCI_ANY_ID,
2476 .subdevice = PCI_ANY_ID,
2477 .setup = pci_xr17c154_setup,
2478 },
2479 {
2480 .vendor = PCI_VENDOR_ID_EXAR,
2481 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2482 .subvendor = PCI_ANY_ID,
2483 .subdevice = PCI_ANY_ID,
2484 .setup = pci_xr17c154_setup,
2485 },
2486 {
2487 .vendor = PCI_VENDOR_ID_EXAR,
2488 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .setup = pci_xr17c154_setup,
2492 },
Matt Schultedc96efb2012-11-19 09:12:04 -06002493 {
2494 .vendor = PCI_VENDOR_ID_EXAR,
2495 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2496 .subvendor = PCI_ANY_ID,
2497 .subdevice = PCI_ANY_ID,
2498 .setup = pci_xr17v35x_setup,
2499 },
2500 {
2501 .vendor = PCI_VENDOR_ID_EXAR,
2502 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .setup = pci_xr17v35x_setup,
2506 },
2507 {
2508 .vendor = PCI_VENDOR_ID_EXAR,
2509 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .setup = pci_xr17v35x_setup,
2513 },
Søren Holm06315342011-09-02 22:55:37 +02002514 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002515 * Xircom cards
2516 */
2517 {
2518 .vendor = PCI_VENDOR_ID_XIRCOM,
2519 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2520 .subvendor = PCI_ANY_ID,
2521 .subdevice = PCI_ANY_ID,
2522 .init = pci_xircom_init,
2523 .setup = pci_default_setup,
2524 },
2525 /*
Russell King61a116e2006-07-03 15:22:35 +01002526 * Netmos cards - these may be called via parport_serial
Linus Torvalds1da177e2005-04-16 15:20:36 -07002527 */
2528 {
2529 .vendor = PCI_VENDOR_ID_NETMOS,
2530 .device = PCI_ANY_ID,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .init = pci_netmos_init,
Nicos Gollan7808edc2011-05-05 21:00:37 +02002534 .setup = pci_netmos_9900_setup,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002535 },
2536 /*
Mike Skoog1bc8cde2014-10-16 13:10:01 -07002537 * EndRun Technologies
2538 */
2539 {
2540 .vendor = PCI_VENDOR_ID_ENDRUN,
2541 .device = PCI_ANY_ID,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .init = pci_endrun_init,
2545 .setup = pci_default_setup,
2546 },
2547 /*
Scott Kilauaa273ae2011-05-11 15:41:59 -05002548 * For Oxford Semiconductor Tornado based devices
Russell King9f2a0362009-01-02 13:44:20 +00002549 */
2550 {
2551 .vendor = PCI_VENDOR_ID_OXSEMI,
2552 .device = PCI_ANY_ID,
2553 .subvendor = PCI_ANY_ID,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_oxsemi_tornado_init,
2556 .setup = pci_default_setup,
2557 },
2558 {
2559 .vendor = PCI_VENDOR_ID_MAINPINE,
2560 .device = PCI_ANY_ID,
2561 .subvendor = PCI_ANY_ID,
2562 .subdevice = PCI_ANY_ID,
2563 .init = pci_oxsemi_tornado_init,
2564 .setup = pci_default_setup,
2565 },
Scott Kilauaa273ae2011-05-11 15:41:59 -05002566 {
2567 .vendor = PCI_VENDOR_ID_DIGI,
2568 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2569 .subvendor = PCI_SUBVENDOR_ID_IBM,
2570 .subdevice = PCI_ANY_ID,
2571 .init = pci_oxsemi_tornado_init,
2572 .setup = pci_default_setup,
2573 },
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002574 {
2575 .vendor = PCI_VENDOR_ID_INTEL,
2576 .device = 0x8811,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002579 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002580 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002581 },
2582 {
2583 .vendor = PCI_VENDOR_ID_INTEL,
2584 .device = 0x8812,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002587 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002588 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002589 },
2590 {
2591 .vendor = PCI_VENDOR_ID_INTEL,
2592 .device = 0x8813,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002593 .subvendor = PCI_ANY_ID,
2594 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002595 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002596 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002597 },
2598 {
2599 .vendor = PCI_VENDOR_ID_INTEL,
2600 .device = 0x8814,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002603 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002604 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002605 },
2606 {
2607 .vendor = 0x10DB,
2608 .device = 0x8027,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002609 .subvendor = PCI_ANY_ID,
2610 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002611 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002612 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002613 },
2614 {
2615 .vendor = 0x10DB,
2616 .device = 0x8028,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002619 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002620 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002621 },
2622 {
2623 .vendor = 0x10DB,
2624 .device = 0x8029,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002625 .subvendor = PCI_ANY_ID,
2626 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002627 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002628 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002629 },
2630 {
2631 .vendor = 0x10DB,
2632 .device = 0x800C,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002633 .subvendor = PCI_ANY_ID,
2634 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002635 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002636 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002637 },
2638 {
2639 .vendor = 0x10DB,
2640 .device = 0x800D,
Arnaud Patardaaa10eb2012-04-25 12:17:24 +02002641 .subvendor = PCI_ANY_ID,
2642 .subdevice = PCI_ANY_ID,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002643 .init = pci_eg20t_init,
Tomoya MORINAGA64d91cf2011-10-07 13:39:49 +09002644 .setup = pci_default_setup,
Tomoya MORINAGAeb7073d2011-06-02 11:31:29 +09002645 },
Russell King9f2a0362009-01-02 13:44:20 +00002646 /*
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04002647 * Cronyx Omega PCI (PLX-chip based)
2648 */
2649 {
2650 .vendor = PCI_VENDOR_ID_PLX,
2651 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2652 .subvendor = PCI_ANY_ID,
2653 .subdevice = PCI_ANY_ID,
2654 .setup = pci_omegapci_setup,
Alan Coxeb26dfe2012-07-12 13:00:31 +01002655 },
Ezequiel Garciafeb58142014-05-24 15:24:51 -03002656 /* WCH CH353 1S1P card (16550 clone) */
2657 {
2658 .vendor = PCI_VENDOR_ID_WCH,
2659 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2660 .subvendor = PCI_ANY_ID,
2661 .subdevice = PCI_ANY_ID,
2662 .setup = pci_wch_ch353_setup,
2663 },
Guainluca Anzolin6971c632012-09-04 15:56:12 +01002664 /* WCH CH353 2S1P card (16550 clone) */
2665 {
Alan Cox27788c52012-09-04 16:21:06 +01002666 .vendor = PCI_VENDOR_ID_WCH,
2667 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2668 .subvendor = PCI_ANY_ID,
2669 .subdevice = PCI_ANY_ID,
2670 .setup = pci_wch_ch353_setup,
2671 },
2672 /* WCH CH353 4S card (16550 clone) */
2673 {
2674 .vendor = PCI_VENDOR_ID_WCH,
2675 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2676 .subvendor = PCI_ANY_ID,
2677 .subdevice = PCI_ANY_ID,
2678 .setup = pci_wch_ch353_setup,
2679 },
2680 /* WCH CH353 2S1PF card (16550 clone) */
2681 {
2682 .vendor = PCI_VENDOR_ID_WCH,
2683 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2684 .subvendor = PCI_ANY_ID,
2685 .subdevice = PCI_ANY_ID,
Guainluca Anzolin6971c632012-09-04 15:56:12 +01002686 .setup = pci_wch_ch353_setup,
2687 },
Wang YanQing8b5c9132013-03-05 23:16:48 +08002688 /* WCH CH352 2S card (16550 clone) */
2689 {
2690 .vendor = PCI_VENDOR_ID_WCH,
2691 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2692 .subvendor = PCI_ANY_ID,
2693 .subdevice = PCI_ANY_ID,
2694 .setup = pci_wch_ch353_setup,
2695 },
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03002696 /* WCH CH382 2S1P card (16850 clone) */
Sergej Pupykin2fdd8c82014-11-06 14:36:31 +03002697 {
2698 .vendor = PCIE_VENDOR_ID_WCH,
2699 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2700 .subvendor = PCI_ANY_ID,
2701 .subdevice = PCI_ANY_ID,
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03002702 .setup = pci_wch_ch38x_setup,
2703 },
2704 /* WCH CH384 4S card (16850 clone) */
2705 {
2706 .vendor = PCIE_VENDOR_ID_WCH,
2707 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2708 .subvendor = PCI_ANY_ID,
2709 .subdevice = PCI_ANY_ID,
2710 .setup = pci_wch_ch38x_setup,
Sergej Pupykin2fdd8c82014-11-06 14:36:31 +03002711 },
Alan Coxeb26dfe2012-07-12 13:00:31 +01002712 /*
2713 * ASIX devices with FIFO bug
2714 */
2715 {
2716 .vendor = PCI_VENDOR_ID_ASIX,
2717 .device = PCI_ANY_ID,
2718 .subvendor = PCI_ANY_ID,
2719 .subdevice = PCI_ANY_ID,
2720 .setup = pci_asix_setup,
2721 },
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04002722 /*
Matt Schulte14faa8c2012-11-21 10:35:15 -06002723 * Commtech, Inc. Fastcom adapters
2724 *
2725 */
2726 {
2727 .vendor = PCI_VENDOR_ID_COMMTECH,
2728 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2729 .subvendor = PCI_ANY_ID,
2730 .subdevice = PCI_ANY_ID,
2731 .setup = pci_fastcom335_setup,
2732 },
2733 {
2734 .vendor = PCI_VENDOR_ID_COMMTECH,
2735 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2736 .subvendor = PCI_ANY_ID,
2737 .subdevice = PCI_ANY_ID,
2738 .setup = pci_fastcom335_setup,
2739 },
2740 {
2741 .vendor = PCI_VENDOR_ID_COMMTECH,
2742 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2743 .subvendor = PCI_ANY_ID,
2744 .subdevice = PCI_ANY_ID,
2745 .setup = pci_fastcom335_setup,
2746 },
2747 {
2748 .vendor = PCI_VENDOR_ID_COMMTECH,
2749 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2752 .setup = pci_fastcom335_setup,
2753 },
2754 {
2755 .vendor = PCI_VENDOR_ID_COMMTECH,
2756 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2757 .subvendor = PCI_ANY_ID,
2758 .subdevice = PCI_ANY_ID,
2759 .setup = pci_xr17v35x_setup,
2760 },
2761 {
2762 .vendor = PCI_VENDOR_ID_COMMTECH,
2763 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2764 .subvendor = PCI_ANY_ID,
2765 .subdevice = PCI_ANY_ID,
2766 .setup = pci_xr17v35x_setup,
2767 },
2768 {
2769 .vendor = PCI_VENDOR_ID_COMMTECH,
2770 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2771 .subvendor = PCI_ANY_ID,
2772 .subdevice = PCI_ANY_ID,
2773 .setup = pci_xr17v35x_setup,
2774 },
2775 /*
Stephen Hurdebebd492013-01-17 14:14:53 -08002776 * Broadcom TruManage (NetXtreme)
2777 */
2778 {
2779 .vendor = PCI_VENDOR_ID_BROADCOM,
2780 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2781 .subvendor = PCI_ANY_ID,
2782 .subdevice = PCI_ANY_ID,
2783 .setup = pci_brcm_trumanage_setup,
2784 },
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07002785 {
2786 .vendor = 0x1c29,
2787 .device = 0x1104,
2788 .subvendor = PCI_ANY_ID,
2789 .subdevice = PCI_ANY_ID,
2790 .setup = pci_fintek_setup,
2791 },
2792 {
2793 .vendor = 0x1c29,
2794 .device = 0x1108,
2795 .subvendor = PCI_ANY_ID,
2796 .subdevice = PCI_ANY_ID,
2797 .setup = pci_fintek_setup,
2798 },
2799 {
2800 .vendor = 0x1c29,
2801 .device = 0x1112,
2802 .subvendor = PCI_ANY_ID,
2803 .subdevice = PCI_ANY_ID,
2804 .setup = pci_fintek_setup,
2805 },
Stephen Hurdebebd492013-01-17 14:14:53 -08002806
2807 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002808 * Default "match everything" terminator entry
2809 */
2810 {
2811 .vendor = PCI_ANY_ID,
2812 .device = PCI_ANY_ID,
2813 .subvendor = PCI_ANY_ID,
2814 .subdevice = PCI_ANY_ID,
2815 .setup = pci_default_setup,
2816 }
2817};
2818
2819static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2820{
2821 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2822}
2823
2824static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2825{
2826 struct pci_serial_quirk *quirk;
2827
2828 for (quirk = pci_serial_quirks; ; quirk++)
2829 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2830 quirk_id_matches(quirk->device, dev->device) &&
2831 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2832 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
Alan Cox5756ee92008-02-08 04:18:51 -08002833 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002834 return quirk;
2835}
2836
Andrew Mortondd68e882006-01-05 10:55:26 +00002837static inline int get_pci_irq(struct pci_dev *dev,
Russell King975a1a72009-01-02 13:44:27 +00002838 const struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002839{
2840 if (board->flags & FL_NOIRQ)
2841 return 0;
2842 else
2843 return dev->irq;
2844}
2845
2846/*
2847 * This is the configuration table for all of the PCI serial boards
2848 * which we support. It is directly indexed by the pci_board_num_t enum
2849 * value, which is encoded in the pci_device_id PCI probe table's
2850 * driver_data member.
2851 *
2852 * The makeup of these names are:
Gareth Howlett26e92862006-01-04 17:00:42 +00002853 * pbn_bn{_bt}_n_baud{_offsetinhex}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002854 *
Gareth Howlett26e92862006-01-04 17:00:42 +00002855 * bn = PCI BAR number
2856 * bt = Index using PCI BARs
2857 * n = number of serial ports
2858 * baud = baud rate
2859 * offsetinhex = offset for each sequential port (in hex)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002860 *
Gareth Howlett26e92862006-01-04 17:00:42 +00002861 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
Russell Kingf1690f32005-05-06 10:19:09 +01002862 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07002863 * Please note: in theory if n = 1, _bt infix should make no difference.
2864 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2865 */
2866enum pci_board_num_t {
2867 pbn_default = 0,
2868
2869 pbn_b0_1_115200,
2870 pbn_b0_2_115200,
2871 pbn_b0_4_115200,
2872 pbn_b0_5_115200,
Alan Coxbf0df632007-10-16 01:24:00 -07002873 pbn_b0_8_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002874
2875 pbn_b0_1_921600,
2876 pbn_b0_2_921600,
2877 pbn_b0_4_921600,
2878
David Ransondb1de152005-07-27 11:43:55 -07002879 pbn_b0_2_1130000,
2880
Andrey Paninfbc0dc02005-07-18 11:38:09 +01002881 pbn_b0_4_1152000,
2882
Matt Schulte14faa8c2012-11-21 10:35:15 -06002883 pbn_b0_2_1152000_200,
2884 pbn_b0_4_1152000_200,
2885 pbn_b0_8_1152000_200,
2886
Gareth Howlett26e92862006-01-04 17:00:42 +00002887 pbn_b0_2_1843200,
2888 pbn_b0_4_1843200,
2889
2890 pbn_b0_2_1843200_200,
2891 pbn_b0_4_1843200_200,
2892 pbn_b0_8_1843200_200,
2893
Lee Howard7106b4e2008-10-21 13:48:58 +01002894 pbn_b0_1_4000000,
2895
Linus Torvalds1da177e2005-04-16 15:20:36 -07002896 pbn_b0_bt_1_115200,
2897 pbn_b0_bt_2_115200,
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08002898 pbn_b0_bt_4_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002899 pbn_b0_bt_8_115200,
2900
2901 pbn_b0_bt_1_460800,
2902 pbn_b0_bt_2_460800,
2903 pbn_b0_bt_4_460800,
2904
2905 pbn_b0_bt_1_921600,
2906 pbn_b0_bt_2_921600,
2907 pbn_b0_bt_4_921600,
2908 pbn_b0_bt_8_921600,
2909
2910 pbn_b1_1_115200,
2911 pbn_b1_2_115200,
2912 pbn_b1_4_115200,
2913 pbn_b1_8_115200,
Will Page04bf7e72009-04-06 17:32:15 +01002914 pbn_b1_16_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002915
2916 pbn_b1_1_921600,
2917 pbn_b1_2_921600,
2918 pbn_b1_4_921600,
2919 pbn_b1_8_921600,
2920
Gareth Howlett26e92862006-01-04 17:00:42 +00002921 pbn_b1_2_1250000,
2922
Niels de Vos84f8c6f2007-08-22 14:01:14 -07002923 pbn_b1_bt_1_115200,
Will Page04bf7e72009-04-06 17:32:15 +01002924 pbn_b1_bt_2_115200,
2925 pbn_b1_bt_4_115200,
2926
Linus Torvalds1da177e2005-04-16 15:20:36 -07002927 pbn_b1_bt_2_921600,
2928
2929 pbn_b1_1_1382400,
2930 pbn_b1_2_1382400,
2931 pbn_b1_4_1382400,
2932 pbn_b1_8_1382400,
2933
2934 pbn_b2_1_115200,
Peter Horton737c1752006-08-26 09:07:36 +01002935 pbn_b2_2_115200,
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08002936 pbn_b2_4_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002937 pbn_b2_8_115200,
2938
2939 pbn_b2_1_460800,
2940 pbn_b2_4_460800,
2941 pbn_b2_8_460800,
2942 pbn_b2_16_460800,
2943
2944 pbn_b2_1_921600,
2945 pbn_b2_4_921600,
2946 pbn_b2_8_921600,
2947
Lytochkin Borise8470032010-07-26 10:02:26 +04002948 pbn_b2_8_1152000,
2949
Linus Torvalds1da177e2005-04-16 15:20:36 -07002950 pbn_b2_bt_1_115200,
2951 pbn_b2_bt_2_115200,
2952 pbn_b2_bt_4_115200,
2953
2954 pbn_b2_bt_2_921600,
2955 pbn_b2_bt_4_921600,
2956
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00002957 pbn_b3_2_115200,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002958 pbn_b3_4_115200,
2959 pbn_b3_8_115200,
2960
Yegor Yefremov66169ad2010-06-04 09:58:18 +02002961 pbn_b4_bt_2_921600,
2962 pbn_b4_bt_4_921600,
2963 pbn_b4_bt_8_921600,
2964
Linus Torvalds1da177e2005-04-16 15:20:36 -07002965 /*
2966 * Board-specific versions.
2967 */
2968 pbn_panacom,
2969 pbn_panacom2,
2970 pbn_panacom4,
2971 pbn_plx_romulus,
Mike Skoog1bc8cde2014-10-16 13:10:01 -07002972 pbn_endrun_2_4000000,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002973 pbn_oxsemi,
Lee Howard7106b4e2008-10-21 13:48:58 +01002974 pbn_oxsemi_1_4000000,
2975 pbn_oxsemi_2_4000000,
2976 pbn_oxsemi_4_4000000,
2977 pbn_oxsemi_8_4000000,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002978 pbn_intel_i960,
2979 pbn_sgi_ioc3,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002980 pbn_computone_4,
2981 pbn_computone_6,
2982 pbn_computone_8,
2983 pbn_sbsxrsio,
2984 pbn_exar_XR17C152,
2985 pbn_exar_XR17C154,
2986 pbn_exar_XR17C158,
Matt Schultedc96efb2012-11-19 09:12:04 -06002987 pbn_exar_XR17V352,
2988 pbn_exar_XR17V354,
2989 pbn_exar_XR17V358,
Benjamin Herrenschmidtc68d2b12009-10-26 16:50:05 -07002990 pbn_exar_ibm_saturn,
Olof Johanssonaa798502007-08-22 14:01:55 -07002991 pbn_pasemi_1682M,
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01002992 pbn_ni8430_2,
2993 pbn_ni8430_4,
2994 pbn_ni8430_8,
2995 pbn_ni8430_16,
Krauth.Julien1b62cbf2009-10-26 16:50:04 -07002996 pbn_ADDIDATA_PCIe_1_3906250,
2997 pbn_ADDIDATA_PCIe_2_3906250,
2998 pbn_ADDIDATA_PCIe_4_3906250,
2999 pbn_ADDIDATA_PCIe_8_3906250,
Dirk Brandewie095e24b2010-11-17 07:35:20 -08003000 pbn_ce4100_1_115200,
Heikki Krogerusb15e5692013-09-27 10:52:59 +03003001 pbn_byt,
Andy Shevchenkof549e942015-02-23 16:24:43 +02003002 pbn_pnw,
Bryan O'Donoghue1ede7dc2014-09-23 01:21:11 +01003003 pbn_qrk,
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04003004 pbn_omegapci,
Nicos Gollan7808edc2011-05-05 21:00:37 +02003005 pbn_NETMOS9900_2s_115200,
Stephen Hurdebebd492013-01-17 14:14:53 -08003006 pbn_brcm_trumanage,
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07003007 pbn_fintek_4,
3008 pbn_fintek_8,
3009 pbn_fintek_12,
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03003010 pbn_wch384_4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003011};
3012
3013/*
3014 * uart_offset - the space between channels
3015 * reg_shift - describes how the UART registers are mapped
3016 * to PCI memory by the card.
3017 * For example IER register on SBS, Inc. PMC-OctPro is located at
3018 * offset 0x10 from the UART base, while UART_IER is defined as 1
3019 * in include/linux/serial_reg.h,
3020 * see first lines of serial_in() and serial_out() in 8250.c
3021*/
3022
Bill Pembertonde88b342012-11-19 13:24:32 -05003023static struct pciserial_board pci_boards[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003024 [pbn_default] = {
3025 .flags = FL_BASE0,
3026 .num_ports = 1,
3027 .base_baud = 115200,
3028 .uart_offset = 8,
3029 },
3030 [pbn_b0_1_115200] = {
3031 .flags = FL_BASE0,
3032 .num_ports = 1,
3033 .base_baud = 115200,
3034 .uart_offset = 8,
3035 },
3036 [pbn_b0_2_115200] = {
3037 .flags = FL_BASE0,
3038 .num_ports = 2,
3039 .base_baud = 115200,
3040 .uart_offset = 8,
3041 },
3042 [pbn_b0_4_115200] = {
3043 .flags = FL_BASE0,
3044 .num_ports = 4,
3045 .base_baud = 115200,
3046 .uart_offset = 8,
3047 },
3048 [pbn_b0_5_115200] = {
3049 .flags = FL_BASE0,
3050 .num_ports = 5,
3051 .base_baud = 115200,
3052 .uart_offset = 8,
3053 },
Alan Coxbf0df632007-10-16 01:24:00 -07003054 [pbn_b0_8_115200] = {
3055 .flags = FL_BASE0,
3056 .num_ports = 8,
3057 .base_baud = 115200,
3058 .uart_offset = 8,
3059 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003060 [pbn_b0_1_921600] = {
3061 .flags = FL_BASE0,
3062 .num_ports = 1,
3063 .base_baud = 921600,
3064 .uart_offset = 8,
3065 },
3066 [pbn_b0_2_921600] = {
3067 .flags = FL_BASE0,
3068 .num_ports = 2,
3069 .base_baud = 921600,
3070 .uart_offset = 8,
3071 },
3072 [pbn_b0_4_921600] = {
3073 .flags = FL_BASE0,
3074 .num_ports = 4,
3075 .base_baud = 921600,
3076 .uart_offset = 8,
3077 },
David Ransondb1de152005-07-27 11:43:55 -07003078
3079 [pbn_b0_2_1130000] = {
3080 .flags = FL_BASE0,
3081 .num_ports = 2,
3082 .base_baud = 1130000,
3083 .uart_offset = 8,
3084 },
3085
Andrey Paninfbc0dc02005-07-18 11:38:09 +01003086 [pbn_b0_4_1152000] = {
3087 .flags = FL_BASE0,
3088 .num_ports = 4,
3089 .base_baud = 1152000,
3090 .uart_offset = 8,
3091 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003092
Matt Schulte14faa8c2012-11-21 10:35:15 -06003093 [pbn_b0_2_1152000_200] = {
3094 .flags = FL_BASE0,
3095 .num_ports = 2,
3096 .base_baud = 1152000,
3097 .uart_offset = 0x200,
3098 },
3099
3100 [pbn_b0_4_1152000_200] = {
3101 .flags = FL_BASE0,
3102 .num_ports = 4,
3103 .base_baud = 1152000,
3104 .uart_offset = 0x200,
3105 },
3106
3107 [pbn_b0_8_1152000_200] = {
3108 .flags = FL_BASE0,
Matt Schulte4f7d67d2012-12-06 22:19:58 -06003109 .num_ports = 8,
Matt Schulte14faa8c2012-11-21 10:35:15 -06003110 .base_baud = 1152000,
3111 .uart_offset = 0x200,
3112 },
3113
Gareth Howlett26e92862006-01-04 17:00:42 +00003114 [pbn_b0_2_1843200] = {
3115 .flags = FL_BASE0,
3116 .num_ports = 2,
3117 .base_baud = 1843200,
3118 .uart_offset = 8,
3119 },
3120 [pbn_b0_4_1843200] = {
3121 .flags = FL_BASE0,
3122 .num_ports = 4,
3123 .base_baud = 1843200,
3124 .uart_offset = 8,
3125 },
3126
3127 [pbn_b0_2_1843200_200] = {
3128 .flags = FL_BASE0,
3129 .num_ports = 2,
3130 .base_baud = 1843200,
3131 .uart_offset = 0x200,
3132 },
3133 [pbn_b0_4_1843200_200] = {
3134 .flags = FL_BASE0,
3135 .num_ports = 4,
3136 .base_baud = 1843200,
3137 .uart_offset = 0x200,
3138 },
3139 [pbn_b0_8_1843200_200] = {
3140 .flags = FL_BASE0,
3141 .num_ports = 8,
3142 .base_baud = 1843200,
3143 .uart_offset = 0x200,
3144 },
Lee Howard7106b4e2008-10-21 13:48:58 +01003145 [pbn_b0_1_4000000] = {
3146 .flags = FL_BASE0,
3147 .num_ports = 1,
3148 .base_baud = 4000000,
3149 .uart_offset = 8,
3150 },
Gareth Howlett26e92862006-01-04 17:00:42 +00003151
Linus Torvalds1da177e2005-04-16 15:20:36 -07003152 [pbn_b0_bt_1_115200] = {
3153 .flags = FL_BASE0|FL_BASE_BARS,
3154 .num_ports = 1,
3155 .base_baud = 115200,
3156 .uart_offset = 8,
3157 },
3158 [pbn_b0_bt_2_115200] = {
3159 .flags = FL_BASE0|FL_BASE_BARS,
3160 .num_ports = 2,
3161 .base_baud = 115200,
3162 .uart_offset = 8,
3163 },
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08003164 [pbn_b0_bt_4_115200] = {
3165 .flags = FL_BASE0|FL_BASE_BARS,
3166 .num_ports = 4,
3167 .base_baud = 115200,
3168 .uart_offset = 8,
3169 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003170 [pbn_b0_bt_8_115200] = {
3171 .flags = FL_BASE0|FL_BASE_BARS,
3172 .num_ports = 8,
3173 .base_baud = 115200,
3174 .uart_offset = 8,
3175 },
3176
3177 [pbn_b0_bt_1_460800] = {
3178 .flags = FL_BASE0|FL_BASE_BARS,
3179 .num_ports = 1,
3180 .base_baud = 460800,
3181 .uart_offset = 8,
3182 },
3183 [pbn_b0_bt_2_460800] = {
3184 .flags = FL_BASE0|FL_BASE_BARS,
3185 .num_ports = 2,
3186 .base_baud = 460800,
3187 .uart_offset = 8,
3188 },
3189 [pbn_b0_bt_4_460800] = {
3190 .flags = FL_BASE0|FL_BASE_BARS,
3191 .num_ports = 4,
3192 .base_baud = 460800,
3193 .uart_offset = 8,
3194 },
3195
3196 [pbn_b0_bt_1_921600] = {
3197 .flags = FL_BASE0|FL_BASE_BARS,
3198 .num_ports = 1,
3199 .base_baud = 921600,
3200 .uart_offset = 8,
3201 },
3202 [pbn_b0_bt_2_921600] = {
3203 .flags = FL_BASE0|FL_BASE_BARS,
3204 .num_ports = 2,
3205 .base_baud = 921600,
3206 .uart_offset = 8,
3207 },
3208 [pbn_b0_bt_4_921600] = {
3209 .flags = FL_BASE0|FL_BASE_BARS,
3210 .num_ports = 4,
3211 .base_baud = 921600,
3212 .uart_offset = 8,
3213 },
3214 [pbn_b0_bt_8_921600] = {
3215 .flags = FL_BASE0|FL_BASE_BARS,
3216 .num_ports = 8,
3217 .base_baud = 921600,
3218 .uart_offset = 8,
3219 },
3220
3221 [pbn_b1_1_115200] = {
3222 .flags = FL_BASE1,
3223 .num_ports = 1,
3224 .base_baud = 115200,
3225 .uart_offset = 8,
3226 },
3227 [pbn_b1_2_115200] = {
3228 .flags = FL_BASE1,
3229 .num_ports = 2,
3230 .base_baud = 115200,
3231 .uart_offset = 8,
3232 },
3233 [pbn_b1_4_115200] = {
3234 .flags = FL_BASE1,
3235 .num_ports = 4,
3236 .base_baud = 115200,
3237 .uart_offset = 8,
3238 },
3239 [pbn_b1_8_115200] = {
3240 .flags = FL_BASE1,
3241 .num_ports = 8,
3242 .base_baud = 115200,
3243 .uart_offset = 8,
3244 },
Will Page04bf7e72009-04-06 17:32:15 +01003245 [pbn_b1_16_115200] = {
3246 .flags = FL_BASE1,
3247 .num_ports = 16,
3248 .base_baud = 115200,
3249 .uart_offset = 8,
3250 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003251
3252 [pbn_b1_1_921600] = {
3253 .flags = FL_BASE1,
3254 .num_ports = 1,
3255 .base_baud = 921600,
3256 .uart_offset = 8,
3257 },
3258 [pbn_b1_2_921600] = {
3259 .flags = FL_BASE1,
3260 .num_ports = 2,
3261 .base_baud = 921600,
3262 .uart_offset = 8,
3263 },
3264 [pbn_b1_4_921600] = {
3265 .flags = FL_BASE1,
3266 .num_ports = 4,
3267 .base_baud = 921600,
3268 .uart_offset = 8,
3269 },
3270 [pbn_b1_8_921600] = {
3271 .flags = FL_BASE1,
3272 .num_ports = 8,
3273 .base_baud = 921600,
3274 .uart_offset = 8,
3275 },
Gareth Howlett26e92862006-01-04 17:00:42 +00003276 [pbn_b1_2_1250000] = {
3277 .flags = FL_BASE1,
3278 .num_ports = 2,
3279 .base_baud = 1250000,
3280 .uart_offset = 8,
3281 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003282
Niels de Vos84f8c6f2007-08-22 14:01:14 -07003283 [pbn_b1_bt_1_115200] = {
3284 .flags = FL_BASE1|FL_BASE_BARS,
3285 .num_ports = 1,
3286 .base_baud = 115200,
3287 .uart_offset = 8,
3288 },
Will Page04bf7e72009-04-06 17:32:15 +01003289 [pbn_b1_bt_2_115200] = {
3290 .flags = FL_BASE1|FL_BASE_BARS,
3291 .num_ports = 2,
3292 .base_baud = 115200,
3293 .uart_offset = 8,
3294 },
3295 [pbn_b1_bt_4_115200] = {
3296 .flags = FL_BASE1|FL_BASE_BARS,
3297 .num_ports = 4,
3298 .base_baud = 115200,
3299 .uart_offset = 8,
3300 },
Niels de Vos84f8c6f2007-08-22 14:01:14 -07003301
Linus Torvalds1da177e2005-04-16 15:20:36 -07003302 [pbn_b1_bt_2_921600] = {
3303 .flags = FL_BASE1|FL_BASE_BARS,
3304 .num_ports = 2,
3305 .base_baud = 921600,
3306 .uart_offset = 8,
3307 },
3308
3309 [pbn_b1_1_1382400] = {
3310 .flags = FL_BASE1,
3311 .num_ports = 1,
3312 .base_baud = 1382400,
3313 .uart_offset = 8,
3314 },
3315 [pbn_b1_2_1382400] = {
3316 .flags = FL_BASE1,
3317 .num_ports = 2,
3318 .base_baud = 1382400,
3319 .uart_offset = 8,
3320 },
3321 [pbn_b1_4_1382400] = {
3322 .flags = FL_BASE1,
3323 .num_ports = 4,
3324 .base_baud = 1382400,
3325 .uart_offset = 8,
3326 },
3327 [pbn_b1_8_1382400] = {
3328 .flags = FL_BASE1,
3329 .num_ports = 8,
3330 .base_baud = 1382400,
3331 .uart_offset = 8,
3332 },
3333
3334 [pbn_b2_1_115200] = {
3335 .flags = FL_BASE2,
3336 .num_ports = 1,
3337 .base_baud = 115200,
3338 .uart_offset = 8,
3339 },
Peter Horton737c1752006-08-26 09:07:36 +01003340 [pbn_b2_2_115200] = {
3341 .flags = FL_BASE2,
3342 .num_ports = 2,
3343 .base_baud = 115200,
3344 .uart_offset = 8,
3345 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08003346 [pbn_b2_4_115200] = {
3347 .flags = FL_BASE2,
3348 .num_ports = 4,
3349 .base_baud = 115200,
3350 .uart_offset = 8,
3351 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003352 [pbn_b2_8_115200] = {
3353 .flags = FL_BASE2,
3354 .num_ports = 8,
3355 .base_baud = 115200,
3356 .uart_offset = 8,
3357 },
3358
3359 [pbn_b2_1_460800] = {
3360 .flags = FL_BASE2,
3361 .num_ports = 1,
3362 .base_baud = 460800,
3363 .uart_offset = 8,
3364 },
3365 [pbn_b2_4_460800] = {
3366 .flags = FL_BASE2,
3367 .num_ports = 4,
3368 .base_baud = 460800,
3369 .uart_offset = 8,
3370 },
3371 [pbn_b2_8_460800] = {
3372 .flags = FL_BASE2,
3373 .num_ports = 8,
3374 .base_baud = 460800,
3375 .uart_offset = 8,
3376 },
3377 [pbn_b2_16_460800] = {
3378 .flags = FL_BASE2,
3379 .num_ports = 16,
3380 .base_baud = 460800,
3381 .uart_offset = 8,
3382 },
3383
3384 [pbn_b2_1_921600] = {
3385 .flags = FL_BASE2,
3386 .num_ports = 1,
3387 .base_baud = 921600,
3388 .uart_offset = 8,
3389 },
3390 [pbn_b2_4_921600] = {
3391 .flags = FL_BASE2,
3392 .num_ports = 4,
3393 .base_baud = 921600,
3394 .uart_offset = 8,
3395 },
3396 [pbn_b2_8_921600] = {
3397 .flags = FL_BASE2,
3398 .num_ports = 8,
3399 .base_baud = 921600,
3400 .uart_offset = 8,
3401 },
3402
Lytochkin Borise8470032010-07-26 10:02:26 +04003403 [pbn_b2_8_1152000] = {
3404 .flags = FL_BASE2,
3405 .num_ports = 8,
3406 .base_baud = 1152000,
3407 .uart_offset = 8,
3408 },
3409
Linus Torvalds1da177e2005-04-16 15:20:36 -07003410 [pbn_b2_bt_1_115200] = {
3411 .flags = FL_BASE2|FL_BASE_BARS,
3412 .num_ports = 1,
3413 .base_baud = 115200,
3414 .uart_offset = 8,
3415 },
3416 [pbn_b2_bt_2_115200] = {
3417 .flags = FL_BASE2|FL_BASE_BARS,
3418 .num_ports = 2,
3419 .base_baud = 115200,
3420 .uart_offset = 8,
3421 },
3422 [pbn_b2_bt_4_115200] = {
3423 .flags = FL_BASE2|FL_BASE_BARS,
3424 .num_ports = 4,
3425 .base_baud = 115200,
3426 .uart_offset = 8,
3427 },
3428
3429 [pbn_b2_bt_2_921600] = {
3430 .flags = FL_BASE2|FL_BASE_BARS,
3431 .num_ports = 2,
3432 .base_baud = 921600,
3433 .uart_offset = 8,
3434 },
3435 [pbn_b2_bt_4_921600] = {
3436 .flags = FL_BASE2|FL_BASE_BARS,
3437 .num_ports = 4,
3438 .base_baud = 921600,
3439 .uart_offset = 8,
3440 },
3441
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00003442 [pbn_b3_2_115200] = {
3443 .flags = FL_BASE3,
3444 .num_ports = 2,
3445 .base_baud = 115200,
3446 .uart_offset = 8,
3447 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003448 [pbn_b3_4_115200] = {
3449 .flags = FL_BASE3,
3450 .num_ports = 4,
3451 .base_baud = 115200,
3452 .uart_offset = 8,
3453 },
3454 [pbn_b3_8_115200] = {
3455 .flags = FL_BASE3,
3456 .num_ports = 8,
3457 .base_baud = 115200,
3458 .uart_offset = 8,
3459 },
3460
Yegor Yefremov66169ad2010-06-04 09:58:18 +02003461 [pbn_b4_bt_2_921600] = {
3462 .flags = FL_BASE4,
3463 .num_ports = 2,
3464 .base_baud = 921600,
3465 .uart_offset = 8,
3466 },
3467 [pbn_b4_bt_4_921600] = {
3468 .flags = FL_BASE4,
3469 .num_ports = 4,
3470 .base_baud = 921600,
3471 .uart_offset = 8,
3472 },
3473 [pbn_b4_bt_8_921600] = {
3474 .flags = FL_BASE4,
3475 .num_ports = 8,
3476 .base_baud = 921600,
3477 .uart_offset = 8,
3478 },
3479
Linus Torvalds1da177e2005-04-16 15:20:36 -07003480 /*
3481 * Entries following this are board-specific.
3482 */
3483
3484 /*
3485 * Panacom - IOMEM
3486 */
3487 [pbn_panacom] = {
3488 .flags = FL_BASE2,
3489 .num_ports = 2,
3490 .base_baud = 921600,
3491 .uart_offset = 0x400,
3492 .reg_shift = 7,
3493 },
3494 [pbn_panacom2] = {
3495 .flags = FL_BASE2|FL_BASE_BARS,
3496 .num_ports = 2,
3497 .base_baud = 921600,
3498 .uart_offset = 0x400,
3499 .reg_shift = 7,
3500 },
3501 [pbn_panacom4] = {
3502 .flags = FL_BASE2|FL_BASE_BARS,
3503 .num_ports = 4,
3504 .base_baud = 921600,
3505 .uart_offset = 0x400,
3506 .reg_shift = 7,
3507 },
3508
3509 /* I think this entry is broken - the first_offset looks wrong --rmk */
3510 [pbn_plx_romulus] = {
3511 .flags = FL_BASE2,
3512 .num_ports = 4,
3513 .base_baud = 921600,
3514 .uart_offset = 8 << 2,
3515 .reg_shift = 2,
3516 .first_offset = 0x03,
3517 },
3518
3519 /*
Mike Skoog1bc8cde2014-10-16 13:10:01 -07003520 * EndRun Technologies
3521 * Uses the size of PCI Base region 0 to
3522 * signal now many ports are available
3523 * 2 port 952 Uart support
3524 */
3525 [pbn_endrun_2_4000000] = {
3526 .flags = FL_BASE0,
3527 .num_ports = 2,
3528 .base_baud = 4000000,
3529 .uart_offset = 0x200,
3530 .first_offset = 0x1000,
3531 },
3532
3533 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003534 * This board uses the size of PCI Base region 0 to
3535 * signal now many ports are available
3536 */
3537 [pbn_oxsemi] = {
3538 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3539 .num_ports = 32,
3540 .base_baud = 115200,
3541 .uart_offset = 8,
3542 },
Lee Howard7106b4e2008-10-21 13:48:58 +01003543 [pbn_oxsemi_1_4000000] = {
3544 .flags = FL_BASE0,
3545 .num_ports = 1,
3546 .base_baud = 4000000,
3547 .uart_offset = 0x200,
3548 .first_offset = 0x1000,
3549 },
3550 [pbn_oxsemi_2_4000000] = {
3551 .flags = FL_BASE0,
3552 .num_ports = 2,
3553 .base_baud = 4000000,
3554 .uart_offset = 0x200,
3555 .first_offset = 0x1000,
3556 },
3557 [pbn_oxsemi_4_4000000] = {
3558 .flags = FL_BASE0,
3559 .num_ports = 4,
3560 .base_baud = 4000000,
3561 .uart_offset = 0x200,
3562 .first_offset = 0x1000,
3563 },
3564 [pbn_oxsemi_8_4000000] = {
3565 .flags = FL_BASE0,
3566 .num_ports = 8,
3567 .base_baud = 4000000,
3568 .uart_offset = 0x200,
3569 .first_offset = 0x1000,
3570 },
3571
Linus Torvalds1da177e2005-04-16 15:20:36 -07003572
3573 /*
3574 * EKF addition for i960 Boards form EKF with serial port.
3575 * Max 256 ports.
3576 */
3577 [pbn_intel_i960] = {
3578 .flags = FL_BASE0,
3579 .num_ports = 32,
3580 .base_baud = 921600,
3581 .uart_offset = 8 << 2,
3582 .reg_shift = 2,
3583 .first_offset = 0x10000,
3584 },
3585 [pbn_sgi_ioc3] = {
3586 .flags = FL_BASE0|FL_NOIRQ,
3587 .num_ports = 1,
3588 .base_baud = 458333,
3589 .uart_offset = 8,
3590 .reg_shift = 0,
3591 .first_offset = 0x20178,
3592 },
3593
3594 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003595 * Computone - uses IOMEM.
3596 */
3597 [pbn_computone_4] = {
3598 .flags = FL_BASE0,
3599 .num_ports = 4,
3600 .base_baud = 921600,
3601 .uart_offset = 0x40,
3602 .reg_shift = 2,
3603 .first_offset = 0x200,
3604 },
3605 [pbn_computone_6] = {
3606 .flags = FL_BASE0,
3607 .num_ports = 6,
3608 .base_baud = 921600,
3609 .uart_offset = 0x40,
3610 .reg_shift = 2,
3611 .first_offset = 0x200,
3612 },
3613 [pbn_computone_8] = {
3614 .flags = FL_BASE0,
3615 .num_ports = 8,
3616 .base_baud = 921600,
3617 .uart_offset = 0x40,
3618 .reg_shift = 2,
3619 .first_offset = 0x200,
3620 },
3621 [pbn_sbsxrsio] = {
3622 .flags = FL_BASE0,
3623 .num_ports = 8,
3624 .base_baud = 460800,
3625 .uart_offset = 256,
3626 .reg_shift = 4,
3627 },
3628 /*
3629 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3630 * Only basic 16550A support.
3631 * XR17C15[24] are not tested, but they should work.
3632 */
3633 [pbn_exar_XR17C152] = {
3634 .flags = FL_BASE0,
3635 .num_ports = 2,
3636 .base_baud = 921600,
3637 .uart_offset = 0x200,
3638 },
3639 [pbn_exar_XR17C154] = {
3640 .flags = FL_BASE0,
3641 .num_ports = 4,
3642 .base_baud = 921600,
3643 .uart_offset = 0x200,
3644 },
3645 [pbn_exar_XR17C158] = {
3646 .flags = FL_BASE0,
3647 .num_ports = 8,
3648 .base_baud = 921600,
3649 .uart_offset = 0x200,
3650 },
Matt Schultedc96efb2012-11-19 09:12:04 -06003651 [pbn_exar_XR17V352] = {
3652 .flags = FL_BASE0,
3653 .num_ports = 2,
3654 .base_baud = 7812500,
3655 .uart_offset = 0x400,
3656 .reg_shift = 0,
3657 .first_offset = 0,
3658 },
3659 [pbn_exar_XR17V354] = {
3660 .flags = FL_BASE0,
3661 .num_ports = 4,
3662 .base_baud = 7812500,
3663 .uart_offset = 0x400,
3664 .reg_shift = 0,
3665 .first_offset = 0,
3666 },
3667 [pbn_exar_XR17V358] = {
3668 .flags = FL_BASE0,
3669 .num_ports = 8,
3670 .base_baud = 7812500,
3671 .uart_offset = 0x400,
3672 .reg_shift = 0,
3673 .first_offset = 0,
3674 },
Benjamin Herrenschmidtc68d2b12009-10-26 16:50:05 -07003675 [pbn_exar_ibm_saturn] = {
3676 .flags = FL_BASE0,
3677 .num_ports = 1,
3678 .base_baud = 921600,
3679 .uart_offset = 0x200,
3680 },
3681
Olof Johanssonaa798502007-08-22 14:01:55 -07003682 /*
3683 * PA Semi PWRficient PA6T-1682M on-chip UART
3684 */
3685 [pbn_pasemi_1682M] = {
3686 .flags = FL_BASE0,
3687 .num_ports = 1,
3688 .base_baud = 8333333,
3689 },
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01003690 /*
3691 * National Instruments 843x
3692 */
3693 [pbn_ni8430_16] = {
3694 .flags = FL_BASE0,
3695 .num_ports = 16,
3696 .base_baud = 3686400,
3697 .uart_offset = 0x10,
3698 .first_offset = 0x800,
3699 },
3700 [pbn_ni8430_8] = {
3701 .flags = FL_BASE0,
3702 .num_ports = 8,
3703 .base_baud = 3686400,
3704 .uart_offset = 0x10,
3705 .first_offset = 0x800,
3706 },
3707 [pbn_ni8430_4] = {
3708 .flags = FL_BASE0,
3709 .num_ports = 4,
3710 .base_baud = 3686400,
3711 .uart_offset = 0x10,
3712 .first_offset = 0x800,
3713 },
3714 [pbn_ni8430_2] = {
3715 .flags = FL_BASE0,
3716 .num_ports = 2,
3717 .base_baud = 3686400,
3718 .uart_offset = 0x10,
3719 .first_offset = 0x800,
3720 },
Krauth.Julien1b62cbf2009-10-26 16:50:04 -07003721 /*
3722 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3723 */
3724 [pbn_ADDIDATA_PCIe_1_3906250] = {
3725 .flags = FL_BASE0,
3726 .num_ports = 1,
3727 .base_baud = 3906250,
3728 .uart_offset = 0x200,
3729 .first_offset = 0x1000,
3730 },
3731 [pbn_ADDIDATA_PCIe_2_3906250] = {
3732 .flags = FL_BASE0,
3733 .num_ports = 2,
3734 .base_baud = 3906250,
3735 .uart_offset = 0x200,
3736 .first_offset = 0x1000,
3737 },
3738 [pbn_ADDIDATA_PCIe_4_3906250] = {
3739 .flags = FL_BASE0,
3740 .num_ports = 4,
3741 .base_baud = 3906250,
3742 .uart_offset = 0x200,
3743 .first_offset = 0x1000,
3744 },
3745 [pbn_ADDIDATA_PCIe_8_3906250] = {
3746 .flags = FL_BASE0,
3747 .num_ports = 8,
3748 .base_baud = 3906250,
3749 .uart_offset = 0x200,
3750 .first_offset = 0x1000,
3751 },
Dirk Brandewie095e24b2010-11-17 07:35:20 -08003752 [pbn_ce4100_1_115200] = {
Maxime Bizon08ec2122012-10-19 10:45:07 +02003753 .flags = FL_BASE_BARS,
3754 .num_ports = 2,
Dirk Brandewie095e24b2010-11-17 07:35:20 -08003755 .base_baud = 921600,
3756 .reg_shift = 2,
3757 },
Aaron Sierra41d3f092014-03-03 19:54:36 -06003758 /*
3759 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3760 * but is overridden by byt_set_termios.
3761 */
Heikki Krogerusb15e5692013-09-27 10:52:59 +03003762 [pbn_byt] = {
3763 .flags = FL_BASE0,
3764 .num_ports = 1,
3765 .base_baud = 2764800,
3766 .uart_offset = 0x80,
3767 .reg_shift = 2,
3768 },
Andy Shevchenkof549e942015-02-23 16:24:43 +02003769 [pbn_pnw] = {
3770 .flags = FL_BASE0,
3771 .num_ports = 1,
3772 .base_baud = 115200,
3773 },
Bryan O'Donoghue1ede7dc2014-09-23 01:21:11 +01003774 [pbn_qrk] = {
3775 .flags = FL_BASE0,
3776 .num_ports = 1,
3777 .base_baud = 2764800,
3778 .reg_shift = 2,
3779 },
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04003780 [pbn_omegapci] = {
3781 .flags = FL_BASE0,
3782 .num_ports = 8,
3783 .base_baud = 115200,
3784 .uart_offset = 0x200,
3785 },
Nicos Gollan7808edc2011-05-05 21:00:37 +02003786 [pbn_NETMOS9900_2s_115200] = {
3787 .flags = FL_BASE0,
3788 .num_ports = 2,
3789 .base_baud = 115200,
3790 },
Stephen Hurdebebd492013-01-17 14:14:53 -08003791 [pbn_brcm_trumanage] = {
3792 .flags = FL_BASE0,
3793 .num_ports = 1,
3794 .reg_shift = 2,
3795 .base_baud = 115200,
3796 },
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07003797 [pbn_fintek_4] = {
3798 .num_ports = 4,
3799 .uart_offset = 8,
3800 .base_baud = 115200,
3801 .first_offset = 0x40,
3802 },
3803 [pbn_fintek_8] = {
3804 .num_ports = 8,
3805 .uart_offset = 8,
3806 .base_baud = 115200,
3807 .first_offset = 0x40,
3808 },
3809 [pbn_fintek_12] = {
3810 .num_ports = 12,
3811 .uart_offset = 8,
3812 .base_baud = 115200,
3813 .first_offset = 0x40,
3814 },
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03003815
3816 [pbn_wch384_4] = {
3817 .flags = FL_BASE0,
3818 .num_ports = 4,
3819 .base_baud = 115200,
3820 .uart_offset = 8,
3821 .first_offset = 0xC0,
3822 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07003823};
3824
Guainluca Anzolin6971c632012-09-04 15:56:12 +01003825static const struct pci_device_id blacklist[] = {
3826 /* softmodems */
Alan Cox5756ee92008-02-08 04:18:51 -08003827 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
Maciej Szmigieroebf7c062010-10-26 21:48:21 +02003828 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3829 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
Guainluca Anzolin6971c632012-09-04 15:56:12 +01003830
3831 /* multi-io cards handled by parport_serial */
3832 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
Ezequiel Garciafeb58142014-05-24 15:24:51 -03003833 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
Sergej Pupykin2fdd8c82014-11-06 14:36:31 +03003834 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03003835 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
Christian Schmidt436bbd42007-08-22 14:01:19 -07003836};
3837
Linus Torvalds1da177e2005-04-16 15:20:36 -07003838/*
3839 * Given a complete unknown PCI device, try to use some heuristics to
3840 * guess what the configuration might be, based on the pitiful PCI
3841 * serial specs. Returns 0 on success, 1 on failure.
3842 */
Bill Pemberton9671f092012-11-19 13:21:50 -05003843static int
Russell King1c7c1fe2005-07-27 11:31:19 +01003844serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003845{
Guainluca Anzolin6971c632012-09-04 15:56:12 +01003846 const struct pci_device_id *bldev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003847 int num_iomem, num_port, first_port = -1, i;
Alan Cox5756ee92008-02-08 04:18:51 -08003848
Linus Torvalds1da177e2005-04-16 15:20:36 -07003849 /*
3850 * If it is not a communications device or the programming
3851 * interface is greater than 6, give up.
3852 *
3853 * (Should we try to make guesses for multiport serial devices
Alan Cox5756ee92008-02-08 04:18:51 -08003854 * later?)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003855 */
3856 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3857 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3858 (dev->class & 0xff) > 6)
3859 return -ENODEV;
3860
Christian Schmidt436bbd42007-08-22 14:01:19 -07003861 /*
3862 * Do not access blacklisted devices that are known not to
Guainluca Anzolin6971c632012-09-04 15:56:12 +01003863 * feature serial ports or are handled by other modules.
Christian Schmidt436bbd42007-08-22 14:01:19 -07003864 */
Guainluca Anzolin6971c632012-09-04 15:56:12 +01003865 for (bldev = blacklist;
3866 bldev < blacklist + ARRAY_SIZE(blacklist);
3867 bldev++) {
3868 if (dev->vendor == bldev->vendor &&
3869 dev->device == bldev->device)
Christian Schmidt436bbd42007-08-22 14:01:19 -07003870 return -ENODEV;
3871 }
3872
Linus Torvalds1da177e2005-04-16 15:20:36 -07003873 num_iomem = num_port = 0;
3874 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3875 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3876 num_port++;
3877 if (first_port == -1)
3878 first_port = i;
3879 }
3880 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3881 num_iomem++;
3882 }
3883
3884 /*
3885 * If there is 1 or 0 iomem regions, and exactly one port,
3886 * use it. We guess the number of ports based on the IO
3887 * region size.
3888 */
3889 if (num_iomem <= 1 && num_port == 1) {
3890 board->flags = first_port;
3891 board->num_ports = pci_resource_len(dev, first_port) / 8;
3892 return 0;
3893 }
3894
3895 /*
3896 * Now guess if we've got a board which indexes by BARs.
3897 * Each IO BAR should be 8 bytes, and they should follow
3898 * consecutively.
3899 */
3900 first_port = -1;
3901 num_port = 0;
3902 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3903 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3904 pci_resource_len(dev, i) == 8 &&
3905 (first_port == -1 || (first_port + num_port) == i)) {
3906 num_port++;
3907 if (first_port == -1)
3908 first_port = i;
3909 }
3910 }
3911
3912 if (num_port > 1) {
3913 board->flags = first_port | FL_BASE_BARS;
3914 board->num_ports = num_port;
3915 return 0;
3916 }
3917
3918 return -ENODEV;
3919}
3920
3921static inline int
Russell King975a1a72009-01-02 13:44:27 +00003922serial_pci_matches(const struct pciserial_board *board,
3923 const struct pciserial_board *guessed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003924{
3925 return
3926 board->num_ports == guessed->num_ports &&
3927 board->base_baud == guessed->base_baud &&
3928 board->uart_offset == guessed->uart_offset &&
3929 board->reg_shift == guessed->reg_shift &&
3930 board->first_offset == guessed->first_offset;
3931}
3932
Russell King241fc432005-07-27 11:35:54 +01003933struct serial_private *
Russell King975a1a72009-01-02 13:44:27 +00003934pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
Russell King241fc432005-07-27 11:35:54 +01003935{
Alan Cox2655a2c2012-07-12 12:59:50 +01003936 struct uart_8250_port uart;
Russell King241fc432005-07-27 11:35:54 +01003937 struct serial_private *priv;
3938 struct pci_serial_quirk *quirk;
3939 int rc, nr_ports, i;
3940
3941 nr_ports = board->num_ports;
3942
3943 /*
3944 * Find an init and setup quirks.
3945 */
3946 quirk = find_quirk(dev);
3947
3948 /*
3949 * Run the new-style initialization function.
3950 * The initialization function returns:
3951 * <0 - error
3952 * 0 - use board->num_ports
3953 * >0 - number of ports
3954 */
3955 if (quirk->init) {
3956 rc = quirk->init(dev);
3957 if (rc < 0) {
3958 priv = ERR_PTR(rc);
3959 goto err_out;
3960 }
3961 if (rc)
3962 nr_ports = rc;
3963 }
3964
Burman Yan8f31bb32007-02-14 00:33:07 -08003965 priv = kzalloc(sizeof(struct serial_private) +
Russell King241fc432005-07-27 11:35:54 +01003966 sizeof(unsigned int) * nr_ports,
3967 GFP_KERNEL);
3968 if (!priv) {
3969 priv = ERR_PTR(-ENOMEM);
3970 goto err_deinit;
3971 }
3972
Russell King241fc432005-07-27 11:35:54 +01003973 priv->dev = dev;
3974 priv->quirk = quirk;
3975
Alan Cox2655a2c2012-07-12 12:59:50 +01003976 memset(&uart, 0, sizeof(uart));
3977 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3978 uart.port.uartclk = board->base_baud * 16;
3979 uart.port.irq = get_pci_irq(dev, board);
3980 uart.port.dev = &dev->dev;
Russell King241fc432005-07-27 11:35:54 +01003981
3982 for (i = 0; i < nr_ports; i++) {
Alan Cox2655a2c2012-07-12 12:59:50 +01003983 if (quirk->setup(priv, board, &uart, i))
Russell King241fc432005-07-27 11:35:54 +01003984 break;
3985
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -07003986 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3987 uart.port.iobase, uart.port.irq, uart.port.iotype);
Alan Cox5756ee92008-02-08 04:18:51 -08003988
Alan Cox2655a2c2012-07-12 12:59:50 +01003989 priv->line[i] = serial8250_register_8250_port(&uart);
Russell King241fc432005-07-27 11:35:54 +01003990 if (priv->line[i] < 0) {
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -07003991 dev_err(&dev->dev,
3992 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3993 uart.port.iobase, uart.port.irq,
3994 uart.port.iotype, priv->line[i]);
Russell King241fc432005-07-27 11:35:54 +01003995 break;
3996 }
3997 }
Russell King241fc432005-07-27 11:35:54 +01003998 priv->nr = i;
Russell King241fc432005-07-27 11:35:54 +01003999 return priv;
4000
Alan Cox5756ee92008-02-08 04:18:51 -08004001err_deinit:
Russell King241fc432005-07-27 11:35:54 +01004002 if (quirk->exit)
4003 quirk->exit(dev);
Alan Cox5756ee92008-02-08 04:18:51 -08004004err_out:
Russell King241fc432005-07-27 11:35:54 +01004005 return priv;
4006}
4007EXPORT_SYMBOL_GPL(pciserial_init_ports);
4008
4009void pciserial_remove_ports(struct serial_private *priv)
4010{
4011 struct pci_serial_quirk *quirk;
4012 int i;
4013
4014 for (i = 0; i < priv->nr; i++)
4015 serial8250_unregister_port(priv->line[i]);
4016
4017 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4018 if (priv->remapped_bar[i])
4019 iounmap(priv->remapped_bar[i]);
4020 priv->remapped_bar[i] = NULL;
4021 }
4022
4023 /*
4024 * Find the exit quirks.
4025 */
4026 quirk = find_quirk(priv->dev);
4027 if (quirk->exit)
4028 quirk->exit(priv->dev);
4029
4030 kfree(priv);
4031}
4032EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4033
4034void pciserial_suspend_ports(struct serial_private *priv)
4035{
4036 int i;
4037
4038 for (i = 0; i < priv->nr; i++)
4039 if (priv->line[i] >= 0)
4040 serial8250_suspend_port(priv->line[i]);
Dan Williams5f1a3892012-04-10 14:11:03 -07004041
4042 /*
4043 * Ensure that every init quirk is properly torn down
4044 */
4045 if (priv->quirk->exit)
4046 priv->quirk->exit(priv->dev);
Russell King241fc432005-07-27 11:35:54 +01004047}
4048EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4049
4050void pciserial_resume_ports(struct serial_private *priv)
4051{
4052 int i;
4053
4054 /*
4055 * Ensure that the board is correctly configured.
4056 */
4057 if (priv->quirk->init)
4058 priv->quirk->init(priv->dev);
4059
4060 for (i = 0; i < priv->nr; i++)
4061 if (priv->line[i] >= 0)
4062 serial8250_resume_port(priv->line[i]);
4063}
4064EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4065
Linus Torvalds1da177e2005-04-16 15:20:36 -07004066/*
4067 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4068 * to the arrangement of serial ports on a PCI card.
4069 */
Bill Pemberton9671f092012-11-19 13:21:50 -05004070static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07004071pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4072{
Frédéric Brière5bf8f502011-05-29 15:08:03 -04004073 struct pci_serial_quirk *quirk;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004074 struct serial_private *priv;
Russell King975a1a72009-01-02 13:44:27 +00004075 const struct pciserial_board *board;
4076 struct pciserial_board tmp;
Russell King241fc432005-07-27 11:35:54 +01004077 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004078
Frédéric Brière5bf8f502011-05-29 15:08:03 -04004079 quirk = find_quirk(dev);
4080 if (quirk->probe) {
4081 rc = quirk->probe(dev);
4082 if (rc)
4083 return rc;
4084 }
4085
Linus Torvalds1da177e2005-04-16 15:20:36 -07004086 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
Greg Kroah-Hartmanaf8c5b82013-09-28 13:01:59 -07004087 dev_err(&dev->dev, "invalid driver_data: %ld\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07004088 ent->driver_data);
4089 return -EINVAL;
4090 }
4091
4092 board = &pci_boards[ent->driver_data];
4093
4094 rc = pci_enable_device(dev);
Michael Reed28071902011-05-31 12:06:28 -05004095 pci_save_state(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004096 if (rc)
4097 return rc;
4098
4099 if (ent->driver_data == pbn_default) {
4100 /*
4101 * Use a copy of the pci_board entry for this;
4102 * avoid changing entries in the table.
4103 */
Russell King1c7c1fe2005-07-27 11:31:19 +01004104 memcpy(&tmp, board, sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004105 board = &tmp;
4106
4107 /*
4108 * We matched one of our class entries. Try to
4109 * determine the parameters of this board.
4110 */
Russell King975a1a72009-01-02 13:44:27 +00004111 rc = serial_pci_guess_board(dev, &tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004112 if (rc)
4113 goto disable;
4114 } else {
4115 /*
4116 * We matched an explicit entry. If we are able to
4117 * detect this boards settings with our heuristic,
4118 * then we no longer need this entry.
4119 */
Russell King1c7c1fe2005-07-27 11:31:19 +01004120 memcpy(&tmp, &pci_boards[pbn_default],
4121 sizeof(struct pciserial_board));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004122 rc = serial_pci_guess_board(dev, &tmp);
4123 if (rc == 0 && serial_pci_matches(board, &tmp))
4124 moan_device("Redundant entry in serial pci_table.",
4125 dev);
4126 }
4127
Russell King241fc432005-07-27 11:35:54 +01004128 priv = pciserial_init_ports(dev, board);
4129 if (!IS_ERR(priv)) {
4130 pci_set_drvdata(dev, priv);
4131 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004132 }
4133
Russell King241fc432005-07-27 11:35:54 +01004134 rc = PTR_ERR(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004135
Linus Torvalds1da177e2005-04-16 15:20:36 -07004136 disable:
4137 pci_disable_device(dev);
4138 return rc;
4139}
4140
Bill Pembertonae8d8a12012-11-19 13:26:18 -05004141static void pciserial_remove_one(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004142{
4143 struct serial_private *priv = pci_get_drvdata(dev);
4144
Russell King241fc432005-07-27 11:35:54 +01004145 pciserial_remove_ports(priv);
Russell King056a8762005-07-22 10:15:04 +01004146
4147 pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004148}
4149
Andy Shevchenko61702c32015-02-02 14:53:26 +02004150#ifdef CONFIG_PM_SLEEP
4151static int pciserial_suspend_one(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004152{
Andy Shevchenko61702c32015-02-02 14:53:26 +02004153 struct pci_dev *pdev = to_pci_dev(dev);
4154 struct serial_private *priv = pci_get_drvdata(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004155
Russell King241fc432005-07-27 11:35:54 +01004156 if (priv)
4157 pciserial_suspend_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004158
Linus Torvalds1da177e2005-04-16 15:20:36 -07004159 return 0;
4160}
4161
Andy Shevchenko61702c32015-02-02 14:53:26 +02004162static int pciserial_resume_one(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004163{
Andy Shevchenko61702c32015-02-02 14:53:26 +02004164 struct pci_dev *pdev = to_pci_dev(dev);
4165 struct serial_private *priv = pci_get_drvdata(pdev);
Dirk Hohndelccb9d592007-10-29 06:28:17 -07004166 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004167
4168 if (priv) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004169 /*
4170 * The device may have been disabled. Re-enable it.
4171 */
Andy Shevchenko61702c32015-02-02 14:53:26 +02004172 err = pci_enable_device(pdev);
Alan Cox40836c42008-10-13 10:36:11 +01004173 /* FIXME: We cannot simply error out here */
Dirk Hohndelccb9d592007-10-29 06:28:17 -07004174 if (err)
Andy Shevchenko61702c32015-02-02 14:53:26 +02004175 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
Russell King241fc432005-07-27 11:35:54 +01004176 pciserial_resume_ports(priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004177 }
4178 return 0;
4179}
Alexey Dobriyan1d5e7992006-09-25 16:51:27 -07004180#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07004181
Andy Shevchenko61702c32015-02-02 14:53:26 +02004182static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4183 pciserial_resume_one);
4184
Linus Torvalds1da177e2005-04-16 15:20:36 -07004185static struct pci_device_id serial_pci_tbl[] = {
Michael Bramer78d70d42009-01-27 11:51:16 +00004186 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4187 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4188 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4189 pbn_b2_8_921600 },
Thomee Wright0c6d7742014-05-19 20:30:51 +00004190 /* Advantech also use 0x3618 and 0xf618 */
4191 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4192 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4193 pbn_b0_4_921600 },
4194 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4195 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4196 pbn_b0_4_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004197 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4198 PCI_SUBVENDOR_ID_CONNECT_TECH,
4199 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4200 pbn_b1_8_1382400 },
4201 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4202 PCI_SUBVENDOR_ID_CONNECT_TECH,
4203 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4204 pbn_b1_4_1382400 },
4205 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4206 PCI_SUBVENDOR_ID_CONNECT_TECH,
4207 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4208 pbn_b1_2_1382400 },
4209 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4210 PCI_SUBVENDOR_ID_CONNECT_TECH,
4211 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4212 pbn_b1_8_1382400 },
4213 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4214 PCI_SUBVENDOR_ID_CONNECT_TECH,
4215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4216 pbn_b1_4_1382400 },
4217 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4218 PCI_SUBVENDOR_ID_CONNECT_TECH,
4219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4220 pbn_b1_2_1382400 },
4221 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4222 PCI_SUBVENDOR_ID_CONNECT_TECH,
4223 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4224 pbn_b1_8_921600 },
4225 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4226 PCI_SUBVENDOR_ID_CONNECT_TECH,
4227 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4228 pbn_b1_8_921600 },
4229 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4230 PCI_SUBVENDOR_ID_CONNECT_TECH,
4231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4232 pbn_b1_4_921600 },
4233 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4234 PCI_SUBVENDOR_ID_CONNECT_TECH,
4235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4236 pbn_b1_4_921600 },
4237 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4238 PCI_SUBVENDOR_ID_CONNECT_TECH,
4239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4240 pbn_b1_2_921600 },
4241 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4242 PCI_SUBVENDOR_ID_CONNECT_TECH,
4243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4244 pbn_b1_8_921600 },
4245 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4246 PCI_SUBVENDOR_ID_CONNECT_TECH,
4247 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4248 pbn_b1_8_921600 },
4249 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4250 PCI_SUBVENDOR_ID_CONNECT_TECH,
4251 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4252 pbn_b1_4_921600 },
Gareth Howlett26e92862006-01-04 17:00:42 +00004253 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4254 PCI_SUBVENDOR_ID_CONNECT_TECH,
4255 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4256 pbn_b1_2_1250000 },
4257 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4258 PCI_SUBVENDOR_ID_CONNECT_TECH,
4259 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4260 pbn_b0_2_1843200 },
4261 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4262 PCI_SUBVENDOR_ID_CONNECT_TECH,
4263 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4264 pbn_b0_4_1843200 },
Yoichi Yuasa85d14942006-02-08 21:46:24 +00004265 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4266 PCI_VENDOR_ID_AFAVLAB,
4267 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4268 pbn_b0_4_1152000 },
Gareth Howlett26e92862006-01-04 17:00:42 +00004269 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4270 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4272 pbn_b0_2_1843200_200 },
4273 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4274 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4276 pbn_b0_4_1843200_200 },
4277 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4278 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4280 pbn_b0_8_1843200_200 },
4281 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4282 PCI_SUBVENDOR_ID_CONNECT_TECH,
4283 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4284 pbn_b0_2_1843200_200 },
4285 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4286 PCI_SUBVENDOR_ID_CONNECT_TECH,
4287 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4288 pbn_b0_4_1843200_200 },
4289 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4290 PCI_SUBVENDOR_ID_CONNECT_TECH,
4291 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4292 pbn_b0_8_1843200_200 },
4293 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4294 PCI_SUBVENDOR_ID_CONNECT_TECH,
4295 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4296 pbn_b0_2_1843200_200 },
4297 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4298 PCI_SUBVENDOR_ID_CONNECT_TECH,
4299 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4300 pbn_b0_4_1843200_200 },
4301 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4302 PCI_SUBVENDOR_ID_CONNECT_TECH,
4303 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4304 pbn_b0_8_1843200_200 },
4305 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4306 PCI_SUBVENDOR_ID_CONNECT_TECH,
4307 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4308 pbn_b0_2_1843200_200 },
4309 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4310 PCI_SUBVENDOR_ID_CONNECT_TECH,
4311 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4312 pbn_b0_4_1843200_200 },
4313 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4314 PCI_SUBVENDOR_ID_CONNECT_TECH,
4315 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4316 pbn_b0_8_1843200_200 },
Benjamin Herrenschmidtc68d2b12009-10-26 16:50:05 -07004317 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4318 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4319 0, 0, pbn_exar_ibm_saturn },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004320
4321 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
Alan Cox5756ee92008-02-08 04:18:51 -08004322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004323 pbn_b2_bt_1_115200 },
4324 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
Alan Cox5756ee92008-02-08 04:18:51 -08004325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004326 pbn_b2_bt_2_115200 },
4327 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
Alan Cox5756ee92008-02-08 04:18:51 -08004328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004329 pbn_b2_bt_4_115200 },
4330 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
Alan Cox5756ee92008-02-08 04:18:51 -08004331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004332 pbn_b2_bt_2_115200 },
4333 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
Alan Cox5756ee92008-02-08 04:18:51 -08004334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004335 pbn_b2_bt_4_115200 },
4336 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
Alan Cox5756ee92008-02-08 04:18:51 -08004337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004338 pbn_b2_8_115200 },
Flavio Leitnere65f0f82009-01-02 13:50:43 +00004339 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341 pbn_b2_8_460800 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004342 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344 pbn_b2_8_115200 },
4345
4346 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b2_bt_2_115200 },
4349 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b2_bt_2_921600 },
4352 /*
4353 * VScom SPCOM800, from sl@s.pl
4354 */
Alan Cox5756ee92008-02-08 04:18:51 -08004355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004357 pbn_b2_8_921600 },
4358 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
Alan Cox5756ee92008-02-08 04:18:51 -08004359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004360 pbn_b2_4_921600 },
Catalin(ux) M BOIEb76c5a02008-07-23 21:29:46 -07004361 /* Unknown card - subdevice 0x1584 */
4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4363 PCI_VENDOR_ID_PLX,
4364 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
Scott Ashcroftd13402a2013-03-03 21:35:06 +00004365 pbn_b2_4_115200 },
4366 /* Unknown card - subdevice 0x1588 */
4367 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4368 PCI_VENDOR_ID_PLX,
4369 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4370 pbn_b2_8_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004371 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4372 PCI_SUBVENDOR_ID_KEYSPAN,
4373 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4374 pbn_panacom },
4375 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377 pbn_panacom4 },
4378 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 pbn_panacom2 },
Matthias Fuchsa9cccd32007-02-10 01:46:05 -08004381 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4382 PCI_VENDOR_ID_ESDGMBH,
4383 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4384 pbn_b2_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004385 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4386 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08004387 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004388 pbn_b2_4_460800 },
4389 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4390 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08004391 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004392 pbn_b2_8_460800 },
4393 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4394 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08004395 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004396 pbn_b2_16_460800 },
4397 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4398 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
Alan Cox5756ee92008-02-08 04:18:51 -08004399 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004400 pbn_b2_16_460800 },
4401 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4402 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
Alan Cox5756ee92008-02-08 04:18:51 -08004403 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004404 pbn_b2_4_460800 },
4405 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4406 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
Alan Cox5756ee92008-02-08 04:18:51 -08004407 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004408 pbn_b2_8_460800 },
Bjorn Helgaasadd7b582005-10-24 22:11:57 +01004409 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4410 PCI_SUBVENDOR_ID_EXSYS,
4411 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
Shawn Bohreree4cd1b2012-05-28 15:20:47 -05004412 pbn_b2_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004413 /*
4414 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4415 * (Exoray@isys.ca)
4416 */
4417 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4418 0x10b5, 0x106a, 0, 0,
4419 pbn_plx_romulus },
Alan Cox55c7c0f2012-11-29 09:03:00 +10304420 /*
Mike Skoog1bc8cde2014-10-16 13:10:01 -07004421 * EndRun Technologies. PCI express device range.
4422 * EndRun PTP/1588 has 2 Native UARTs.
4423 */
4424 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_endrun_2_4000000 },
4427 /*
Alan Cox55c7c0f2012-11-29 09:03:00 +10304428 * Quatech cards. These actually have configurable clocks but for
4429 * now we just use the default.
4430 *
4431 * 100 series are RS232, 200 series RS422,
4432 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004433 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b1_4_115200 },
4436 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_b1_2_115200 },
Alan Cox55c7c0f2012-11-29 09:03:00 +10304439 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b2_2_115200 },
4442 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b1_2_115200 },
4445 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b2_2_115200 },
4448 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 pbn_b1_4_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004451 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 pbn_b1_8_115200 },
4454 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 pbn_b1_8_115200 },
Alan Cox55c7c0f2012-11-29 09:03:00 +10304457 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_b1_4_115200 },
4460 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_b1_2_115200 },
4463 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_b1_4_115200 },
4466 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_b1_2_115200 },
4469 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b2_4_115200 },
4472 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b2_2_115200 },
4475 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b2_1_115200 },
4478 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b2_4_115200 },
4481 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_b2_2_115200 },
4484 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_b2_1_115200 },
4487 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b0_8_115200 },
4490
Linus Torvalds1da177e2005-04-16 15:20:36 -07004491 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
Alan Cox5756ee92008-02-08 04:18:51 -08004492 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4493 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004494 pbn_b0_4_921600 },
4495 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Alan Cox5756ee92008-02-08 04:18:51 -08004496 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4497 0, 0,
Andrey Paninfbc0dc02005-07-18 11:38:09 +01004498 pbn_b0_4_1152000 },
Mikulas Patockac9bd9d02010-10-26 14:20:48 -04004499 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 pbn_b0_bt_2_921600 },
David Ransondb1de152005-07-27 11:43:55 -07004502
4503 /*
4504 * The below card is a little controversial since it is the
4505 * subject of a PCI vendor/device ID clash. (See
4506 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4507 * For now just used the hex ID 0x950a.
4508 */
4509 { PCI_VENDOR_ID_OXSEMI, 0x950a,
Flavio Leitner26e82202012-09-21 21:04:34 -03004510 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4511 0, 0, pbn_b0_2_115200 },
4512 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4513 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4514 0, 0, pbn_b0_2_115200 },
Niels de Vos39aced62009-01-02 13:46:58 +00004515 { PCI_VENDOR_ID_OXSEMI, 0x950a,
David Ransondb1de152005-07-27 11:43:55 -07004516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_b0_2_1130000 },
Andre Przywara70fd8fd2009-06-11 12:41:57 +01004518 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4519 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4520 pbn_b0_1_921600 },
Andrey Paninfbc0dc02005-07-18 11:38:09 +01004521 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_b0_4_115200 },
4524 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_b0_bt_2_921600 },
Lytochkin Borise8470032010-07-26 10:02:26 +04004527 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4528 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4529 pbn_b2_8_1152000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004530
4531 /*
Lee Howard7106b4e2008-10-21 13:48:58 +01004532 * Oxford Semiconductor Inc. Tornado PCI express device range.
4533 */
4534 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_b0_1_4000000 },
4537 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b0_1_4000000 },
4540 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_oxsemi_1_4000000 },
4543 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_oxsemi_1_4000000 },
4546 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b0_1_4000000 },
4549 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b0_1_4000000 },
4552 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_oxsemi_1_4000000 },
4555 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_oxsemi_1_4000000 },
4558 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b0_1_4000000 },
4561 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_b0_1_4000000 },
4564 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_b0_1_4000000 },
4567 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_b0_1_4000000 },
4570 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_oxsemi_2_4000000 },
4573 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_oxsemi_2_4000000 },
4576 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_oxsemi_4_4000000 },
4579 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_oxsemi_4_4000000 },
4582 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_oxsemi_8_4000000 },
4585 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_oxsemi_8_4000000 },
4588 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_oxsemi_1_4000000 },
4591 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_oxsemi_1_4000000 },
4594 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_oxsemi_1_4000000 },
4597 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_oxsemi_1_4000000 },
4600 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_oxsemi_1_4000000 },
4603 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_oxsemi_1_4000000 },
4606 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_oxsemi_1_4000000 },
4609 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_oxsemi_1_4000000 },
4612 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_oxsemi_1_4000000 },
4615 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_oxsemi_1_4000000 },
4618 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_oxsemi_1_4000000 },
4621 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_oxsemi_1_4000000 },
4624 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_oxsemi_1_4000000 },
4627 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_oxsemi_1_4000000 },
4630 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_oxsemi_1_4000000 },
4633 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_oxsemi_1_4000000 },
4636 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_oxsemi_1_4000000 },
4639 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_oxsemi_1_4000000 },
4642 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_oxsemi_1_4000000 },
4645 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_oxsemi_1_4000000 },
4648 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_oxsemi_1_4000000 },
4651 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_oxsemi_1_4000000 },
4654 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_oxsemi_1_4000000 },
4657 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_oxsemi_1_4000000 },
4660 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_oxsemi_1_4000000 },
4663 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_oxsemi_1_4000000 },
Lee Howardb80de362008-10-21 13:50:14 +01004666 /*
4667 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4668 */
4669 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4670 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4671 pbn_oxsemi_1_4000000 },
4672 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4673 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4674 pbn_oxsemi_2_4000000 },
4675 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4676 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4677 pbn_oxsemi_4_4000000 },
4678 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4679 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4680 pbn_oxsemi_8_4000000 },
Scott Kilauaa273ae2011-05-11 15:41:59 -05004681
4682 /*
4683 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4684 */
4685 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4686 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4687 pbn_oxsemi_2_4000000 },
4688
Lee Howard7106b4e2008-10-21 13:48:58 +01004689 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004690 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4691 * from skokodyn@yahoo.com
4692 */
4693 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4694 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4695 pbn_sbsxrsio },
4696 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4697 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4698 pbn_sbsxrsio },
4699 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4700 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4701 pbn_sbsxrsio },
4702 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4703 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4704 pbn_sbsxrsio },
4705
4706 /*
4707 * Digitan DS560-558, from jimd@esoft.com
4708 */
4709 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
Alan Cox5756ee92008-02-08 04:18:51 -08004710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004711 pbn_b1_1_115200 },
4712
4713 /*
4714 * Titan Electronic cards
4715 * The 400L and 800L have a custom setup quirk.
4716 */
4717 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
Alan Cox5756ee92008-02-08 04:18:51 -08004718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004719 pbn_b0_1_921600 },
4720 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
Alan Cox5756ee92008-02-08 04:18:51 -08004721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004722 pbn_b0_2_921600 },
4723 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
Alan Cox5756ee92008-02-08 04:18:51 -08004724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004725 pbn_b0_4_921600 },
4726 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
Alan Cox5756ee92008-02-08 04:18:51 -08004727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004728 pbn_b0_4_921600 },
4729 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_b1_1_921600 },
4732 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b1_bt_2_921600 },
4735 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_b0_bt_4_921600 },
4738 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_b0_bt_8_921600 },
Yegor Yefremov66169ad2010-06-04 09:58:18 +02004741 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_b4_bt_2_921600 },
4744 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_b4_bt_4_921600 },
4747 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_b4_bt_8_921600 },
4750 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_b0_4_921600 },
4753 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_b0_4_921600 },
4756 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_b0_4_921600 },
4759 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_oxsemi_1_4000000 },
4762 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_oxsemi_2_4000000 },
4765 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_oxsemi_4_4000000 },
4768 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_oxsemi_8_4000000 },
4771 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_oxsemi_2_4000000 },
4774 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_oxsemi_2_4000000 },
Yegor Yefremov48c02472013-12-09 12:11:15 +01004777 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b0_bt_2_921600 },
Yegor Yefremov1e9deb12011-12-27 15:47:37 +01004780 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_b0_4_921600 },
4783 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b0_4_921600 },
4786 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_4_921600 },
4789 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b0_4_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004792
4793 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_b2_1_460800 },
4796 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 pbn_b2_1_460800 },
4799 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 pbn_b2_1_460800 },
4802 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_b2_bt_2_921600 },
4805 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 pbn_b2_bt_2_921600 },
4808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_b2_bt_2_921600 },
4811 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 pbn_b2_bt_4_921600 },
4814 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816 pbn_b2_bt_4_921600 },
4817 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 pbn_b2_bt_4_921600 },
4820 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 pbn_b0_1_921600 },
4823 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 pbn_b0_1_921600 },
4826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 pbn_b0_1_921600 },
4829 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4831 pbn_b0_bt_2_921600 },
4832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834 pbn_b0_bt_2_921600 },
4835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 pbn_b0_bt_2_921600 },
4838 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 pbn_b0_bt_4_921600 },
4841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 pbn_b0_bt_4_921600 },
4844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 pbn_b0_bt_4_921600 },
Andrey Panin3ec9c592006-02-02 20:15:09 +00004847 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 pbn_b0_bt_8_921600 },
4850 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852 pbn_b0_bt_8_921600 },
4853 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855 pbn_b0_bt_8_921600 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004856
4857 /*
4858 * Computone devices submitted by Doug McNash dmcnash@computone.com
4859 */
4860 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4861 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4862 0, 0, pbn_computone_4 },
4863 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4864 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4865 0, 0, pbn_computone_8 },
4866 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4867 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4868 0, 0, pbn_computone_6 },
4869
4870 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_oxsemi },
4873 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4874 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4875 pbn_b0_bt_1_921600 },
4876
4877 /*
Stephen Chiversabd7bac2013-01-28 19:49:20 +11004878 * SUNIX (TIMEDIA)
4879 */
4880 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4881 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4882 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4883 pbn_b0_bt_1_921600 },
4884
4885 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4886 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4887 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4888 pbn_b0_bt_1_921600 },
4889
4890 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004891 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4892 */
4893 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_bt_8_115200 },
4896 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_bt_8_115200 },
4899
4900 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b0_bt_2_115200 },
4903 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_bt_2_115200 },
4906 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b0_bt_2_115200 },
Lennert Buytenhekb87e5e22009-11-11 14:26:42 -08004909 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b0_bt_2_115200 },
4912 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_b0_bt_2_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07004915 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_b0_bt_4_460800 },
4918 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_b0_bt_4_460800 },
4921 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b0_bt_2_460800 },
4924 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b0_bt_2_460800 },
4927 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_b0_bt_2_460800 },
4930 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_b0_bt_1_115200 },
4933 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_b0_bt_1_460800 },
4936
4937 /*
Russell King1fb8cac2006-12-13 14:45:46 +00004938 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4939 * Cards are identified by their subsystem vendor IDs, which
4940 * (in hex) match the model number.
4941 *
4942 * Note that JC140x are RS422/485 cards which require ox950
4943 * ACR = 0x10, and as such are not currently fully supported.
4944 */
4945 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4946 0x1204, 0x0004, 0, 0,
4947 pbn_b0_4_921600 },
4948 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4949 0x1208, 0x0004, 0, 0,
4950 pbn_b0_4_921600 },
4951/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4952 0x1402, 0x0002, 0, 0,
4953 pbn_b0_2_921600 }, */
4954/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4955 0x1404, 0x0004, 0, 0,
4956 pbn_b0_4_921600 }, */
4957 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4958 0x1208, 0x0004, 0, 0,
4959 pbn_b0_4_921600 },
4960
Kiros Yeh2a52fcb2009-12-21 16:26:48 -08004961 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4962 0x1204, 0x0004, 0, 0,
4963 pbn_b0_4_921600 },
4964 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4965 0x1208, 0x0004, 0, 0,
4966 pbn_b0_4_921600 },
4967 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4968 0x1208, 0x0004, 0, 0,
4969 pbn_b0_4_921600 },
Russell King1fb8cac2006-12-13 14:45:46 +00004970 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004971 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4972 */
4973 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_b1_1_1382400 },
4976
4977 /*
4978 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4979 */
4980 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982 pbn_b1_1_1382400 },
4983
4984 /*
4985 * RAStel 2 port modem, gerg@moreton.com.au
4986 */
4987 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b2_bt_2_115200 },
4990
4991 /*
4992 * EKF addition for i960 Boards form EKF with serial port
4993 */
4994 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4995 0xE4BF, PCI_ANY_ID, 0, 0,
4996 pbn_intel_i960 },
4997
4998 /*
4999 * Xircom Cardbus/Ethernet combos
5000 */
5001 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003 pbn_b0_1_115200 },
5004 /*
5005 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5006 */
5007 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5009 pbn_b0_1_115200 },
5010
5011 /*
5012 * Untested PCI modems, sent in from various folks...
5013 */
5014
5015 /*
5016 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5017 */
5018 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5019 0x1048, 0x1500, 0, 0,
5020 pbn_b1_1_115200 },
5021
5022 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5023 0xFF00, 0, 0, 0,
5024 pbn_sgi_ioc3 },
5025
5026 /*
5027 * HP Diva card
5028 */
5029 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5030 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5031 pbn_b1_1_115200 },
5032 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5034 pbn_b0_5_115200 },
5035 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5037 pbn_b2_1_115200 },
5038
Alon Bar-Levd9004eb2006-01-18 11:47:33 +00005039 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 pbn_b3_2_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07005042 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044 pbn_b3_4_115200 },
5045 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047 pbn_b3_8_115200 },
5048
5049 /*
5050 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5051 */
5052 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5053 PCI_ANY_ID, PCI_ANY_ID,
5054 0,
5055 0, pbn_exar_XR17C152 },
5056 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5057 PCI_ANY_ID, PCI_ANY_ID,
5058 0,
5059 0, pbn_exar_XR17C154 },
5060 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5061 PCI_ANY_ID, PCI_ANY_ID,
5062 0,
5063 0, pbn_exar_XR17C158 },
Matt Schultedc96efb2012-11-19 09:12:04 -06005064 /*
5065 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
5066 */
5067 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5068 PCI_ANY_ID, PCI_ANY_ID,
5069 0,
5070 0, pbn_exar_XR17V352 },
5071 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5072 PCI_ANY_ID, PCI_ANY_ID,
5073 0,
5074 0, pbn_exar_XR17V354 },
5075 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5076 PCI_ANY_ID, PCI_ANY_ID,
5077 0,
5078 0, pbn_exar_XR17V358 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07005079
5080 /*
5081 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5082 */
5083 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 pbn_b0_1_115200 },
Niels de Vos84f8c6f2007-08-22 14:01:14 -07005086 /*
5087 * ITE
5088 */
5089 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5090 PCI_ANY_ID, PCI_ANY_ID,
5091 0, 0,
5092 pbn_b1_bt_1_115200 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07005093
5094 /*
Peter Horton737c1752006-08-26 09:07:36 +01005095 * IntaShield IS-200
5096 */
5097 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5099 pbn_b2_2_115200 },
Ignacio García Pérez4b6f6ce2008-05-23 13:04:28 -07005100 /*
5101 * IntaShield IS-400
5102 */
5103 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5105 pbn_b2_4_115200 },
Peter Horton737c1752006-08-26 09:07:36 +01005106 /*
Thomas Hoehn48212002007-02-10 01:46:05 -08005107 * Perle PCI-RAS cards
5108 */
5109 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5110 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5111 0, 0, pbn_b2_4_921600 },
5112 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5113 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5114 0, 0, pbn_b2_8_921600 },
Alan Coxbf0df632007-10-16 01:24:00 -07005115
5116 /*
5117 * Mainpine series cards: Fairly standard layout but fools
5118 * parts of the autodetect in some cases and uses otherwise
5119 * unmatched communications subclasses in the PCI Express case
5120 */
5121
5122 { /* RockForceDUO */
5123 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5124 PCI_VENDOR_ID_MAINPINE, 0x0200,
5125 0, 0, pbn_b0_2_115200 },
5126 { /* RockForceQUATRO */
5127 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5128 PCI_VENDOR_ID_MAINPINE, 0x0300,
5129 0, 0, pbn_b0_4_115200 },
5130 { /* RockForceDUO+ */
5131 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5132 PCI_VENDOR_ID_MAINPINE, 0x0400,
5133 0, 0, pbn_b0_2_115200 },
5134 { /* RockForceQUATRO+ */
5135 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5136 PCI_VENDOR_ID_MAINPINE, 0x0500,
5137 0, 0, pbn_b0_4_115200 },
5138 { /* RockForce+ */
5139 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5140 PCI_VENDOR_ID_MAINPINE, 0x0600,
5141 0, 0, pbn_b0_2_115200 },
5142 { /* RockForce+ */
5143 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5144 PCI_VENDOR_ID_MAINPINE, 0x0700,
5145 0, 0, pbn_b0_4_115200 },
5146 { /* RockForceOCTO+ */
5147 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5148 PCI_VENDOR_ID_MAINPINE, 0x0800,
5149 0, 0, pbn_b0_8_115200 },
5150 { /* RockForceDUO+ */
5151 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5152 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5153 0, 0, pbn_b0_2_115200 },
5154 { /* RockForceQUARTRO+ */
5155 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5156 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5157 0, 0, pbn_b0_4_115200 },
5158 { /* RockForceOCTO+ */
5159 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5160 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5161 0, 0, pbn_b0_8_115200 },
5162 { /* RockForceD1 */
5163 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5164 PCI_VENDOR_ID_MAINPINE, 0x2000,
5165 0, 0, pbn_b0_1_115200 },
5166 { /* RockForceF1 */
5167 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5168 PCI_VENDOR_ID_MAINPINE, 0x2100,
5169 0, 0, pbn_b0_1_115200 },
5170 { /* RockForceD2 */
5171 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5172 PCI_VENDOR_ID_MAINPINE, 0x2200,
5173 0, 0, pbn_b0_2_115200 },
5174 { /* RockForceF2 */
5175 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5176 PCI_VENDOR_ID_MAINPINE, 0x2300,
5177 0, 0, pbn_b0_2_115200 },
5178 { /* RockForceD4 */
5179 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5180 PCI_VENDOR_ID_MAINPINE, 0x2400,
5181 0, 0, pbn_b0_4_115200 },
5182 { /* RockForceF4 */
5183 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5184 PCI_VENDOR_ID_MAINPINE, 0x2500,
5185 0, 0, pbn_b0_4_115200 },
5186 { /* RockForceD8 */
5187 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5188 PCI_VENDOR_ID_MAINPINE, 0x2600,
5189 0, 0, pbn_b0_8_115200 },
5190 { /* RockForceF8 */
5191 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5192 PCI_VENDOR_ID_MAINPINE, 0x2700,
5193 0, 0, pbn_b0_8_115200 },
5194 { /* IQ Express D1 */
5195 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5196 PCI_VENDOR_ID_MAINPINE, 0x3000,
5197 0, 0, pbn_b0_1_115200 },
5198 { /* IQ Express F1 */
5199 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5200 PCI_VENDOR_ID_MAINPINE, 0x3100,
5201 0, 0, pbn_b0_1_115200 },
5202 { /* IQ Express D2 */
5203 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5204 PCI_VENDOR_ID_MAINPINE, 0x3200,
5205 0, 0, pbn_b0_2_115200 },
5206 { /* IQ Express F2 */
5207 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5208 PCI_VENDOR_ID_MAINPINE, 0x3300,
5209 0, 0, pbn_b0_2_115200 },
5210 { /* IQ Express D4 */
5211 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5212 PCI_VENDOR_ID_MAINPINE, 0x3400,
5213 0, 0, pbn_b0_4_115200 },
5214 { /* IQ Express F4 */
5215 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5216 PCI_VENDOR_ID_MAINPINE, 0x3500,
5217 0, 0, pbn_b0_4_115200 },
5218 { /* IQ Express D8 */
5219 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5220 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5221 0, 0, pbn_b0_8_115200 },
5222 { /* IQ Express F8 */
5223 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5224 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5225 0, 0, pbn_b0_8_115200 },
5226
5227
Thomas Hoehn48212002007-02-10 01:46:05 -08005228 /*
Olof Johanssonaa798502007-08-22 14:01:55 -07005229 * PA Semi PA6T-1682M on-chip UART
5230 */
5231 { PCI_VENDOR_ID_PASEMI, 0xa004,
5232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5233 pbn_pasemi_1682M },
5234
5235 /*
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01005236 * National Instruments
5237 */
Will Page04bf7e72009-04-06 17:32:15 +01005238 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5240 pbn_b1_16_115200 },
5241 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5243 pbn_b1_8_115200 },
5244 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5246 pbn_b1_bt_4_115200 },
5247 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5249 pbn_b1_bt_2_115200 },
5250 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5252 pbn_b1_bt_4_115200 },
5253 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255 pbn_b1_bt_2_115200 },
5256 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258 pbn_b1_16_115200 },
5259 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261 pbn_b1_8_115200 },
5262 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264 pbn_b1_bt_4_115200 },
5265 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267 pbn_b1_bt_2_115200 },
5268 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270 pbn_b1_bt_4_115200 },
5271 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273 pbn_b1_bt_2_115200 },
Shawn Bohrer46a0fac2009-04-06 17:32:07 +01005274 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276 pbn_ni8430_2 },
5277 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279 pbn_ni8430_2 },
5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282 pbn_ni8430_4 },
5283 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285 pbn_ni8430_4 },
5286 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288 pbn_ni8430_8 },
5289 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291 pbn_ni8430_8 },
5292 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294 pbn_ni8430_16 },
5295 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297 pbn_ni8430_16 },
5298 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300 pbn_ni8430_2 },
5301 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303 pbn_ni8430_2 },
5304 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306 pbn_ni8430_4 },
5307 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309 pbn_ni8430_4 },
5310
5311 /*
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08005312 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5313 */
5314 { PCI_VENDOR_ID_ADDIDATA,
5315 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5316 PCI_ANY_ID,
5317 PCI_ANY_ID,
5318 0,
5319 0,
5320 pbn_b0_4_115200 },
5321
5322 { PCI_VENDOR_ID_ADDIDATA,
5323 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5324 PCI_ANY_ID,
5325 PCI_ANY_ID,
5326 0,
5327 0,
5328 pbn_b0_2_115200 },
5329
5330 { PCI_VENDOR_ID_ADDIDATA,
5331 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5332 PCI_ANY_ID,
5333 PCI_ANY_ID,
5334 0,
5335 0,
5336 pbn_b0_1_115200 },
5337
Ian Abbott086231f2013-07-16 16:14:39 +01005338 { PCI_VENDOR_ID_AMCC,
Ian Abbott57c1f0e2013-07-16 16:14:40 +01005339 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08005340 PCI_ANY_ID,
5341 PCI_ANY_ID,
5342 0,
5343 0,
5344 pbn_b1_8_115200 },
5345
5346 { PCI_VENDOR_ID_ADDIDATA,
5347 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5348 PCI_ANY_ID,
5349 PCI_ANY_ID,
5350 0,
5351 0,
5352 pbn_b0_4_115200 },
5353
5354 { PCI_VENDOR_ID_ADDIDATA,
5355 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5356 PCI_ANY_ID,
5357 PCI_ANY_ID,
5358 0,
5359 0,
5360 pbn_b0_2_115200 },
5361
5362 { PCI_VENDOR_ID_ADDIDATA,
5363 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5364 PCI_ANY_ID,
5365 PCI_ANY_ID,
5366 0,
5367 0,
5368 pbn_b0_1_115200 },
5369
5370 { PCI_VENDOR_ID_ADDIDATA,
5371 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5372 PCI_ANY_ID,
5373 PCI_ANY_ID,
5374 0,
5375 0,
5376 pbn_b0_4_115200 },
5377
5378 { PCI_VENDOR_ID_ADDIDATA,
5379 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5380 PCI_ANY_ID,
5381 PCI_ANY_ID,
5382 0,
5383 0,
5384 pbn_b0_2_115200 },
5385
5386 { PCI_VENDOR_ID_ADDIDATA,
5387 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5388 PCI_ANY_ID,
5389 PCI_ANY_ID,
5390 0,
5391 0,
5392 pbn_b0_1_115200 },
5393
5394 { PCI_VENDOR_ID_ADDIDATA,
5395 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5396 PCI_ANY_ID,
5397 PCI_ANY_ID,
5398 0,
5399 0,
5400 pbn_b0_8_115200 },
5401
Krauth.Julien1b62cbf2009-10-26 16:50:04 -07005402 { PCI_VENDOR_ID_ADDIDATA,
5403 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5404 PCI_ANY_ID,
5405 PCI_ANY_ID,
5406 0,
5407 0,
5408 pbn_ADDIDATA_PCIe_4_3906250 },
5409
5410 { PCI_VENDOR_ID_ADDIDATA,
5411 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5412 PCI_ANY_ID,
5413 PCI_ANY_ID,
5414 0,
5415 0,
5416 pbn_ADDIDATA_PCIe_2_3906250 },
5417
5418 { PCI_VENDOR_ID_ADDIDATA,
5419 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5420 PCI_ANY_ID,
5421 PCI_ANY_ID,
5422 0,
5423 0,
5424 pbn_ADDIDATA_PCIe_1_3906250 },
5425
5426 { PCI_VENDOR_ID_ADDIDATA,
5427 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5428 PCI_ANY_ID,
5429 PCI_ANY_ID,
5430 0,
5431 0,
5432 pbn_ADDIDATA_PCIe_8_3906250 },
5433
Jiri Slaby25cf9bc2009-01-15 13:30:34 +00005434 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5435 PCI_VENDOR_ID_IBM, 0x0299,
5436 0, 0, pbn_b0_bt_2_115200 },
5437
Stefan Seyfried972ce082013-07-01 09:14:21 +02005438 /*
5439 * other NetMos 9835 devices are most likely handled by the
5440 * parport_serial driver, check drivers/parport/parport_serial.c
5441 * before adding them here.
5442 */
5443
Michael Bueschc4285b42009-06-30 11:41:21 -07005444 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5445 0xA000, 0x1000,
5446 0, 0, pbn_b0_1_115200 },
5447
Nicos Gollan7808edc2011-05-05 21:00:37 +02005448 /* the 9901 is a rebranded 9912 */
5449 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5450 0xA000, 0x1000,
5451 0, 0, pbn_b0_1_115200 },
5452
5453 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5454 0xA000, 0x1000,
5455 0, 0, pbn_b0_1_115200 },
5456
5457 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5458 0xA000, 0x1000,
5459 0, 0, pbn_b0_1_115200 },
5460
5461 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5462 0xA000, 0x1000,
5463 0, 0, pbn_b0_1_115200 },
5464
5465 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5466 0xA000, 0x3002,
5467 0, 0, pbn_NETMOS9900_2s_115200 },
5468
Krauth.Julien02c9b5c2008-02-04 22:27:49 -08005469 /*
Eric Smith44178172011-07-11 22:53:13 -06005470 * Best Connectivity and Rosewill PCI Multi I/O cards
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08005471 */
5472
5473 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5474 0xA000, 0x1000,
5475 0, 0, pbn_b0_1_115200 },
5476
5477 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
Eric Smith44178172011-07-11 22:53:13 -06005478 0xA000, 0x3002,
5479 0, 0, pbn_b0_bt_2_115200 },
5480
5481 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08005482 0xA000, 0x3004,
5483 0, 0, pbn_b0_bt_4_115200 },
Dirk Brandewie095e24b2010-11-17 07:35:20 -08005484 /* Intel CE4100 */
5485 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5487 pbn_ce4100_1_115200 },
Heikki Krogerusb15e5692013-09-27 10:52:59 +03005488 /* Intel BayTrail */
5489 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5490 PCI_ANY_ID, PCI_ANY_ID,
5491 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5492 pbn_byt },
5493 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5494 PCI_ANY_ID, PCI_ANY_ID,
5495 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5496 pbn_byt },
Alan Cox29897082014-08-19 20:29:23 +03005497 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5498 PCI_ANY_ID, PCI_ANY_ID,
5499 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5500 pbn_byt },
5501 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5502 PCI_ANY_ID, PCI_ANY_ID,
5503 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5504 pbn_byt },
Dirk Brandewie095e24b2010-11-17 07:35:20 -08005505
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04005506 /*
Andy Shevchenkof549e942015-02-23 16:24:43 +02005507 * Intel Penwell
5508 */
5509 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5511 pbn_pnw},
5512 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5514 pbn_pnw},
5515 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5517 pbn_pnw},
5518
5519 /*
Bryan O'Donoghue1ede7dc2014-09-23 01:21:11 +01005520 * Intel Quark x1000
5521 */
5522 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5524 pbn_qrk },
5525 /*
Antony Pavlovd9a0fbf2011-05-18 22:38:30 +04005526 * Cronyx Omega PCI
5527 */
5528 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5530 pbn_omegapci },
Ira W. Snyderac6ec5b2009-12-21 16:26:45 -08005531
5532 /*
Stephen Hurdebebd492013-01-17 14:14:53 -08005533 * Broadcom TruManage
5534 */
5535 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5537 pbn_brcm_trumanage },
5538
5539 /*
Alan Cox66835492012-08-16 12:01:33 +01005540 * AgeStar as-prs2-009
5541 */
5542 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5543 PCI_ANY_ID, PCI_ANY_ID,
5544 0, 0, pbn_b0_bt_2_115200 },
Alan Cox27788c52012-09-04 16:21:06 +01005545
5546 /*
5547 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5548 * so not listed here.
5549 */
5550 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5551 PCI_ANY_ID, PCI_ANY_ID,
5552 0, 0, pbn_b0_bt_4_115200 },
5553
5554 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5555 PCI_ANY_ID, PCI_ANY_ID,
5556 0, 0, pbn_b0_bt_2_115200 },
5557
Sergej Pupykin72a3c0e2014-12-30 16:16:50 +03005558 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5559 PCI_ANY_ID, PCI_ANY_ID,
5560 0, 0, pbn_wch384_4 },
5561
Alan Cox66835492012-08-16 12:01:33 +01005562 /*
Matt Schulte14faa8c2012-11-21 10:35:15 -06005563 * Commtech, Inc. Fastcom adapters
5564 */
5565 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5566 PCI_ANY_ID, PCI_ANY_ID,
5567 0,
5568 0, pbn_b0_2_1152000_200 },
5569 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5570 PCI_ANY_ID, PCI_ANY_ID,
5571 0,
5572 0, pbn_b0_4_1152000_200 },
5573 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5574 PCI_ANY_ID, PCI_ANY_ID,
5575 0,
5576 0, pbn_b0_4_1152000_200 },
5577 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5578 PCI_ANY_ID, PCI_ANY_ID,
5579 0,
5580 0, pbn_b0_8_1152000_200 },
5581 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5582 PCI_ANY_ID, PCI_ANY_ID,
5583 0,
5584 0, pbn_exar_XR17V352 },
5585 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5586 PCI_ANY_ID, PCI_ANY_ID,
5587 0,
5588 0, pbn_exar_XR17V354 },
5589 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5590 PCI_ANY_ID, PCI_ANY_ID,
5591 0,
5592 0, pbn_exar_XR17V358 },
5593
Greg Kroah-Hartman2c62a3c2013-10-17 10:44:26 -07005594 /* Fintek PCI serial cards */
5595 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5596 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5597 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5598
Matt Schulte14faa8c2012-11-21 10:35:15 -06005599 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07005600 * These entries match devices with class COMMUNICATION_SERIAL,
5601 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5602 */
5603 { PCI_ANY_ID, PCI_ANY_ID,
5604 PCI_ANY_ID, PCI_ANY_ID,
5605 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5606 0xffff00, pbn_default },
5607 { PCI_ANY_ID, PCI_ANY_ID,
5608 PCI_ANY_ID, PCI_ANY_ID,
5609 PCI_CLASS_COMMUNICATION_MODEM << 8,
5610 0xffff00, pbn_default },
5611 { PCI_ANY_ID, PCI_ANY_ID,
5612 PCI_ANY_ID, PCI_ANY_ID,
5613 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5614 0xffff00, pbn_default },
5615 { 0, }
5616};
5617
Michael Reed28071902011-05-31 12:06:28 -05005618static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5619 pci_channel_state_t state)
5620{
5621 struct serial_private *priv = pci_get_drvdata(dev);
5622
5623 if (state == pci_channel_io_perm_failure)
5624 return PCI_ERS_RESULT_DISCONNECT;
5625
5626 if (priv)
5627 pciserial_suspend_ports(priv);
5628
5629 pci_disable_device(dev);
5630
5631 return PCI_ERS_RESULT_NEED_RESET;
5632}
5633
5634static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5635{
5636 int rc;
5637
5638 rc = pci_enable_device(dev);
5639
5640 if (rc)
5641 return PCI_ERS_RESULT_DISCONNECT;
5642
5643 pci_restore_state(dev);
5644 pci_save_state(dev);
5645
5646 return PCI_ERS_RESULT_RECOVERED;
5647}
5648
5649static void serial8250_io_resume(struct pci_dev *dev)
5650{
5651 struct serial_private *priv = pci_get_drvdata(dev);
5652
5653 if (priv)
5654 pciserial_resume_ports(priv);
5655}
5656
Stephen Hemminger1d352032012-09-07 09:33:17 -07005657static const struct pci_error_handlers serial8250_err_handler = {
Michael Reed28071902011-05-31 12:06:28 -05005658 .error_detected = serial8250_io_error_detected,
5659 .slot_reset = serial8250_io_slot_reset,
5660 .resume = serial8250_io_resume,
5661};
5662
Linus Torvalds1da177e2005-04-16 15:20:36 -07005663static struct pci_driver serial_pci_driver = {
5664 .name = "serial",
5665 .probe = pciserial_init_one,
Bill Pemberton2d47b712012-11-19 13:21:34 -05005666 .remove = pciserial_remove_one,
Andy Shevchenko61702c32015-02-02 14:53:26 +02005667 .driver = {
5668 .pm = &pciserial_pm_ops,
5669 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07005670 .id_table = serial_pci_tbl,
Michael Reed28071902011-05-31 12:06:28 -05005671 .err_handler = &serial8250_err_handler,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005672};
5673
Wei Yongjun15a12e82012-10-26 23:04:22 +08005674module_pci_driver(serial_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005675
5676MODULE_LICENSE("GPL");
5677MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5678MODULE_DEVICE_TABLE(pci, serial_pci_tbl);