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gerrit-public.fairphone.software / kernel / msm-5.4 / ca2c68cc7bc80fc4504fb420df04cce99c9ee6ec / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: d7a5ca7225485dd91fbc0cea30362db572de866a [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
Sujith Manoharan5b681382011-05-17 13:36:18 +0530[diff] [blame]2 * Copyright (c) 2010-2011 Atheros Communications Inc.
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]17#include <asm/unaligned.h>
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]18#include "hw.h"
19#include "ar9003_phy.h"
20#include "ar9003_eeprom.h"
21
22#define COMP_HDR_LEN 4
23#define COMP_CKSUM_LEN 2
24
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]25#define LE16(x) __constant_cpu_to_le16(x)
26#define LE32(x) __constant_cpu_to_le32(x)
27
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]28/* Local defines to distinguish between extension and control CTL's */
29#define EXT_ADDITIVE (0x8000)
30#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
33#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
34#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
35#define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
36#define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
37#define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
38
39#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
40#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
41
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]42#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
43
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]44#define EEPROM_DATA_LEN_9485 1088
45
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]46static int ar9003_hw_power_interpolate(int32_t x,
47 int32_t *px, int32_t *py, u_int16_t np);
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]48
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]49
50static const struct ar9300_eeprom ar9300_default = {
51 .eepromVersion = 2,
52 .templateVersion = 2,
Senthil Balasubramanianb503c7a2011-08-19 18:43:06 +0530[diff] [blame]53 .macAddr = {0, 2, 3, 4, 5, 6},
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]54 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
55 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
56 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]57 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]58 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
59 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]60 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]61 .eepMisc = 0,
62 },
63 .rfSilent = 0,
64 .blueToothOptions = 0,
65 .deviceCap = 0,
66 .deviceType = 5, /* takes lower byte in eeprom location */
67 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
68 .params_for_tuning_caps = {0, 0},
69 .featureEnable = 0x0c,
70 /*
71 * bit0 - enable tx temp comp - disabled
72 * bit1 - enable tx volt comp - disabled
73 * bit2 - enable fastClock - enabled
74 * bit3 - enable doubling - enabled
75 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]76 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]77 */
78 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
79 .eepromWriteEnableGpio = 3,
80 .wlanDisableGpio = 0,
81 .wlanLedGpio = 8,
82 .rxBandSelectGpio = 0xff,
83 .txrxgain = 0,
84 .swreg = 0,
85 },
86 .modalHeader2G = {
87 /* ar9300_modal_eep_header 2g */
88 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]89 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]90 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]91 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]92
93 /*
94 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
95 * rx1, rx12, b (2 bits each)
96 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]97 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]98
99 /*
100 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
101 * for ar9280 (0xa20c/b20c 5:0)
102 */
103 .xatten1DB = {0, 0, 0},
104
105 /*
106 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
107 * for ar9280 (0xa20c/b20c 16:12
108 */
109 .xatten1Margin = {0, 0, 0},
110 .tempSlope = 36,
111 .voltSlope = 0,
112
113 /*
114 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
115 * channels in usual fbin coding format
116 */
117 .spurChans = {0, 0, 0, 0, 0},
118
119 /*
120 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
121 * if the register is per chain
122 */
123 .noiseFloorThreshCh = {-1, 0, 0},
124 .ob = {1, 1, 1},/* 3 chain */
125 .db_stage2 = {1, 1, 1}, /* 3 chain */
126 .db_stage3 = {0, 0, 0},
127 .db_stage4 = {0, 0, 0},
128 .xpaBiasLvl = 0,
129 .txFrameToDataStart = 0x0e,
130 .txFrameToPaOn = 0x0e,
131 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
132 .antennaGain = 0,
133 .switchSettling = 0x2c,
134 .adcDesiredSize = -30,
135 .txEndToXpaOff = 0,
136 .txEndToRxOn = 0x2,
137 .txFrameToXpaOn = 0xe,
138 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]139 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
140 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]141 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]142 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]143 },
144 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]145 .base_ext1 = {
146 .ant_div_control = 0,
147 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
148 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]149 .calFreqPier2G = {
150 FREQ2FBIN(2412, 1),
151 FREQ2FBIN(2437, 1),
152 FREQ2FBIN(2472, 1),
153 },
154 /* ar9300_cal_data_per_freq_op_loop 2g */
155 .calPierData2G = {
156 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
157 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
158 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
159 },
160 .calTarget_freqbin_Cck = {
161 FREQ2FBIN(2412, 1),
162 FREQ2FBIN(2484, 1),
163 },
164 .calTarget_freqbin_2G = {
165 FREQ2FBIN(2412, 1),
166 FREQ2FBIN(2437, 1),
167 FREQ2FBIN(2472, 1)
168 },
169 .calTarget_freqbin_2GHT20 = {
170 FREQ2FBIN(2412, 1),
171 FREQ2FBIN(2437, 1),
172 FREQ2FBIN(2472, 1)
173 },
174 .calTarget_freqbin_2GHT40 = {
175 FREQ2FBIN(2412, 1),
176 FREQ2FBIN(2437, 1),
177 FREQ2FBIN(2472, 1)
178 },
179 .calTargetPowerCck = {
180 /* 1L-5L,5S,11L,11S */
181 { {36, 36, 36, 36} },
182 { {36, 36, 36, 36} },
183 },
184 .calTargetPower2G = {
185 /* 6-24,36,48,54 */
186 { {32, 32, 28, 24} },
187 { {32, 32, 28, 24} },
188 { {32, 32, 28, 24} },
189 },
190 .calTargetPower2GHT20 = {
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
192 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
193 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
194 },
195 .calTargetPower2GHT40 = {
196 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
197 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
198 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
199 },
200 .ctlIndex_2G = {
201 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
202 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
203 },
204 .ctl_freqbin_2G = {
205 {
206 FREQ2FBIN(2412, 1),
207 FREQ2FBIN(2417, 1),
208 FREQ2FBIN(2457, 1),
209 FREQ2FBIN(2462, 1)
210 },
211 {
212 FREQ2FBIN(2412, 1),
213 FREQ2FBIN(2417, 1),
214 FREQ2FBIN(2462, 1),
215 0xFF,
216 },
217
218 {
219 FREQ2FBIN(2412, 1),
220 FREQ2FBIN(2417, 1),
221 FREQ2FBIN(2462, 1),
222 0xFF,
223 },
224 {
225 FREQ2FBIN(2422, 1),
226 FREQ2FBIN(2427, 1),
227 FREQ2FBIN(2447, 1),
228 FREQ2FBIN(2452, 1)
229 },
230
231 {
232 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
233 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
234 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
235 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
236 },
237
238 {
239 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
240 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
241 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
242 0,
243 },
244
245 {
246 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
247 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
248 FREQ2FBIN(2472, 1),
249 0,
250 },
251
252 {
253 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
254 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
255 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
256 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
257 },
258
259 {
260 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
261 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
262 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
263 },
264
265 {
266 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
267 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
268 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
269 0
270 },
271
272 {
273 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
274 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
275 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
276 0
277 },
278
279 {
280 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
281 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
282 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]283 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]284 }
285 },
286 .ctlPowerData_2G = {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]287 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
288 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
289 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]290
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]291 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]294
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]295 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
296 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
297 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]298
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]299 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
300 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
301 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]302 },
303 .modalHeader5G = {
304 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]305 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]306 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]307 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]308 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
309 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]310 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]311 },
312 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
313 .xatten1DB = {0, 0, 0},
314
315 /*
316 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
317 * for merlin (0xa20c/b20c 16:12
318 */
319 .xatten1Margin = {0, 0, 0},
320 .tempSlope = 68,
321 .voltSlope = 0,
322 /* spurChans spur channels in usual fbin coding format */
323 .spurChans = {0, 0, 0, 0, 0},
324 /* noiseFloorThreshCh Check if the register is per chain */
325 .noiseFloorThreshCh = {-1, 0, 0},
326 .ob = {3, 3, 3}, /* 3 chain */
327 .db_stage2 = {3, 3, 3}, /* 3 chain */
328 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
329 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
330 .xpaBiasLvl = 0,
331 .txFrameToDataStart = 0x0e,
332 .txFrameToPaOn = 0x0e,
333 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
334 .antennaGain = 0,
335 .switchSettling = 0x2d,
336 .adcDesiredSize = -30,
337 .txEndToXpaOff = 0,
338 .txEndToRxOn = 0x2,
339 .txFrameToXpaOn = 0xe,
340 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]341 .papdRateMaskHt20 = LE32(0x0c80c080),
342 .papdRateMaskHt40 = LE32(0x0080c080),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]343 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]344 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]345 },
346 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]347 .base_ext2 = {
348 .tempSlopeLow = 0,
349 .tempSlopeHigh = 0,
350 .xatten1DBLow = {0, 0, 0},
351 .xatten1MarginLow = {0, 0, 0},
352 .xatten1DBHigh = {0, 0, 0},
353 .xatten1MarginHigh = {0, 0, 0}
354 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]355 .calFreqPier5G = {
356 FREQ2FBIN(5180, 0),
357 FREQ2FBIN(5220, 0),
358 FREQ2FBIN(5320, 0),
359 FREQ2FBIN(5400, 0),
360 FREQ2FBIN(5500, 0),
361 FREQ2FBIN(5600, 0),
362 FREQ2FBIN(5725, 0),
363 FREQ2FBIN(5825, 0)
364 },
365 .calPierData5G = {
366 {
367 {0, 0, 0, 0, 0},
368 {0, 0, 0, 0, 0},
369 {0, 0, 0, 0, 0},
370 {0, 0, 0, 0, 0},
371 {0, 0, 0, 0, 0},
372 {0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 0},
374 {0, 0, 0, 0, 0},
375 },
376 {
377 {0, 0, 0, 0, 0},
378 {0, 0, 0, 0, 0},
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 },
386 {
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 {0, 0, 0, 0, 0},
392 {0, 0, 0, 0, 0},
393 {0, 0, 0, 0, 0},
394 {0, 0, 0, 0, 0},
395 },
396
397 },
398 .calTarget_freqbin_5G = {
399 FREQ2FBIN(5180, 0),
400 FREQ2FBIN(5220, 0),
401 FREQ2FBIN(5320, 0),
402 FREQ2FBIN(5400, 0),
403 FREQ2FBIN(5500, 0),
404 FREQ2FBIN(5600, 0),
405 FREQ2FBIN(5725, 0),
406 FREQ2FBIN(5825, 0)
407 },
408 .calTarget_freqbin_5GHT20 = {
409 FREQ2FBIN(5180, 0),
410 FREQ2FBIN(5240, 0),
411 FREQ2FBIN(5320, 0),
412 FREQ2FBIN(5500, 0),
413 FREQ2FBIN(5700, 0),
414 FREQ2FBIN(5745, 0),
415 FREQ2FBIN(5725, 0),
416 FREQ2FBIN(5825, 0)
417 },
418 .calTarget_freqbin_5GHT40 = {
419 FREQ2FBIN(5180, 0),
420 FREQ2FBIN(5240, 0),
421 FREQ2FBIN(5320, 0),
422 FREQ2FBIN(5500, 0),
423 FREQ2FBIN(5700, 0),
424 FREQ2FBIN(5745, 0),
425 FREQ2FBIN(5725, 0),
426 FREQ2FBIN(5825, 0)
427 },
428 .calTargetPower5G = {
429 /* 6-24,36,48,54 */
430 { {20, 20, 20, 10} },
431 { {20, 20, 20, 10} },
432 { {20, 20, 20, 10} },
433 { {20, 20, 20, 10} },
434 { {20, 20, 20, 10} },
435 { {20, 20, 20, 10} },
436 { {20, 20, 20, 10} },
437 { {20, 20, 20, 10} },
438 },
439 .calTargetPower5GHT20 = {
440 /*
441 * 0_8_16,1-3_9-11_17-19,
442 * 4,5,6,7,12,13,14,15,20,21,22,23
443 */
444 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
445 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
446 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
447 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
448 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
452 },
453 .calTargetPower5GHT40 = {
454 /*
455 * 0_8_16,1-3_9-11_17-19,
456 * 4,5,6,7,12,13,14,15,20,21,22,23
457 */
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
466 },
467 .ctlIndex_5G = {
468 0x10, 0x16, 0x18, 0x40, 0x46,
469 0x48, 0x30, 0x36, 0x38
470 },
471 .ctl_freqbin_5G = {
472 {
473 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
474 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
475 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
476 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
477 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
478 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
479 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
480 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
481 },
482 {
483 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
484 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
485 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
486 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
487 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
488 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
489 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
490 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
491 },
492
493 {
494 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
495 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
496 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
497 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
498 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
499 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
500 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
501 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
502 },
503
504 {
505 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
506 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
507 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
508 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
509 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
510 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
511 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
512 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
513 },
514
515 {
516 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
517 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
518 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
519 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
520 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
521 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
522 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
523 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
524 },
525
526 {
527 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
528 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
529 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
530 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
531 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
532 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
533 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
534 /* Data[5].ctlEdges[7].bChannel */ 0xFF
535 },
536
537 {
538 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
539 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
540 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
541 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
542 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
543 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
544 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
545 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
546 },
547
548 {
549 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
550 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
551 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
552 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
553 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
554 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
555 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
556 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
557 },
558
559 {
560 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
561 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
562 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
563 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
564 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
565 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
566 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
567 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
568 }
569 },
570 .ctlPowerData_5G = {
571 {
572 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]573 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
574 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]575 }
576 },
577 {
578 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]579 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
580 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]581 }
582 },
583 {
584 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]585 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
586 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]587 }
588 },
589 {
590 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]591 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
592 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]593 }
594 },
595 {
596 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
598 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]599 }
600 },
601 {
602 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]603 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
604 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]605 }
606 },
607 {
608 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]609 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
610 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]611 }
612 },
613 {
614 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]615 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
616 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]617 }
618 },
619 {
620 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]621 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
622 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]623 }
624 },
625 }
626};
627
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]628static const struct ar9300_eeprom ar9300_x113 = {
629 .eepromVersion = 2,
630 .templateVersion = 6,
631 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
632 .custData = {"x113-023-f0000"},
633 .baseEepHeader = {
634 .regDmn = { LE16(0), LE16(0x1f) },
635 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
636 .opCapFlags = {
Luis R. Rodriguez9ba7f4f2011-05-11 14:57:26 -0700[diff] [blame]637 .opFlags = AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]638 .eepMisc = 0,
639 },
640 .rfSilent = 0,
641 .blueToothOptions = 0,
642 .deviceCap = 0,
643 .deviceType = 5, /* takes lower byte in eeprom location */
644 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
645 .params_for_tuning_caps = {0, 0},
646 .featureEnable = 0x0d,
647 /*
648 * bit0 - enable tx temp comp - disabled
649 * bit1 - enable tx volt comp - disabled
650 * bit2 - enable fastClock - enabled
651 * bit3 - enable doubling - enabled
652 * bit4 - enable internal regulator - disabled
653 * bit5 - enable pa predistortion - disabled
654 */
655 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
656 .eepromWriteEnableGpio = 6,
657 .wlanDisableGpio = 0,
658 .wlanLedGpio = 8,
659 .rxBandSelectGpio = 0xff,
660 .txrxgain = 0x21,
661 .swreg = 0,
662 },
663 .modalHeader2G = {
664 /* ar9300_modal_eep_header 2g */
665 /* 4 idle,t1,t2,b(4 bits per setting) */
666 .antCtrlCommon = LE32(0x110),
667 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
668 .antCtrlCommon2 = LE32(0x44444),
669
670 /*
671 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
672 * rx1, rx12, b (2 bits each)
673 */
674 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
675
676 /*
677 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
678 * for ar9280 (0xa20c/b20c 5:0)
679 */
680 .xatten1DB = {0, 0, 0},
681
682 /*
683 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
684 * for ar9280 (0xa20c/b20c 16:12
685 */
686 .xatten1Margin = {0, 0, 0},
687 .tempSlope = 25,
688 .voltSlope = 0,
689
690 /*
691 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
692 * channels in usual fbin coding format
693 */
694 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
695
696 /*
697 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
698 * if the register is per chain
699 */
700 .noiseFloorThreshCh = {-1, 0, 0},
701 .ob = {1, 1, 1},/* 3 chain */
702 .db_stage2 = {1, 1, 1}, /* 3 chain */
703 .db_stage3 = {0, 0, 0},
704 .db_stage4 = {0, 0, 0},
705 .xpaBiasLvl = 0,
706 .txFrameToDataStart = 0x0e,
707 .txFrameToPaOn = 0x0e,
708 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
709 .antennaGain = 0,
710 .switchSettling = 0x2c,
711 .adcDesiredSize = -30,
712 .txEndToXpaOff = 0,
713 .txEndToRxOn = 0x2,
714 .txFrameToXpaOn = 0xe,
715 .thresh62 = 28,
716 .papdRateMaskHt20 = LE32(0x0c80c080),
717 .papdRateMaskHt40 = LE32(0x0080c080),
718 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]719 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]720 },
721 },
722 .base_ext1 = {
723 .ant_div_control = 0,
724 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
725 },
726 .calFreqPier2G = {
727 FREQ2FBIN(2412, 1),
728 FREQ2FBIN(2437, 1),
729 FREQ2FBIN(2472, 1),
730 },
731 /* ar9300_cal_data_per_freq_op_loop 2g */
732 .calPierData2G = {
733 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
734 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
735 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
736 },
737 .calTarget_freqbin_Cck = {
738 FREQ2FBIN(2412, 1),
739 FREQ2FBIN(2472, 1),
740 },
741 .calTarget_freqbin_2G = {
742 FREQ2FBIN(2412, 1),
743 FREQ2FBIN(2437, 1),
744 FREQ2FBIN(2472, 1)
745 },
746 .calTarget_freqbin_2GHT20 = {
747 FREQ2FBIN(2412, 1),
748 FREQ2FBIN(2437, 1),
749 FREQ2FBIN(2472, 1)
750 },
751 .calTarget_freqbin_2GHT40 = {
752 FREQ2FBIN(2412, 1),
753 FREQ2FBIN(2437, 1),
754 FREQ2FBIN(2472, 1)
755 },
756 .calTargetPowerCck = {
757 /* 1L-5L,5S,11L,11S */
758 { {34, 34, 34, 34} },
759 { {34, 34, 34, 34} },
760 },
761 .calTargetPower2G = {
762 /* 6-24,36,48,54 */
763 { {34, 34, 32, 32} },
764 { {34, 34, 32, 32} },
765 { {34, 34, 32, 32} },
766 },
767 .calTargetPower2GHT20 = {
768 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
769 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
770 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
771 },
772 .calTargetPower2GHT40 = {
773 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
774 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
775 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
776 },
777 .ctlIndex_2G = {
778 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
779 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
780 },
781 .ctl_freqbin_2G = {
782 {
783 FREQ2FBIN(2412, 1),
784 FREQ2FBIN(2417, 1),
785 FREQ2FBIN(2457, 1),
786 FREQ2FBIN(2462, 1)
787 },
788 {
789 FREQ2FBIN(2412, 1),
790 FREQ2FBIN(2417, 1),
791 FREQ2FBIN(2462, 1),
792 0xFF,
793 },
794
795 {
796 FREQ2FBIN(2412, 1),
797 FREQ2FBIN(2417, 1),
798 FREQ2FBIN(2462, 1),
799 0xFF,
800 },
801 {
802 FREQ2FBIN(2422, 1),
803 FREQ2FBIN(2427, 1),
804 FREQ2FBIN(2447, 1),
805 FREQ2FBIN(2452, 1)
806 },
807
808 {
809 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
810 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
811 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
812 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
813 },
814
815 {
816 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
817 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
818 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
819 0,
820 },
821
822 {
823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
825 FREQ2FBIN(2472, 1),
826 0,
827 },
828
829 {
830 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
831 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
832 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
833 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
834 },
835
836 {
837 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
838 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
839 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
840 },
841
842 {
843 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
844 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
845 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
846 0
847 },
848
849 {
850 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
851 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
852 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
853 0
854 },
855
856 {
857 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
858 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
859 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
860 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
861 }
862 },
863 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]864 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
866 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]867
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]868 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]869 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
870 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]871
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]872 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
873 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
874 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]875
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]876 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
877 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
878 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]879 },
880 .modalHeader5G = {
881 /* 4 idle,t1,t2,b (4 bits per setting) */
882 .antCtrlCommon = LE32(0x220),
883 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
884 .antCtrlCommon2 = LE32(0x11111),
885 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
886 .antCtrlChain = {
887 LE16(0x150), LE16(0x150), LE16(0x150),
888 },
889 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
890 .xatten1DB = {0, 0, 0},
891
892 /*
893 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
894 * for merlin (0xa20c/b20c 16:12
895 */
896 .xatten1Margin = {0, 0, 0},
897 .tempSlope = 68,
898 .voltSlope = 0,
899 /* spurChans spur channels in usual fbin coding format */
900 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
901 /* noiseFloorThreshCh Check if the register is per chain */
902 .noiseFloorThreshCh = {-1, 0, 0},
903 .ob = {3, 3, 3}, /* 3 chain */
904 .db_stage2 = {3, 3, 3}, /* 3 chain */
905 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
906 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
Senthil Balasubramanianbe0e6aa2011-05-12 16:24:28 +0530[diff] [blame]907 .xpaBiasLvl = 0xf,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]908 .txFrameToDataStart = 0x0e,
909 .txFrameToPaOn = 0x0e,
910 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
911 .antennaGain = 0,
912 .switchSettling = 0x2d,
913 .adcDesiredSize = -30,
914 .txEndToXpaOff = 0,
915 .txEndToRxOn = 0x2,
916 .txFrameToXpaOn = 0xe,
917 .thresh62 = 28,
918 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
919 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
920 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]921 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]922 },
923 },
924 .base_ext2 = {
925 .tempSlopeLow = 72,
926 .tempSlopeHigh = 105,
927 .xatten1DBLow = {0, 0, 0},
928 .xatten1MarginLow = {0, 0, 0},
929 .xatten1DBHigh = {0, 0, 0},
930 .xatten1MarginHigh = {0, 0, 0}
931 },
932 .calFreqPier5G = {
933 FREQ2FBIN(5180, 0),
934 FREQ2FBIN(5240, 0),
935 FREQ2FBIN(5320, 0),
936 FREQ2FBIN(5400, 0),
937 FREQ2FBIN(5500, 0),
938 FREQ2FBIN(5600, 0),
939 FREQ2FBIN(5745, 0),
940 FREQ2FBIN(5785, 0)
941 },
942 .calPierData5G = {
943 {
944 {0, 0, 0, 0, 0},
945 {0, 0, 0, 0, 0},
946 {0, 0, 0, 0, 0},
947 {0, 0, 0, 0, 0},
948 {0, 0, 0, 0, 0},
949 {0, 0, 0, 0, 0},
950 {0, 0, 0, 0, 0},
951 {0, 0, 0, 0, 0},
952 },
953 {
954 {0, 0, 0, 0, 0},
955 {0, 0, 0, 0, 0},
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 {0, 0, 0, 0, 0},
960 {0, 0, 0, 0, 0},
961 {0, 0, 0, 0, 0},
962 },
963 {
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 {0, 0, 0, 0, 0},
970 {0, 0, 0, 0, 0},
971 {0, 0, 0, 0, 0},
972 },
973
974 },
975 .calTarget_freqbin_5G = {
976 FREQ2FBIN(5180, 0),
977 FREQ2FBIN(5220, 0),
978 FREQ2FBIN(5320, 0),
979 FREQ2FBIN(5400, 0),
980 FREQ2FBIN(5500, 0),
981 FREQ2FBIN(5600, 0),
982 FREQ2FBIN(5745, 0),
983 FREQ2FBIN(5785, 0)
984 },
985 .calTarget_freqbin_5GHT20 = {
986 FREQ2FBIN(5180, 0),
987 FREQ2FBIN(5240, 0),
988 FREQ2FBIN(5320, 0),
989 FREQ2FBIN(5400, 0),
990 FREQ2FBIN(5500, 0),
991 FREQ2FBIN(5700, 0),
992 FREQ2FBIN(5745, 0),
993 FREQ2FBIN(5825, 0)
994 },
995 .calTarget_freqbin_5GHT40 = {
996 FREQ2FBIN(5190, 0),
997 FREQ2FBIN(5230, 0),
998 FREQ2FBIN(5320, 0),
999 FREQ2FBIN(5410, 0),
1000 FREQ2FBIN(5510, 0),
1001 FREQ2FBIN(5670, 0),
1002 FREQ2FBIN(5755, 0),
1003 FREQ2FBIN(5825, 0)
1004 },
1005 .calTargetPower5G = {
1006 /* 6-24,36,48,54 */
1007 { {42, 40, 40, 34} },
1008 { {42, 40, 40, 34} },
1009 { {42, 40, 40, 34} },
1010 { {42, 40, 40, 34} },
1011 { {42, 40, 40, 34} },
1012 { {42, 40, 40, 34} },
1013 { {42, 40, 40, 34} },
1014 { {42, 40, 40, 34} },
1015 },
1016 .calTargetPower5GHT20 = {
1017 /*
1018 * 0_8_16,1-3_9-11_17-19,
1019 * 4,5,6,7,12,13,14,15,20,21,22,23
1020 */
1021 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1022 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1023 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1024 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1025 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1026 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1027 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1028 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1029 },
1030 .calTargetPower5GHT40 = {
1031 /*
1032 * 0_8_16,1-3_9-11_17-19,
1033 * 4,5,6,7,12,13,14,15,20,21,22,23
1034 */
1035 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1036 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1037 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1038 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1039 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1040 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1041 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1042 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1043 },
1044 .ctlIndex_5G = {
1045 0x10, 0x16, 0x18, 0x40, 0x46,
1046 0x48, 0x30, 0x36, 0x38
1047 },
1048 .ctl_freqbin_5G = {
1049 {
1050 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1051 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1052 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1053 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1054 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1055 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1056 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1057 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1058 },
1059 {
1060 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1061 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1062 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1063 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1064 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1065 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1066 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1067 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1068 },
1069
1070 {
1071 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1072 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1073 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1074 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1075 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1076 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1077 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1078 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1079 },
1080
1081 {
1082 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1083 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1084 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1085 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1086 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1087 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1088 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1089 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1090 },
1091
1092 {
1093 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1094 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1095 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1096 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1097 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1098 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1099 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1100 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1101 },
1102
1103 {
1104 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1105 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1106 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1107 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1108 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1109 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1110 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1111 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1112 },
1113
1114 {
1115 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1116 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1117 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1118 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1119 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1120 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1121 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1122 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1123 },
1124
1125 {
1126 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1127 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1128 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1129 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1130 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1131 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1132 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1133 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1134 },
1135
1136 {
1137 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1138 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1139 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1140 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1141 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1142 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1143 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1144 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1145 }
1146 },
1147 .ctlPowerData_5G = {
1148 {
1149 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1151 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1152 }
1153 },
1154 {
1155 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1156 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1157 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1158 }
1159 },
1160 {
1161 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1162 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1163 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1164 }
1165 },
1166 {
1167 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1168 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1169 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1170 }
1171 },
1172 {
1173 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1175 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1176 }
1177 },
1178 {
1179 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1181 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1182 }
1183 },
1184 {
1185 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1186 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1187 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1188 }
1189 },
1190 {
1191 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1192 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1193 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1194 }
1195 },
1196 {
1197 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1198 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1199 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1200 }
1201 },
1202 }
1203};
1204
1205
1206static const struct ar9300_eeprom ar9300_h112 = {
1207 .eepromVersion = 2,
1208 .templateVersion = 3,
1209 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1210 .custData = {"h112-241-f0000"},
1211 .baseEepHeader = {
1212 .regDmn = { LE16(0), LE16(0x1f) },
1213 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1214 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1215 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1216 .eepMisc = 0,
1217 },
1218 .rfSilent = 0,
1219 .blueToothOptions = 0,
1220 .deviceCap = 0,
1221 .deviceType = 5, /* takes lower byte in eeprom location */
1222 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1223 .params_for_tuning_caps = {0, 0},
1224 .featureEnable = 0x0d,
1225 /*
1226 * bit0 - enable tx temp comp - disabled
1227 * bit1 - enable tx volt comp - disabled
1228 * bit2 - enable fastClock - enabled
1229 * bit3 - enable doubling - enabled
1230 * bit4 - enable internal regulator - disabled
1231 * bit5 - enable pa predistortion - disabled
1232 */
1233 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1234 .eepromWriteEnableGpio = 6,
1235 .wlanDisableGpio = 0,
1236 .wlanLedGpio = 8,
1237 .rxBandSelectGpio = 0xff,
1238 .txrxgain = 0x10,
1239 .swreg = 0,
1240 },
1241 .modalHeader2G = {
1242 /* ar9300_modal_eep_header 2g */
1243 /* 4 idle,t1,t2,b(4 bits per setting) */
1244 .antCtrlCommon = LE32(0x110),
1245 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1246 .antCtrlCommon2 = LE32(0x44444),
1247
1248 /*
1249 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1250 * rx1, rx12, b (2 bits each)
1251 */
1252 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1253
1254 /*
1255 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1256 * for ar9280 (0xa20c/b20c 5:0)
1257 */
1258 .xatten1DB = {0, 0, 0},
1259
1260 /*
1261 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1262 * for ar9280 (0xa20c/b20c 16:12
1263 */
1264 .xatten1Margin = {0, 0, 0},
1265 .tempSlope = 25,
1266 .voltSlope = 0,
1267
1268 /*
1269 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1270 * channels in usual fbin coding format
1271 */
1272 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1273
1274 /*
1275 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1276 * if the register is per chain
1277 */
1278 .noiseFloorThreshCh = {-1, 0, 0},
1279 .ob = {1, 1, 1},/* 3 chain */
1280 .db_stage2 = {1, 1, 1}, /* 3 chain */
1281 .db_stage3 = {0, 0, 0},
1282 .db_stage4 = {0, 0, 0},
1283 .xpaBiasLvl = 0,
1284 .txFrameToDataStart = 0x0e,
1285 .txFrameToPaOn = 0x0e,
1286 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1287 .antennaGain = 0,
1288 .switchSettling = 0x2c,
1289 .adcDesiredSize = -30,
1290 .txEndToXpaOff = 0,
1291 .txEndToRxOn = 0x2,
1292 .txFrameToXpaOn = 0xe,
1293 .thresh62 = 28,
1294 .papdRateMaskHt20 = LE32(0x80c080),
1295 .papdRateMaskHt40 = LE32(0x80c080),
1296 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]1297 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1298 },
1299 },
1300 .base_ext1 = {
1301 .ant_div_control = 0,
1302 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1303 },
1304 .calFreqPier2G = {
1305 FREQ2FBIN(2412, 1),
1306 FREQ2FBIN(2437, 1),
1307 FREQ2FBIN(2472, 1),
1308 },
1309 /* ar9300_cal_data_per_freq_op_loop 2g */
1310 .calPierData2G = {
1311 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1312 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1313 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1314 },
1315 .calTarget_freqbin_Cck = {
1316 FREQ2FBIN(2412, 1),
1317 FREQ2FBIN(2484, 1),
1318 },
1319 .calTarget_freqbin_2G = {
1320 FREQ2FBIN(2412, 1),
1321 FREQ2FBIN(2437, 1),
1322 FREQ2FBIN(2472, 1)
1323 },
1324 .calTarget_freqbin_2GHT20 = {
1325 FREQ2FBIN(2412, 1),
1326 FREQ2FBIN(2437, 1),
1327 FREQ2FBIN(2472, 1)
1328 },
1329 .calTarget_freqbin_2GHT40 = {
1330 FREQ2FBIN(2412, 1),
1331 FREQ2FBIN(2437, 1),
1332 FREQ2FBIN(2472, 1)
1333 },
1334 .calTargetPowerCck = {
1335 /* 1L-5L,5S,11L,11S */
1336 { {34, 34, 34, 34} },
1337 { {34, 34, 34, 34} },
1338 },
1339 .calTargetPower2G = {
1340 /* 6-24,36,48,54 */
1341 { {34, 34, 32, 32} },
1342 { {34, 34, 32, 32} },
1343 { {34, 34, 32, 32} },
1344 },
1345 .calTargetPower2GHT20 = {
1346 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1347 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1348 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1349 },
1350 .calTargetPower2GHT40 = {
1351 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1352 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1353 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1354 },
1355 .ctlIndex_2G = {
1356 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1357 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1358 },
1359 .ctl_freqbin_2G = {
1360 {
1361 FREQ2FBIN(2412, 1),
1362 FREQ2FBIN(2417, 1),
1363 FREQ2FBIN(2457, 1),
1364 FREQ2FBIN(2462, 1)
1365 },
1366 {
1367 FREQ2FBIN(2412, 1),
1368 FREQ2FBIN(2417, 1),
1369 FREQ2FBIN(2462, 1),
1370 0xFF,
1371 },
1372
1373 {
1374 FREQ2FBIN(2412, 1),
1375 FREQ2FBIN(2417, 1),
1376 FREQ2FBIN(2462, 1),
1377 0xFF,
1378 },
1379 {
1380 FREQ2FBIN(2422, 1),
1381 FREQ2FBIN(2427, 1),
1382 FREQ2FBIN(2447, 1),
1383 FREQ2FBIN(2452, 1)
1384 },
1385
1386 {
1387 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1388 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1389 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1390 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1391 },
1392
1393 {
1394 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1395 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1396 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1397 0,
1398 },
1399
1400 {
1401 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1402 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1403 FREQ2FBIN(2472, 1),
1404 0,
1405 },
1406
1407 {
1408 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1409 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1410 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1411 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1412 },
1413
1414 {
1415 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1416 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1417 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1418 },
1419
1420 {
1421 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1422 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1423 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1424 0
1425 },
1426
1427 {
1428 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1429 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1430 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1431 0
1432 },
1433
1434 {
1435 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1436 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1437 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1438 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1439 }
1440 },
1441 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1442 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1444 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1445
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]1446 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1447 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1448 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1449
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1450 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1451 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1452 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1453
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1454 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1455 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1456 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1457 },
1458 .modalHeader5G = {
1459 /* 4 idle,t1,t2,b (4 bits per setting) */
1460 .antCtrlCommon = LE32(0x220),
1461 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1462 .antCtrlCommon2 = LE32(0x44444),
1463 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1464 .antCtrlChain = {
1465 LE16(0x150), LE16(0x150), LE16(0x150),
1466 },
1467 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1468 .xatten1DB = {0, 0, 0},
1469
1470 /*
1471 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1472 * for merlin (0xa20c/b20c 16:12
1473 */
1474 .xatten1Margin = {0, 0, 0},
1475 .tempSlope = 45,
1476 .voltSlope = 0,
1477 /* spurChans spur channels in usual fbin coding format */
1478 .spurChans = {0, 0, 0, 0, 0},
1479 /* noiseFloorThreshCh Check if the register is per chain */
1480 .noiseFloorThreshCh = {-1, 0, 0},
1481 .ob = {3, 3, 3}, /* 3 chain */
1482 .db_stage2 = {3, 3, 3}, /* 3 chain */
1483 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1484 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1485 .xpaBiasLvl = 0,
1486 .txFrameToDataStart = 0x0e,
1487 .txFrameToPaOn = 0x0e,
1488 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1489 .antennaGain = 0,
1490 .switchSettling = 0x2d,
1491 .adcDesiredSize = -30,
1492 .txEndToXpaOff = 0,
1493 .txEndToRxOn = 0x2,
1494 .txFrameToXpaOn = 0xe,
1495 .thresh62 = 28,
1496 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1497 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1498 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]1499 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1500 },
1501 },
1502 .base_ext2 = {
1503 .tempSlopeLow = 40,
1504 .tempSlopeHigh = 50,
1505 .xatten1DBLow = {0, 0, 0},
1506 .xatten1MarginLow = {0, 0, 0},
1507 .xatten1DBHigh = {0, 0, 0},
1508 .xatten1MarginHigh = {0, 0, 0}
1509 },
1510 .calFreqPier5G = {
1511 FREQ2FBIN(5180, 0),
1512 FREQ2FBIN(5220, 0),
1513 FREQ2FBIN(5320, 0),
1514 FREQ2FBIN(5400, 0),
1515 FREQ2FBIN(5500, 0),
1516 FREQ2FBIN(5600, 0),
1517 FREQ2FBIN(5700, 0),
1518 FREQ2FBIN(5825, 0)
1519 },
1520 .calPierData5G = {
1521 {
1522 {0, 0, 0, 0, 0},
1523 {0, 0, 0, 0, 0},
1524 {0, 0, 0, 0, 0},
1525 {0, 0, 0, 0, 0},
1526 {0, 0, 0, 0, 0},
1527 {0, 0, 0, 0, 0},
1528 {0, 0, 0, 0, 0},
1529 {0, 0, 0, 0, 0},
1530 },
1531 {
1532 {0, 0, 0, 0, 0},
1533 {0, 0, 0, 0, 0},
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 {0, 0, 0, 0, 0},
1539 {0, 0, 0, 0, 0},
1540 },
1541 {
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 {0, 0, 0, 0, 0},
1549 {0, 0, 0, 0, 0},
1550 },
1551
1552 },
1553 .calTarget_freqbin_5G = {
1554 FREQ2FBIN(5180, 0),
1555 FREQ2FBIN(5240, 0),
1556 FREQ2FBIN(5320, 0),
1557 FREQ2FBIN(5400, 0),
1558 FREQ2FBIN(5500, 0),
1559 FREQ2FBIN(5600, 0),
1560 FREQ2FBIN(5700, 0),
1561 FREQ2FBIN(5825, 0)
1562 },
1563 .calTarget_freqbin_5GHT20 = {
1564 FREQ2FBIN(5180, 0),
1565 FREQ2FBIN(5240, 0),
1566 FREQ2FBIN(5320, 0),
1567 FREQ2FBIN(5400, 0),
1568 FREQ2FBIN(5500, 0),
1569 FREQ2FBIN(5700, 0),
1570 FREQ2FBIN(5745, 0),
1571 FREQ2FBIN(5825, 0)
1572 },
1573 .calTarget_freqbin_5GHT40 = {
1574 FREQ2FBIN(5180, 0),
1575 FREQ2FBIN(5240, 0),
1576 FREQ2FBIN(5320, 0),
1577 FREQ2FBIN(5400, 0),
1578 FREQ2FBIN(5500, 0),
1579 FREQ2FBIN(5700, 0),
1580 FREQ2FBIN(5745, 0),
1581 FREQ2FBIN(5825, 0)
1582 },
1583 .calTargetPower5G = {
1584 /* 6-24,36,48,54 */
1585 { {30, 30, 28, 24} },
1586 { {30, 30, 28, 24} },
1587 { {30, 30, 28, 24} },
1588 { {30, 30, 28, 24} },
1589 { {30, 30, 28, 24} },
1590 { {30, 30, 28, 24} },
1591 { {30, 30, 28, 24} },
1592 { {30, 30, 28, 24} },
1593 },
1594 .calTargetPower5GHT20 = {
1595 /*
1596 * 0_8_16,1-3_9-11_17-19,
1597 * 4,5,6,7,12,13,14,15,20,21,22,23
1598 */
1599 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1600 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1601 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1602 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1603 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1604 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1605 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1606 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1607 },
1608 .calTargetPower5GHT40 = {
1609 /*
1610 * 0_8_16,1-3_9-11_17-19,
1611 * 4,5,6,7,12,13,14,15,20,21,22,23
1612 */
1613 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1614 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1615 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1616 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1617 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1618 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1619 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1620 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1621 },
1622 .ctlIndex_5G = {
1623 0x10, 0x16, 0x18, 0x40, 0x46,
1624 0x48, 0x30, 0x36, 0x38
1625 },
1626 .ctl_freqbin_5G = {
1627 {
1628 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1629 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1630 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1631 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1632 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1633 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1634 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1635 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1636 },
1637 {
1638 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1639 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1640 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1641 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1642 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1643 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1644 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1645 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1646 },
1647
1648 {
1649 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1650 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1651 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1652 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1653 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1654 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1655 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1656 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1657 },
1658
1659 {
1660 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1661 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1662 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1663 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1664 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1665 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1666 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1667 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1668 },
1669
1670 {
1671 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1672 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1673 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1674 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1675 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1676 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1677 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1678 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1679 },
1680
1681 {
1682 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1683 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1684 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1685 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1686 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1687 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1688 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1689 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1690 },
1691
1692 {
1693 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1694 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1695 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1696 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1697 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1698 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1699 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1700 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1701 },
1702
1703 {
1704 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1705 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1706 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1707 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1708 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1709 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1710 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1711 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1712 },
1713
1714 {
1715 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1716 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1717 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1718 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1719 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1720 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1721 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1722 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1723 }
1724 },
1725 .ctlPowerData_5G = {
1726 {
1727 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1728 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1729 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1730 }
1731 },
1732 {
1733 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1734 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1736 }
1737 },
1738 {
1739 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1740 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1742 }
1743 },
1744 {
1745 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1746 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1747 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1748 }
1749 },
1750 {
1751 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1752 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1753 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1754 }
1755 },
1756 {
1757 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1758 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1759 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1760 }
1761 },
1762 {
1763 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1764 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1765 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1766 }
1767 },
1768 {
1769 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1770 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1771 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1772 }
1773 },
1774 {
1775 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1776 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1777 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1778 }
1779 },
1780 }
1781};
1782
1783
1784static const struct ar9300_eeprom ar9300_x112 = {
1785 .eepromVersion = 2,
1786 .templateVersion = 5,
1787 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1788 .custData = {"x112-041-f0000"},
1789 .baseEepHeader = {
1790 .regDmn = { LE16(0), LE16(0x1f) },
1791 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1792 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1793 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1794 .eepMisc = 0,
1795 },
1796 .rfSilent = 0,
1797 .blueToothOptions = 0,
1798 .deviceCap = 0,
1799 .deviceType = 5, /* takes lower byte in eeprom location */
1800 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1801 .params_for_tuning_caps = {0, 0},
1802 .featureEnable = 0x0d,
1803 /*
1804 * bit0 - enable tx temp comp - disabled
1805 * bit1 - enable tx volt comp - disabled
1806 * bit2 - enable fastclock - enabled
1807 * bit3 - enable doubling - enabled
1808 * bit4 - enable internal regulator - disabled
1809 * bit5 - enable pa predistortion - disabled
1810 */
1811 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1812 .eepromWriteEnableGpio = 6,
1813 .wlanDisableGpio = 0,
1814 .wlanLedGpio = 8,
1815 .rxBandSelectGpio = 0xff,
1816 .txrxgain = 0x0,
1817 .swreg = 0,
1818 },
1819 .modalHeader2G = {
1820 /* ar9300_modal_eep_header 2g */
1821 /* 4 idle,t1,t2,b(4 bits per setting) */
1822 .antCtrlCommon = LE32(0x110),
1823 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1824 .antCtrlCommon2 = LE32(0x22222),
1825
1826 /*
1827 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1828 * rx1, rx12, b (2 bits each)
1829 */
1830 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1831
1832 /*
1833 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1834 * for ar9280 (0xa20c/b20c 5:0)
1835 */
1836 .xatten1DB = {0x1b, 0x1b, 0x1b},
1837
1838 /*
1839 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1840 * for ar9280 (0xa20c/b20c 16:12
1841 */
1842 .xatten1Margin = {0x15, 0x15, 0x15},
1843 .tempSlope = 50,
1844 .voltSlope = 0,
1845
1846 /*
1847 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1848 * channels in usual fbin coding format
1849 */
1850 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1851
1852 /*
1853 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1854 * if the register is per chain
1855 */
1856 .noiseFloorThreshCh = {-1, 0, 0},
1857 .ob = {1, 1, 1},/* 3 chain */
1858 .db_stage2 = {1, 1, 1}, /* 3 chain */
1859 .db_stage3 = {0, 0, 0},
1860 .db_stage4 = {0, 0, 0},
1861 .xpaBiasLvl = 0,
1862 .txFrameToDataStart = 0x0e,
1863 .txFrameToPaOn = 0x0e,
1864 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1865 .antennaGain = 0,
1866 .switchSettling = 0x2c,
1867 .adcDesiredSize = -30,
1868 .txEndToXpaOff = 0,
1869 .txEndToRxOn = 0x2,
1870 .txFrameToXpaOn = 0xe,
1871 .thresh62 = 28,
1872 .papdRateMaskHt20 = LE32(0x0c80c080),
1873 .papdRateMaskHt40 = LE32(0x0080c080),
1874 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]1875 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1876 },
1877 },
1878 .base_ext1 = {
1879 .ant_div_control = 0,
1880 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1881 },
1882 .calFreqPier2G = {
1883 FREQ2FBIN(2412, 1),
1884 FREQ2FBIN(2437, 1),
1885 FREQ2FBIN(2472, 1),
1886 },
1887 /* ar9300_cal_data_per_freq_op_loop 2g */
1888 .calPierData2G = {
1889 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1890 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1891 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1892 },
1893 .calTarget_freqbin_Cck = {
1894 FREQ2FBIN(2412, 1),
1895 FREQ2FBIN(2472, 1),
1896 },
1897 .calTarget_freqbin_2G = {
1898 FREQ2FBIN(2412, 1),
1899 FREQ2FBIN(2437, 1),
1900 FREQ2FBIN(2472, 1)
1901 },
1902 .calTarget_freqbin_2GHT20 = {
1903 FREQ2FBIN(2412, 1),
1904 FREQ2FBIN(2437, 1),
1905 FREQ2FBIN(2472, 1)
1906 },
1907 .calTarget_freqbin_2GHT40 = {
1908 FREQ2FBIN(2412, 1),
1909 FREQ2FBIN(2437, 1),
1910 FREQ2FBIN(2472, 1)
1911 },
1912 .calTargetPowerCck = {
1913 /* 1L-5L,5S,11L,11s */
1914 { {38, 38, 38, 38} },
1915 { {38, 38, 38, 38} },
1916 },
1917 .calTargetPower2G = {
1918 /* 6-24,36,48,54 */
1919 { {38, 38, 36, 34} },
1920 { {38, 38, 36, 34} },
1921 { {38, 38, 34, 32} },
1922 },
1923 .calTargetPower2GHT20 = {
1924 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1925 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1926 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1927 },
1928 .calTargetPower2GHT40 = {
1929 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1930 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1931 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1932 },
1933 .ctlIndex_2G = {
1934 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1935 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1936 },
1937 .ctl_freqbin_2G = {
1938 {
1939 FREQ2FBIN(2412, 1),
1940 FREQ2FBIN(2417, 1),
1941 FREQ2FBIN(2457, 1),
1942 FREQ2FBIN(2462, 1)
1943 },
1944 {
1945 FREQ2FBIN(2412, 1),
1946 FREQ2FBIN(2417, 1),
1947 FREQ2FBIN(2462, 1),
1948 0xFF,
1949 },
1950
1951 {
1952 FREQ2FBIN(2412, 1),
1953 FREQ2FBIN(2417, 1),
1954 FREQ2FBIN(2462, 1),
1955 0xFF,
1956 },
1957 {
1958 FREQ2FBIN(2422, 1),
1959 FREQ2FBIN(2427, 1),
1960 FREQ2FBIN(2447, 1),
1961 FREQ2FBIN(2452, 1)
1962 },
1963
1964 {
1965 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1966 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1967 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1968 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1969 },
1970
1971 {
1972 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1973 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1974 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1975 0,
1976 },
1977
1978 {
1979 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1980 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1981 FREQ2FBIN(2472, 1),
1982 0,
1983 },
1984
1985 {
1986 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1987 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1988 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1989 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1990 },
1991
1992 {
1993 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1994 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1995 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1996 },
1997
1998 {
1999 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2000 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2001 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2002 0
2003 },
2004
2005 {
2006 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2007 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2008 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2009 0
2010 },
2011
2012 {
2013 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2014 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2015 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2016 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2017 }
2018 },
2019 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2021 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2022 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2023
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]2024 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2026 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2027
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2028 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2029 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2030 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2031
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2032 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2033 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2034 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2035 },
2036 .modalHeader5G = {
2037 /* 4 idle,t1,t2,b (4 bits per setting) */
2038 .antCtrlCommon = LE32(0x110),
2039 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2040 .antCtrlCommon2 = LE32(0x22222),
2041 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2042 .antCtrlChain = {
2043 LE16(0x0), LE16(0x0), LE16(0x0),
2044 },
2045 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2046 .xatten1DB = {0x13, 0x19, 0x17},
2047
2048 /*
2049 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2050 * for merlin (0xa20c/b20c 16:12
2051 */
2052 .xatten1Margin = {0x19, 0x19, 0x19},
2053 .tempSlope = 70,
2054 .voltSlope = 15,
2055 /* spurChans spur channels in usual fbin coding format */
2056 .spurChans = {0, 0, 0, 0, 0},
2057 /* noiseFloorThreshch check if the register is per chain */
2058 .noiseFloorThreshCh = {-1, 0, 0},
2059 .ob = {3, 3, 3}, /* 3 chain */
2060 .db_stage2 = {3, 3, 3}, /* 3 chain */
2061 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2062 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2063 .xpaBiasLvl = 0,
2064 .txFrameToDataStart = 0x0e,
2065 .txFrameToPaOn = 0x0e,
2066 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2067 .antennaGain = 0,
2068 .switchSettling = 0x2d,
2069 .adcDesiredSize = -30,
2070 .txEndToXpaOff = 0,
2071 .txEndToRxOn = 0x2,
2072 .txFrameToXpaOn = 0xe,
2073 .thresh62 = 28,
2074 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2075 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2076 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]2077 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2078 },
2079 },
2080 .base_ext2 = {
2081 .tempSlopeLow = 72,
2082 .tempSlopeHigh = 105,
2083 .xatten1DBLow = {0x10, 0x14, 0x10},
2084 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2085 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2086 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2087 },
2088 .calFreqPier5G = {
2089 FREQ2FBIN(5180, 0),
2090 FREQ2FBIN(5220, 0),
2091 FREQ2FBIN(5320, 0),
2092 FREQ2FBIN(5400, 0),
2093 FREQ2FBIN(5500, 0),
2094 FREQ2FBIN(5600, 0),
2095 FREQ2FBIN(5700, 0),
2096 FREQ2FBIN(5785, 0)
2097 },
2098 .calPierData5G = {
2099 {
2100 {0, 0, 0, 0, 0},
2101 {0, 0, 0, 0, 0},
2102 {0, 0, 0, 0, 0},
2103 {0, 0, 0, 0, 0},
2104 {0, 0, 0, 0, 0},
2105 {0, 0, 0, 0, 0},
2106 {0, 0, 0, 0, 0},
2107 {0, 0, 0, 0, 0},
2108 },
2109 {
2110 {0, 0, 0, 0, 0},
2111 {0, 0, 0, 0, 0},
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 {0, 0, 0, 0, 0},
2118 },
2119 {
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 {0, 0, 0, 0, 0},
2128 },
2129
2130 },
2131 .calTarget_freqbin_5G = {
2132 FREQ2FBIN(5180, 0),
2133 FREQ2FBIN(5220, 0),
2134 FREQ2FBIN(5320, 0),
2135 FREQ2FBIN(5400, 0),
2136 FREQ2FBIN(5500, 0),
2137 FREQ2FBIN(5600, 0),
2138 FREQ2FBIN(5725, 0),
2139 FREQ2FBIN(5825, 0)
2140 },
2141 .calTarget_freqbin_5GHT20 = {
2142 FREQ2FBIN(5180, 0),
2143 FREQ2FBIN(5220, 0),
2144 FREQ2FBIN(5320, 0),
2145 FREQ2FBIN(5400, 0),
2146 FREQ2FBIN(5500, 0),
2147 FREQ2FBIN(5600, 0),
2148 FREQ2FBIN(5725, 0),
2149 FREQ2FBIN(5825, 0)
2150 },
2151 .calTarget_freqbin_5GHT40 = {
2152 FREQ2FBIN(5180, 0),
2153 FREQ2FBIN(5220, 0),
2154 FREQ2FBIN(5320, 0),
2155 FREQ2FBIN(5400, 0),
2156 FREQ2FBIN(5500, 0),
2157 FREQ2FBIN(5600, 0),
2158 FREQ2FBIN(5725, 0),
2159 FREQ2FBIN(5825, 0)
2160 },
2161 .calTargetPower5G = {
2162 /* 6-24,36,48,54 */
2163 { {32, 32, 28, 26} },
2164 { {32, 32, 28, 26} },
2165 { {32, 32, 28, 26} },
2166 { {32, 32, 26, 24} },
2167 { {32, 32, 26, 24} },
2168 { {32, 32, 24, 22} },
2169 { {30, 30, 24, 22} },
2170 { {30, 30, 24, 22} },
2171 },
2172 .calTargetPower5GHT20 = {
2173 /*
2174 * 0_8_16,1-3_9-11_17-19,
2175 * 4,5,6,7,12,13,14,15,20,21,22,23
2176 */
2177 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2178 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2179 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2180 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2181 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2182 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2183 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2184 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2185 },
2186 .calTargetPower5GHT40 = {
2187 /*
2188 * 0_8_16,1-3_9-11_17-19,
2189 * 4,5,6,7,12,13,14,15,20,21,22,23
2190 */
2191 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2193 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2194 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2195 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2196 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2197 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2198 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2199 },
2200 .ctlIndex_5G = {
2201 0x10, 0x16, 0x18, 0x40, 0x46,
2202 0x48, 0x30, 0x36, 0x38
2203 },
2204 .ctl_freqbin_5G = {
2205 {
2206 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2207 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2208 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2209 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2210 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2211 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2212 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2213 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2214 },
2215 {
2216 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2217 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2218 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2219 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2220 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2221 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2222 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2223 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2224 },
2225
2226 {
2227 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2228 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2229 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2230 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2231 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2232 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2233 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2234 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2235 },
2236
2237 {
2238 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2239 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2240 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2241 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2242 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2243 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2244 /* Data[3].ctledges[6].bchannel */ 0xFF,
2245 /* Data[3].ctledges[7].bchannel */ 0xFF,
2246 },
2247
2248 {
2249 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2250 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2251 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2252 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2253 /* Data[4].ctledges[4].bchannel */ 0xFF,
2254 /* Data[4].ctledges[5].bchannel */ 0xFF,
2255 /* Data[4].ctledges[6].bchannel */ 0xFF,
2256 /* Data[4].ctledges[7].bchannel */ 0xFF,
2257 },
2258
2259 {
2260 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2261 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2262 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2263 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2264 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2265 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2266 /* Data[5].ctledges[6].bchannel */ 0xFF,
2267 /* Data[5].ctledges[7].bchannel */ 0xFF
2268 },
2269
2270 {
2271 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2272 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2273 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2274 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2275 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2276 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2277 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2278 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2279 },
2280
2281 {
2282 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2283 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2284 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2285 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2286 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2287 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2288 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2289 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2290 },
2291
2292 {
2293 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2294 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2295 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2296 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2297 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2298 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2299 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2300 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2301 }
2302 },
2303 .ctlPowerData_5G = {
2304 {
2305 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2306 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2307 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2308 }
2309 },
2310 {
2311 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2312 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2313 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2314 }
2315 },
2316 {
2317 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2318 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2319 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2320 }
2321 },
2322 {
2323 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2324 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2325 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2326 }
2327 },
2328 {
2329 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2330 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2331 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2332 }
2333 },
2334 {
2335 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2336 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2337 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2338 }
2339 },
2340 {
2341 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2342 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2343 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2344 }
2345 },
2346 {
2347 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2348 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2349 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2350 }
2351 },
2352 {
2353 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2354 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2355 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2356 }
2357 },
2358 }
2359};
2360
2361static const struct ar9300_eeprom ar9300_h116 = {
2362 .eepromVersion = 2,
2363 .templateVersion = 4,
2364 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2365 .custData = {"h116-041-f0000"},
2366 .baseEepHeader = {
2367 .regDmn = { LE16(0), LE16(0x1f) },
2368 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2369 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2370 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2371 .eepMisc = 0,
2372 },
2373 .rfSilent = 0,
2374 .blueToothOptions = 0,
2375 .deviceCap = 0,
2376 .deviceType = 5, /* takes lower byte in eeprom location */
2377 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2378 .params_for_tuning_caps = {0, 0},
2379 .featureEnable = 0x0d,
2380 /*
2381 * bit0 - enable tx temp comp - disabled
2382 * bit1 - enable tx volt comp - disabled
2383 * bit2 - enable fastClock - enabled
2384 * bit3 - enable doubling - enabled
2385 * bit4 - enable internal regulator - disabled
2386 * bit5 - enable pa predistortion - disabled
2387 */
2388 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2389 .eepromWriteEnableGpio = 6,
2390 .wlanDisableGpio = 0,
2391 .wlanLedGpio = 8,
2392 .rxBandSelectGpio = 0xff,
2393 .txrxgain = 0x10,
2394 .swreg = 0,
2395 },
2396 .modalHeader2G = {
2397 /* ar9300_modal_eep_header 2g */
2398 /* 4 idle,t1,t2,b(4 bits per setting) */
2399 .antCtrlCommon = LE32(0x110),
2400 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2401 .antCtrlCommon2 = LE32(0x44444),
2402
2403 /*
2404 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2405 * rx1, rx12, b (2 bits each)
2406 */
2407 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2408
2409 /*
2410 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2411 * for ar9280 (0xa20c/b20c 5:0)
2412 */
2413 .xatten1DB = {0x1f, 0x1f, 0x1f},
2414
2415 /*
2416 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2417 * for ar9280 (0xa20c/b20c 16:12
2418 */
2419 .xatten1Margin = {0x12, 0x12, 0x12},
2420 .tempSlope = 25,
2421 .voltSlope = 0,
2422
2423 /*
2424 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2425 * channels in usual fbin coding format
2426 */
2427 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2428
2429 /*
2430 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2431 * if the register is per chain
2432 */
2433 .noiseFloorThreshCh = {-1, 0, 0},
2434 .ob = {1, 1, 1},/* 3 chain */
2435 .db_stage2 = {1, 1, 1}, /* 3 chain */
2436 .db_stage3 = {0, 0, 0},
2437 .db_stage4 = {0, 0, 0},
2438 .xpaBiasLvl = 0,
2439 .txFrameToDataStart = 0x0e,
2440 .txFrameToPaOn = 0x0e,
2441 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2442 .antennaGain = 0,
2443 .switchSettling = 0x2c,
2444 .adcDesiredSize = -30,
2445 .txEndToXpaOff = 0,
2446 .txEndToRxOn = 0x2,
2447 .txFrameToXpaOn = 0xe,
2448 .thresh62 = 28,
2449 .papdRateMaskHt20 = LE32(0x0c80C080),
2450 .papdRateMaskHt40 = LE32(0x0080C080),
2451 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]2452 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2453 },
2454 },
2455 .base_ext1 = {
2456 .ant_div_control = 0,
2457 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2458 },
2459 .calFreqPier2G = {
2460 FREQ2FBIN(2412, 1),
2461 FREQ2FBIN(2437, 1),
2462 FREQ2FBIN(2472, 1),
2463 },
2464 /* ar9300_cal_data_per_freq_op_loop 2g */
2465 .calPierData2G = {
2466 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2467 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2468 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2469 },
2470 .calTarget_freqbin_Cck = {
2471 FREQ2FBIN(2412, 1),
2472 FREQ2FBIN(2472, 1),
2473 },
2474 .calTarget_freqbin_2G = {
2475 FREQ2FBIN(2412, 1),
2476 FREQ2FBIN(2437, 1),
2477 FREQ2FBIN(2472, 1)
2478 },
2479 .calTarget_freqbin_2GHT20 = {
2480 FREQ2FBIN(2412, 1),
2481 FREQ2FBIN(2437, 1),
2482 FREQ2FBIN(2472, 1)
2483 },
2484 .calTarget_freqbin_2GHT40 = {
2485 FREQ2FBIN(2412, 1),
2486 FREQ2FBIN(2437, 1),
2487 FREQ2FBIN(2472, 1)
2488 },
2489 .calTargetPowerCck = {
2490 /* 1L-5L,5S,11L,11S */
2491 { {34, 34, 34, 34} },
2492 { {34, 34, 34, 34} },
2493 },
2494 .calTargetPower2G = {
2495 /* 6-24,36,48,54 */
2496 { {34, 34, 32, 32} },
2497 { {34, 34, 32, 32} },
2498 { {34, 34, 32, 32} },
2499 },
2500 .calTargetPower2GHT20 = {
2501 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2502 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2503 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2504 },
2505 .calTargetPower2GHT40 = {
2506 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2507 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2508 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2509 },
2510 .ctlIndex_2G = {
2511 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2512 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2513 },
2514 .ctl_freqbin_2G = {
2515 {
2516 FREQ2FBIN(2412, 1),
2517 FREQ2FBIN(2417, 1),
2518 FREQ2FBIN(2457, 1),
2519 FREQ2FBIN(2462, 1)
2520 },
2521 {
2522 FREQ2FBIN(2412, 1),
2523 FREQ2FBIN(2417, 1),
2524 FREQ2FBIN(2462, 1),
2525 0xFF,
2526 },
2527
2528 {
2529 FREQ2FBIN(2412, 1),
2530 FREQ2FBIN(2417, 1),
2531 FREQ2FBIN(2462, 1),
2532 0xFF,
2533 },
2534 {
2535 FREQ2FBIN(2422, 1),
2536 FREQ2FBIN(2427, 1),
2537 FREQ2FBIN(2447, 1),
2538 FREQ2FBIN(2452, 1)
2539 },
2540
2541 {
2542 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2543 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2544 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2545 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2546 },
2547
2548 {
2549 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2550 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2551 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2552 0,
2553 },
2554
2555 {
2556 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2557 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2558 FREQ2FBIN(2472, 1),
2559 0,
2560 },
2561
2562 {
2563 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2564 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2565 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2566 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2567 },
2568
2569 {
2570 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2571 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2572 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2573 },
2574
2575 {
2576 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2577 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2578 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2579 0
2580 },
2581
2582 {
2583 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2584 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2585 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2586 0
2587 },
2588
2589 {
2590 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2591 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2592 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2593 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2594 }
2595 },
2596 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2597 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2599 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2600
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]2601 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2602 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2603 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2604
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2605 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2606 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2607 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2608
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2609 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2610 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2611 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2612 },
2613 .modalHeader5G = {
2614 /* 4 idle,t1,t2,b (4 bits per setting) */
2615 .antCtrlCommon = LE32(0x220),
2616 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2617 .antCtrlCommon2 = LE32(0x44444),
2618 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2619 .antCtrlChain = {
2620 LE16(0x150), LE16(0x150), LE16(0x150),
2621 },
2622 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2623 .xatten1DB = {0x19, 0x19, 0x19},
2624
2625 /*
2626 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2627 * for merlin (0xa20c/b20c 16:12
2628 */
2629 .xatten1Margin = {0x14, 0x14, 0x14},
2630 .tempSlope = 70,
2631 .voltSlope = 0,
2632 /* spurChans spur channels in usual fbin coding format */
2633 .spurChans = {0, 0, 0, 0, 0},
2634 /* noiseFloorThreshCh Check if the register is per chain */
2635 .noiseFloorThreshCh = {-1, 0, 0},
2636 .ob = {3, 3, 3}, /* 3 chain */
2637 .db_stage2 = {3, 3, 3}, /* 3 chain */
2638 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2639 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2640 .xpaBiasLvl = 0,
2641 .txFrameToDataStart = 0x0e,
2642 .txFrameToPaOn = 0x0e,
2643 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2644 .antennaGain = 0,
2645 .switchSettling = 0x2d,
2646 .adcDesiredSize = -30,
2647 .txEndToXpaOff = 0,
2648 .txEndToRxOn = 0x2,
2649 .txFrameToXpaOn = 0xe,
2650 .thresh62 = 28,
2651 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2652 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2653 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]2654 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2655 },
2656 },
2657 .base_ext2 = {
2658 .tempSlopeLow = 35,
2659 .tempSlopeHigh = 50,
2660 .xatten1DBLow = {0, 0, 0},
2661 .xatten1MarginLow = {0, 0, 0},
2662 .xatten1DBHigh = {0, 0, 0},
2663 .xatten1MarginHigh = {0, 0, 0}
2664 },
2665 .calFreqPier5G = {
2666 FREQ2FBIN(5180, 0),
2667 FREQ2FBIN(5220, 0),
2668 FREQ2FBIN(5320, 0),
2669 FREQ2FBIN(5400, 0),
2670 FREQ2FBIN(5500, 0),
2671 FREQ2FBIN(5600, 0),
2672 FREQ2FBIN(5700, 0),
2673 FREQ2FBIN(5785, 0)
2674 },
2675 .calPierData5G = {
2676 {
2677 {0, 0, 0, 0, 0},
2678 {0, 0, 0, 0, 0},
2679 {0, 0, 0, 0, 0},
2680 {0, 0, 0, 0, 0},
2681 {0, 0, 0, 0, 0},
2682 {0, 0, 0, 0, 0},
2683 {0, 0, 0, 0, 0},
2684 {0, 0, 0, 0, 0},
2685 },
2686 {
2687 {0, 0, 0, 0, 0},
2688 {0, 0, 0, 0, 0},
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 },
2696 {
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 {0, 0, 0, 0, 0},
2705 },
2706
2707 },
2708 .calTarget_freqbin_5G = {
2709 FREQ2FBIN(5180, 0),
2710 FREQ2FBIN(5240, 0),
2711 FREQ2FBIN(5320, 0),
2712 FREQ2FBIN(5400, 0),
2713 FREQ2FBIN(5500, 0),
2714 FREQ2FBIN(5600, 0),
2715 FREQ2FBIN(5700, 0),
2716 FREQ2FBIN(5825, 0)
2717 },
2718 .calTarget_freqbin_5GHT20 = {
2719 FREQ2FBIN(5180, 0),
2720 FREQ2FBIN(5240, 0),
2721 FREQ2FBIN(5320, 0),
2722 FREQ2FBIN(5400, 0),
2723 FREQ2FBIN(5500, 0),
2724 FREQ2FBIN(5700, 0),
2725 FREQ2FBIN(5745, 0),
2726 FREQ2FBIN(5825, 0)
2727 },
2728 .calTarget_freqbin_5GHT40 = {
2729 FREQ2FBIN(5180, 0),
2730 FREQ2FBIN(5240, 0),
2731 FREQ2FBIN(5320, 0),
2732 FREQ2FBIN(5400, 0),
2733 FREQ2FBIN(5500, 0),
2734 FREQ2FBIN(5700, 0),
2735 FREQ2FBIN(5745, 0),
2736 FREQ2FBIN(5825, 0)
2737 },
2738 .calTargetPower5G = {
2739 /* 6-24,36,48,54 */
2740 { {30, 30, 28, 24} },
2741 { {30, 30, 28, 24} },
2742 { {30, 30, 28, 24} },
2743 { {30, 30, 28, 24} },
2744 { {30, 30, 28, 24} },
2745 { {30, 30, 28, 24} },
2746 { {30, 30, 28, 24} },
2747 { {30, 30, 28, 24} },
2748 },
2749 .calTargetPower5GHT20 = {
2750 /*
2751 * 0_8_16,1-3_9-11_17-19,
2752 * 4,5,6,7,12,13,14,15,20,21,22,23
2753 */
2754 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2755 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2756 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2757 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2758 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2759 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2760 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2761 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2762 },
2763 .calTargetPower5GHT40 = {
2764 /*
2765 * 0_8_16,1-3_9-11_17-19,
2766 * 4,5,6,7,12,13,14,15,20,21,22,23
2767 */
2768 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2769 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2770 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2771 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2772 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2773 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2774 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2775 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2776 },
2777 .ctlIndex_5G = {
2778 0x10, 0x16, 0x18, 0x40, 0x46,
2779 0x48, 0x30, 0x36, 0x38
2780 },
2781 .ctl_freqbin_5G = {
2782 {
2783 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2784 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2785 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2786 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2787 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2788 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2789 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2790 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2791 },
2792 {
2793 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2794 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2795 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2796 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2797 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2798 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2799 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2800 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2801 },
2802
2803 {
2804 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2805 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2806 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2807 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2808 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2809 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2810 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2811 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2812 },
2813
2814 {
2815 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2816 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2817 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2818 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2819 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2820 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2821 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2822 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2823 },
2824
2825 {
2826 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2827 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2828 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2829 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2831 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2832 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2833 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2834 },
2835
2836 {
2837 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2838 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2839 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2840 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2841 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2842 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2843 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2844 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2845 },
2846
2847 {
2848 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2849 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2850 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2851 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2852 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2853 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2854 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2855 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2856 },
2857
2858 {
2859 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2860 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2861 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2862 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2863 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2864 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2865 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2866 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2867 },
2868
2869 {
2870 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2871 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2872 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2873 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2874 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2875 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2876 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2877 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2878 }
2879 },
2880 .ctlPowerData_5G = {
2881 {
2882 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2883 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2884 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2885 }
2886 },
2887 {
2888 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2889 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2890 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2891 }
2892 },
2893 {
2894 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2895 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2896 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2897 }
2898 },
2899 {
2900 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2901 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2902 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2903 }
2904 },
2905 {
2906 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2907 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2908 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2909 }
2910 },
2911 {
2912 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2913 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2914 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2915 }
2916 },
2917 {
2918 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2919 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2920 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2921 }
2922 },
2923 {
2924 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2925 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2926 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2927 }
2928 },
2929 {
2930 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2931 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2932 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2933 }
2934 },
2935 }
2936};
2937
2938
2939static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2940 &ar9300_default,
2941 &ar9300_x112,
2942 &ar9300_h116,
2943 &ar9300_h112,
2944 &ar9300_x113,
2945};
2946
2947static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2948{
2949#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2950 int it;
2951
2952 for (it = 0; it < N_LOOP; it++)
2953 if (ar9300_eep_templates[it]->templateVersion == id)
2954 return ar9300_eep_templates[it];
2955 return NULL;
2956#undef N_LOOP
2957}
2958
2959
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]2960static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2961{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2962 if (fbin == AR5416_BCHAN_UNUSED)
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]2963 return fbin;
2964
2965 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2966}
2967
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2968static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2969{
2970 return 0;
2971}
2972
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]2973static int interpolate(int x, int xa, int xb, int ya, int yb)
2974{
2975 int bf, factor, plus;
2976
2977 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2978 factor = bf / 2;
2979 plus = bf % 2;
2980 return ya + factor + plus;
2981}
2982
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2983static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2984 enum eeprom_param param)
2985{
2986 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2987 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2988
2989 switch (param) {
2990 case EEP_MAC_LSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2991 return get_unaligned_be16(eep->macAddr);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2992 case EEP_MAC_MID:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2993 return get_unaligned_be16(eep->macAddr + 2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2994 case EEP_MAC_MSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2995 return get_unaligned_be16(eep->macAddr + 4);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2996 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2997 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2998 case EEP_REG_1:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2999 return le16_to_cpu(pBase->regDmn[1]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3000 case EEP_OP_CAP:
3001 return pBase->deviceCap;
3002 case EEP_OP_MODE:
3003 return pBase->opCapFlags.opFlags;
3004 case EEP_RF_SILENT:
3005 return pBase->rfSilent;
3006 case EEP_TX_MASK:
3007 return (pBase->txrxMask >> 4) & 0xf;
3008 case EEP_RX_MASK:
3009 return pBase->txrxMask & 0xf;
3010 case EEP_DRIVE_STRENGTH:
3011#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3012 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3013 case EEP_INTERNAL_REGULATOR:
3014 /* Bit 4 is internal regulator flag */
3015 return (pBase->featureEnable & 0x10) >> 4;
3016 case EEP_SWREG:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3017 return le32_to_cpu(pBase->swreg);
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]3018 case EEP_PAPRD:
3019 return !!(pBase->featureEnable & BIT(5));
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +0530[diff] [blame]3020 case EEP_CHAIN_MASK_REDUCE:
3021 return (pBase->miscConfiguration >> 0x3) & 0x1;
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3022 case EEP_ANT_DIV_CTL1:
Rajkumar Manoharan5479de62011-07-17 11:43:02 +0530[diff] [blame]3023 return eep->base_ext1.ant_div_control;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame^]3024 case EEP_ANTENNA_GAIN_5G:
3025 return eep->modalHeader5G.antennaGain;
3026 case EEP_ANTENNA_GAIN_2G:
3027 return eep->modalHeader2G.antennaGain;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3028 default:
3029 return 0;
3030 }
3031}
3032
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3033static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3034 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3035{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3036 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3037
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3038 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3039 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3040
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3041 *buffer = (val >> (8 * (address % 2))) & 0xff;
3042 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3043}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3044
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3045static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3046 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3047{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3048 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3049
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3050 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3051 return false;
3052
3053 buffer[0] = val >> 8;
3054 buffer[1] = val & 0xff;
3055
3056 return true;
3057}
3058
3059static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3060 int count)
3061{
3062 struct ath_common *common = ath9k_hw_common(ah);
3063 int i;
3064
3065 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3066 ath_dbg(common, ATH_DBG_EEPROM,
3067 "eeprom address not in range\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3068 return false;
3069 }
3070
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3071 /*
3072 * Since we're reading the bytes in reverse order from a little-endian
3073 * word stream, an even address means we only use the lower half of
3074 * the 16-bit word at that address
3075 */
3076 if (address % 2 == 0) {
3077 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3078 goto error;
3079
3080 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3081 }
3082
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3083 for (i = 0; i < count / 2; i++) {
3084 if (!ar9300_eeprom_read_word(common, address, buffer))
3085 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3086
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3087 address -= 2;
3088 buffer += 2;
3089 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3090
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3091 if (count % 2)
3092 if (!ar9300_eeprom_read_byte(common, address, buffer))
3093 goto error;
3094
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3095 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3096
3097error:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3098 ath_dbg(common, ATH_DBG_EEPROM,
3099 "unable to read eeprom region at offset %d\n", address);
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3100 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3101}
3102
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3103static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3104{
3105 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3106
3107 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3108 AR9300_OTP_STATUS_VALID, 1000))
3109 return false;
3110
3111 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3112 return true;
3113}
3114
3115static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3116 int count)
3117{
3118 u32 data;
3119 int i;
3120
3121 for (i = 0; i < count; i++) {
3122 int offset = 8 * ((address - i) % 4);
3123 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3124 return false;
3125
3126 buffer[i] = (data >> offset) & 0xff;
3127 }
3128
3129 return true;
3130}
3131
3132
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3133static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3134 int *length, int *major, int *minor)
3135{
3136 unsigned long value[4];
3137
3138 value[0] = best[0];
3139 value[1] = best[1];
3140 value[2] = best[2];
3141 value[3] = best[3];
3142 *code = ((value[0] >> 5) & 0x0007);
3143 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3144 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3145 *major = (value[2] & 0x000f);
3146 *minor = (value[3] & 0x00ff);
3147}
3148
3149static u16 ar9300_comp_cksum(u8 *data, int dsize)
3150{
3151 int it, checksum = 0;
3152
3153 for (it = 0; it < dsize; it++) {
3154 checksum += data[it];
3155 checksum &= 0xffff;
3156 }
3157
3158 return checksum;
3159}
3160
3161static bool ar9300_uncompress_block(struct ath_hw *ah,
3162 u8 *mptr,
3163 int mdataSize,
3164 u8 *block,
3165 int size)
3166{
3167 int it;
3168 int spot;
3169 int offset;
3170 int length;
3171 struct ath_common *common = ath9k_hw_common(ah);
3172
3173 spot = 0;
3174
3175 for (it = 0; it < size; it += (length+2)) {
3176 offset = block[it];
3177 offset &= 0xff;
3178 spot += offset;
3179 length = block[it+1];
3180 length &= 0xff;
3181
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3182 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3183 ath_dbg(common, ATH_DBG_EEPROM,
3184 "Restore at %d: spot=%d offset=%d length=%d\n",
3185 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3186 memcpy(&mptr[spot], &block[it+2], length);
3187 spot += length;
3188 } else if (length > 0) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3189 ath_dbg(common, ATH_DBG_EEPROM,
3190 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3191 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3192 return false;
3193 }
3194 }
3195 return true;
3196}
3197
3198static int ar9300_compress_decision(struct ath_hw *ah,
3199 int it,
3200 int code,
3201 int reference,
3202 u8 *mptr,
3203 u8 *word, int length, int mdata_size)
3204{
3205 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3206 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3207
3208 switch (code) {
3209 case _CompressNone:
3210 if (length != mdata_size) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3211 ath_dbg(common, ATH_DBG_EEPROM,
3212 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3213 mdata_size, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3214 return -1;
3215 }
3216 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3217 ath_dbg(common, ATH_DBG_EEPROM,
3218 "restored eeprom %d: uncompressed, length %d\n",
3219 it, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3220 break;
3221 case _CompressBlock:
3222 if (reference == 0) {
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3223 } else {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3224 eep = ar9003_eeprom_struct_find_by_id(reference);
3225 if (eep == NULL) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3226 ath_dbg(common, ATH_DBG_EEPROM,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]3227 "can't find reference eeprom struct %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3228 reference);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3229 return -1;
3230 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3231 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3232 }
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3233 ath_dbg(common, ATH_DBG_EEPROM,
3234 "restore eeprom %d: block, reference %d, length %d\n",
3235 it, reference, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3236 ar9300_uncompress_block(ah, mptr, mdata_size,
3237 (u8 *) (word + COMP_HDR_LEN), length);
3238 break;
3239 default:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3240 ath_dbg(common, ATH_DBG_EEPROM,
3241 "unknown compression code %d\n", code);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3242 return -1;
3243 }
3244 return 0;
3245}
3246
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3247typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3248 int count);
3249
3250static bool ar9300_check_header(void *data)
3251{
3252 u32 *word = data;
3253 return !(*word == 0 || *word == ~0);
3254}
3255
3256static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3257 int base_addr)
3258{
3259 u8 header[4];
3260
3261 if (!read(ah, base_addr, header, 4))
3262 return false;
3263
3264 return ar9300_check_header(header);
3265}
3266
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3267static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3268 int mdata_size)
3269{
3270 struct ath_common *common = ath9k_hw_common(ah);
3271 u16 *data = (u16 *) mptr;
3272 int i;
3273
3274 for (i = 0; i < mdata_size / 2; i++, data++)
3275 ath9k_hw_nvram_read(common, i, data);
3276
3277 return 0;
3278}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3279/*
3280 * Read the configuration data from the eeprom.
3281 * The data can be put in any specified memory buffer.
3282 *
3283 * Returns -1 on error.
3284 * Returns address of next memory location on success.
3285 */
3286static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3287 u8 *mptr, int mdata_size)
3288{
3289#define MDEFAULT 15
3290#define MSTATE 100
3291 int cptr;
3292 u8 *word;
3293 int code;
3294 int reference, length, major, minor;
3295 int osize;
3296 int it;
3297 u16 checksum, mchecksum;
3298 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3299 eeprom_read_op read;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3300
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3301 if (ath9k_hw_use_flash(ah))
3302 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3303
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3304 word = kzalloc(2048, GFP_KERNEL);
3305 if (!word)
Larry Finger1ba45b92011-08-27 13:56:00 -0500[diff] [blame]3306 return -ENOMEM;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3307
3308 memcpy(mptr, &ar9300_default, mdata_size);
3309
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3310 read = ar9300_read_eeprom;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3311 if (AR_SREV_9485(ah))
3312 cptr = AR9300_BASE_ADDR_4K;
Gabor Juhos5b5c0332011-06-21 11:23:38 +0200[diff] [blame]3313 else if (AR_SREV_9330(ah))
3314 cptr = AR9300_BASE_ADDR_512;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3315 else
3316 cptr = AR9300_BASE_ADDR;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3317 ath_dbg(common, ATH_DBG_EEPROM,
Justin P. Mattock70f23fd2011-05-10 10:16:21 +0200[diff] [blame]3318 "Trying EEPROM access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3319 if (ar9300_check_eeprom_header(ah, read, cptr))
3320 goto found;
3321
3322 cptr = AR9300_BASE_ADDR_512;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3323 ath_dbg(common, ATH_DBG_EEPROM,
Justin P. Mattock70f23fd2011-05-10 10:16:21 +0200[diff] [blame]3324 "Trying EEPROM access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3325 if (ar9300_check_eeprom_header(ah, read, cptr))
3326 goto found;
3327
3328 read = ar9300_read_otp;
3329 cptr = AR9300_BASE_ADDR;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3330 ath_dbg(common, ATH_DBG_EEPROM,
Justin P. Mattock70f23fd2011-05-10 10:16:21 +0200[diff] [blame]3331 "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3332 if (ar9300_check_eeprom_header(ah, read, cptr))
3333 goto found;
3334
3335 cptr = AR9300_BASE_ADDR_512;
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3336 ath_dbg(common, ATH_DBG_EEPROM,
Justin P. Mattock70f23fd2011-05-10 10:16:21 +0200[diff] [blame]3337 "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3338 if (ar9300_check_eeprom_header(ah, read, cptr))
3339 goto found;
3340
3341 goto fail;
3342
3343found:
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3344 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3345
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3346 for (it = 0; it < MSTATE; it++) {
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3347 if (!read(ah, cptr, word, COMP_HDR_LEN))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3348 goto fail;
3349
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3350 if (!ar9300_check_header(word))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3351 break;
3352
3353 ar9300_comp_hdr_unpack(word, &code, &reference,
3354 &length, &major, &minor);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3355 ath_dbg(common, ATH_DBG_EEPROM,
3356 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3357 cptr, code, reference, length, major, minor);
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3358 if ((!AR_SREV_9485(ah) && length >= 1024) ||
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]3359 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3360 ath_dbg(common, ATH_DBG_EEPROM,
3361 "Skipping bad header\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3362 cptr -= COMP_HDR_LEN;
3363 continue;
3364 }
3365
3366 osize = length;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3367 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3368 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]3369 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3370 ath_dbg(common, ATH_DBG_EEPROM,
3371 "checksum %x %x\n", checksum, mchecksum);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3372 if (checksum == mchecksum) {
3373 ar9300_compress_decision(ah, it, code, reference, mptr,
3374 word, length, mdata_size);
3375 } else {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3376 ath_dbg(common, ATH_DBG_EEPROM,
3377 "skipping block with bad checksum\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3378 }
3379 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3380 }
3381
3382 kfree(word);
3383 return cptr;
3384
3385fail:
3386 kfree(word);
3387 return -1;
3388}
3389
3390/*
3391 * Restore the configuration structure by reading the eeprom.
3392 * This function destroys any existing in-memory structure
3393 * content.
3394 */
3395static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3396{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3397 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3398
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3399 if (ar9300_eeprom_restore_internal(ah, mptr,
3400 sizeof(struct ar9300_eeprom)) < 0)
3401 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3402
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3403 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3404}
3405
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3406#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3407static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3408 struct ar9300_modal_eep_header *modal_hdr)
3409{
3410 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3411 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3412 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3413 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3414 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3415 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3416 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3417 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3418 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3419 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3420 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3421 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3422 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3423 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3424 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3425 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3426 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3427 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3428 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3429 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3430 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3431 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3432 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3433 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3434 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3435 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3436 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3437 PR_EEP("txClip", modal_hdr->txClip);
3438 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3439 PR_EEP("Chain0 ob", modal_hdr->ob[0]);
3440 PR_EEP("Chain1 ob", modal_hdr->ob[1]);
3441 PR_EEP("Chain2 ob", modal_hdr->ob[2]);
3442
3443 PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]);
3444 PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]);
3445 PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]);
3446 PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]);
3447 PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]);
3448 PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]);
3449 PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]);
3450 PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]);
3451 PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]);
3452
3453 return len;
3454}
3455
3456static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3457 u8 *buf, u32 len, u32 size)
3458{
3459 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3460 struct ar9300_base_eep_hdr *pBase;
3461
3462 if (!dump_base_hdr) {
3463 len += snprintf(buf + len, size - len,
3464 "%20s :\n", "2GHz modal Header");
3465 len += ar9003_dump_modal_eeprom(buf, len, size,
3466 &eep->modalHeader2G);
3467 len += snprintf(buf + len, size - len,
3468 "%20s :\n", "5GHz modal Header");
3469 len += ar9003_dump_modal_eeprom(buf, len, size,
3470 &eep->modalHeader5G);
3471 goto out;
3472 }
3473
3474 pBase = &eep->baseEepHeader;
3475
3476 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3477 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3478 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3479 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3480 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3481 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3482 AR5416_OPFLAGS_11A));
3483 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3484 AR5416_OPFLAGS_11G));
3485 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3486 AR5416_OPFLAGS_N_2G_HT20));
3487 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3488 AR5416_OPFLAGS_N_2G_HT40));
3489 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3490 AR5416_OPFLAGS_N_5G_HT20));
3491 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3492 AR5416_OPFLAGS_N_5G_HT40));
3493 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3494 PR_EEP("RF Silent", pBase->rfSilent);
3495 PR_EEP("BT option", pBase->blueToothOptions);
3496 PR_EEP("Device Cap", pBase->deviceCap);
3497 PR_EEP("Device Type", pBase->deviceType);
3498 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3499 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3500 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3501 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3502 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3503 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3504 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3505 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3506 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3507 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3508 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3509 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3510 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3511 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3512 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3513 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3514 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3515 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3516
3517 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3518 ah->eeprom.ar9300_eep.macAddr);
3519out:
3520 if (len > size)
3521 len = size;
3522
3523 return len;
3524}
3525#else
3526static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3527 u8 *buf, u32 len, u32 size)
3528{
3529 return 0;
3530}
3531#endif
3532
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3533/* XXX: review hardware docs */
3534static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3535{
3536 return ah->eeprom.ar9300_eep.eepromVersion;
3537}
3538
3539/* XXX: could be read from the eepromVersion, not sure yet */
3540static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3541{
3542 return 0;
3543}
3544
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3545static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3546{
3547 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3548
3549 if (is2ghz)
3550 return eep->modalHeader2G.xpaBiasLvl;
3551 else
3552 return eep->modalHeader5G.xpaBiasLvl;
3553}
3554
3555static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3556{
3557 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3558
Gabor Juhosdc9aa5f2011-06-21 11:23:39 +0200[diff] [blame]3559 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3560 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3561 else if (AR_SREV_9480(ah))
3562 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3563 else {
3564 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Rajkumar Manoharan165af962011-05-09 19:11:26 +0530[diff] [blame]3565 REG_RMW_FIELD(ah, AR_CH0_THERM,
3566 AR_CH0_THERM_XPABIASLVL_MSB,
3567 bias >> 2);
3568 REG_RMW_FIELD(ah, AR_CH0_THERM,
3569 AR_CH0_THERM_XPASHORT2GND, 1);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3570 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3571}
3572
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3573static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3574{
3575 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3576 __le32 val;
3577
3578 if (is_2ghz)
3579 val = eep->modalHeader2G.switchcomspdt;
3580 else
3581 val = eep->modalHeader5G.switchcomspdt;
3582 return le32_to_cpu(val);
3583}
3584
3585
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3586static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3587{
3588 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3589 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3590
3591 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3592 val = eep->modalHeader2G.antCtrlCommon;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3593 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3594 val = eep->modalHeader5G.antCtrlCommon;
3595 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3596}
3597
3598static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3599{
3600 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3601 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3602
3603 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3604 val = eep->modalHeader2G.antCtrlCommon2;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3605 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3606 val = eep->modalHeader5G.antCtrlCommon2;
3607 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3608}
3609
3610static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3611 int chain,
3612 bool is2ghz)
3613{
3614 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3615 __le16 val = 0;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3616
3617 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3618 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3619 val = eep->modalHeader2G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3620 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3621 val = eep->modalHeader5G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3622 }
3623
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3624 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3625}
3626
3627static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3628{
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3629 int chain;
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3630 u32 regval;
3631 u32 ant_div_ctl1;
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3632 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3633 AR_PHY_SWITCH_CHAIN_0,
3634 AR_PHY_SWITCH_CHAIN_1,
3635 AR_PHY_SWITCH_CHAIN_2,
3636 };
3637
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3638 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3639
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3640 if (AR_SREV_9480(ah)) {
3641 if (AR_SREV_9480_10(ah)) {
3642 value &= ~AR_SWITCH_TABLE_COM_SPDT;
3643 value |= 0x00100000;
3644 }
3645 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3646 AR_SWITCH_TABLE_COM_AR9480_ALL, value);
3647 } else
3648 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3649 AR_SWITCH_TABLE_COM_ALL, value);
3650
3651
3652 /*
3653 * AR9480 defines new switch table for BT/WLAN,
3654 * here's new field name in XXX.ref for both 2G and 5G.
3655 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3656 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3657 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3658 *
3659 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3660 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3661 *
3662 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3663 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3664 */
3665 if (AR_SREV_9480_20_OR_LATER(ah)) {
3666 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3667 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3668 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3669 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3670
3671 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3672 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3673
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3674 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3675 if ((ah->rxchainmask & BIT(chain)) ||
3676 (ah->txchainmask & BIT(chain))) {
3677 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3678 is2ghz);
3679 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3680 AR_SWITCH_TABLE_ALL, value);
3681 }
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3682 }
3683
Gabor Juhos7b09e492011-06-21 11:23:49 +0200[diff] [blame]3684 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3685 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3686 /*
3687 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3688 * are the fields present
3689 */
3690 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3691 regval &= (~AR_ANT_DIV_CTRL_ALL);
3692 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3693 /* enable_lnadiv */
3694 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3695 regval |= ((value >> 6) & 0x1) <<
3696 AR_PHY_9485_ANT_DIV_LNADIV_S;
3697 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3698
3699 /*enable fast_div */
3700 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3701 regval &= (~AR_FAST_DIV_ENABLE);
3702 regval |= ((value >> 7) & 0x1) <<
3703 AR_FAST_DIV_ENABLE_S;
3704 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3705 ant_div_ctl1 =
3706 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3707 /* check whether antenna diversity is enabled */
3708 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3709 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3710 /*
3711 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3712 * main_tb, alt_tb
3713 */
3714 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3715 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3716 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3717 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3718 /* by default use LNA1 for the main antenna */
3719 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3720 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3721 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3722 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3723 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3724 }
3725
3726
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3727 }
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3728
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3729}
3730
3731static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3732{
3733 int drive_strength;
3734 unsigned long reg;
3735
3736 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3737
3738 if (!drive_strength)
3739 return;
3740
3741 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3742 reg &= ~0x00ffffc0;
3743 reg |= 0x5 << 21;
3744 reg |= 0x5 << 18;
3745 reg |= 0x5 << 15;
3746 reg |= 0x5 << 12;
3747 reg |= 0x5 << 9;
3748 reg |= 0x5 << 6;
3749 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3750
3751 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3752 reg &= ~0xffffffe0;
3753 reg |= 0x5 << 29;
3754 reg |= 0x5 << 26;
3755 reg |= 0x5 << 23;
3756 reg |= 0x5 << 20;
3757 reg |= 0x5 << 17;
3758 reg |= 0x5 << 14;
3759 reg |= 0x5 << 11;
3760 reg |= 0x5 << 8;
3761 reg |= 0x5 << 5;
3762 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3763
3764 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3765 reg &= ~0xff800000;
3766 reg |= 0x5 << 29;
3767 reg |= 0x5 << 26;
3768 reg |= 0x5 << 23;
3769 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3770}
3771
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3772static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3773 struct ath9k_channel *chan)
3774{
3775 int f[3], t[3];
3776 u16 value;
3777 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3778
3779 if (chain >= 0 && chain < 3) {
3780 if (IS_CHAN_2GHZ(chan))
3781 return eep->modalHeader2G.xatten1DB[chain];
3782 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3783 t[0] = eep->base_ext2.xatten1DBLow[chain];
3784 f[0] = 5180;
3785 t[1] = eep->modalHeader5G.xatten1DB[chain];
3786 f[1] = 5500;
3787 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3788 f[2] = 5785;
3789 value = ar9003_hw_power_interpolate((s32) chan->channel,
3790 f, t, 3);
3791 return value;
3792 } else
3793 return eep->modalHeader5G.xatten1DB[chain];
3794 }
3795
3796 return 0;
3797}
3798
3799
3800static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3801 struct ath9k_channel *chan)
3802{
3803 int f[3], t[3];
3804 u16 value;
3805 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3806
3807 if (chain >= 0 && chain < 3) {
3808 if (IS_CHAN_2GHZ(chan))
3809 return eep->modalHeader2G.xatten1Margin[chain];
3810 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3811 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3812 f[0] = 5180;
3813 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3814 f[1] = 5500;
3815 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3816 f[2] = 5785;
3817 value = ar9003_hw_power_interpolate((s32) chan->channel,
3818 f, t, 3);
3819 return value;
3820 } else
3821 return eep->modalHeader5G.xatten1Margin[chain];
3822 }
3823
3824 return 0;
3825}
3826
3827static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3828{
3829 int i;
3830 u16 value;
3831 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3832 AR_PHY_EXT_ATTEN_CTL_1,
3833 AR_PHY_EXT_ATTEN_CTL_2,
3834 };
3835
3836 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3837 for (i = 0; i < 3; i++) {
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3838 if (ah->txchainmask & BIT(i)) {
3839 value = ar9003_hw_atten_chain_get(ah, i, chan);
3840 REG_RMW_FIELD(ah, ext_atten_reg[i],
3841 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3842
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3843 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3844 REG_RMW_FIELD(ah, ext_atten_reg[i],
3845 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3846 value);
3847 }
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3848 }
3849}
3850
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3851static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3852{
3853 int timeout = 100;
3854
3855 while (pmu_set != REG_READ(ah, pmu_reg)) {
3856 if (timeout-- == 0)
3857 return false;
3858 REG_WRITE(ah, pmu_reg, pmu_set);
3859 udelay(10);
3860 }
3861
3862 return true;
3863}
3864
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3865static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3866{
3867 int internal_regulator =
3868 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3869 u32 reg_val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3870
3871 if (internal_regulator) {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3872 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3873 int reg_pmu_set;
3874
3875 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3876 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3877 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3878 return;
3879
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3880 if (AR_SREV_9330(ah)) {
3881 if (ah->is_clk_25mhz) {
3882 reg_pmu_set = (3 << 1) | (8 << 4) |
3883 (3 << 8) | (1 << 14) |
3884 (6 << 17) | (1 << 20) |
3885 (3 << 24);
3886 } else {
3887 reg_pmu_set = (4 << 1) | (7 << 4) |
3888 (3 << 8) | (1 << 14) |
3889 (6 << 17) | (1 << 20) |
3890 (3 << 24);
3891 }
3892 } else {
3893 reg_pmu_set = (5 << 1) | (7 << 4) |
Rajkumar Manoharan1fa707a2011-07-29 17:38:17 +0530[diff] [blame]3894 (2 << 8) | (2 << 14) |
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3895 (6 << 17) | (1 << 20) |
3896 (3 << 24) | (1 << 28);
3897 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3898
3899 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3900 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3901 return;
3902
3903 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3904 | (4 << 26);
3905 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3906 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3907 return;
3908
3909 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3910 | (1 << 21);
3911 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3912 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3913 return;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3914 } else if (AR_SREV_9480(ah)) {
3915 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3916 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3917 } else {
3918 /* Internal regulator is ON. Write swreg register. */
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3919 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3920 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3921 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3922 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3923 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3924 /* Set REG_CONTROL1.SWREG_PROGRAM */
3925 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3926 REG_READ(ah,
3927 AR_RTC_REG_CONTROL1) |
3928 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3929 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3930 } else {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3931 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3932 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3933 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3934 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3935 udelay(10);
3936
3937 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3938 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3939 AR_PHY_PMU1_PWD))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3940 udelay(10);
3941 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3942 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3943 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3944 udelay(10);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3945 } else if (AR_SREV_9480(ah))
3946 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3947 else {
3948 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3949 AR_RTC_FORCE_SWREG_PRD;
3950 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3951 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3952 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3953
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3954}
3955
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3956static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3957{
3958 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3959 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3960
3961 if (eep->baseEepHeader.featureEnable & 0x40) {
3962 tuning_caps_param &= 0x7f;
3963 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3964 tuning_caps_param);
3965 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3966 tuning_caps_param);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3967 }
3968}
3969
3970static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3971 struct ath9k_channel *chan)
3972{
3973 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3974 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3975 ar9003_hw_drive_strength_apply(ah);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3976 ar9003_hw_atten_apply(ah, chan);
Gabor Juhos7dc59662011-06-21 11:23:36 +0200[diff] [blame]3977 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
Vasanthakumar Thiagarajan3594bea2011-04-19 19:29:12 +0530[diff] [blame]3978 ar9003_hw_internal_regulator_apply(ah);
Gabor Juhos7d790a212011-06-21 11:23:37 +0200[diff] [blame]3979 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3980 ar9003_hw_apply_tuning_caps(ah);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3981}
3982
3983static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3984 struct ath9k_channel *chan)
3985{
3986}
3987
3988/*
3989 * Returns the interpolated y value corresponding to the specified x value
3990 * from the np ordered pairs of data (px,py).
3991 * The pairs do not have to be in any order.
3992 * If the specified x value is less than any of the px,
3993 * the returned y value is equal to the py for the lowest px.
3994 * If the specified x value is greater than any of the px,
3995 * the returned y value is equal to the py for the highest px.
3996 */
3997static int ar9003_hw_power_interpolate(int32_t x,
3998 int32_t *px, int32_t *py, u_int16_t np)
3999{
4000 int ip = 0;
4001 int lx = 0, ly = 0, lhave = 0;
4002 int hx = 0, hy = 0, hhave = 0;
4003 int dx = 0;
4004 int y = 0;
4005
4006 lhave = 0;
4007 hhave = 0;
4008
4009 /* identify best lower and higher x calibration measurement */
4010 for (ip = 0; ip < np; ip++) {
4011 dx = x - px[ip];
4012
4013 /* this measurement is higher than our desired x */
4014 if (dx <= 0) {
4015 if (!hhave || dx > (x - hx)) {
4016 /* new best higher x measurement */
4017 hx = px[ip];
4018 hy = py[ip];
4019 hhave = 1;
4020 }
4021 }
4022 /* this measurement is lower than our desired x */
4023 if (dx >= 0) {
4024 if (!lhave || dx < (x - lx)) {
4025 /* new best lower x measurement */
4026 lx = px[ip];
4027 ly = py[ip];
4028 lhave = 1;
4029 }
4030 }
4031 }
4032
4033 /* the low x is good */
4034 if (lhave) {
4035 /* so is the high x */
4036 if (hhave) {
4037 /* they're the same, so just pick one */
4038 if (hx == lx)
4039 y = ly;
4040 else /* interpolate */
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4041 y = interpolate(x, lx, hx, ly, hy);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4042 } else /* only low is good, use it */
4043 y = ly;
4044 } else if (hhave) /* only high is good, use it */
4045 y = hy;
4046 else /* nothing is good,this should never happen unless np=0, ???? */
4047 y = -(1 << 30);
4048 return y;
4049}
4050
4051static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4052 u16 rateIndex, u16 freq, bool is2GHz)
4053{
4054 u16 numPiers, i;
4055 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4056 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4057 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4058 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4059 u8 *pFreqBin;
4060
4061 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4062 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4063 pEepromTargetPwr = eep->calTargetPower2G;
4064 pFreqBin = eep->calTarget_freqbin_2G;
4065 } else {
4066 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4067 pEepromTargetPwr = eep->calTargetPower5G;
4068 pFreqBin = eep->calTarget_freqbin_5G;
4069 }
4070
4071 /*
4072 * create array of channels and targetpower from
4073 * targetpower piers stored on eeprom
4074 */
4075 for (i = 0; i < numPiers; i++) {
4076 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4077 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4078 }
4079
4080 /* interpolate to get target power for given frequency */
4081 return (u8) ar9003_hw_power_interpolate((s32) freq,
4082 freqArray,
4083 targetPowerArray, numPiers);
4084}
4085
4086static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4087 u16 rateIndex,
4088 u16 freq, bool is2GHz)
4089{
4090 u16 numPiers, i;
4091 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4092 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4093 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4094 struct cal_tgt_pow_ht *pEepromTargetPwr;
4095 u8 *pFreqBin;
4096
4097 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4098 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4099 pEepromTargetPwr = eep->calTargetPower2GHT20;
4100 pFreqBin = eep->calTarget_freqbin_2GHT20;
4101 } else {
4102 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4103 pEepromTargetPwr = eep->calTargetPower5GHT20;
4104 pFreqBin = eep->calTarget_freqbin_5GHT20;
4105 }
4106
4107 /*
4108 * create array of channels and targetpower
4109 * from targetpower piers stored on eeprom
4110 */
4111 for (i = 0; i < numPiers; i++) {
4112 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4113 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4114 }
4115
4116 /* interpolate to get target power for given frequency */
4117 return (u8) ar9003_hw_power_interpolate((s32) freq,
4118 freqArray,
4119 targetPowerArray, numPiers);
4120}
4121
4122static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4123 u16 rateIndex,
4124 u16 freq, bool is2GHz)
4125{
4126 u16 numPiers, i;
4127 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4128 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4129 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4130 struct cal_tgt_pow_ht *pEepromTargetPwr;
4131 u8 *pFreqBin;
4132
4133 if (is2GHz) {
4134 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4135 pEepromTargetPwr = eep->calTargetPower2GHT40;
4136 pFreqBin = eep->calTarget_freqbin_2GHT40;
4137 } else {
4138 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4139 pEepromTargetPwr = eep->calTargetPower5GHT40;
4140 pFreqBin = eep->calTarget_freqbin_5GHT40;
4141 }
4142
4143 /*
4144 * create array of channels and targetpower from
4145 * targetpower piers stored on eeprom
4146 */
4147 for (i = 0; i < numPiers; i++) {
4148 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4149 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4150 }
4151
4152 /* interpolate to get target power for given frequency */
4153 return (u8) ar9003_hw_power_interpolate((s32) freq,
4154 freqArray,
4155 targetPowerArray, numPiers);
4156}
4157
4158static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4159 u16 rateIndex, u16 freq)
4160{
4161 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4162 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4163 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4164 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4165 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4166 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4167
4168 /*
4169 * create array of channels and targetpower from
4170 * targetpower piers stored on eeprom
4171 */
4172 for (i = 0; i < numPiers; i++) {
4173 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4174 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4175 }
4176
4177 /* interpolate to get target power for given frequency */
4178 return (u8) ar9003_hw_power_interpolate((s32) freq,
4179 freqArray,
4180 targetPowerArray, numPiers);
4181}
4182
4183/* Set tx power registers to array of values passed in */
4184static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4185{
4186#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4187 /* make sure forced gain is not set */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4188 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4189
4190 /* Write the OFDM power per rate set */
4191
4192 /* 6 (LSB), 9, 12, 18 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4193 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4194 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4195 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4196 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4197 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4198
4199 /* 24 (LSB), 36, 48, 54 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4200 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4201 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4202 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4203 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4204 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4205
4206 /* Write the CCK power per rate set */
4207
4208 /* 1L (LSB), reserved, 2L, 2S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4209 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4210 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4211 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4212 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4213 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4214
4215 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4216 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4217 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4218 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4219 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4220 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4221 );
4222
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4223 /* Write the power for duplicated frames - HT40 */
4224
4225 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
Alex Hacker8d7763b2011-08-03 17:41:54 +0600[diff] [blame]4226 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4227 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4228 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4229 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4230 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4231 );
4232
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4233 /* Write the HT20 power per rate set */
4234
4235 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4236 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4237 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4238 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4239 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4240 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4241 );
4242
4243 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4244 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4245 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4246 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4247 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4248 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4249 );
4250
4251 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4252 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4253 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4254 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4255 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4256 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4257 );
4258
4259 /* Mixed HT20 and HT40 rates */
4260
4261 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4262 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4263 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4264 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4265 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4266 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4267 );
4268
4269 /*
4270 * Write the HT40 power per rate set
4271 * correct PAR difference between HT40 and HT20/LEGACY
4272 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4273 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4274 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4275 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4276 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4277 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4278 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4279 );
4280
4281 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4282 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4283 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4284 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4285 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4286 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4287 );
4288
4289 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4290 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4291 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4292 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4293 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4294 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4295 );
4296
4297 return 0;
4298#undef POW_SM
4299}
4300
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4301static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4302 u8 *targetPowerValT2)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4303{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4304 /* XXX: hard code for now, need to get from eeprom struct */
4305 u8 ht40PowerIncForPdadc = 0;
4306 bool is2GHz = false;
4307 unsigned int i = 0;
4308 struct ath_common *common = ath9k_hw_common(ah);
4309
4310 if (freq < 4000)
4311 is2GHz = true;
4312
4313 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4314 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4315 is2GHz);
4316 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4317 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4318 is2GHz);
4319 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4320 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4321 is2GHz);
4322 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4323 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4324 is2GHz);
4325 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4326 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4327 freq);
4328 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4329 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4330 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4331 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4332 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4333 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4334 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4335 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4336 is2GHz);
4337 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4338 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4339 freq, is2GHz);
4340 targetPowerValT2[ALL_TARGET_HT20_4] =
4341 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4342 is2GHz);
4343 targetPowerValT2[ALL_TARGET_HT20_5] =
4344 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4345 is2GHz);
4346 targetPowerValT2[ALL_TARGET_HT20_6] =
4347 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4348 is2GHz);
4349 targetPowerValT2[ALL_TARGET_HT20_7] =
4350 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4351 is2GHz);
4352 targetPowerValT2[ALL_TARGET_HT20_12] =
4353 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4354 is2GHz);
4355 targetPowerValT2[ALL_TARGET_HT20_13] =
4356 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4357 is2GHz);
4358 targetPowerValT2[ALL_TARGET_HT20_14] =
4359 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4360 is2GHz);
4361 targetPowerValT2[ALL_TARGET_HT20_15] =
4362 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4363 is2GHz);
4364 targetPowerValT2[ALL_TARGET_HT20_20] =
4365 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4366 is2GHz);
4367 targetPowerValT2[ALL_TARGET_HT20_21] =
4368 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4369 is2GHz);
4370 targetPowerValT2[ALL_TARGET_HT20_22] =
4371 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4372 is2GHz);
4373 targetPowerValT2[ALL_TARGET_HT20_23] =
4374 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4375 is2GHz);
4376 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4377 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4378 is2GHz) + ht40PowerIncForPdadc;
4379 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4380 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4381 freq,
4382 is2GHz) + ht40PowerIncForPdadc;
4383 targetPowerValT2[ALL_TARGET_HT40_4] =
4384 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4385 is2GHz) + ht40PowerIncForPdadc;
4386 targetPowerValT2[ALL_TARGET_HT40_5] =
4387 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4388 is2GHz) + ht40PowerIncForPdadc;
4389 targetPowerValT2[ALL_TARGET_HT40_6] =
4390 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4391 is2GHz) + ht40PowerIncForPdadc;
4392 targetPowerValT2[ALL_TARGET_HT40_7] =
4393 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4394 is2GHz) + ht40PowerIncForPdadc;
4395 targetPowerValT2[ALL_TARGET_HT40_12] =
4396 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4397 is2GHz) + ht40PowerIncForPdadc;
4398 targetPowerValT2[ALL_TARGET_HT40_13] =
4399 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4400 is2GHz) + ht40PowerIncForPdadc;
4401 targetPowerValT2[ALL_TARGET_HT40_14] =
4402 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4403 is2GHz) + ht40PowerIncForPdadc;
4404 targetPowerValT2[ALL_TARGET_HT40_15] =
4405 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4406 is2GHz) + ht40PowerIncForPdadc;
4407 targetPowerValT2[ALL_TARGET_HT40_20] =
4408 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4409 is2GHz) + ht40PowerIncForPdadc;
4410 targetPowerValT2[ALL_TARGET_HT40_21] =
4411 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4412 is2GHz) + ht40PowerIncForPdadc;
4413 targetPowerValT2[ALL_TARGET_HT40_22] =
4414 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4415 is2GHz) + ht40PowerIncForPdadc;
4416 targetPowerValT2[ALL_TARGET_HT40_23] =
4417 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4418 is2GHz) + ht40PowerIncForPdadc;
4419
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4420 for (i = 0; i < ar9300RateSize; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4421 ath_dbg(common, ATH_DBG_EEPROM,
4422 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4423 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4424}
4425
4426static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4427 int mode,
4428 int ipier,
4429 int ichain,
4430 int *pfrequency,
4431 int *pcorrection,
4432 int *ptemperature, int *pvoltage)
4433{
4434 u8 *pCalPier;
4435 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4436 int is2GHz;
4437 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4438 struct ath_common *common = ath9k_hw_common(ah);
4439
4440 if (ichain >= AR9300_MAX_CHAINS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4441 ath_dbg(common, ATH_DBG_EEPROM,
4442 "Invalid chain index, must be less than %d\n",
4443 AR9300_MAX_CHAINS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4444 return -1;
4445 }
4446
4447 if (mode) { /* 5GHz */
4448 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4449 ath_dbg(common, ATH_DBG_EEPROM,
4450 "Invalid 5GHz cal pier index, must be less than %d\n",
4451 AR9300_NUM_5G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4452 return -1;
4453 }
4454 pCalPier = &(eep->calFreqPier5G[ipier]);
4455 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4456 is2GHz = 0;
4457 } else {
4458 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4459 ath_dbg(common, ATH_DBG_EEPROM,
4460 "Invalid 2GHz cal pier index, must be less than %d\n",
4461 AR9300_NUM_2G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4462 return -1;
4463 }
4464
4465 pCalPier = &(eep->calFreqPier2G[ipier]);
4466 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4467 is2GHz = 1;
4468 }
4469
4470 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4471 *pcorrection = pCalPierStruct->refPower;
4472 *ptemperature = pCalPierStruct->tempMeas;
4473 *pvoltage = pCalPierStruct->voltMeas;
4474
4475 return 0;
4476}
4477
4478static int ar9003_hw_power_control_override(struct ath_hw *ah,
4479 int frequency,
4480 int *correction,
4481 int *voltage, int *temperature)
4482{
4483 int tempSlope = 0;
4484 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4485 int f[3], t[3];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4486
4487 REG_RMW(ah, AR_PHY_TPC_11_B0,
4488 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4489 AR_PHY_TPC_OLPC_GAIN_DELTA);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4490 if (ah->caps.tx_chainmask & BIT(1))
4491 REG_RMW(ah, AR_PHY_TPC_11_B1,
4492 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4493 AR_PHY_TPC_OLPC_GAIN_DELTA);
4494 if (ah->caps.tx_chainmask & BIT(2))
4495 REG_RMW(ah, AR_PHY_TPC_11_B2,
4496 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4497 AR_PHY_TPC_OLPC_GAIN_DELTA);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4498
4499 /* enable open loop power control on chip */
4500 REG_RMW(ah, AR_PHY_TPC_6_B0,
4501 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4502 AR_PHY_TPC_6_ERROR_EST_MODE);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4503 if (ah->caps.tx_chainmask & BIT(1))
4504 REG_RMW(ah, AR_PHY_TPC_6_B1,
4505 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4506 AR_PHY_TPC_6_ERROR_EST_MODE);
4507 if (ah->caps.tx_chainmask & BIT(2))
4508 REG_RMW(ah, AR_PHY_TPC_6_B2,
4509 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4510 AR_PHY_TPC_6_ERROR_EST_MODE);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4511
4512 /*
4513 * enable temperature compensation
4514 * Need to use register names
4515 */
4516 if (frequency < 4000)
4517 tempSlope = eep->modalHeader2G.tempSlope;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4518 else if (eep->base_ext2.tempSlopeLow != 0) {
4519 t[0] = eep->base_ext2.tempSlopeLow;
4520 f[0] = 5180;
4521 t[1] = eep->modalHeader5G.tempSlope;
4522 f[1] = 5500;
4523 t[2] = eep->base_ext2.tempSlopeHigh;
4524 f[2] = 5785;
4525 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4526 f, t, 3);
4527 } else
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4528 tempSlope = eep->modalHeader5G.tempSlope;
4529
4530 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4531
4532 if (AR_SREV_9480_20(ah))
4533 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4534 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4535
4536
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4537 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4538 temperature[0]);
4539
4540 return 0;
4541}
4542
4543/* Apply the recorded correction values. */
4544static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4545{
4546 int ichain, ipier, npier;
4547 int mode;
4548 int lfrequency[AR9300_MAX_CHAINS],
4549 lcorrection[AR9300_MAX_CHAINS],
4550 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4551 int hfrequency[AR9300_MAX_CHAINS],
4552 hcorrection[AR9300_MAX_CHAINS],
4553 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4554 int fdiff;
4555 int correction[AR9300_MAX_CHAINS],
4556 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4557 int pfrequency, pcorrection, ptemperature, pvoltage;
4558 struct ath_common *common = ath9k_hw_common(ah);
4559
4560 mode = (frequency >= 4000);
4561 if (mode)
4562 npier = AR9300_NUM_5G_CAL_PIERS;
4563 else
4564 npier = AR9300_NUM_2G_CAL_PIERS;
4565
4566 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4567 lfrequency[ichain] = 0;
4568 hfrequency[ichain] = 100000;
4569 }
4570 /* identify best lower and higher frequency calibration measurement */
4571 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4572 for (ipier = 0; ipier < npier; ipier++) {
4573 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4574 &pfrequency, &pcorrection,
4575 &ptemperature, &pvoltage)) {
4576 fdiff = frequency - pfrequency;
4577
4578 /*
4579 * this measurement is higher than
4580 * our desired frequency
4581 */
4582 if (fdiff <= 0) {
4583 if (hfrequency[ichain] <= 0 ||
4584 hfrequency[ichain] >= 100000 ||
4585 fdiff >
4586 (frequency - hfrequency[ichain])) {
4587 /*
4588 * new best higher
4589 * frequency measurement
4590 */
4591 hfrequency[ichain] = pfrequency;
4592 hcorrection[ichain] =
4593 pcorrection;
4594 htemperature[ichain] =
4595 ptemperature;
4596 hvoltage[ichain] = pvoltage;
4597 }
4598 }
4599 if (fdiff >= 0) {
4600 if (lfrequency[ichain] <= 0
4601 || fdiff <
4602 (frequency - lfrequency[ichain])) {
4603 /*
4604 * new best lower
4605 * frequency measurement
4606 */
4607 lfrequency[ichain] = pfrequency;
4608 lcorrection[ichain] =
4609 pcorrection;
4610 ltemperature[ichain] =
4611 ptemperature;
4612 lvoltage[ichain] = pvoltage;
4613 }
4614 }
4615 }
4616 }
4617 }
4618
4619 /* interpolate */
4620 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4621 ath_dbg(common, ATH_DBG_EEPROM,
4622 "ch=%d f=%d low=%d %d h=%d %d\n",
4623 ichain, frequency, lfrequency[ichain],
4624 lcorrection[ichain], hfrequency[ichain],
4625 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4626 /* they're the same, so just pick one */
4627 if (hfrequency[ichain] == lfrequency[ichain]) {
4628 correction[ichain] = lcorrection[ichain];
4629 voltage[ichain] = lvoltage[ichain];
4630 temperature[ichain] = ltemperature[ichain];
4631 }
4632 /* the low frequency is good */
4633 else if (frequency - lfrequency[ichain] < 1000) {
4634 /* so is the high frequency, interpolate */
4635 if (hfrequency[ichain] - frequency < 1000) {
4636
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4637 correction[ichain] = interpolate(frequency,
4638 lfrequency[ichain],
4639 hfrequency[ichain],
4640 lcorrection[ichain],
4641 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4642
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4643 temperature[ichain] = interpolate(frequency,
4644 lfrequency[ichain],
4645 hfrequency[ichain],
4646 ltemperature[ichain],
4647 htemperature[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4648
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4649 voltage[ichain] = interpolate(frequency,
4650 lfrequency[ichain],
4651 hfrequency[ichain],
4652 lvoltage[ichain],
4653 hvoltage[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4654 }
4655 /* only low is good, use it */
4656 else {
4657 correction[ichain] = lcorrection[ichain];
4658 temperature[ichain] = ltemperature[ichain];
4659 voltage[ichain] = lvoltage[ichain];
4660 }
4661 }
4662 /* only high is good, use it */
4663 else if (hfrequency[ichain] - frequency < 1000) {
4664 correction[ichain] = hcorrection[ichain];
4665 temperature[ichain] = htemperature[ichain];
4666 voltage[ichain] = hvoltage[ichain];
4667 } else { /* nothing is good, presume 0???? */
4668 correction[ichain] = 0;
4669 temperature[ichain] = 0;
4670 voltage[ichain] = 0;
4671 }
4672 }
4673
4674 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4675 temperature);
4676
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4677 ath_dbg(common, ATH_DBG_EEPROM,
4678 "for frequency=%d, calibration correction = %d %d %d\n",
4679 frequency, correction[0], correction[1], correction[2]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4680
4681 return 0;
4682}
4683
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4684static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4685 int idx,
4686 int edge,
4687 bool is2GHz)
4688{
4689 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4690 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4691
4692 if (is2GHz)
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4693 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4694 else
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4695 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4696}
4697
4698static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4699 int idx,
4700 unsigned int edge,
4701 u16 freq,
4702 bool is2GHz)
4703{
4704 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4705 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4706
4707 u8 *ctl_freqbin = is2GHz ?
4708 &eep->ctl_freqbin_2G[idx][0] :
4709 &eep->ctl_freqbin_5G[idx][0];
4710
4711 if (is2GHz) {
4712 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4713 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4714 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4715 } else {
4716 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4717 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4718 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4719 }
4720
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4721 return MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4722}
4723
4724/*
4725 * Find the maximum conformance test limit for the given channel and CTL info
4726 */
4727static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4728 u16 freq, int idx, bool is2GHz)
4729{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4730 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4731 u8 *ctl_freqbin = is2GHz ?
4732 &eep->ctl_freqbin_2G[idx][0] :
4733 &eep->ctl_freqbin_5G[idx][0];
4734 u16 num_edges = is2GHz ?
4735 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4736 unsigned int edge;
4737
4738 /* Get the edge power */
4739 for (edge = 0;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4740 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4741 edge++) {
4742 /*
4743 * If there's an exact channel match or an inband flag set
4744 * on the lower channel use the given rdEdgePower
4745 */
4746 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4747 twiceMaxEdgePower =
4748 ar9003_hw_get_direct_edge_power(eep, idx,
4749 edge, is2GHz);
4750 break;
4751 } else if ((edge > 0) &&
4752 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4753 is2GHz))) {
4754 twiceMaxEdgePower =
4755 ar9003_hw_get_indirect_edge_power(eep, idx,
4756 edge, freq,
4757 is2GHz);
4758 /*
4759 * Leave loop - no more affecting edges possible in
4760 * this monotonic increasing list
4761 */
4762 break;
4763 }
4764 }
4765 return twiceMaxEdgePower;
4766}
4767
4768static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4769 struct ath9k_channel *chan,
4770 u8 *pPwrArray, u16 cfgCtl,
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame^]4771 u8 antenna_reduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4772 u16 powerLimit)
4773{
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4774 struct ath_common *common = ath9k_hw_common(ah);
4775 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4776 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4777 int i;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame^]4778 u16 scaledPower = 0, minCtlPower;
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4779 static const u16 ctlModesFor11a[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4780 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4781 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4782 static const u16 ctlModesFor11g[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4783 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4784 CTL_11G_EXT, CTL_2GHT40
4785 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4786 u16 numCtlModes;
4787 const u16 *pCtlMode;
4788 u16 ctlMode, freq;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4789 struct chan_centers centers;
4790 u8 *ctlIndex;
4791 u8 ctlNum;
4792 u16 twiceMinEdgePower;
4793 bool is2ghz = IS_CHAN_2GHZ(chan);
4794
4795 ath9k_hw_get_channel_centers(ah, chan, &centers);
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame^]4796 scaledPower = powerLimit - antenna_reduction;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4797
4798 /*
4799 * Reduce scaled Power by number of chains active to get
4800 * to per chain tx power level
4801 */
4802 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4803 case 1:
4804 break;
4805 case 2:
Daniel Halperin21fdc872011-05-31 11:59:30 -0700[diff] [blame]4806 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4807 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4808 else
4809 scaledPower = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4810 break;
4811 case 3:
Daniel Halperin21fdc872011-05-31 11:59:30 -0700[diff] [blame]4812 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4813 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4814 else
4815 scaledPower = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4816 break;
4817 }
4818
4819 scaledPower = max((u16)0, scaledPower);
4820
4821 /*
4822 * Get target powers from EEPROM - our baseline for TX Power
4823 */
4824 if (is2ghz) {
4825 /* Setup for CTL modes */
4826 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4827 numCtlModes =
4828 ARRAY_SIZE(ctlModesFor11g) -
4829 SUB_NUM_CTL_MODES_AT_2G_40;
4830 pCtlMode = ctlModesFor11g;
4831 if (IS_CHAN_HT40(chan))
4832 /* All 2G CTL's */
4833 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4834 } else {
4835 /* Setup for CTL modes */
4836 /* CTL_11A, CTL_5GHT20 */
4837 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4838 SUB_NUM_CTL_MODES_AT_5G_40;
4839 pCtlMode = ctlModesFor11a;
4840 if (IS_CHAN_HT40(chan))
4841 /* All 5G CTL's */
4842 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4843 }
4844
4845 /*
4846 * For MIMO, need to apply regulatory caps individually across
4847 * dynamically running modes: CCK, OFDM, HT20, HT40
4848 *
4849 * The outer loop walks through each possible applicable runtime mode.
4850 * The inner loop walks through each ctlIndex entry in EEPROM.
4851 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4852 */
4853 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4854 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4855 (pCtlMode[ctlMode] == CTL_2GHT40);
4856 if (isHt40CtlMode)
4857 freq = centers.synth_center;
4858 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4859 freq = centers.ext_center;
4860 else
4861 freq = centers.ctl_center;
4862
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4863 ath_dbg(common, ATH_DBG_REGULATORY,
4864 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4865 ctlMode, numCtlModes, isHt40CtlMode,
4866 (pCtlMode[ctlMode] & EXT_ADDITIVE));
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4867
4868 /* walk through each CTL index stored in EEPROM */
4869 if (is2ghz) {
4870 ctlIndex = pEepData->ctlIndex_2G;
4871 ctlNum = AR9300_NUM_CTLS_2G;
4872 } else {
4873 ctlIndex = pEepData->ctlIndex_5G;
4874 ctlNum = AR9300_NUM_CTLS_5G;
4875 }
4876
4877 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4878 ath_dbg(common, ATH_DBG_REGULATORY,
4879 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4880 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4881 chan->channel);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4882
4883 /*
4884 * compare test group from regulatory
4885 * channel list with test mode from pCtlMode
4886 * list
4887 */
4888 if ((((cfgCtl & ~CTL_MODE_M) |
4889 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4890 ctlIndex[i]) ||
4891 (((cfgCtl & ~CTL_MODE_M) |
4892 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4893 ((ctlIndex[i] & CTL_MODE_M) |
4894 SD_NO_CTL))) {
4895 twiceMinEdgePower =
4896 ar9003_hw_get_max_edge_power(pEepData,
4897 freq, i,
4898 is2ghz);
4899
4900 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4901 /*
4902 * Find the minimum of all CTL
4903 * edge powers that apply to
4904 * this channel
4905 */
4906 twiceMaxEdgePower =
4907 min(twiceMaxEdgePower,
4908 twiceMinEdgePower);
4909 else {
4910 /* specific */
4911 twiceMaxEdgePower =
4912 twiceMinEdgePower;
4913 break;
4914 }
4915 }
4916 }
4917
4918 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4919
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4920 ath_dbg(common, ATH_DBG_REGULATORY,
4921 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4922 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4923 scaledPower, minCtlPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4924
4925 /* Apply ctl mode to correct target power set */
4926 switch (pCtlMode[ctlMode]) {
4927 case CTL_11B:
4928 for (i = ALL_TARGET_LEGACY_1L_5L;
4929 i <= ALL_TARGET_LEGACY_11S; i++)
4930 pPwrArray[i] =
4931 (u8)min((u16)pPwrArray[i],
4932 minCtlPower);
4933 break;
4934 case CTL_11A:
4935 case CTL_11G:
4936 for (i = ALL_TARGET_LEGACY_6_24;
4937 i <= ALL_TARGET_LEGACY_54; i++)
4938 pPwrArray[i] =
4939 (u8)min((u16)pPwrArray[i],
4940 minCtlPower);
4941 break;
4942 case CTL_5GHT20:
4943 case CTL_2GHT20:
4944 for (i = ALL_TARGET_HT20_0_8_16;
4945 i <= ALL_TARGET_HT20_21; i++)
4946 pPwrArray[i] =
4947 (u8)min((u16)pPwrArray[i],
4948 minCtlPower);
4949 pPwrArray[ALL_TARGET_HT20_22] =
4950 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4951 minCtlPower);
4952 pPwrArray[ALL_TARGET_HT20_23] =
4953 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4954 minCtlPower);
4955 break;
4956 case CTL_5GHT40:
4957 case CTL_2GHT40:
4958 for (i = ALL_TARGET_HT40_0_8_16;
4959 i <= ALL_TARGET_HT40_23; i++)
4960 pPwrArray[i] =
4961 (u8)min((u16)pPwrArray[i],
4962 minCtlPower);
4963 break;
4964 default:
4965 break;
4966 }
4967 } /* end ctl mode checking */
4968}
4969
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4970static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4971{
4972 u8 mod_idx = mcs_idx % 8;
4973
4974 if (mod_idx <= 3)
4975 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4976 else
4977 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4978}
4979
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4980static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4981 struct ath9k_channel *chan, u16 cfgCtl,
4982 u8 twiceAntennaReduction,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4983 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4984{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]4985 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4986 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4987 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4988 struct ar9300_modal_eep_header *modal_hdr;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4989 u8 targetPowerValT2[ar9300RateSize];
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4990 u8 target_power_val_t2_eep[ar9300RateSize];
4991 unsigned int i = 0, paprd_scale_factor = 0;
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4992 u8 pwr_idx, min_pwridx = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4993
4994 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4995
4996 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4997 if (IS_CHAN_2GHZ(chan))
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4998 modal_hdr = &eep->modalHeader2G;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4999 else
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5000 modal_hdr = &eep->modalHeader5G;
5001
5002 ah->paprd_ratemask =
5003 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5004 AR9300_PAPRD_RATE_MASK;
5005
5006 ah->paprd_ratemask_ht40 =
5007 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5008 AR9300_PAPRD_RATE_MASK;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5009
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]5010 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5011 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5012 ALL_TARGET_HT20_0_8_16;
5013
5014 if (!ah->paprd_table_write_done) {
5015 memcpy(target_power_val_t2_eep, targetPowerValT2,
5016 sizeof(targetPowerValT2));
5017 for (i = 0; i < 24; i++) {
5018 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5019 if (ah->paprd_ratemask & (1 << i)) {
5020 if (targetPowerValT2[pwr_idx] &&
5021 targetPowerValT2[pwr_idx] ==
5022 target_power_val_t2_eep[pwr_idx])
5023 targetPowerValT2[pwr_idx] -=
5024 paprd_scale_factor;
5025 }
5026 }
5027 }
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5028 memcpy(target_power_val_t2_eep, targetPowerValT2,
5029 sizeof(targetPowerValT2));
5030 }
5031
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5032 ar9003_hw_set_power_per_rate_table(ah, chan,
5033 targetPowerValT2, cfgCtl,
5034 twiceAntennaReduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5035 powerLimit);
5036
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5037 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5038 for (i = 0; i < ar9300RateSize; i++) {
5039 if ((ah->paprd_ratemask & (1 << i)) &&
5040 (abs(targetPowerValT2[i] -
5041 target_power_val_t2_eep[i]) >
5042 paprd_scale_factor)) {
5043 ah->paprd_ratemask &= ~(1 << i);
5044 ath_dbg(common, ATH_DBG_EEPROM,
5045 "paprd disabled for mcs %d\n", i);
5046 }
5047 }
5048 }
5049
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5050 regulatory->max_power_level = 0;
5051 for (i = 0; i < ar9300RateSize; i++) {
5052 if (targetPowerValT2[i] > regulatory->max_power_level)
5053 regulatory->max_power_level = targetPowerValT2[i];
5054 }
5055
5056 if (test)
5057 return;
5058
5059 for (i = 0; i < ar9300RateSize; i++) {
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]5060 ath_dbg(common, ATH_DBG_EEPROM,
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]5061 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5062 }
5063
Felix Fietkau071bfef2011-07-27 15:01:04 +0200[diff] [blame]5064 ah->txpower_limit = regulatory->max_power_level;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5065
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5066 /* Write target power array to registers */
5067 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5068 ar9003_hw_calibration_apply(ah, chan->channel);
Felix Fietkau1bf38662010-12-13 08:40:54 +0100[diff] [blame]5069
5070 if (IS_CHAN_2GHZ(chan)) {
5071 if (IS_CHAN_HT40(chan))
5072 i = ALL_TARGET_HT40_0_8_16;
5073 else
5074 i = ALL_TARGET_HT20_0_8_16;
5075 } else {
5076 if (IS_CHAN_HT40(chan))
5077 i = ALL_TARGET_HT40_7;
5078 else
5079 i = ALL_TARGET_HT20_7;
5080 }
5081 ah->paprd_target_power = targetPowerValT2[i];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5082}
5083
5084static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5085 u16 i, bool is2GHz)
5086{
5087 return AR_NO_SPUR;
5088}
5089
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]5090s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5091{
5092 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5093
5094 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5095}
5096
5097s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5098{
5099 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5100
5101 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5102}
5103
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]5104u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5105{
5106 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5107
5108 if (is_2ghz)
5109 return eep->modalHeader2G.spurChans;
5110 else
5111 return eep->modalHeader5G.spurChans;
5112}
5113
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]5114unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5115 struct ath9k_channel *chan)
5116{
5117 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5118
5119 if (IS_CHAN_2GHZ(chan))
5120 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5121 AR9300_PAPRD_SCALE_1);
5122 else {
5123 if (chan->channel >= 5700)
5124 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5125 AR9300_PAPRD_SCALE_1);
5126 else if (chan->channel >= 5400)
5127 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5128 AR9300_PAPRD_SCALE_2);
5129 else
5130 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5131 AR9300_PAPRD_SCALE_1);
5132 }
5133}
5134
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5135const struct eeprom_ops eep_ar9300_ops = {
5136 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5137 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5138 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]5139 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5140 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5141 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5142 .set_board_values = ath9k_hw_ar9300_set_board_values,
5143 .set_addac = ath9k_hw_ar9300_set_addac,
5144 .set_txpower = ath9k_hw_ar9300_set_txpower,
5145 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5146};