| Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 4 | */ |
| 5 | /dts-v1/; |
| 6 | |
| 7 | #include "am33xx.dtsi" |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 8 | #include <dt-bindings/pwm/pwm.h> |
| Enric Balletbo i Serra | 9843532 | 2018-06-06 17:54:10 +0200 | [diff] [blame] | 9 | #include <dt-bindings/interrupt-controller/irq.h> |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 10 | |
| 11 | / { |
| 12 | model = "Toby Churchill SL50 Series"; |
| 13 | compatible = "tcl,am335x-sl50", "ti,am33xx"; |
| 14 | |
| 15 | cpus { |
| 16 | cpu@0 { |
| 17 | cpu0-supply = <&dcdc2_reg>; |
| 18 | }; |
| 19 | }; |
| 20 | |
| Javier Martinez Canillas | 278cb79 | 2016-08-31 12:35:30 +0200 | [diff] [blame] | 21 | memory@80000000 { |
| Javier Martinez Canillas | 35852c6 | 2016-08-31 12:35:15 +0200 | [diff] [blame] | 22 | device_type = "memory"; |
| 23 | reg = <0x80000000 0x20000000>; /* 512 MB */ |
| 24 | }; |
| 25 | |
| Enric Balletbo i Serra | 01c37be4 | 2016-01-16 11:51:12 +0100 | [diff] [blame] | 26 | chosen { |
| 27 | stdout-path = &uart0; |
| 28 | }; |
| 29 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 30 | leds { |
| 31 | compatible = "gpio-leds"; |
| 32 | pinctrl-names = "default"; |
| 33 | pinctrl-0 = <&led_pins>; |
| 34 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 35 | led0 { |
| Enric Balletbo i Serra | 70bd28e | 2018-06-06 17:54:12 +0200 | [diff] [blame] | 36 | label = "sl50:red:usr0"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 37 | gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; |
| 38 | default-state = "off"; |
| 39 | }; |
| 40 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 41 | led1 { |
| Enric Balletbo i Serra | 70bd28e | 2018-06-06 17:54:12 +0200 | [diff] [blame] | 42 | label = "sl50:green:usr1"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 43 | gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; |
| 44 | default-state = "off"; |
| 45 | }; |
| 46 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 47 | led2 { |
| Enric Balletbo i Serra | 70bd28e | 2018-06-06 17:54:12 +0200 | [diff] [blame] | 48 | label = "sl50:red:usr2"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 49 | gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; |
| 50 | default-state = "off"; |
| 51 | }; |
| 52 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 53 | led3 { |
| Enric Balletbo i Serra | 70bd28e | 2018-06-06 17:54:12 +0200 | [diff] [blame] | 54 | label = "sl50:green:usr3"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 55 | gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; |
| 56 | default-state = "off"; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | backlight0: disp0 { |
| 61 | compatible = "pwm-backlight"; |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 62 | pinctrl-names = "default"; |
| 63 | pinctrl-0 = <&backlight0_pins>; |
| 64 | pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; |
| 65 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 66 | 10 11 12 13 14 15 16 17 18 19 |
| 67 | 20 21 22 23 24 25 26 27 28 29 |
| 68 | 30 31 32 33 34 35 36 37 38 39 |
| 69 | 40 41 42 43 44 45 46 47 48 49 |
| 70 | 50 51 52 53 54 55 56 57 58 59 |
| 71 | 60 61 62 63 64 65 66 67 68 69 |
| 72 | 70 71 72 73 74 75 76 77 78 79 |
| 73 | 80 81 82 83 84 85 86 87 88 89 |
| 74 | 90 91 92 93 94 95 96 97 98 99 |
| 75 | 100>; |
| 76 | default-brightness-level = <50>; |
| 77 | enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; |
| 78 | power-supply = <&vdd_sys_reg>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | backlight1: disp1 { |
| 82 | compatible = "pwm-backlight"; |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 83 | pinctrl-names = "default"; |
| 84 | pinctrl-0 = <&backlight1_pins>; |
| 85 | pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; |
| 86 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 87 | 10 11 12 13 14 15 16 17 18 19 |
| 88 | 20 21 22 23 24 25 26 27 28 29 |
| 89 | 30 31 32 33 34 35 36 37 38 39 |
| 90 | 40 41 42 43 44 45 46 47 48 49 |
| 91 | 50 51 52 53 54 55 56 57 58 59 |
| 92 | 60 61 62 63 64 65 66 67 68 69 |
| 93 | 70 71 72 73 74 75 76 77 78 79 |
| 94 | 80 81 82 83 84 85 86 87 88 89 |
| 95 | 90 91 92 93 94 95 96 97 98 99 |
| 96 | 100>; |
| 97 | default-brightness-level = <50>; |
| 98 | enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; |
| 99 | power-supply = <&vdd_sys_reg>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 100 | }; |
| 101 | |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 102 | clocks { |
| 103 | compatible = "simple-bus"; |
| 104 | #address-cells = <1>; |
| 105 | #size-cells = <0>; |
| 106 | |
| 107 | /* audio external oscillator */ |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 108 | audio_mclk_fixed: oscillator@0 { |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 109 | compatible = "fixed-clock"; |
| 110 | #clock-cells = <0>; |
| 111 | clock-frequency = <24576000>; /* 24.576MHz */ |
| 112 | }; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 113 | |
| 114 | audio_mclk: audio_mclk_gate@0 { |
| 115 | compatible = "gpio-gate-clock"; |
| 116 | #clock-cells = <0>; |
| 117 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&audio_mclk_pins>; |
| 119 | clocks = <&audio_mclk_fixed>; |
| 120 | enable-gpios = <&gpio1 27 0>; |
| 121 | }; |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 122 | }; |
| 123 | |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 124 | panel: lcd_panel { |
| 125 | compatible = "ti,tilcdc,panel"; |
| 126 | pinctrl-names = "default"; |
| 127 | pinctrl-0 = <&lcd_pins>; |
| 128 | |
| 129 | panel-info { |
| 130 | ac-bias = <255>; |
| 131 | ac-bias-intrpt = <0>; |
| 132 | dma-burst-sz = <16>; |
| 133 | bpp = <16>; |
| 134 | fdd = <0x80>; |
| 135 | tft-alt-mode = <0>; |
| 136 | mono-8bit-mode = <0>; |
| 137 | sync-edge = <0>; |
| 138 | sync-ctrl = <1>; |
| 139 | raster-order = <0>; |
| 140 | fifo-th = <0>; |
| 141 | }; |
| 142 | |
| 143 | display-timings { |
| 144 | native-mode = <&timing0>; |
| 145 | timing0: 960x128 { |
| 146 | clock-frequency = <18000000>; |
| 147 | hactive = <960>; |
| 148 | vactive = <272>; |
| 149 | |
| 150 | hback-porch = <40>; |
| 151 | hfront-porch = <16>; |
| 152 | hsync-len = <24>; |
| 153 | hsync-active = <0>; |
| 154 | |
| 155 | vback-porch = <3>; |
| 156 | vfront-porch = <8>; |
| 157 | vsync-len = <4>; |
| 158 | vsync-active = <0>; |
| 159 | }; |
| 160 | }; |
| 161 | }; |
| 162 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 163 | sound { |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 164 | compatible = "audio-graph-card"; |
| 165 | label = "sound-card"; |
| 166 | pinctrl-names = "default"; |
| 167 | pinctrl-0 = <&audio_pa_pins>; |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 168 | |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 169 | widgets = "Headphone", "Headphone Jack", |
| 170 | "Speaker", "Speaker External", |
| 171 | "Line", "Line In", |
| 172 | "Microphone", "Microphone Jack"; |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 173 | |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 174 | routing = "Headphone Jack", "HPLOUT", |
| 175 | "Headphone Jack", "HPROUT", |
| 176 | "Amplifier", "MONO_LOUT", |
| 177 | "Speaker External", "Amplifier", |
| 178 | "LINE1R", "Line In", |
| 179 | "LINE1L", "Line In", |
| 180 | "MIC3L", "Microphone Jack", |
| 181 | "MIC3R", "Microphone Jack", |
| 182 | "Microphone Jack", "Mic Bias"; |
| 183 | |
| 184 | dais = <&cpu_port>; |
| 185 | |
| 186 | pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | emmc_pwrseq: pwrseq@0 { |
| 190 | compatible = "mmc-pwrseq-emmc"; |
| 191 | pinctrl-names = "default"; |
| 192 | pinctrl-0 = <&emmc_pwrseq_pins>; |
| 193 | reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; |
| 194 | }; |
| 195 | |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 196 | vdd_sys_reg: regulator@0 { |
| 197 | compatible = "regulator-fixed"; |
| 198 | regulator-name = "vdd_sys_reg"; |
| 199 | regulator-min-microvolt = <5000000>; |
| 200 | regulator-max-microvolt = <5000000>; |
| 201 | regulator-always-on; |
| 202 | }; |
| 203 | |
| Javier Martinez Canillas | 4c049a5 | 2016-08-01 12:46:58 -0400 | [diff] [blame] | 204 | vmmcsd_fixed: fixedregulator0 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 205 | compatible = "regulator-fixed"; |
| 206 | regulator-name = "vmmcsd_fixed"; |
| 207 | regulator-min-microvolt = <3300000>; |
| 208 | regulator-max-microvolt = <3300000>; |
| 209 | }; |
| 210 | }; |
| 211 | |
| 212 | &am33xx_pinmux { |
| 213 | pinctrl-names = "default"; |
| 214 | pinctrl-0 = <&lwb_pins>; |
| 215 | |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 216 | audio_pins: pinmux_audio_pins { |
| 217 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 218 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) |
| 219 | AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) |
| 220 | AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) |
| 221 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) |
| 222 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 223 | >; |
| 224 | }; |
| 225 | |
| 226 | audio_pa_pins: pinmux_audio_pa_pins { |
| 227 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 228 | AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 229 | >; |
| 230 | }; |
| 231 | |
| 232 | audio_mclk_pins: pinmux_audio_mclk_pins { |
| 233 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 234 | AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 235 | >; |
| 236 | }; |
| 237 | |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 238 | backlight0_pins: pinmux_backlight0_pins { |
| 239 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 240 | AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 241 | >; |
| 242 | }; |
| 243 | |
| 244 | backlight1_pins: pinmux_backlight1_pins { |
| 245 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 246 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 247 | >; |
| 248 | }; |
| 249 | |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 250 | lcd_pins: pinmux_lcd_pins { |
| 251 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 252 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) |
| 253 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) |
| 254 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) |
| 255 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) |
| 256 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) |
| 257 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) |
| 258 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) |
| 259 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) |
| 260 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) |
| 261 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) |
| 262 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) |
| 263 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) |
| 264 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) |
| 265 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) |
| 266 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) |
| 267 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) |
| 268 | AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 269 | AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 270 | AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 271 | AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 272 | >; |
| 273 | }; |
| 274 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 275 | led_pins: pinmux_led_pins { |
| 276 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 277 | AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 278 | AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 279 | AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* gpmc_a7.gpio1_23 */ |
| 280 | AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 281 | >; |
| 282 | }; |
| 283 | |
| 284 | uart0_pins: pinmux_uart0_pins { |
| 285 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 286 | AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) |
| 287 | AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 288 | >; |
| 289 | }; |
| 290 | |
| Enric Balletbo i Serra | e9c7beb | 2017-01-16 17:57:32 +0100 | [diff] [blame] | 291 | uart1_pins: pinmux_uart1_pins { |
| 292 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 293 | AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) |
| 294 | AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| Enric Balletbo i Serra | e9c7beb | 2017-01-16 17:57:32 +0100 | [diff] [blame] | 295 | >; |
| 296 | }; |
| 297 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 298 | uart4_pins: pinmux_uart4_pins { |
| 299 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 300 | AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ |
| 301 | AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 302 | >; |
| 303 | }; |
| 304 | |
| 305 | i2c0_pins: pinmux_i2c0_pins { |
| 306 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 307 | AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) |
| 308 | AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 309 | >; |
| 310 | }; |
| 311 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 312 | i2c2_pins: pinmux_i2c2_pins { |
| 313 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 314 | AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ |
| 315 | AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 316 | >; |
| 317 | }; |
| 318 | |
| 319 | cpsw_default: cpsw_default { |
| 320 | pinctrl-single,pins = < |
| 321 | /* Slave 1 */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 322 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) |
| 323 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 324 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) |
| 325 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 326 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 327 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 328 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 329 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| 330 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| 331 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) |
| 332 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) |
| 333 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) |
| 334 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 335 | >; |
| 336 | }; |
| 337 | |
| 338 | cpsw_sleep: cpsw_sleep { |
| 339 | pinctrl-single,pins = < |
| 340 | /* Slave 1 reset value */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 341 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 342 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 343 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 344 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 345 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 346 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 347 | AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 348 | AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 349 | AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 350 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 351 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 352 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 353 | AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 354 | >; |
| 355 | }; |
| 356 | |
| 357 | davinci_mdio_default: davinci_mdio_default { |
| 358 | pinctrl-single,pins = < |
| 359 | /* MDIO */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 360 | AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) |
| 361 | AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) |
| Enric Balletbo i Serra | 25d2ee9 | 2018-06-06 17:54:07 +0200 | [diff] [blame] | 362 | /* Ethernet */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 363 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 364 | >; |
| 365 | }; |
| 366 | |
| 367 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 368 | pinctrl-single,pins = < |
| 369 | /* MDIO reset value */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 370 | AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| 371 | AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 372 | >; |
| 373 | }; |
| 374 | |
| 375 | mmc1_pins: pinmux_mmc1_pins { |
| 376 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 377 | AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 378 | >; |
| 379 | }; |
| 380 | |
| 381 | emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { |
| 382 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 383 | AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 384 | >; |
| 385 | }; |
| 386 | |
| 387 | emmc_pins: pinmux_emmc_pins { |
| 388 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 389 | AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 390 | AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 391 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 392 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 393 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 394 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 395 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 396 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 397 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 398 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 399 | >; |
| 400 | }; |
| 401 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 402 | ehrpwm1_pins: pinmux_ehrpwm1a_pins { |
| 403 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 404 | AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ |
| 405 | AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 406 | >; |
| 407 | }; |
| 408 | |
| Enric Balletbo i Serra | 9843532 | 2018-06-06 17:54:10 +0200 | [diff] [blame] | 409 | rtc0_irq_pins: pinmux_rtc0_irq_pins { |
| 410 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 411 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ |
| Enric Balletbo i Serra | 9843532 | 2018-06-06 17:54:10 +0200 | [diff] [blame] | 412 | >; |
| 413 | }; |
| 414 | |
| Enric Balletbo i Serra | f37f911 | 2017-01-16 17:57:33 +0100 | [diff] [blame] | 415 | spi0_pins: pinmux_spi0_pins { |
| 416 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 417 | AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ |
| 418 | AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ |
| 419 | AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) |
| 420 | AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS0 (NBATTSS) */ |
| 421 | AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) */ |
| Enric Balletbo i Serra | f37f911 | 2017-01-16 17:57:33 +0100 | [diff] [blame] | 422 | >; |
| 423 | }; |
| 424 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 425 | lwb_pins: pinmux_lwb_pins { |
| 426 | pinctrl-single,pins = < |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 427 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ |
| 428 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ |
| 429 | AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 430 | /* PDI Bus - Battery system */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 431 | AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ |
| 432 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ |
| Enric Balletbo i Serra | 70bd28e | 2018-06-06 17:54:12 +0200 | [diff] [blame] | 433 | /* FPGA */ |
| Christina Quast | b1e0c48 | 2019-04-12 18:26:26 +0200 | [diff] [blame] | 434 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_DONE - gpmc_ad8.gpio0_22 */ |
| 435 | AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7) /* FPGA_NRST - gpmc_a0.gpio1_16 */ |
| 436 | AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_RUN - gpmc_a1.gpio1_17 */ |
| 437 | AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) /* ENFPGA - gpmc_a9.gpio1_25 */ |
| 438 | AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* FPGA_PROGRAM - gpmc_a10.gpio1_26 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 439 | >; |
| 440 | }; |
| 441 | }; |
| 442 | |
| 443 | &i2c0 { |
| 444 | status = "okay"; |
| 445 | pinctrl-names = "default"; |
| 446 | pinctrl-0 = <&i2c0_pins>; |
| 447 | |
| 448 | clock-frequency = <400000>; |
| 449 | |
| 450 | tps: tps@24 { |
| 451 | reg = <0x24>; |
| 452 | }; |
| 453 | |
| Enric Balletbo i Serra | 9843532 | 2018-06-06 17:54:10 +0200 | [diff] [blame] | 454 | rtc0: rtc@68 { |
| 455 | compatible = "dallas,ds1339"; |
| 456 | pinctrl-names = "default"; |
| 457 | pinctrl-0 = <&rtc0_irq_pins>; |
| 458 | interrupt-parent = <&gpio0>; |
| 459 | interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */ |
| 460 | wakeup-source; |
| 461 | trickle-resistor-ohms = <2000>; |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 462 | reg = <0x68>; |
| 463 | }; |
| 464 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 465 | eeprom: eeprom@50 { |
| Javier Martinez Canillas | 05e7d62 | 2017-05-23 15:34:31 +0200 | [diff] [blame] | 466 | compatible = "atmel,24c256"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 467 | reg = <0x50>; |
| 468 | }; |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 469 | |
| Enric Balletbo i Serra | 4340f9d | 2017-01-16 17:57:35 +0100 | [diff] [blame] | 470 | gpio_exp: mcp23017@20 { |
| 471 | compatible = "microchip,mcp23017"; |
| 472 | reg = <0x20>; |
| 473 | }; |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 474 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 475 | }; |
| 476 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 477 | &i2c2 { |
| 478 | status = "okay"; |
| 479 | pinctrl-names = "default"; |
| 480 | pinctrl-0 = <&i2c2_pins>; |
| 481 | |
| 482 | clock-frequency = <400000>; |
| 483 | |
| 484 | audio_codec: tlv320aic3106@1b { |
| 485 | status = "okay"; |
| 486 | compatible = "ti,tlv320aic3106"; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 487 | #sound-dai-cells = <0>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 488 | reg = <0x1b>; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 489 | ai3x-micbias-vg = <2>; /* 2.5V */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 490 | |
| 491 | AVDD-supply = <&ldo4_reg>; |
| 492 | IOVDD-supply = <&ldo4_reg>; |
| 493 | DRVDD-supply = <&ldo4_reg>; |
| 494 | DVDD-supply = <&ldo3_reg>; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 495 | |
| 496 | codec_port: port { |
| 497 | codec_endpoint: endpoint { |
| 498 | remote-endpoint = <&cpu_endpoint>; |
| 499 | clocks = <&audio_mclk>; |
| 500 | }; |
| 501 | }; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 502 | }; |
| Enric Balletbo i Serra | 885658f | 2017-01-16 17:57:36 +0100 | [diff] [blame] | 503 | |
| 504 | /* Ambient Light Sensor */ |
| 505 | als: isl29023@44 { |
| 506 | compatible = "isil,isl29023"; |
| 507 | reg = <0x44>; |
| 508 | }; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 509 | }; |
| 510 | |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 511 | &rtc { |
| 512 | status = "disabled"; |
| 513 | }; |
| 514 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 515 | &usb { |
| 516 | status = "okay"; |
| 517 | }; |
| 518 | |
| 519 | &usb_ctrl_mod { |
| 520 | status = "okay"; |
| 521 | }; |
| 522 | |
| 523 | &usb0_phy { |
| 524 | status = "okay"; |
| 525 | }; |
| 526 | |
| 527 | &usb1_phy { |
| 528 | status = "okay"; |
| 529 | }; |
| 530 | |
| 531 | &usb0 { |
| 532 | status = "okay"; |
| Enric Balletbo i Serra | f9d1dec | 2018-06-06 17:54:09 +0200 | [diff] [blame] | 533 | dr_mode = "otg"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 534 | }; |
| 535 | |
| 536 | &usb1 { |
| 537 | status = "okay"; |
| 538 | dr_mode = "host"; |
| 539 | }; |
| 540 | |
| 541 | &cppi41dma { |
| 542 | status = "okay"; |
| 543 | }; |
| 544 | |
| 545 | &mmc1 { |
| 546 | status = "okay"; |
| 547 | pinctrl-names = "default"; |
| 548 | pinctrl-0 = <&mmc1_pins>; |
| 549 | bus-width = <4>; |
| Enric Balletbo i Serra | 56b74ed | 2017-05-22 11:01:52 +0200 | [diff] [blame] | 550 | cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 551 | vmmc-supply = <&vmmcsd_fixed>; |
| 552 | }; |
| 553 | |
| 554 | &mmc2 { |
| 555 | status = "okay"; |
| 556 | pinctrl-names = "default"; |
| 557 | pinctrl-0 = <&emmc_pins>; |
| 558 | bus-width = <8>; |
| 559 | vmmc-supply = <&vmmcsd_fixed>; |
| 560 | mmc-pwrseq = <&emmc_pwrseq>; |
| 561 | }; |
| 562 | |
| 563 | &mcasp0 { |
| 564 | status = "okay"; |
| 565 | pinctrl-names = "default"; |
| 566 | pinctrl-0 = <&audio_pins>; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 567 | #sound-dai-cells = <0>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 568 | op-mode = <0>; /* MCASP_ISS_MODE */ |
| 569 | tdm-slots = <2>; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 570 | /* 4 serializers */ |
| 571 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 572 | 0 0 1 2 |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 573 | >; |
| Enric Balletbo i Serra | e5f89db | 2018-06-06 17:54:11 +0200 | [diff] [blame] | 574 | tx-num-evt = <32>; |
| 575 | rx-num-evt = <32>; |
| 576 | |
| 577 | cpu_port: port { |
| 578 | cpu_endpoint: endpoint { |
| 579 | remote-endpoint = <&codec_endpoint>; |
| 580 | |
| 581 | dai-format = "dsp_b"; |
| 582 | bitclock-master = <&codec_port>; |
| 583 | frame-master = <&codec_port>; |
| 584 | bitclock-inversion; |
| 585 | clocks = <&audio_mclk>; |
| 586 | }; |
| 587 | }; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 588 | }; |
| 589 | |
| 590 | &uart0 { |
| 591 | status = "okay"; |
| 592 | pinctrl-names = "default"; |
| 593 | pinctrl-0 = <&uart0_pins>; |
| 594 | }; |
| 595 | |
| Enric Balletbo i Serra | e9c7beb | 2017-01-16 17:57:32 +0100 | [diff] [blame] | 596 | &uart1 { |
| 597 | status = "okay"; |
| 598 | pinctrl-names = "default"; |
| 599 | pinctrl-0 = <&uart1_pins>; |
| 600 | }; |
| 601 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 602 | &uart4 { |
| 603 | status = "okay"; |
| 604 | pinctrl-names = "default"; |
| 605 | pinctrl-0 = <&uart4_pins>; |
| 606 | }; |
| 607 | |
| Enric Balletbo i Serra | f37f911 | 2017-01-16 17:57:33 +0100 | [diff] [blame] | 608 | &spi0 { |
| 609 | status = "okay"; |
| 610 | pinctrl-names = "default"; |
| 611 | pinctrl-0 = <&spi0_pins>; |
| 612 | |
| 613 | flash: n25q032@1 { |
| 614 | #address-cells = <1>; |
| 615 | #size-cells = <1>; |
| 616 | compatible = "micron,n25q032"; |
| 617 | reg = <1>; |
| 618 | spi-max-frequency = <5000000>; |
| 619 | }; |
| 620 | }; |
| 621 | |
| Peter Ujfalusi | e327b3f | 2016-02-19 16:12:19 +0200 | [diff] [blame] | 622 | #include "tps65217.dtsi" |
| 623 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 624 | &tps { |
| 625 | ti,pmic-shutdown-controller; |
| 626 | |
| 627 | interrupt-parent = <&intc>; |
| 628 | interrupts = <7>; /* NNMI */ |
| 629 | |
| 630 | regulators { |
| 631 | dcdc1_reg: regulator@0 { |
| 632 | /* VDDS_DDR */ |
| 633 | regulator-min-microvolt = <1500000>; |
| 634 | regulator-max-microvolt = <1500000>; |
| 635 | regulator-always-on; |
| 636 | }; |
| 637 | |
| 638 | dcdc2_reg: regulator@1 { |
| 639 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 640 | regulator-name = "vdd_mpu"; |
| 641 | regulator-min-microvolt = <925000>; |
| 642 | regulator-max-microvolt = <1325000>; |
| 643 | regulator-boot-on; |
| 644 | regulator-always-on; |
| 645 | }; |
| 646 | |
| 647 | dcdc3_reg: regulator@2 { |
| 648 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 649 | regulator-name = "vdd_core"; |
| 650 | regulator-min-microvolt = <925000>; |
| 651 | regulator-max-microvolt = <1150000>; |
| 652 | regulator-boot-on; |
| 653 | regulator-always-on; |
| 654 | }; |
| 655 | |
| 656 | ldo1_reg: regulator@3 { |
| 657 | /* VRTC / VIO / VDDS*/ |
| 658 | regulator-always-on; |
| 659 | regulator-min-microvolt = <1800000>; |
| 660 | regulator-max-microvolt = <1800000>; |
| 661 | }; |
| 662 | |
| 663 | ldo2_reg: regulator@4 { |
| 664 | /* VDD_3V3AUX */ |
| 665 | regulator-always-on; |
| 666 | regulator-min-microvolt = <3300000>; |
| 667 | regulator-max-microvolt = <3300000>; |
| 668 | }; |
| 669 | |
| 670 | ldo3_reg: regulator@5 { |
| 671 | /* VDD_1V8 */ |
| 672 | regulator-min-microvolt = <1800000>; |
| 673 | regulator-max-microvolt = <1800000>; |
| 674 | regulator-always-on; |
| 675 | }; |
| 676 | |
| 677 | ldo4_reg: regulator@6 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 678 | /* VDD_3V3A */ |
| 679 | regulator-min-microvolt = <3300000>; |
| 680 | regulator-max-microvolt = <3300000>; |
| 681 | regulator-always-on; |
| 682 | }; |
| 683 | }; |
| 684 | }; |
| 685 | |
| 686 | &cpsw_emac0 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 687 | phy-mode = "mii"; |
| Enric Balletbo i Serra | 25d2ee9 | 2018-06-06 17:54:07 +0200 | [diff] [blame] | 688 | phy-handle = <ðphy0>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 689 | }; |
| 690 | |
| 691 | &mac { |
| 692 | status = "okay"; |
| 693 | pinctrl-names = "default", "sleep"; |
| 694 | pinctrl-0 = <&cpsw_default>; |
| 695 | pinctrl-1 = <&cpsw_sleep>; |
| 696 | }; |
| 697 | |
| 698 | &davinci_mdio { |
| 699 | status = "okay"; |
| 700 | pinctrl-names = "default", "sleep"; |
| 701 | pinctrl-0 = <&davinci_mdio_default>; |
| 702 | pinctrl-1 = <&davinci_mdio_sleep>; |
| Enric Balletbo i Serra | 25d2ee9 | 2018-06-06 17:54:07 +0200 | [diff] [blame] | 703 | reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; |
| 704 | reset-delay-us = <100>; /* PHY datasheet states 100us min */ |
| 705 | |
| 706 | ethphy0: ethernet-phy@0 { |
| 707 | reg = <0>; |
| 708 | }; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 709 | }; |
| 710 | |
| 711 | &sham { |
| 712 | status = "okay"; |
| 713 | }; |
| 714 | |
| 715 | &aes { |
| 716 | status = "okay"; |
| 717 | }; |
| 718 | |
| 719 | &epwmss1 { |
| 720 | status = "okay"; |
| 721 | }; |
| 722 | |
| 723 | &ehrpwm1 { |
| 724 | status = "okay"; |
| 725 | pinctrl-names = "default"; |
| 726 | pinctrl-0 = <&ehrpwm1_pins>; |
| 727 | }; |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 728 | |
| 729 | &lcdc { |
| 730 | status = "okay"; |
| 731 | }; |
| Enric Balletbo i Serra | 5e2e1c4 | 2018-06-06 17:54:13 +0200 | [diff] [blame] | 732 | |
| 733 | &tscadc { |
| 734 | status = "okay"; |
| 735 | }; |
| 736 | |
| 737 | &am335x_adc { |
| 738 | ti,adc-channels = <0 1 2 3 4 5 6 7>; |
| 739 | }; |