blob: c2ac0371d1218c1cff1084b6bcb4dfeb6420900e [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010044#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020045#include <linux/dcbnl.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020046#include <net/switchdev.h>
47
Elad Raz3a49b4f2016-01-10 21:06:28 +010048#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020049#include "core.h"
50
51#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
Ido Schimmelb555cf42016-04-05 10:20:02 +020053#define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +010054#define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
55
Jiri Pirko0d65fc12015-12-03 12:12:28 +010056#define MLXSW_SP_LAG_MAX 64
57#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020058
Elad Raz53ae6282016-01-10 21:06:26 +010059#define MLXSW_SP_MID_MAX 7000
60
Ido Schimmel18f1e702016-02-26 17:32:31 +010061#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
62
63#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
64
Ido Schimmel1a198442016-04-06 17:10:02 +020065#define MLXSW_SP_BYTES_PER_CELL 96
66
67#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
Jiri Pirko0f433fa2016-04-14 18:19:24 +020068#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
Ido Schimmel1a198442016-04-06 17:10:02 +020069
Ido Schimmel9f7ec052016-04-06 17:10:14 +020070/* Maximum delay buffer needed in case of PAUSE frames, in cells.
71 * Assumes 100m cable and maximum MTU.
72 */
73#define MLXSW_SP_PAUSE_DELAY 612
74
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020075#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
76
Ido Schimmel464dce12016-07-02 11:00:15 +020077#define MLXSW_SP_RIF_MAX 800
78
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020079static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
80{
81 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
82 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
83}
84
Jiri Pirko56ade8f2015-10-16 14:01:37 +020085struct mlxsw_sp_port;
86
Jiri Pirko0d65fc12015-12-03 12:12:28 +010087struct mlxsw_sp_upper {
88 struct net_device *dev;
89 unsigned int ref_count;
90};
91
Ido Schimmeld0ec8752016-06-20 23:04:12 +020092struct mlxsw_sp_fid {
Ido Schimmel1c800752016-06-20 23:04:20 +020093 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel7f71eb42015-12-15 16:03:37 +010094 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +020095 unsigned int ref_count;
96 struct net_device *dev;
97 u16 fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +010098 u16 vid;
99};
100
Elad Raz3a49b4f2016-01-10 21:06:28 +0100101struct mlxsw_sp_mid {
102 struct list_head list;
103 unsigned char addr[ETH_ALEN];
104 u16 vid;
105 u16 mid;
106 unsigned int ref_count;
107};
108
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100109static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
110{
111 return MLXSW_SP_VFID_BASE + vfid;
112}
113
Ido Schimmelaac78a42015-12-15 16:03:42 +0100114static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
115{
116 return fid - MLXSW_SP_VFID_BASE;
117}
118
119static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
120{
121 return fid >= MLXSW_SP_VFID_BASE;
122}
123
Jiri Pirko078f9c72016-04-14 18:19:19 +0200124struct mlxsw_sp_sb_pr {
125 enum mlxsw_reg_sbpr_mode mode;
126 u32 size;
127};
128
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200129struct mlxsw_cp_sb_occ {
130 u32 cur;
131 u32 max;
132};
133
Jiri Pirko078f9c72016-04-14 18:19:19 +0200134struct mlxsw_sp_sb_cm {
135 u32 min_buff;
136 u32 max_buff;
137 u8 pool;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200138 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200139};
140
141struct mlxsw_sp_sb_pm {
142 u32 min_buff;
143 u32 max_buff;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200144 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200145};
146
147#define MLXSW_SP_SB_POOL_COUNT 4
148#define MLXSW_SP_SB_TC_COUNT 8
149
150struct mlxsw_sp_sb {
151 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
152 struct {
153 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
154 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
155 } ports[MLXSW_PORT_MAX_PORTS];
156};
157
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200158struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100159 struct {
160 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200161 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_PORT_MAX);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100162 } port_vfids;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100163 struct {
164 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200165 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_BR_MAX);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100166 } br_vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100167 struct {
168 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200169 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
Elad Raz3a49b4f2016-01-10 21:06:28 +0100170 } br_mids;
Ido Schimmel14d39462016-06-20 23:04:15 +0200171 struct list_head fids; /* VLAN-aware bridge FIDs */
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200172 struct mlxsw_sp_port **ports;
173 struct mlxsw_core *core;
174 const struct mlxsw_bus_info *bus_info;
175 unsigned char base_mac[ETH_ALEN];
176 struct {
177 struct delayed_work dw;
178#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
179 unsigned int interval; /* ms */
180 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800181#define MLXSW_SP_MIN_AGEING_TIME 10
182#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200183#define MLXSW_SP_DEFAULT_AGEING_TIME 300
184 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100185 struct mlxsw_sp_upper master_bridge;
186 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100187 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200188 struct mlxsw_sp_sb sb;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200189};
190
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100191static inline struct mlxsw_sp_upper *
192mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
193{
194 return &mlxsw_sp->lags[lag_id];
195}
196
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200197struct mlxsw_sp_port_pcpu_stats {
198 u64 rx_packets;
199 u64 rx_bytes;
200 u64 tx_packets;
201 u64 tx_bytes;
202 struct u64_stats_sync syncp;
203 u32 tx_dropped;
204};
205
206struct mlxsw_sp_port {
Jiri Pirko932762b2016-04-08 19:11:21 +0200207 struct mlxsw_core_port core_port; /* must be first */
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200208 struct net_device *dev;
209 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
210 struct mlxsw_sp *mlxsw_sp;
211 u8 local_port;
212 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100213 u8 learning:1,
214 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100215 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100216 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100217 lagged:1,
218 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200219 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100220 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100221 struct {
222 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200223 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100224 u16 vid;
225 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200226 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200227 u8 tx_pause:1,
228 rx_pause:1;
229 } link;
230 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200231 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200232 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200233 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200234 } dcb;
Ido Schimmeld664b412016-06-09 09:51:40 +0200235 struct {
236 u8 module;
237 u8 width;
238 u8 lane;
239 } mapping;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200240 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100241 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100242 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200243 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100244 struct list_head vports_list;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200245};
246
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200247static inline bool
248mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
249{
250 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
251}
252
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100253static inline struct mlxsw_sp_port *
254mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
255{
256 struct mlxsw_sp_port *mlxsw_sp_port;
257 u8 local_port;
258
259 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
260 lag_id, port_index);
261 mlxsw_sp_port = mlxsw_sp->ports[local_port];
262 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
263}
264
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100265static inline u16
266mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
267{
268 return mlxsw_sp_vport->vport.vid;
269}
270
Ido Schimmel6381b3a2016-06-20 23:04:16 +0200271static inline bool
272mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
273{
274 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
275
276 return vid != 0;
277}
278
Ido Schimmel41b996c2016-06-20 23:04:17 +0200279static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
280 struct mlxsw_sp_fid *f)
281{
282 mlxsw_sp_vport->vport.f = f;
283}
284
285static inline struct mlxsw_sp_fid *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200286mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100287{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200288 return mlxsw_sp_vport->vport.f;
289}
290
291static inline struct net_device *
292mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
293{
294 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
295
Ido Schimmel56918b62016-06-20 23:04:18 +0200296 return f ? f->dev : NULL;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100297}
298
299static inline struct mlxsw_sp_port *
300mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
301{
302 struct mlxsw_sp_port *mlxsw_sp_vport;
303
304 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
305 vport.list) {
306 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
307 return mlxsw_sp_vport;
308 }
309
310 return NULL;
311}
312
Ido Schimmelaac78a42015-12-15 16:03:42 +0100313static inline struct mlxsw_sp_port *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200314mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
315 u16 fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100316{
317 struct mlxsw_sp_port *mlxsw_sp_vport;
318
319 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
320 vport.list) {
Ido Schimmel41b996c2016-06-20 23:04:17 +0200321 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
322
Ido Schimmel56918b62016-06-20 23:04:18 +0200323 if (f && f->fid == fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100324 return mlxsw_sp_vport;
325 }
326
327 return NULL;
328}
329
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200330enum mlxsw_sp_flood_table {
331 MLXSW_SP_FLOOD_TABLE_UC,
332 MLXSW_SP_FLOOD_TABLE_BM,
333};
334
335int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200336void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200337int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200338int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
339 unsigned int sb_index, u16 pool_index,
340 struct devlink_sb_pool_info *pool_info);
341int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
342 unsigned int sb_index, u16 pool_index, u32 size,
343 enum devlink_sb_threshold_type threshold_type);
344int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
345 unsigned int sb_index, u16 pool_index,
346 u32 *p_threshold);
347int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
348 unsigned int sb_index, u16 pool_index,
349 u32 threshold);
350int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
351 unsigned int sb_index, u16 tc_index,
352 enum devlink_sb_pool_type pool_type,
353 u16 *p_pool_index, u32 *p_threshold);
354int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
355 unsigned int sb_index, u16 tc_index,
356 enum devlink_sb_pool_type pool_type,
357 u16 pool_index, u32 threshold);
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200358int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
359 unsigned int sb_index);
360int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
361 unsigned int sb_index);
362int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
363 unsigned int sb_index, u16 pool_index,
364 u32 *p_cur, u32 *p_max);
365int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
366 unsigned int sb_index, u16 tc_index,
367 enum devlink_sb_pool_type pool_type,
368 u32 *p_cur, u32 *p_max);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200369
370int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
371void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
372int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
373void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
374void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
375int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
376 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
377 u16 vid);
378int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
379 u16 vid_end, bool is_member, bool untagged);
380int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
381 u16 vid);
Ido Schimmele6060022016-06-20 23:04:11 +0200382int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200383 bool set);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100384void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100385int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +0200386int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200387int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
388 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
389 bool dwrr, u8 dwrr_weight);
390int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
391 u8 switch_prio, u8 tclass);
392int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200393 u8 *prio_tc, bool pause_en,
394 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200395int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
396 enum mlxsw_reg_qeec_hr hr, u8 index,
397 u8 next_index, u32 maxrate);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200398
Ido Schimmelf00817d2016-04-06 17:10:09 +0200399#ifdef CONFIG_MLXSW_SPECTRUM_DCB
400
401int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
402void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
403
404#else
405
406static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
407{
408 return 0;
409}
410
411static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
412{}
413
414#endif
415
Ido Schimmel464dce12016-07-02 11:00:15 +0200416int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
417void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
418
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200419#endif