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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
H. Peter Anvin1965aae2008-10-22 22:26:29 -07002#ifndef _ASM_X86_PROCESSOR_H
3#define _ASM_X86_PROCESSOR_H
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +01004
Glauber de Oliveira Costa053de042008-01-30 13:31:27 +01005#include <asm/processor-flags.h>
6
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +01007/* Forward declaration, a strange C thing */
8struct task_struct;
9struct mm_struct;
Brian Gerst9fda6a02015-07-29 01:41:16 -040010struct vm86;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +010011
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010012#include <asm/math_emu.h>
13#include <asm/segment.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010014#include <asm/types.h>
Ingo Molnardecb4c42015-09-05 09:32:43 +020015#include <uapi/asm/sigcontext.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010016#include <asm/current.h>
Borislav Petkovcd4d09e2016-01-26 22:12:04 +010017#include <asm/cpufeatures.h>
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +010018#include <asm/page.h>
Jeremy Fitzhardinge54321d92009-02-11 10:20:05 -080019#include <asm/pgtable_types.h>
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +010020#include <asm/percpu.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010021#include <asm/msr.h>
22#include <asm/desc_defs.h>
Andi Kleenbd616432008-01-30 13:32:38 +010023#include <asm/nops.h>
David Howellsf05e7982012-03-28 18:11:12 +010024#include <asm/special_insns.h>
Ingo Molnar14b96752015-04-22 09:57:24 +020025#include <asm/fpu/types.h>
Josh Poimboeuf76846bf2017-07-11 10:33:45 -050026#include <asm/unwind_hints.h>
Ingo Molnar4d46a892008-02-21 04:24:40 +010027
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010028#include <linux/personality.h>
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +010029#include <linux/cache.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010030#include <linux/threads.h>
Peter Zijlstra5cbc19a2009-09-02 11:49:52 +020031#include <linux/math64.h>
Peter Zijlstrafaa46022010-03-25 14:51:50 +010032#include <linux/err.h>
David Howellsf05e7982012-03-28 18:11:12 +010033#include <linux/irqflags.h>
Tom Lendacky21729f82017-07-17 16:10:07 -050034#include <linux/mem_encrypt.h>
David Howellsf05e7982012-03-28 18:11:12 +010035
36/*
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
39 *
40 * Based on this we disable the IP header alignment in network drivers.
41 */
42#define NET_IP_ALIGN 0
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +010043
K.Prasadb332828c2009-06-01 23:43:10 +053044#define HBP_NUM 4
Glauber de Oliveira Costa0ccb8ac2008-01-30 13:31:27 +010045
Ingo Molnarb8c1b8ea2015-05-24 09:58:12 +020046/*
47 * These alignment constraints are for performance in the vSMP case,
48 * but in the task_struct case we must also meet hardware imposed
49 * alignment requirements of the FPU state:
50 */
Glauber de Oliveira Costadbcb4662008-01-30 13:31:31 +010051#ifdef CONFIG_X86_VSMP
Ingo Molnar4d46a892008-02-21 04:24:40 +010052# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
53# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
Glauber de Oliveira Costadbcb4662008-01-30 13:31:31 +010054#else
Ingo Molnarb8c1b8ea2015-05-24 09:58:12 +020055# define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
Ingo Molnar4d46a892008-02-21 04:24:40 +010056# define ARCH_MIN_MMSTRUCT_ALIGN 0
Glauber de Oliveira Costadbcb4662008-01-30 13:31:31 +010057#endif
58
Alex Shie0ba94f2012-06-28 09:02:16 +080059enum tlb_infos {
60 ENTRIES,
61 NR_INFO
62};
63
64extern u16 __read_mostly tlb_lli_4k[NR_INFO];
65extern u16 __read_mostly tlb_lli_2m[NR_INFO];
66extern u16 __read_mostly tlb_lli_4m[NR_INFO];
67extern u16 __read_mostly tlb_lld_4k[NR_INFO];
68extern u16 __read_mostly tlb_lld_2m[NR_INFO];
69extern u16 __read_mostly tlb_lld_4m[NR_INFO];
Kirill A. Shutemovdd360392013-12-23 14:16:58 +020070extern u16 __read_mostly tlb_lld_1g[NR_INFO];
Alex Shic4211f42012-06-28 09:02:19 +080071
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +010072/*
73 * CPU type and hardware bug flags. Kept separately for each CPU.
Mathias Krause04402112017-02-12 22:12:07 +010074 * Members of this structure are referenced in head_32.S, so think twice
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +010075 * before touching them. [mj]
76 */
77
78struct cpuinfo_x86 {
Ingo Molnar4d46a892008-02-21 04:24:40 +010079 __u8 x86; /* CPU family */
80 __u8 x86_vendor; /* CPU vendor */
81 __u8 x86_model;
Jia Zhangb3991512018-01-01 09:52:10 +080082 __u8 x86_stepping;
Mathias Krause64158132017-02-12 22:12:08 +010083#ifdef CONFIG_X86_64
Ingo Molnar4d46a892008-02-21 04:24:40 +010084 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
H. Peter Anvinb1882e62009-01-23 17:18:52 -080085 int x86_tlbsize;
Jan Beulich13c6c532009-03-12 12:37:34 +000086#endif
Ingo Molnar4d46a892008-02-21 04:24:40 +010087 __u8 x86_virt_bits;
88 __u8 x86_phys_bits;
89 /* CPUID returned core id bits: */
90 __u8 x86_coreid_bits;
Borislav Petkov79a8b9a2017-02-05 11:50:21 +010091 __u8 cu_id;
Ingo Molnar4d46a892008-02-21 04:24:40 +010092 /* Max extended CPUID function supported: */
93 __u32 extended_cpuid_level;
Ingo Molnar4d46a892008-02-21 04:24:40 +010094 /* Maximum supported CPUID level, -1=no CPUID: */
95 int cpuid_level;
Borislav Petkov65fc9852013-03-20 15:07:23 +010096 __u32 x86_capability[NCAPINTS + NBUGINTS];
Ingo Molnar4d46a892008-02-21 04:24:40 +010097 char x86_vendor_id[16];
98 char x86_model_id[64];
99 /* in KB - valid for CPUS which support this call: */
Gustavo A. R. Silva24dbc602018-02-13 13:22:08 -0600100 unsigned int x86_cache_size;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100101 int x86_cache_alignment; /* In bytes */
Peter P Waskiewicz Jrcbc82b12015-01-23 18:45:43 +0000102 /* Cache QoS architectural values: */
103 int x86_cache_max_rmid; /* max index */
104 int x86_cache_occ_scale; /* scale to bytes */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100105 int x86_power;
106 unsigned long loops_per_jiffy;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100107 /* cpuid returned max cores value: */
108 u16 x86_max_cores;
109 u16 apicid;
Yinghai Lu01aaea12008-03-06 13:46:39 -0800110 u16 initial_apicid;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100111 u16 x86_clflush_size;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100112 /* number of cores as seen by the OS: */
113 u16 booted_cores;
114 /* Physical processor id: */
115 u16 phys_proc_id;
Thomas Gleixner1f12e322016-02-22 22:19:15 +0000116 /* Logical processor id: */
117 u16 logical_proc_id;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100118 /* Core id: */
119 u16 cpu_core_id;
120 /* Index into per_cpu list: */
121 u16 cpu_index;
Andi Kleen506ed6b2011-10-12 17:46:33 -0700122 u32 microcode;
Andi Kleencc51e542018-08-24 10:03:50 -0700123 /* Address space bits used by the cache internally */
124 u8 x86_cache_bits;
Andi Kleen30bb9812017-11-14 07:42:56 -0500125 unsigned initialized : 1;
Kees Cook3859a272016-10-28 01:22:25 -0700126} __randomize_layout;
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100127
He Chen47f10a32016-11-11 17:25:34 +0800128struct cpuid_regs {
129 u32 eax, ebx, ecx, edx;
130};
131
132enum cpuid_regs_idx {
133 CPUID_EAX = 0,
134 CPUID_EBX,
135 CPUID_ECX,
136 CPUID_EDX,
137};
138
Ingo Molnar4d46a892008-02-21 04:24:40 +0100139#define X86_VENDOR_INTEL 0
140#define X86_VENDOR_CYRIX 1
141#define X86_VENDOR_AMD 2
142#define X86_VENDOR_UMC 3
Ingo Molnar4d46a892008-02-21 04:24:40 +0100143#define X86_VENDOR_CENTAUR 5
144#define X86_VENDOR_TRANSMETA 7
145#define X86_VENDOR_NSC 8
Pu Wenc9661c12018-09-23 17:33:12 +0800146#define X86_VENDOR_HYGON 9
147#define X86_VENDOR_NUM 10
Ingo Molnar4d46a892008-02-21 04:24:40 +0100148
149#define X86_VENDOR_UNKNOWN 0xff
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100150
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100151/*
152 * capabilities of CPUs
153 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100154extern struct cpuinfo_x86 boot_cpu_data;
155extern struct cpuinfo_x86 new_cpu_data;
156
Andy Lutomirski7fb983b2017-12-04 15:07:17 +0100157extern struct x86_hw_tss doublefault_tss;
Thomas Gleixner6cbd2172017-12-04 15:07:32 +0100158extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
159extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100160
161#ifdef CONFIG_SMP
Jan Beulich2c773dd2014-11-04 08:26:42 +0000162DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100163#define cpu_data(cpu) per_cpu(cpu_info, cpu)
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100164#else
Tejun Heo7b543a52010-12-18 16:30:05 +0100165#define cpu_info boot_cpu_data
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100166#define cpu_data(cpu) boot_cpu_data
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100167#endif
168
Jaswinder Singh1c6c7272008-07-21 22:40:37 +0530169extern const struct seq_operations cpuinfo_op;
170
Ingo Molnar4d46a892008-02-21 04:24:40 +0100171#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
172
173extern void cpu_detect(struct cpuinfo_x86 *c);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100174
Vlastimil Babka9df95162018-08-20 11:58:35 +0200175static inline unsigned long long l1tf_pfn_limit(void)
Andi Kleen17dbca12018-06-13 15:48:26 -0700176{
Andi Kleencc51e542018-08-24 10:03:50 -0700177 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
Andi Kleen17dbca12018-06-13 15:48:26 -0700178}
179
Yinghai Luf5803662008-06-21 03:24:19 -0700180extern void early_cpu_init(void);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100181extern void identify_boot_cpu(void);
182extern void identify_secondary_cpu(struct cpuinfo_x86 *);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100183extern void print_cpu_info(struct cpuinfo_x86 *);
Yinghai Lu21c3fcf2012-02-12 09:53:57 -0800184void print_cpu_msr(struct cpuinfo_x86 *);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100185
Fenghua Yud288e1c2012-12-20 23:44:23 -0800186#ifdef CONFIG_X86_32
187extern int have_cpuid_p(void);
188#else
189static inline int have_cpuid_p(void)
190{
191 return 1;
192}
193#endif
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100194static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
Ingo Molnar4d46a892008-02-21 04:24:40 +0100195 unsigned int *ecx, unsigned int *edx)
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100196{
197 /* ecx is often an input as well as an output. */
Suresh Siddha45a94d72009-12-16 16:25:42 -0800198 asm volatile("cpuid"
Joe Perchescca2e6f2008-03-23 01:03:15 -0700199 : "=a" (*eax),
200 "=b" (*ebx),
201 "=c" (*ecx),
202 "=d" (*edx)
Andi Kleen506ed6b2011-10-12 17:46:33 -0700203 : "0" (*eax), "2" (*ecx)
204 : "memory");
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100205}
206
Borislav Petkov5dedade2017-01-09 12:41:43 +0100207#define native_cpuid_reg(reg) \
208static inline unsigned int native_cpuid_##reg(unsigned int op) \
209{ \
210 unsigned int eax = op, ebx, ecx = 0, edx; \
211 \
212 native_cpuid(&eax, &ebx, &ecx, &edx); \
213 \
214 return reg; \
215}
216
217/*
218 * Native CPUID functions returning a single datum.
219 */
220native_cpuid_reg(eax)
221native_cpuid_reg(ebx)
222native_cpuid_reg(ecx)
223native_cpuid_reg(edx)
224
Andy Lutomirski6c690ee2017-06-12 10:26:14 -0700225/*
226 * Friendlier CR3 helpers.
227 */
228static inline unsigned long read_cr3_pa(void)
229{
230 return __read_cr3() & CR3_ADDR_MASK;
231}
232
Tom Lendackyeef9c4a2017-07-17 16:10:08 -0500233static inline unsigned long native_read_cr3_pa(void)
234{
235 return __native_read_cr3() & CR3_ADDR_MASK;
236}
237
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +0100238static inline void load_cr3(pgd_t *pgdir)
239{
Tom Lendacky21729f82017-07-17 16:10:07 -0500240 write_cr3(__sme_pa(pgdir));
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +0100241}
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100242
Andy Lutomirski7fb983b2017-12-04 15:07:17 +0100243/*
244 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
245 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
246 * unrelated to the task-switch mechanism:
247 */
Thomas Gleixner96a388d2007-10-11 11:20:03 +0200248#ifdef CONFIG_X86_32
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100249/* This is the TSS defined by the hardware. */
250struct x86_hw_tss {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100251 unsigned short back_link, __blh;
252 unsigned long sp0;
253 unsigned short ss0, __ss0h;
Andy Lutomirskicf9328c2015-04-02 12:41:45 -0700254 unsigned long sp1;
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700255
256 /*
Andy Lutomirskicf9328c2015-04-02 12:41:45 -0700257 * We don't use ring 1, so ss1 is a convenient scratch space in
258 * the same cacheline as sp0. We use ss1 to cache the value in
259 * MSR_IA32_SYSENTER_CS. When we context switch
260 * MSR_IA32_SYSENTER_CS, we first check if the new value being
261 * written matches ss1, and, if it's not, then we wrmsr the new
262 * value and update ss1.
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700263 *
Andy Lutomirskicf9328c2015-04-02 12:41:45 -0700264 * The only reason we context switch MSR_IA32_SYSENTER_CS is
265 * that we set it to zero in vm86 tasks to avoid corrupting the
266 * stack if we were to go through the sysenter path from vm86
267 * mode.
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700268 */
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700269 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
270
271 unsigned short __ss1h;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100272 unsigned long sp2;
273 unsigned short ss2, __ss2h;
274 unsigned long __cr3;
275 unsigned long ip;
276 unsigned long flags;
277 unsigned long ax;
278 unsigned long cx;
279 unsigned long dx;
280 unsigned long bx;
281 unsigned long sp;
282 unsigned long bp;
283 unsigned long si;
284 unsigned long di;
285 unsigned short es, __esh;
286 unsigned short cs, __csh;
287 unsigned short ss, __ssh;
288 unsigned short ds, __dsh;
289 unsigned short fs, __fsh;
290 unsigned short gs, __gsh;
291 unsigned short ldt, __ldth;
292 unsigned short trace;
293 unsigned short io_bitmap_base;
294
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100295} __attribute__((packed));
296#else
297struct x86_hw_tss {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100298 u32 reserved1;
299 u64 sp0;
Andy Lutomirski9aaefe72017-12-04 15:07:21 +0100300
301 /*
302 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
303 * Linux does not use ring 1, so sp1 is not otherwise needed.
304 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100305 u64 sp1;
Andy Lutomirski9aaefe72017-12-04 15:07:21 +0100306
Andy Lutomirski98f05b52018-09-03 15:59:43 -0700307 /*
308 * Since Linux does not use ring 2, the 'sp2' slot is unused by
309 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
310 * the user RSP value.
311 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100312 u64 sp2;
Andy Lutomirski98f05b52018-09-03 15:59:43 -0700313
Ingo Molnar4d46a892008-02-21 04:24:40 +0100314 u64 reserved2;
315 u64 ist[7];
316 u32 reserved3;
317 u32 reserved4;
318 u16 reserved5;
319 u16 io_bitmap_base;
320
Andy Lutomirskid3273de2017-02-20 08:56:13 -0800321} __attribute__((packed));
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100322#endif
323
324/*
Ingo Molnar4d46a892008-02-21 04:24:40 +0100325 * IO-bitmap sizes:
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100326 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100327#define IO_BITMAP_BITS 65536
328#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
329#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
Andy Lutomirski7fb983b2017-12-04 15:07:17 +0100330#define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
Ingo Molnar4d46a892008-02-21 04:24:40 +0100331#define INVALID_IO_BITMAP_OFFSET 0x8000
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100332
Dave Hansen4fe2d8b2017-12-04 17:25:07 -0800333struct entry_stack {
Andy Lutomirski0f9a4812017-12-04 15:07:28 +0100334 unsigned long words[64];
335};
336
Dave Hansen4fe2d8b2017-12-04 17:25:07 -0800337struct entry_stack_page {
338 struct entry_stack stack;
Andy Lutomirskic482fee2017-12-04 15:07:29 +0100339} __aligned(PAGE_SIZE);
Andy Lutomirski1a935bc2017-12-04 15:07:19 +0100340
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100341struct tss_struct {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100342 /*
Andy Lutomirski1a935bc2017-12-04 15:07:19 +0100343 * The fixed hardware portion. This must not cross a page boundary
344 * at risk of violating the SDM's advice and potentially triggering
345 * errata.
Ingo Molnar4d46a892008-02-21 04:24:40 +0100346 */
347 struct x86_hw_tss x86_tss;
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100348
349 /*
350 * The extra 1 is there because the CPU will access an
351 * additional byte beyond the end of the IO permission
352 * bitmap. The extra byte must be all 1 bits, and must
353 * be within the limit.
354 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100355 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
Andy Lutomirski1a935bc2017-12-04 15:07:19 +0100356} __aligned(PAGE_SIZE);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100357
Andy Lutomirskic482fee2017-12-04 15:07:29 +0100358DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100359
Andy Lutomirski4f53ab12017-02-20 08:56:09 -0800360/*
361 * sizeof(unsigned long) coming from an extra "long" at the end
362 * of the iobitmap.
363 *
364 * -1? seg base+limit should be pointing to the address of the
365 * last valid byte
366 */
367#define __KERNEL_TSS_LIMIT \
368 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
369
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800370#ifdef CONFIG_X86_32
371DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
Andy Lutomirski9aaefe72017-12-04 15:07:21 +0100372#else
Andy Lutomirskic482fee2017-12-04 15:07:29 +0100373/* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
374#define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800375#endif
376
Ingo Molnar4d46a892008-02-21 04:24:40 +0100377/*
378 * Save the original ist values for checking stack pointers during debugging
379 */
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100380struct orig_ist {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100381 unsigned long ist[7];
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100382};
383
Glauber Costafe676202008-03-03 14:12:56 -0300384#ifdef CONFIG_X86_64
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100385DECLARE_PER_CPU(struct orig_ist, orig_ist);
Brian Gerst26f80bd2009-01-19 00:38:58 +0900386
Brian Gerst947e76c2009-01-19 12:21:28 +0900387union irq_stack_union {
388 char irq_stack[IRQ_STACK_SIZE];
389 /*
390 * GCC hardcodes the stack canary as %gs:40. Since the
391 * irq_stack is the object at %gs:0, we reserve the bottom
392 * 48 bytes of the irq stack for the canary.
393 */
394 struct {
395 char gs_base[40];
396 unsigned long stack_canary;
397 };
398};
399
Andi Kleen277d5b42013-08-05 15:02:43 -0700400DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
Brian Gerst2add8e22009-02-08 09:58:39 -0500401DECLARE_INIT_PER_CPU(irq_stack_union);
402
Vitaly Kuznetsov35060ed2018-03-13 18:48:05 +0100403static inline unsigned long cpu_kernelmode_gs_base(int cpu)
404{
405 return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu);
406}
407
Brian Gerst26f80bd2009-01-19 00:38:58 +0900408DECLARE_PER_CPU(char *, irq_stack_ptr);
Jaswinder Singh Rajput9766cdb2009-03-14 11:19:49 +0530409DECLARE_PER_CPU(unsigned int, irq_count);
Jaswinder Singh Rajput9766cdb2009-03-14 11:19:49 +0530410extern asmlinkage void ignore_sysret(void);
Vitaly Kuznetsov42b933b2018-03-13 18:48:04 +0100411
412#if IS_ENABLED(CONFIG_KVM)
413/* Save actual FS/GS selectors and bases to current->thread */
414void save_fsgs_for_kvm(void);
415#endif
Tejun Heo60a53172009-02-09 22:17:40 +0900416#else /* X86_64 */
Linus Torvalds050e9ba2018-06-14 12:21:18 +0900417#ifdef CONFIG_STACKPROTECTOR
Jeremy Fitzhardinge1ea0d142009-09-03 12:27:15 -0700418/*
419 * Make sure stack canary segment base is cached-aligned:
420 * "For Intel Atom processors, avoid non zero segment base address
421 * that is not aligned to cache line boundary at all cost."
422 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
423 */
424struct stack_canary {
425 char __pad[20]; /* canary at %gs:20 */
426 unsigned long canary;
427};
Jeremy Fitzhardinge53f82452009-09-03 14:31:44 -0700428DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
Thomas Gleixner96a388d2007-10-11 11:20:03 +0200429#endif
Steven Rostedt198d2082014-02-06 09:41:31 -0500430/*
431 * per-CPU IRQ handling stacks
432 */
433struct irq_stack {
434 u32 stack[THREAD_SIZE/sizeof(u32)];
435} __aligned(THREAD_SIZE);
436
437DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
438DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
Tejun Heo60a53172009-02-09 22:17:40 +0900439#endif /* X86_64 */
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100440
Fenghua Yubf15a8c2016-05-20 10:47:06 -0700441extern unsigned int fpu_kernel_xstate_size;
Fenghua Yua1141e02016-05-20 10:47:05 -0700442extern unsigned int fpu_user_xstate_size;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100443
Frederic Weisbecker24f1e32c2009-09-09 19:22:48 +0200444struct perf_event;
445
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700446typedef struct {
447 unsigned long seg;
448} mm_segment_t;
449
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100450struct thread_struct {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100451 /* Cached TLS descriptors: */
452 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
Andy Lutomirskid375cf12017-11-02 00:59:16 -0700453#ifdef CONFIG_X86_32
Ingo Molnar4d46a892008-02-21 04:24:40 +0100454 unsigned long sp0;
Andy Lutomirskid375cf12017-11-02 00:59:16 -0700455#endif
Ingo Molnar4d46a892008-02-21 04:24:40 +0100456 unsigned long sp;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100457#ifdef CONFIG_X86_32
Ingo Molnar4d46a892008-02-21 04:24:40 +0100458 unsigned long sysenter_cs;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100459#else
Ingo Molnar4d46a892008-02-21 04:24:40 +0100460 unsigned short es;
461 unsigned short ds;
462 unsigned short fsindex;
463 unsigned short gsindex;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100464#endif
Andy Lutomirskib9d989c2016-09-13 14:29:21 -0700465
Alexey Dobriyand756f4ad2009-05-04 03:29:52 +0400466#ifdef CONFIG_X86_64
Andy Lutomirski296f7812016-04-26 12:23:29 -0700467 unsigned long fsbase;
468 unsigned long gsbase;
469#else
470 /*
471 * XXX: this could presumably be unsigned short. Alternatively,
472 * 32-bit kernels could be taught to use fsindex instead.
473 */
474 unsigned long fs;
475 unsigned long gs;
Alexey Dobriyand756f4ad2009-05-04 03:29:52 +0400476#endif
Ingo Molnarc5bedc62015-04-23 12:49:20 +0200477
Frederic Weisbecker24f1e32c2009-09-09 19:22:48 +0200478 /* Save middle states of ptrace breakpoints */
479 struct perf_event *ptrace_bps[HBP_NUM];
480 /* Debug status used for traps, single steps, etc... */
481 unsigned long debugreg6;
Frederic Weisbecker326264a2010-02-18 18:24:18 +0100482 /* Keep track of the exact dr7 value set by the user */
483 unsigned long ptrace_dr7;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100484 /* Fault info: */
485 unsigned long cr2;
Srikar Dronamraju51e7dc72012-03-12 14:55:55 +0530486 unsigned long trap_nr;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100487 unsigned long error_code;
Brian Gerst9fda6a02015-07-29 01:41:16 -0400488#ifdef CONFIG_VM86
Ingo Molnar4d46a892008-02-21 04:24:40 +0100489 /* Virtual 86 mode info */
Brian Gerst9fda6a02015-07-29 01:41:16 -0400490 struct vm86 *vm86;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100491#endif
Ingo Molnar4d46a892008-02-21 04:24:40 +0100492 /* IO permissions: */
493 unsigned long *io_bitmap_ptr;
494 unsigned long iopl;
495 /* Max allowed port in the bitmap, in bytes: */
496 unsigned io_bitmap_max;
Dave Hansen0c8c0f02015-07-17 12:28:11 +0200497
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700498 mm_segment_t addr_limit;
499
Ingo Molnar2a53ccb2016-07-15 10:21:11 +0200500 unsigned int sig_on_uaccess_err:1;
Andy Lutomirskidfa9a942016-07-14 13:22:56 -0700501 unsigned int uaccess_err:1; /* uaccess failed */
502
Dave Hansen0c8c0f02015-07-17 12:28:11 +0200503 /* Floating point and extended processor state */
504 struct fpu fpu;
505 /*
506 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
507 * the end.
508 */
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100509};
510
Kees Cookf7d83c12017-08-16 13:26:03 -0700511/* Whitelist the FPU state from the task_struct for hardened usercopy. */
512static inline void arch_thread_struct_whitelist(unsigned long *offset,
513 unsigned long *size)
514{
515 *offset = offsetof(struct thread_struct, fpu.state);
516 *size = fpu_kernel_xstate_size;
517}
518
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100519/*
Andy Lutomirskib9d989c2016-09-13 14:29:21 -0700520 * Thread-synchronous status.
521 *
522 * This is different from the flags in that nobody else
523 * ever touches our thread-synchronous status, so we don't
524 * have to worry about atomic accesses.
525 */
526#define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
527
528/*
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100529 * Set IOPL bits in EFLAGS from given mask
530 */
531static inline void native_set_iopl_mask(unsigned mask)
532{
533#ifdef CONFIG_X86_32
534 unsigned int reg;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100535
Joe Perchescca2e6f2008-03-23 01:03:15 -0700536 asm volatile ("pushfl;"
537 "popl %0;"
538 "andl %1, %0;"
539 "orl %2, %0;"
540 "pushl %0;"
541 "popfl"
542 : "=&r" (reg)
543 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100544#endif
545}
546
Ingo Molnar4d46a892008-02-21 04:24:40 +0100547static inline void
Andy Lutomirskida51da12017-11-02 00:59:10 -0700548native_load_sp0(unsigned long sp0)
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100549{
Andy Lutomirskic482fee2017-12-04 15:07:29 +0100550 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100551}
Glauber de Oliveira Costa1b46cbe2008-01-30 13:31:27 +0100552
Glauber de Oliveira Costae801f862008-01-30 13:32:08 +0100553static inline void native_swapgs(void)
554{
555#ifdef CONFIG_X86_64
556 asm volatile("swapgs" ::: "memory");
557#endif
558}
559
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800560static inline unsigned long current_top_of_stack(void)
Andy Lutomirski8ef46a62015-03-05 19:19:02 -0800561{
Andy Lutomirski9aaefe72017-12-04 15:07:21 +0100562 /*
563 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
564 * and around vm86 mode and sp0 on x86_64 is special because of the
565 * entry trampoline.
566 */
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800567 return this_cpu_read_stable(cpu_current_top_of_stack);
Andy Lutomirski8ef46a62015-03-05 19:19:02 -0800568}
569
Andy Lutomirski33836422017-11-02 00:59:17 -0700570static inline bool on_thread_stack(void)
571{
572 return (unsigned long)(current_top_of_stack() -
573 current_stack_pointer) < THREAD_SIZE;
574}
575
Juergen Gross9bad5652018-08-28 09:40:23 +0200576#ifdef CONFIG_PARAVIRT_XXL
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100577#include <asm/paravirt.h>
578#else
Ingo Molnar4d46a892008-02-21 04:24:40 +0100579#define __cpuid native_cpuid
Glauber de Oliveira Costa1b46cbe2008-01-30 13:31:27 +0100580
Andy Lutomirskida51da12017-11-02 00:59:10 -0700581static inline void load_sp0(unsigned long sp0)
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100582{
Andy Lutomirskida51da12017-11-02 00:59:10 -0700583 native_load_sp0(sp0);
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100584}
585
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100586#define set_iopl_mask native_set_iopl_mask
Juergen Gross9bad5652018-08-28 09:40:23 +0200587#endif /* CONFIG_PARAVIRT_XXL */
Glauber de Oliveira Costa1b46cbe2008-01-30 13:31:27 +0100588
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100589/* Free all resources held by a thread. */
590extern void release_thread(struct task_struct *);
591
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100592unsigned long get_wchan(struct task_struct *p);
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100593
594/*
595 * Generic CPUID function
596 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
597 * resulting in stale register contents being returned.
598 */
599static inline void cpuid(unsigned int op,
600 unsigned int *eax, unsigned int *ebx,
601 unsigned int *ecx, unsigned int *edx)
602{
603 *eax = op;
604 *ecx = 0;
605 __cpuid(eax, ebx, ecx, edx);
606}
607
608/* Some CPUID calls want 'count' to be placed in ecx */
609static inline void cpuid_count(unsigned int op, int count,
610 unsigned int *eax, unsigned int *ebx,
611 unsigned int *ecx, unsigned int *edx)
612{
613 *eax = op;
614 *ecx = count;
615 __cpuid(eax, ebx, ecx, edx);
616}
617
618/*
619 * CPUID functions returning a single datum
620 */
621static inline unsigned int cpuid_eax(unsigned int op)
622{
623 unsigned int eax, ebx, ecx, edx;
624
625 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100626
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100627 return eax;
628}
Ingo Molnar4d46a892008-02-21 04:24:40 +0100629
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100630static inline unsigned int cpuid_ebx(unsigned int op)
631{
632 unsigned int eax, ebx, ecx, edx;
633
634 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100635
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100636 return ebx;
637}
Ingo Molnar4d46a892008-02-21 04:24:40 +0100638
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100639static inline unsigned int cpuid_ecx(unsigned int op)
640{
641 unsigned int eax, ebx, ecx, edx;
642
643 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100644
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100645 return ecx;
646}
Ingo Molnar4d46a892008-02-21 04:24:40 +0100647
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100648static inline unsigned int cpuid_edx(unsigned int op)
649{
650 unsigned int eax, ebx, ecx, edx;
651
652 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100653
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100654 return edx;
655}
656
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100657/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
Denys Vlasenko0b101e62015-09-24 14:02:29 +0200658static __always_inline void rep_nop(void)
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100659{
Joe Perchescca2e6f2008-03-23 01:03:15 -0700660 asm volatile("rep; nop" ::: "memory");
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100661}
662
Denys Vlasenko0b101e62015-09-24 14:02:29 +0200663static __always_inline void cpu_relax(void)
Ingo Molnar4d46a892008-02-21 04:24:40 +0100664{
665 rep_nop();
666}
667
Andy Lutomirskic198b122016-12-09 10:24:08 -0800668/*
669 * This function forces the icache and prefetched instruction stream to
670 * catch up with reality in two very specific cases:
671 *
672 * a) Text was modified using one virtual address and is about to be executed
673 * from the same physical page at a different virtual address.
674 *
675 * b) Text was modified on a different CPU, may subsequently be
676 * executed on this CPU, and you want to make sure the new version
677 * gets executed. This generally means you're calling this in a IPI.
678 *
679 * If you're calling this for a different reason, you're probably doing
680 * it wrong.
681 */
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100682static inline void sync_core(void)
683{
Andy Lutomirskic198b122016-12-09 10:24:08 -0800684 /*
685 * There are quite a few ways to do this. IRET-to-self is nice
686 * because it works on every CPU, at any CPL (so it's compatible
687 * with paravirtualization), and it never exits to a hypervisor.
688 * The only down sides are that it's a bit slow (it seems to be
689 * a bit more than 2x slower than the fastest options) and that
690 * it unmasks NMIs. The "push %cs" is needed because, in
691 * paravirtual environments, __KERNEL_CS may not be a valid CS
692 * value when we do IRET directly.
693 *
694 * In case NMI unmasking or performance ever becomes a problem,
695 * the next best option appears to be MOV-to-CR2 and an
696 * unconditional jump. That sequence also works on all CPUs,
Juergen Grossecda85e2017-08-16 19:31:57 +0200697 * but it will fault at CPL3 (i.e. Xen PV).
Andy Lutomirskic198b122016-12-09 10:24:08 -0800698 *
699 * CPUID is the conventional way, but it's nasty: it doesn't
700 * exist on some 486-like CPUs, and it usually exits to a
701 * hypervisor.
702 *
703 * Like all of Linux's memory ordering operations, this is a
704 * compiler barrier as well.
705 */
Andy Lutomirski1c52d852016-12-09 10:24:05 -0800706#ifdef CONFIG_X86_32
Andy Lutomirskic198b122016-12-09 10:24:08 -0800707 asm volatile (
708 "pushfl\n\t"
709 "pushl %%cs\n\t"
710 "pushl $1f\n\t"
711 "iret\n\t"
712 "1:"
Josh Poimboeuff5caf622017-09-20 16:24:33 -0500713 : ASM_CALL_CONSTRAINT : : "memory");
H. Peter Anvin45c39fb2012-11-28 11:50:30 -0800714#else
Andy Lutomirskic198b122016-12-09 10:24:08 -0800715 unsigned int tmp;
716
717 asm volatile (
Josh Poimboeuf76846bf2017-07-11 10:33:45 -0500718 UNWIND_HINT_SAVE
Andy Lutomirskic198b122016-12-09 10:24:08 -0800719 "mov %%ss, %0\n\t"
720 "pushq %q0\n\t"
721 "pushq %%rsp\n\t"
722 "addq $8, (%%rsp)\n\t"
723 "pushfq\n\t"
724 "mov %%cs, %0\n\t"
725 "pushq %q0\n\t"
726 "pushq $1f\n\t"
727 "iretq\n\t"
Josh Poimboeuf76846bf2017-07-11 10:33:45 -0500728 UNWIND_HINT_RESTORE
Andy Lutomirskic198b122016-12-09 10:24:08 -0800729 "1:"
Josh Poimboeuff5caf622017-09-20 16:24:33 -0500730 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
Ben Hutchings5367b682009-09-10 02:53:50 +0100731#endif
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100732}
733
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100734extern void select_idle_routine(const struct cpuinfo_x86 *c);
Borislav Petkov07c94a32016-12-09 19:29:11 +0100735extern void amd_e400_c1e_apic_setup(void);
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100736
Ingo Molnar4d46a892008-02-21 04:24:40 +0100737extern unsigned long boot_option_idle_override;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100738
Thomas Renningerd1896042010-11-03 17:06:14 +0100739enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
Len Brown69fb3672013-02-10 01:38:39 -0500740 IDLE_POLL};
Thomas Renningerd1896042010-11-03 17:06:14 +0100741
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100742extern void enable_sep_cpu(void);
743extern int sysenter_setup(void);
744
H. Peter Anvin8170e6b2013-01-24 12:19:52 -0800745void early_trap_pf_init(void);
Jan Kiszka29c84392010-05-20 21:04:29 -0500746
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100747/* Defined in head.S */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100748extern struct desc_ptr early_gdt_descr;
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100749
Brian Gerst552be872009-01-30 17:47:53 +0900750extern void switch_to_new_gdt(int);
Thomas Garnier45fc8752017-03-14 10:05:08 -0700751extern void load_direct_gdt(int);
Thomas Garnier69218e42017-03-14 10:05:07 -0700752extern void load_fixmap_gdt(int);
Jeremy Fitzhardinge11e3a842009-01-30 17:47:54 +0900753extern void load_percpu_segment(int);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100754extern void cpu_init(void);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100755
Markus Metzgerc2724772008-12-11 13:49:59 +0100756static inline unsigned long get_debugctlmsr(void)
757{
Peter Zijlstraea8e61b2010-03-25 14:51:51 +0100758 unsigned long debugctlmsr = 0;
Markus Metzgerc2724772008-12-11 13:49:59 +0100759
760#ifndef CONFIG_X86_DEBUGCTLMSR
761 if (boot_cpu_data.x86 < 6)
762 return 0;
763#endif
764 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
765
Peter Zijlstraea8e61b2010-03-25 14:51:51 +0100766 return debugctlmsr;
Markus Metzgerc2724772008-12-11 13:49:59 +0100767}
768
Jan Beulich5b0e5082008-03-10 13:11:17 +0000769static inline void update_debugctlmsr(unsigned long debugctlmsr)
770{
771#ifndef CONFIG_X86_DEBUGCTLMSR
772 if (boot_cpu_data.x86 < 6)
773 return;
774#endif
775 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
776}
777
Oleg Nesterov9bd11902012-09-03 15:24:17 +0200778extern void set_task_blockstep(struct task_struct *task, bool on);
779
Ingo Molnar4d46a892008-02-21 04:24:40 +0100780/* Boot loader type from the setup header: */
781extern int bootloader_type;
H. Peter Anvin50312962009-05-07 16:54:11 -0700782extern int bootloader_version;
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100783
Ingo Molnar4d46a892008-02-21 04:24:40 +0100784extern char ignore_fpu_irq;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100785
786#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
787#define ARCH_HAS_PREFETCHW
788#define ARCH_HAS_SPINLOCK_PREFETCH
789
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100790#ifdef CONFIG_X86_32
Borislav Petkova930dc42015-01-18 17:48:18 +0100791# define BASE_PREFETCH ""
Ingo Molnar4d46a892008-02-21 04:24:40 +0100792# define ARCH_HAS_PREFETCH
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100793#else
Borislav Petkova930dc42015-01-18 17:48:18 +0100794# define BASE_PREFETCH "prefetcht0 %P1"
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100795#endif
796
Ingo Molnar4d46a892008-02-21 04:24:40 +0100797/*
798 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
799 *
800 * It's not worth to care about 3dnow prefetches for the K6
801 * because they are microcoded there and very slow.
802 */
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100803static inline void prefetch(const void *x)
804{
Borislav Petkova930dc42015-01-18 17:48:18 +0100805 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100806 X86_FEATURE_XMM,
Borislav Petkova930dc42015-01-18 17:48:18 +0100807 "m" (*(const char *)x));
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100808}
809
Ingo Molnar4d46a892008-02-21 04:24:40 +0100810/*
811 * 3dnow prefetch to get an exclusive cache line.
812 * Useful for spinlocks to avoid one state transition in the
813 * cache coherency protocol:
814 */
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100815static inline void prefetchw(const void *x)
816{
Borislav Petkova930dc42015-01-18 17:48:18 +0100817 alternative_input(BASE_PREFETCH, "prefetchw %P1",
818 X86_FEATURE_3DNOWPREFETCH,
819 "m" (*(const char *)x));
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100820}
821
Ingo Molnar4d46a892008-02-21 04:24:40 +0100822static inline void spin_lock_prefetch(const void *x)
823{
824 prefetchw(x);
825}
826
Andy Lutomirskid9e05cc2015-03-10 11:05:59 -0700827#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
828 TOP_OF_KERNEL_STACK_PADDING)
829
Andy Lutomirski35001302017-11-02 00:59:11 -0700830#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
831
Andy Lutomirskid375cf12017-11-02 00:59:16 -0700832#define task_pt_regs(task) \
833({ \
834 unsigned long __ptr = (unsigned long)task_stack_page(task); \
835 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
836 ((struct pt_regs *)__ptr) - 1; \
837})
838
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100839#ifdef CONFIG_X86_32
840/*
841 * User space process size: 3GB (default).
842 */
Dmitry Safonov8f3e4742017-03-06 17:17:18 +0300843#define IA32_PAGE_OFFSET PAGE_OFFSET
Ingo Molnar4d46a892008-02-21 04:24:40 +0100844#define TASK_SIZE PAGE_OFFSET
Kirill A. Shutemovb569bab2017-07-17 01:59:52 +0300845#define TASK_SIZE_LOW TASK_SIZE
Ingo Molnard9517342009-02-20 23:32:28 +0100846#define TASK_SIZE_MAX TASK_SIZE
Kirill A. Shutemov44b04912017-07-17 01:59:51 +0300847#define DEFAULT_MAP_WINDOW TASK_SIZE
Ingo Molnar4d46a892008-02-21 04:24:40 +0100848#define STACK_TOP TASK_SIZE
849#define STACK_TOP_MAX STACK_TOP
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100850
Ingo Molnar4d46a892008-02-21 04:24:40 +0100851#define INIT_THREAD { \
Andy Lutomirskid9e05cc2015-03-10 11:05:59 -0700852 .sp0 = TOP_OF_INIT_STACK, \
Ingo Molnar4d46a892008-02-21 04:24:40 +0100853 .sysenter_cs = __KERNEL_CS, \
854 .io_bitmap_ptr = NULL, \
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700855 .addr_limit = KERNEL_DS, \
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100856}
857
Ingo Molnar4d46a892008-02-21 04:24:40 +0100858#define KSTK_ESP(task) (task_pt_regs(task)->sp)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100859
860#else
861/*
Andy Lutomirskif55f0502017-12-12 07:56:45 -0800862 * User space process size. This is the first address outside the user range.
863 * There are a few constraints that determine this:
864 *
865 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
866 * address, then that syscall will enter the kernel with a
867 * non-canonical return address, and SYSRET will explode dangerously.
868 * We avoid this particular problem by preventing anything executable
869 * from being mapped at the maximum canonical address.
870 *
871 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
872 * CPUs malfunction if they execute code from the highest canonical page.
873 * They'll speculate right off the end of the canonical space, and
874 * bad things happen. This is worked around in the same way as the
875 * Intel problem.
876 *
877 * With page table isolation enabled, we map the LDT in ... [stay tuned]
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100878 */
Kirill A. Shutemovee00f4a2017-07-17 01:59:53 +0300879#define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100880
Kirill A. Shutemovee00f4a2017-07-17 01:59:53 +0300881#define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100882
883/* This decides where the kernel will search for a free chunk of vm
884 * space during mmap's.
885 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100886#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
887 0xc0000000 : 0xFFFFe000)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100888
Kirill A. Shutemovb569bab2017-07-17 01:59:52 +0300889#define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
890 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
H. Peter Anvin6bd33002012-02-06 13:03:09 -0800891#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
Ingo Molnard9517342009-02-20 23:32:28 +0100892 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
H. Peter Anvin6bd33002012-02-06 13:03:09 -0800893#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
Ingo Molnard9517342009-02-20 23:32:28 +0100894 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100895
Kirill A. Shutemovb569bab2017-07-17 01:59:52 +0300896#define STACK_TOP TASK_SIZE_LOW
Ingo Molnard9517342009-02-20 23:32:28 +0100897#define STACK_TOP_MAX TASK_SIZE_MAX
David Howells922a70d2008-02-08 04:19:26 -0800898
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700899#define INIT_THREAD { \
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700900 .addr_limit = KERNEL_DS, \
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100901}
902
Stefani Seibold89240ba2009-11-03 10:22:40 +0100903extern unsigned long KSTK_ESP(struct task_struct *task);
H. J. Lud046ff82012-02-14 13:49:48 -0800904
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100905#endif /* CONFIG_X86_64 */
906
Ingo Molnar513ad842008-02-21 05:18:40 +0100907extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
908 unsigned long new_sp);
909
Ingo Molnar4d46a892008-02-21 04:24:40 +0100910/*
911 * This decides where the kernel will search for a free chunk of vm
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100912 * space during mmap's.
913 */
Dmitry Safonov8f3e4742017-03-06 17:17:18 +0300914#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
Kirill A. Shutemovb569bab2017-07-17 01:59:52 +0300915#define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100916
Ingo Molnar4d46a892008-02-21 04:24:40 +0100917#define KSTK_EIP(task) (task_pt_regs(task)->ip)
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100918
Erik Bosman529e25f2008-04-14 00:24:18 +0200919/* Get/set a process' ability to use the timestamp counter instruction */
920#define GET_TSC_CTL(adr) get_tsc_mode((adr))
921#define SET_TSC_CTL(val) set_tsc_mode((val))
922
923extern int get_tsc_mode(unsigned long adr);
924extern int set_tsc_mode(unsigned int val);
925
Kyle Hueye9ea1e72017-03-20 01:16:26 -0700926DECLARE_PER_CPU(u64, msr_misc_features_shadow);
927
Dave Hansenfe3d1972014-11-14 07:18:29 -0800928/* Register/unregister a process' MPX related resource */
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700929#define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
930#define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
Dave Hansenfe3d1972014-11-14 07:18:29 -0800931
932#ifdef CONFIG_X86_INTEL_MPX
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700933extern int mpx_enable_management(void);
934extern int mpx_disable_management(void);
Dave Hansenfe3d1972014-11-14 07:18:29 -0800935#else
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700936static inline int mpx_enable_management(void)
Dave Hansenfe3d1972014-11-14 07:18:29 -0800937{
938 return -EINVAL;
939}
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700940static inline int mpx_disable_management(void)
Dave Hansenfe3d1972014-11-14 07:18:29 -0800941{
942 return -EINVAL;
943}
944#endif /* CONFIG_X86_INTEL_MPX */
945
Borislav Petkovbc8e80d2017-06-13 18:28:30 +0200946#ifdef CONFIG_CPU_SUP_AMD
Daniel J Blueman8b84c8d2012-11-27 14:32:10 +0800947extern u16 amd_get_nb_id(int cpu);
Aravind Gopalakrishnancc2749e2015-06-15 10:28:15 +0200948extern u32 amd_get_nodes_per_socket(void);
Borislav Petkovbc8e80d2017-06-13 18:28:30 +0200949#else
950static inline u16 amd_get_nb_id(int cpu) { return 0; }
951static inline u32 amd_get_nodes_per_socket(void) { return 0; }
952#endif
Andreas Herrmann6a812692009-09-16 11:33:40 +0200953
Jason Wang96e39ac2013-07-25 16:54:32 +0800954static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
955{
956 uint32_t base, eax, signature[3];
957
958 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
959 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
960
961 if (!memcmp(sig, signature, 12) &&
962 (leaves == 0 || ((eax - base) >= leaves)))
963 return base;
964 }
965
966 return 0;
967}
968
David Howellsf05e7982012-03-28 18:11:12 +0100969extern unsigned long arch_align_stack(unsigned long sp);
970extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
Dave Hansen6ea27382018-08-02 15:58:29 -0700971extern void free_kernel_image_pages(void *begin, void *end);
David Howellsf05e7982012-03-28 18:11:12 +0100972
973void default_idle(void);
Len Brown6a377dd2013-02-09 23:08:07 -0500974#ifdef CONFIG_XEN
975bool xen_set_default_idle(void);
976#else
977#define xen_set_default_idle 0
978#endif
David Howellsf05e7982012-03-28 18:11:12 +0100979
980void stop_this_cpu(void *dummy);
Borislav Petkov4d067d82013-05-09 12:02:29 +0200981void df_debug(struct pt_regs *regs, long error_code);
Borislav Petkov1008c522018-02-16 12:26:39 +0100982void microcode_check(void);
Jiri Kosinad90a7a02018-07-13 16:23:25 +0200983
984enum l1tf_mitigations {
985 L1TF_MITIGATION_OFF,
986 L1TF_MITIGATION_FLUSH_NOWARN,
987 L1TF_MITIGATION_FLUSH,
988 L1TF_MITIGATION_FLUSH_NOSMT,
989 L1TF_MITIGATION_FULL,
990 L1TF_MITIGATION_FULL_FORCE
991};
992
993extern enum l1tf_mitigations l1tf_mitigation;
994
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700995#endif /* _ASM_X86_PROCESSOR_H */