Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * pata_optidma.c - Opti DMA PATA for new ATA layer |
| 3 | * (C) 2006 Red Hat Inc |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 4 | * |
| 5 | * The Opti DMA controllers are related to the older PIO PCI controllers |
| 6 | * and indeed the VLB ones. The main differences are that the timing |
| 7 | * numbers are now based off PCI clocks not VLB and differ, and that |
| 8 | * MWDMA is supported. |
| 9 | * |
| 10 | * This driver should support Viper-N+, FireStar, FireStar Plus. |
| 11 | * |
| 12 | * These devices support virtual DMA for read (aka the CS5520). Later |
| 13 | * chips support UDMA33, but only if the rest of the board logic does, |
| 14 | * so you have to get this right. We don't support the virtual DMA |
| 15 | * but we do handle UDMA. |
| 16 | * |
| 17 | * Bits that are worth knowing |
| 18 | * Most control registers are shadowed into I/O registers |
| 19 | * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz |
| 20 | * Virtual DMA registers *move* between rev 0x02 and rev 0x10 |
| 21 | * UDMA requires a 66MHz FSB |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/pci.h> |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/blkdev.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <scsi/scsi_host.h> |
| 32 | #include <linux/libata.h> |
| 33 | |
| 34 | #define DRV_NAME "pata_optidma" |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 35 | #define DRV_VERSION "0.3.2" |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 36 | |
| 37 | enum { |
| 38 | READ_REG = 0, /* index of Read cycle timing register */ |
| 39 | WRITE_REG = 1, /* index of Write cycle timing register */ |
| 40 | CNTRL_REG = 3, /* index of Control register */ |
| 41 | STRAP_REG = 5, /* index of Strap register */ |
| 42 | MISC_REG = 6 /* index of Miscellaneous register */ |
| 43 | }; |
| 44 | |
| 45 | static int pci_clock; /* 0 = 33 1 = 25 */ |
| 46 | |
| 47 | /** |
| 48 | * optidma_pre_reset - probe begin |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 49 | * @link: ATA link |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 50 | * @deadline: deadline jiffies for the operation |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 51 | * |
| 52 | * Set up cable type and use generic probe init |
| 53 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 54 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 55 | static int optidma_pre_reset(struct ata_link *link, unsigned long deadline) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 56 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 57 | struct ata_port *ap = link->ap; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 58 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 59 | static const struct pci_bits optidma_enable_bits = { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 60 | 0x40, 1, 0x08, 0x00 |
| 61 | }; |
| 62 | |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 63 | if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) |
| 64 | return -ENOENT; |
| 65 | |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 66 | return ata_sff_prereset(link, deadline); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 70 | * optidma_unlock - unlock control registers |
| 71 | * @ap: ATA port |
| 72 | * |
| 73 | * Unlock the control register block for this adapter. Registers must not |
| 74 | * be unlocked in a situation where libata might look at them. |
| 75 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 76 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 77 | static void optidma_unlock(struct ata_port *ap) |
| 78 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 79 | void __iomem *regio = ap->ioaddr.cmd_addr; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 80 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 81 | /* These 3 unlock the control register access */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 82 | ioread16(regio + 1); |
| 83 | ioread16(regio + 1); |
| 84 | iowrite8(3, regio + 2); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | /** |
| 88 | * optidma_lock - issue temporary relock |
| 89 | * @ap: ATA port |
| 90 | * |
| 91 | * Re-lock the configuration register settings. |
| 92 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 93 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 94 | static void optidma_lock(struct ata_port *ap) |
| 95 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 96 | void __iomem *regio = ap->ioaddr.cmd_addr; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 97 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 98 | /* Relock */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 99 | iowrite8(0x83, regio + 2); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | /** |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 103 | * optidma_mode_setup - set mode data |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 104 | * @ap: ATA interface |
| 105 | * @adev: ATA device |
| 106 | * @mode: Mode to set |
| 107 | * |
| 108 | * Called to do the DMA or PIO mode setup. Timing numbers are all |
| 109 | * pre computed to keep the code clean. There are two tables depending |
| 110 | * on the hardware clock speed. |
| 111 | * |
| 112 | * WARNING: While we do this the IDE registers vanish. If we take an |
| 113 | * IRQ here we depend on the host set locking to avoid catastrophe. |
| 114 | */ |
| 115 | |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 116 | static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 117 | { |
| 118 | struct ata_device *pair = ata_dev_pair(adev); |
| 119 | int pio = adev->pio_mode - XFER_PIO_0; |
| 120 | int dma = adev->dma_mode - XFER_MW_DMA_0; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 121 | void __iomem *regio = ap->ioaddr.cmd_addr; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 122 | u8 addr; |
| 123 | |
| 124 | /* Address table precomputed with a DCLK of 2 */ |
| 125 | static const u8 addr_timing[2][5] = { |
| 126 | { 0x30, 0x20, 0x20, 0x10, 0x10 }, |
| 127 | { 0x20, 0x20, 0x10, 0x10, 0x10 } |
| 128 | }; |
| 129 | static const u8 data_rec_timing[2][5] = { |
| 130 | { 0x59, 0x46, 0x30, 0x20, 0x20 }, |
| 131 | { 0x46, 0x32, 0x20, 0x20, 0x10 } |
| 132 | }; |
| 133 | static const u8 dma_data_rec_timing[2][3] = { |
| 134 | { 0x76, 0x20, 0x20 }, |
| 135 | { 0x54, 0x20, 0x10 } |
| 136 | }; |
| 137 | |
| 138 | /* Switch from IDE to control mode */ |
| 139 | optidma_unlock(ap); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 140 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 141 | |
| 142 | /* |
| 143 | * As with many controllers the address setup time is shared |
| 144 | * and must suit both devices if present. FIXME: Check if we |
| 145 | * need to look at slowest of PIO/DMA mode of either device |
| 146 | */ |
| 147 | |
| 148 | if (mode >= XFER_MW_DMA_0) |
| 149 | addr = 0; |
| 150 | else |
| 151 | addr = addr_timing[pci_clock][pio]; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 152 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 153 | if (pair) { |
| 154 | u8 pair_addr; |
| 155 | /* Hardware constraint */ |
| 156 | if (pair->dma_mode) |
| 157 | pair_addr = 0; |
| 158 | else |
| 159 | pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0]; |
| 160 | if (pair_addr > addr) |
| 161 | addr = pair_addr; |
| 162 | } |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 163 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 164 | /* Commence primary programming sequence */ |
| 165 | /* First we load the device number into the timing select */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 166 | iowrite8(adev->devno, regio + MISC_REG); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 167 | /* Now we load the data timings into read data/write data */ |
| 168 | if (mode < XFER_MW_DMA_0) { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 169 | iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); |
| 170 | iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 171 | } else if (mode < XFER_UDMA_0) { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 172 | iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); |
| 173 | iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 174 | } |
| 175 | /* Finally we load the address setup into the misc register */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 176 | iowrite8(addr | adev->devno, regio + MISC_REG); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 177 | |
| 178 | /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 179 | iowrite8(0x85, regio + CNTRL_REG); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 180 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 181 | /* Switch back to IDE mode */ |
| 182 | optidma_lock(ap); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 183 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 184 | /* Note: at this point our programming is incomplete. We are |
| 185 | not supposed to program PCI 0x43 "things we hacked onto the chip" |
| 186 | until we've done both sets of PIO/DMA timings */ |
| 187 | } |
| 188 | |
| 189 | /** |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 190 | * optiplus_mode_setup - DMA setup for Firestar Plus |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 191 | * @ap: ATA port |
| 192 | * @adev: device |
| 193 | * @mode: desired mode |
| 194 | * |
| 195 | * The Firestar plus has additional UDMA functionality for UDMA0-2 and |
| 196 | * requires we do some additional work. Because the base work we must do |
| 197 | * is mostly shared we wrap the Firestar setup functionality in this |
| 198 | * one |
| 199 | */ |
| 200 | |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 201 | static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 202 | { |
| 203 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 204 | u8 udcfg; |
| 205 | u8 udslave; |
| 206 | int dev2 = 2 * adev->devno; |
| 207 | int unit = 2 * ap->port_no + adev->devno; |
| 208 | int udma = mode - XFER_UDMA_0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 209 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 210 | pci_read_config_byte(pdev, 0x44, &udcfg); |
| 211 | if (mode <= XFER_UDMA_0) { |
| 212 | udcfg &= ~(1 << unit); |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 213 | optidma_mode_setup(ap, adev, adev->dma_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 214 | } else { |
| 215 | udcfg |= (1 << unit); |
| 216 | if (ap->port_no) { |
| 217 | pci_read_config_byte(pdev, 0x45, &udslave); |
| 218 | udslave &= ~(0x03 << dev2); |
| 219 | udslave |= (udma << dev2); |
| 220 | pci_write_config_byte(pdev, 0x45, udslave); |
| 221 | } else { |
| 222 | udcfg &= ~(0x30 << dev2); |
| 223 | udcfg |= (udma << dev2); |
| 224 | } |
| 225 | } |
| 226 | pci_write_config_byte(pdev, 0x44, udcfg); |
| 227 | } |
| 228 | |
| 229 | /** |
| 230 | * optidma_set_pio_mode - PIO setup callback |
| 231 | * @ap: ATA port |
| 232 | * @adev: Device |
| 233 | * |
| 234 | * The libata core provides separate functions for handling PIO and |
| 235 | * DMA programming. The architecture of the Firestar makes it easier |
| 236 | * for us to have a common function so we provide wrappers |
| 237 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 238 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 239 | static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev) |
| 240 | { |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 241 | optidma_mode_setup(ap, adev, adev->pio_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | /** |
| 245 | * optidma_set_dma_mode - DMA setup callback |
| 246 | * @ap: ATA port |
| 247 | * @adev: Device |
| 248 | * |
| 249 | * The libata core provides separate functions for handling PIO and |
| 250 | * DMA programming. The architecture of the Firestar makes it easier |
| 251 | * for us to have a common function so we provide wrappers |
| 252 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 253 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 254 | static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev) |
| 255 | { |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 256 | optidma_mode_setup(ap, adev, adev->dma_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /** |
| 260 | * optiplus_set_pio_mode - PIO setup callback |
| 261 | * @ap: ATA port |
| 262 | * @adev: Device |
| 263 | * |
| 264 | * The libata core provides separate functions for handling PIO and |
| 265 | * DMA programming. The architecture of the Firestar makes it easier |
| 266 | * for us to have a common function so we provide wrappers |
| 267 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 268 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 269 | static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev) |
| 270 | { |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 271 | optiplus_mode_setup(ap, adev, adev->pio_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | /** |
| 275 | * optiplus_set_dma_mode - DMA setup callback |
| 276 | * @ap: ATA port |
| 277 | * @adev: Device |
| 278 | * |
| 279 | * The libata core provides separate functions for handling PIO and |
| 280 | * DMA programming. The architecture of the Firestar makes it easier |
| 281 | * for us to have a common function so we provide wrappers |
| 282 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 283 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 284 | static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev) |
| 285 | { |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 286 | optiplus_mode_setup(ap, adev, adev->dma_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | /** |
| 290 | * optidma_make_bits - PCI setup helper |
| 291 | * @adev: ATA device |
| 292 | * |
| 293 | * Turn the ATA device setup into PCI configuration bits |
| 294 | * for register 0x43 and return the two bits needed. |
| 295 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 296 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 297 | static u8 optidma_make_bits43(struct ata_device *adev) |
| 298 | { |
| 299 | static const u8 bits43[5] = { |
| 300 | 0, 0, 0, 1, 2 |
| 301 | }; |
| 302 | if (!ata_dev_enabled(adev)) |
| 303 | return 0; |
| 304 | if (adev->dma_mode) |
| 305 | return adev->dma_mode - XFER_MW_DMA_0; |
| 306 | return bits43[adev->pio_mode - XFER_PIO_0]; |
| 307 | } |
| 308 | |
| 309 | /** |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 310 | * optidma_set_mode - mode setup |
Tejun Heo | 0260731 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 311 | * @link: link to set up |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 312 | * |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 313 | * Use the standard setup to tune the chipset and then finalise the |
| 314 | * configuration by writing the nibble of extra bits of data into |
| 315 | * the chip. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 316 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 317 | |
Tejun Heo | 0260731 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 318 | static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 319 | { |
Tejun Heo | 0260731 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 320 | struct ata_port *ap = link->ap; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 321 | u8 r; |
| 322 | int nybble = 4 * ap->port_no; |
| 323 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Tejun Heo | 0260731 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 324 | int rc = ata_do_set_mode(link, r_failed); |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 325 | if (rc == 0) { |
| 326 | pci_read_config_byte(pdev, 0x43, &r); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 327 | |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 328 | r &= (0x0F << nybble); |
Tejun Heo | 0260731 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 329 | r |= (optidma_make_bits43(&link->device[0]) + |
| 330 | (optidma_make_bits43(&link->device[0]) << 2)) << nybble; |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 331 | pci_write_config_byte(pdev, 0x43, r); |
| 332 | } |
| 333 | return rc; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static struct scsi_host_template optidma_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 337 | ATA_BMDMA_SHT(DRV_NAME), |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 338 | }; |
| 339 | |
| 340 | static struct ata_port_operations optidma_port_ops = { |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 341 | .inherits = &ata_bmdma_port_ops, |
| 342 | .cable_detect = ata_cable_40wire, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 343 | .set_piomode = optidma_set_pio_mode, |
| 344 | .set_dmamode = optidma_set_dma_mode, |
Alan Cox | 5c25bf0 | 2007-03-26 21:43:43 -0800 | [diff] [blame] | 345 | .set_mode = optidma_set_mode, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 346 | .prereset = optidma_pre_reset, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 347 | }; |
| 348 | |
| 349 | static struct ata_port_operations optiplus_port_ops = { |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 350 | .inherits = &optidma_port_ops, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 351 | .set_piomode = optiplus_set_pio_mode, |
| 352 | .set_dmamode = optiplus_set_dma_mode, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | /** |
| 356 | * optiplus_with_udma - Look for UDMA capable setup |
| 357 | * @pdev; ATA controller |
| 358 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 359 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 360 | static int optiplus_with_udma(struct pci_dev *pdev) |
| 361 | { |
| 362 | u8 r; |
| 363 | int ret = 0; |
| 364 | int ioport = 0x22; |
| 365 | struct pci_dev *dev1; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 366 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 367 | /* Find function 1 */ |
| 368 | dev1 = pci_get_device(0x1045, 0xC701, NULL); |
Jeff Garzik | b447916 | 2007-10-25 20:47:30 -0400 | [diff] [blame] | 369 | if (dev1 == NULL) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 370 | return 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 371 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 372 | /* Rev must be >= 0x10 */ |
| 373 | pci_read_config_byte(dev1, 0x08, &r); |
| 374 | if (r < 0x10) |
| 375 | goto done_nomsg; |
| 376 | /* Read the chipset system configuration to check our mode */ |
| 377 | pci_read_config_byte(dev1, 0x5F, &r); |
| 378 | ioport |= (r << 8); |
| 379 | outb(0x10, ioport); |
| 380 | /* Must be 66Mhz sync */ |
| 381 | if ((inb(ioport + 2) & 1) == 0) |
| 382 | goto done; |
| 383 | |
| 384 | /* Check the ATA arbitration/timing is suitable */ |
| 385 | pci_read_config_byte(pdev, 0x42, &r); |
| 386 | if ((r & 0x36) != 0x36) |
| 387 | goto done; |
| 388 | pci_read_config_byte(dev1, 0x52, &r); |
| 389 | if (r & 0x80) /* IDEDIR disabled */ |
| 390 | ret = 1; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 391 | done: |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 392 | printk(KERN_WARNING "UDMA not supported in this configuration.\n"); |
| 393 | done_nomsg: /* Wrong chip revision */ |
| 394 | pci_dev_put(dev1); |
| 395 | return ret; |
| 396 | } |
| 397 | |
| 398 | static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 399 | { |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 400 | static const struct ata_port_info info_82c700 = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 401 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 402 | .pio_mask = ATA_PIO4, |
| 403 | .mwdma_mask = ATA_MWDMA2, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 404 | .port_ops = &optidma_port_ops |
| 405 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 406 | static const struct ata_port_info info_82c700_udma = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 407 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 408 | .pio_mask = ATA_PIO4, |
| 409 | .mwdma_mask = ATA_MWDMA2, |
| 410 | .udma_mask = ATA_UDMA2, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 411 | .port_ops = &optiplus_port_ops |
| 412 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 413 | const struct ata_port_info *ppi[] = { &info_82c700, NULL }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 414 | static int printed_version; |
Tejun Heo | f08048e | 2008-03-25 12:22:47 +0900 | [diff] [blame] | 415 | int rc; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 416 | |
| 417 | if (!printed_version++) |
| 418 | dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); |
| 419 | |
Tejun Heo | f08048e | 2008-03-25 12:22:47 +0900 | [diff] [blame] | 420 | rc = pcim_enable_device(dev); |
| 421 | if (rc) |
| 422 | return rc; |
| 423 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 424 | /* Fixed location chipset magic */ |
| 425 | inw(0x1F1); |
| 426 | inw(0x1F1); |
| 427 | pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 428 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 429 | if (optiplus_with_udma(dev)) |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 430 | ppi[0] = &info_82c700_udma; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 431 | |
Tejun Heo | 1c5afdf | 2010-05-19 22:10:22 +0200 | [diff] [blame] | 432 | return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | static const struct pci_device_id optidma[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 436 | { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */ |
| 437 | |
| 438 | { }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 439 | }; |
| 440 | |
| 441 | static struct pci_driver optidma_pci_driver = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 442 | .name = DRV_NAME, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 443 | .id_table = optidma, |
| 444 | .probe = optidma_init_one, |
Alan | 30ced0f | 2006-11-22 16:57:36 +0000 | [diff] [blame] | 445 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 446 | #ifdef CONFIG_PM |
Alan | 30ced0f | 2006-11-22 16:57:36 +0000 | [diff] [blame] | 447 | .suspend = ata_pci_device_suspend, |
| 448 | .resume = ata_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 449 | #endif |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 450 | }; |
| 451 | |
| 452 | static int __init optidma_init(void) |
| 453 | { |
| 454 | return pci_register_driver(&optidma_pci_driver); |
| 455 | } |
| 456 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 457 | static void __exit optidma_exit(void) |
| 458 | { |
| 459 | pci_unregister_driver(&optidma_pci_driver); |
| 460 | } |
| 461 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 462 | MODULE_AUTHOR("Alan Cox"); |
| 463 | MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus"); |
| 464 | MODULE_LICENSE("GPL"); |
| 465 | MODULE_DEVICE_TABLE(pci, optidma); |
| 466 | MODULE_VERSION(DRV_VERSION); |
| 467 | |
| 468 | module_init(optidma_init); |
| 469 | module_exit(optidma_exit); |