blob: 3a0b87e8ec678886166a004c181ace4541012636 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070029#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030
31#include "clock-local.h"
32#include "clock-rpm.h"
33#include "clock-voter.h"
34#include "clock-dss-8960.h"
35#include "devices.h"
Vikram Mulukutla681d8682012-03-09 23:56:20 -080036#include "clock-pll.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070037
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080044#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070045#define CE1_HCLK_CTL_REG REG(0x2720)
46#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou05e01102012-02-08 22:15:49 -080047#define PRNG_CLK_NS_REG REG(0x2E80)
Tianyi Gou41515e22011-09-01 19:37:43 -070048#define CE3_HCLK_CTL_REG REG(0x36C4)
49#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
50#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou6613de52012-01-27 17:57:53 -080052#define CLK_HALT_AFAB_SFAB_STATEA_REG REG(0x2FC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070053#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
55#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
56#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
57#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070058/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
60#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070061#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070062#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070063#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
64#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070065#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
66#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
67#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
68#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
69#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
70#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070072/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#define BB_PLL_ENA_SC0_REG REG(0x34C0)
Tianyi Gou59608a72012-01-31 22:19:30 -080074#define BB_PLL_ENA_RPM_REG REG(0x34A0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070075#define BB_PLL0_STATUS_REG REG(0x30D8)
76#define BB_PLL5_STATUS_REG REG(0x30F8)
77#define BB_PLL6_STATUS_REG REG(0x3118)
78#define BB_PLL7_STATUS_REG REG(0x3138)
79#define BB_PLL8_L_VAL_REG REG(0x3144)
80#define BB_PLL8_M_VAL_REG REG(0x3148)
81#define BB_PLL8_MODE_REG REG(0x3140)
82#define BB_PLL8_N_VAL_REG REG(0x314C)
83#define BB_PLL8_STATUS_REG REG(0x3158)
84#define BB_PLL8_CONFIG_REG REG(0x3154)
85#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070086#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
87#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070088#define BB_PLL14_MODE_REG REG(0x31C0)
89#define BB_PLL14_L_VAL_REG REG(0x31C4)
90#define BB_PLL14_M_VAL_REG REG(0x31C8)
91#define BB_PLL14_N_VAL_REG REG(0x31CC)
92#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
93#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070094#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070095#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
96#define PMEM_ACLK_CTL_REG REG(0x25A0)
97#define RINGOSC_NS_REG REG(0x2DC0)
98#define RINGOSC_STATUS_REG REG(0x2DCC)
99#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -0800100#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700101#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
102#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
103#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
104#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
105#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
106#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
107#define TSIF_HCLK_CTL_REG REG(0x2700)
108#define TSIF_REF_CLK_MD_REG REG(0x270C)
109#define TSIF_REF_CLK_NS_REG REG(0x2710)
110#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700111#define SATA_CLK_SRC_NS_REG REG(0x2C08)
112#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
113#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
114#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
115#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700116#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
117#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
118#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
119#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
120#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
121#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700122#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700123#define USB_HS1_RESET_REG REG(0x2910)
124#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
125#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700126#define USB_HS3_HCLK_CTL_REG REG(0x3700)
127#define USB_HS3_HCLK_FS_REG REG(0x3704)
128#define USB_HS3_RESET_REG REG(0x3710)
129#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
130#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
131#define USB_HS4_HCLK_CTL_REG REG(0x3720)
132#define USB_HS4_HCLK_FS_REG REG(0x3724)
133#define USB_HS4_RESET_REG REG(0x3730)
134#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
135#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700136#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
137#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
138#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
139#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
140#define USB_HSIC_RESET_REG REG(0x2934)
141#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
142#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
143#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700144#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700145#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
Tianyi Gou6613de52012-01-27 17:57:53 -0800146#define PCIE_ACLK_CTL_REG REG(0x22C0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700147#define PCIE_HCLK_CTL_REG REG(0x22CC)
Tianyi Gou6613de52012-01-27 17:57:53 -0800148#define PCIE_PCLK_CTL_REG REG(0x22D0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700149#define GPLL1_MODE_REG REG(0x3160)
150#define GPLL1_L_VAL_REG REG(0x3164)
151#define GPLL1_M_VAL_REG REG(0x3168)
152#define GPLL1_N_VAL_REG REG(0x316C)
153#define GPLL1_CONFIG_REG REG(0x3174)
154#define GPLL1_STATUS_REG REG(0x3178)
155#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700156
157/* Multimedia clock registers. */
158#define AHB_EN_REG REG_MM(0x0008)
159#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700160#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700161#define AHB_NS_REG REG_MM(0x0004)
162#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700163#define CAMCLK0_NS_REG REG_MM(0x0148)
164#define CAMCLK0_CC_REG REG_MM(0x0140)
165#define CAMCLK0_MD_REG REG_MM(0x0144)
166#define CAMCLK1_NS_REG REG_MM(0x015C)
167#define CAMCLK1_CC_REG REG_MM(0x0154)
168#define CAMCLK1_MD_REG REG_MM(0x0158)
169#define CAMCLK2_NS_REG REG_MM(0x0228)
170#define CAMCLK2_CC_REG REG_MM(0x0220)
171#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700172#define CSI0_NS_REG REG_MM(0x0048)
173#define CSI0_CC_REG REG_MM(0x0040)
174#define CSI0_MD_REG REG_MM(0x0044)
175#define CSI1_NS_REG REG_MM(0x0010)
176#define CSI1_CC_REG REG_MM(0x0024)
177#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700178#define CSI2_NS_REG REG_MM(0x0234)
179#define CSI2_CC_REG REG_MM(0x022C)
180#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700181#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
182#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
183#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
184#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
185#define DSI1_BYTE_CC_REG REG_MM(0x0090)
186#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
187#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
188#define DSI1_ESC_NS_REG REG_MM(0x011C)
189#define DSI1_ESC_CC_REG REG_MM(0x00CC)
190#define DSI2_ESC_NS_REG REG_MM(0x0150)
191#define DSI2_ESC_CC_REG REG_MM(0x013C)
192#define DSI_PIXEL_CC_REG REG_MM(0x0130)
193#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
194#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
195#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
196#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
197#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
198#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
199#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
200#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
201#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
202#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700203#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700204#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
205#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
206#define GFX2D0_CC_REG REG_MM(0x0060)
207#define GFX2D0_MD0_REG REG_MM(0x0064)
208#define GFX2D0_MD1_REG REG_MM(0x0068)
209#define GFX2D0_NS_REG REG_MM(0x0070)
210#define GFX2D1_CC_REG REG_MM(0x0074)
211#define GFX2D1_MD0_REG REG_MM(0x0078)
212#define GFX2D1_MD1_REG REG_MM(0x006C)
213#define GFX2D1_NS_REG REG_MM(0x007C)
214#define GFX3D_CC_REG REG_MM(0x0080)
215#define GFX3D_MD0_REG REG_MM(0x0084)
216#define GFX3D_MD1_REG REG_MM(0x0088)
217#define GFX3D_NS_REG REG_MM(0x008C)
218#define IJPEG_CC_REG REG_MM(0x0098)
219#define IJPEG_MD_REG REG_MM(0x009C)
220#define IJPEG_NS_REG REG_MM(0x00A0)
221#define JPEGD_CC_REG REG_MM(0x00A4)
222#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700223#define VCAP_CC_REG REG_MM(0x0178)
224#define VCAP_NS_REG REG_MM(0x021C)
225#define VCAP_MD0_REG REG_MM(0x01EC)
226#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700227#define MAXI_EN_REG REG_MM(0x0018)
228#define MAXI_EN2_REG REG_MM(0x0020)
229#define MAXI_EN3_REG REG_MM(0x002C)
230#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700231#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700232#define MDP_CC_REG REG_MM(0x00C0)
233#define MDP_LUT_CC_REG REG_MM(0x016C)
234#define MDP_MD0_REG REG_MM(0x00C4)
235#define MDP_MD1_REG REG_MM(0x00C8)
236#define MDP_NS_REG REG_MM(0x00D0)
237#define MISC_CC_REG REG_MM(0x0058)
238#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700239#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700240#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700241#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
242#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
243#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
244#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
245#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
246#define MM_PLL1_STATUS_REG REG_MM(0x0334)
247#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700248#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
249#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
250#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
251#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
252#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
253#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700254#define ROT_CC_REG REG_MM(0x00E0)
255#define ROT_NS_REG REG_MM(0x00E8)
256#define SAXI_EN_REG REG_MM(0x0030)
257#define SW_RESET_AHB_REG REG_MM(0x020C)
258#define SW_RESET_AHB2_REG REG_MM(0x0200)
259#define SW_RESET_ALL_REG REG_MM(0x0204)
260#define SW_RESET_AXI_REG REG_MM(0x0208)
261#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700262#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700263#define TV_CC_REG REG_MM(0x00EC)
264#define TV_CC2_REG REG_MM(0x0124)
265#define TV_MD_REG REG_MM(0x00F0)
266#define TV_NS_REG REG_MM(0x00F4)
267#define VCODEC_CC_REG REG_MM(0x00F8)
268#define VCODEC_MD0_REG REG_MM(0x00FC)
269#define VCODEC_MD1_REG REG_MM(0x0128)
270#define VCODEC_NS_REG REG_MM(0x0100)
271#define VFE_CC_REG REG_MM(0x0104)
272#define VFE_MD_REG REG_MM(0x0108)
273#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700274#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700275#define VPE_CC_REG REG_MM(0x0110)
276#define VPE_NS_REG REG_MM(0x0118)
277
278/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700279#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700280#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
281#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
282#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
283#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
284#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
285#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
286#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
287#define LCC_MI2S_MD_REG REG_LPA(0x004C)
288#define LCC_MI2S_NS_REG REG_LPA(0x0048)
289#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
290#define LCC_PCM_MD_REG REG_LPA(0x0058)
291#define LCC_PCM_NS_REG REG_LPA(0x0054)
292#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700293#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
294#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
295#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
296#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
297#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700298#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700299#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
300#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
301#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
302#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
303#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
304#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
305#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
306#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
307#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
308#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700309#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700310
Matt Wagantall8b38f942011-08-02 18:23:18 -0700311#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
312
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700313/* MUX source input identifiers. */
314#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700315#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700316#define pll0_to_bb_mux 2
317#define pll8_to_bb_mux 3
318#define pll6_to_bb_mux 4
319#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700320#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700321#define pxo_to_mm_mux 0
322#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700323#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
324#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700325#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700326#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700327#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700328#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700329#define hdmi_pll_to_mm_mux 3
330#define cxo_to_xo_mux 0
331#define pxo_to_xo_mux 1
332#define gnd_to_xo_mux 3
333#define pxo_to_lpa_mux 0
334#define cxo_to_lpa_mux 1
335#define pll4_to_lpa_mux 2
336#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700337#define pxo_to_pcie_mux 0
338#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700339
340/* Test Vector Macros */
341#define TEST_TYPE_PER_LS 1
342#define TEST_TYPE_PER_HS 2
343#define TEST_TYPE_MM_LS 3
344#define TEST_TYPE_MM_HS 4
345#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700346#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700347#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700348#define TEST_TYPE_SHIFT 24
349#define TEST_CLK_SEL_MASK BM(23, 0)
350#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
351#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
352#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
353#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
354#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
355#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700356#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700357#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700358
359#define MN_MODE_DUAL_EDGE 0x2
360
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700361struct pll_rate {
362 const uint32_t l_val;
363 const uint32_t m_val;
364 const uint32_t n_val;
365 const uint32_t vco;
366 const uint32_t post_div;
367 const uint32_t i_bits;
368};
369#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
370
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700371enum vdd_dig_levels {
372 VDD_DIG_NONE,
373 VDD_DIG_LOW,
374 VDD_DIG_NOMINAL,
375 VDD_DIG_HIGH
376};
377
Saravana Kannan298ec392012-02-08 19:21:47 -0800378static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700379{
380 static const int vdd_uv[] = {
381 [VDD_DIG_NONE] = 0,
382 [VDD_DIG_LOW] = 945000,
383 [VDD_DIG_NOMINAL] = 1050000,
384 [VDD_DIG_HIGH] = 1150000
385 };
Saravana Kannan298ec392012-02-08 19:21:47 -0800386 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700387 vdd_uv[level], 1150000, 1);
388}
389
Saravana Kannan298ec392012-02-08 19:21:47 -0800390static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960);
391
392static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level)
393{
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800394 static const int vdd_corner[] = {
395 [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE,
396 [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW,
397 [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL,
398 [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH,
Saravana Kannan298ec392012-02-08 19:21:47 -0800399 };
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800400 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_VDD_DIG_CORNER,
401 RPM_VREG_VOTER3,
402 vdd_corner[level],
403 RPM_VREG_CORNER_HIGH, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800404}
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700405
406#define VDD_DIG_FMAX_MAP1(l1, f1) \
407 .vdd_class = &vdd_dig, \
408 .fmax[VDD_DIG_##l1] = (f1)
409#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
410 .vdd_class = &vdd_dig, \
411 .fmax[VDD_DIG_##l1] = (f1), \
412 .fmax[VDD_DIG_##l2] = (f2)
413#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
414 .vdd_class = &vdd_dig, \
415 .fmax[VDD_DIG_##l1] = (f1), \
416 .fmax[VDD_DIG_##l2] = (f2), \
417 .fmax[VDD_DIG_##l3] = (f3)
418
Tianyi Goue1faaf22012-01-24 16:07:19 -0800419enum vdd_sr2_pll_levels {
420 VDD_SR2_PLL_OFF,
421 VDD_SR2_PLL_ON
Matt Wagantallc57577d2011-10-06 17:06:53 -0700422};
423
Saravana Kannan298ec392012-02-08 19:21:47 -0800424static int set_vdd_sr2_pll_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantallc57577d2011-10-06 17:06:53 -0700425{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800426 int rc = 0;
Saravana Kannan298ec392012-02-08 19:21:47 -0800427
428 if (level == VDD_SR2_PLL_OFF) {
429 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
430 RPM_VREG_VOTER3, 0, 0, 1);
431 if (rc)
432 return rc;
433 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
434 RPM_VREG_VOTER3, 0, 0, 1);
435 if (rc)
436 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
437 RPM_VREG_VOTER3, 1800000, 1800000, 1);
Tianyi Goue1faaf22012-01-24 16:07:19 -0800438 } else {
Saravana Kannan298ec392012-02-08 19:21:47 -0800439 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
David Collins9a81d6c2012-03-29 15:11:33 -0700440 RPM_VREG_VOTER3, 2050000, 2100000, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800441 if (rc)
442 return rc;
443 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
444 RPM_VREG_VOTER3, 1800000, 1800000, 1);
445 if (rc)
446 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800447 RPM_VREG_VOTER3, 0, 0, 1);
Matt Wagantallc57577d2011-10-06 17:06:53 -0700448 }
449
450 return rc;
451}
452
Saravana Kannan298ec392012-02-08 19:21:47 -0800453static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll_8960);
454
455static int sr2_lreg_uv[] = {
456 [VDD_SR2_PLL_OFF] = 0,
457 [VDD_SR2_PLL_ON] = 1800000,
458};
459
460static int set_vdd_sr2_pll_8064(struct clk_vdd_class *vdd_class, int level)
461{
462 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3,
463 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
464}
465
466static int set_vdd_sr2_pll_8930(struct clk_vdd_class *vdd_class, int level)
467{
468 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3,
469 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
470}
Matt Wagantallc57577d2011-10-06 17:06:53 -0700471
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700472/*
473 * Clock Descriptions
474 */
475
Stephen Boyd72a80352012-01-26 15:57:38 -0800476DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000);
477DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700478
479static struct pll_clk pll2_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700480 .mode_reg = MM_PLL1_MODE_REG,
481 .parent = &pxo_clk.c,
482 .c = {
483 .dbg_name = "pll2_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800484 .rate = 800000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800485 .ops = &clk_ops_local_pll,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700486 CLK_INIT(pll2_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800487 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700488 },
489};
490
Stephen Boyd94625ef2011-07-12 17:06:01 -0700491static struct pll_clk pll3_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700492 .mode_reg = BB_MMCC_PLL2_MODE_REG,
493 .parent = &pxo_clk.c,
494 .c = {
495 .dbg_name = "pll3_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800496 .rate = 1200000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800497 .ops = &clk_ops_local_pll,
Tianyi Goue1faaf22012-01-24 16:07:19 -0800498 .vdd_class = &vdd_sr2_pll,
499 .fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700500 CLK_INIT(pll3_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800501 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700502 },
503};
504
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700505static struct pll_vote_clk pll4_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700506 .en_reg = BB_PLL_ENA_SC0_REG,
507 .en_mask = BIT(4),
508 .status_reg = LCC_PLL0_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800509 .status_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700510 .parent = &pxo_clk.c,
511 .c = {
512 .dbg_name = "pll4_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800513 .rate = 393216000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700514 .ops = &clk_ops_pll_vote,
515 CLK_INIT(pll4_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800516 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700517 },
518};
519
520static struct pll_vote_clk pll8_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700521 .en_reg = BB_PLL_ENA_SC0_REG,
522 .en_mask = BIT(8),
523 .status_reg = BB_PLL8_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800524 .status_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700525 .parent = &pxo_clk.c,
526 .c = {
527 .dbg_name = "pll8_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800528 .rate = 384000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700529 .ops = &clk_ops_pll_vote,
530 CLK_INIT(pll8_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800531 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700532 },
533};
534
Stephen Boyd94625ef2011-07-12 17:06:01 -0700535static struct pll_vote_clk pll14_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700536 .en_reg = BB_PLL_ENA_SC0_REG,
537 .en_mask = BIT(14),
538 .status_reg = BB_PLL14_STATUS_REG,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800539 .status_mask = BIT(16),
Stephen Boyd94625ef2011-07-12 17:06:01 -0700540 .parent = &pxo_clk.c,
541 .c = {
542 .dbg_name = "pll14_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800543 .rate = 480000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700544 .ops = &clk_ops_pll_vote,
545 CLK_INIT(pll14_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800546 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700547 },
548};
549
Tianyi Gou41515e22011-09-01 19:37:43 -0700550static struct pll_clk pll15_clk = {
Tianyi Gou41515e22011-09-01 19:37:43 -0700551 .mode_reg = MM_PLL3_MODE_REG,
552 .parent = &pxo_clk.c,
553 .c = {
554 .dbg_name = "pll15_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800555 .rate = 975000000,
Vikram Mulukutla681d8682012-03-09 23:56:20 -0800556 .ops = &clk_ops_local_pll,
Tianyi Gou41515e22011-09-01 19:37:43 -0700557 CLK_INIT(pll15_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800558 .warned = true,
Tianyi Gou41515e22011-09-01 19:37:43 -0700559 },
560};
561
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700562/* AXI Interfaces */
563static struct branch_clk gmem_axi_clk = {
564 .b = {
565 .ctl_reg = MAXI_EN_REG,
566 .en_mask = BIT(24),
567 .halt_reg = DBG_BUS_VEC_E_REG,
568 .halt_bit = 6,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800569 .retain_reg = MAXI_EN2_REG,
570 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700571 },
572 .c = {
573 .dbg_name = "gmem_axi_clk",
574 .ops = &clk_ops_branch,
575 CLK_INIT(gmem_axi_clk.c),
576 },
577};
578
579static struct branch_clk ijpeg_axi_clk = {
580 .b = {
581 .ctl_reg = MAXI_EN_REG,
582 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800583 .hwcg_reg = MAXI_EN_REG,
584 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700585 .reset_reg = SW_RESET_AXI_REG,
586 .reset_mask = BIT(14),
587 .halt_reg = DBG_BUS_VEC_E_REG,
588 .halt_bit = 4,
589 },
590 .c = {
591 .dbg_name = "ijpeg_axi_clk",
592 .ops = &clk_ops_branch,
593 CLK_INIT(ijpeg_axi_clk.c),
594 },
595};
596
597static struct branch_clk imem_axi_clk = {
598 .b = {
599 .ctl_reg = MAXI_EN_REG,
600 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800601 .hwcg_reg = MAXI_EN_REG,
602 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700603 .reset_reg = SW_RESET_CORE_REG,
604 .reset_mask = BIT(10),
605 .halt_reg = DBG_BUS_VEC_E_REG,
606 .halt_bit = 7,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800607 .retain_reg = MAXI_EN2_REG,
608 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700609 },
610 .c = {
611 .dbg_name = "imem_axi_clk",
612 .ops = &clk_ops_branch,
613 CLK_INIT(imem_axi_clk.c),
614 },
615};
616
617static struct branch_clk jpegd_axi_clk = {
618 .b = {
619 .ctl_reg = MAXI_EN_REG,
620 .en_mask = BIT(25),
621 .halt_reg = DBG_BUS_VEC_E_REG,
622 .halt_bit = 5,
623 },
624 .c = {
625 .dbg_name = "jpegd_axi_clk",
626 .ops = &clk_ops_branch,
627 CLK_INIT(jpegd_axi_clk.c),
628 },
629};
630
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700631static struct branch_clk vcodec_axi_b_clk = {
632 .b = {
633 .ctl_reg = MAXI_EN4_REG,
634 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800635 .hwcg_reg = MAXI_EN4_REG,
636 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700637 .halt_reg = DBG_BUS_VEC_I_REG,
638 .halt_bit = 25,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800639 .retain_reg = MAXI_EN4_REG,
640 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700641 },
642 .c = {
643 .dbg_name = "vcodec_axi_b_clk",
644 .ops = &clk_ops_branch,
645 CLK_INIT(vcodec_axi_b_clk.c),
646 },
647};
648
Matt Wagantall91f42702011-07-14 12:01:15 -0700649static struct branch_clk vcodec_axi_a_clk = {
650 .b = {
651 .ctl_reg = MAXI_EN4_REG,
652 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800653 .hwcg_reg = MAXI_EN4_REG,
654 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700655 .halt_reg = DBG_BUS_VEC_I_REG,
656 .halt_bit = 26,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800657 .retain_reg = MAXI_EN4_REG,
658 .retain_mask = BIT(10),
Matt Wagantall91f42702011-07-14 12:01:15 -0700659 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700660 .c = {
661 .dbg_name = "vcodec_axi_a_clk",
662 .ops = &clk_ops_branch,
663 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700664 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700665 },
666};
667
668static struct branch_clk vcodec_axi_clk = {
669 .b = {
670 .ctl_reg = MAXI_EN_REG,
671 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800672 .hwcg_reg = MAXI_EN_REG,
673 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700674 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800675 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700676 .halt_reg = DBG_BUS_VEC_E_REG,
677 .halt_bit = 3,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800678 .retain_reg = MAXI_EN2_REG,
679 .retain_mask = BIT(28),
Matt Wagantall91f42702011-07-14 12:01:15 -0700680 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700681 .c = {
682 .dbg_name = "vcodec_axi_clk",
683 .ops = &clk_ops_branch,
684 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700685 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700686 },
687};
688
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700689static struct branch_clk vfe_axi_clk = {
690 .b = {
691 .ctl_reg = MAXI_EN_REG,
692 .en_mask = BIT(18),
693 .reset_reg = SW_RESET_AXI_REG,
694 .reset_mask = BIT(9),
695 .halt_reg = DBG_BUS_VEC_E_REG,
696 .halt_bit = 0,
697 },
698 .c = {
699 .dbg_name = "vfe_axi_clk",
700 .ops = &clk_ops_branch,
701 CLK_INIT(vfe_axi_clk.c),
702 },
703};
704
705static struct branch_clk mdp_axi_clk = {
706 .b = {
707 .ctl_reg = MAXI_EN_REG,
708 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800709 .hwcg_reg = MAXI_EN_REG,
710 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700711 .reset_reg = SW_RESET_AXI_REG,
712 .reset_mask = BIT(13),
713 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700714 .halt_bit = 8,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800715 .retain_reg = MAXI_EN_REG,
716 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700717 },
718 .c = {
719 .dbg_name = "mdp_axi_clk",
720 .ops = &clk_ops_branch,
721 CLK_INIT(mdp_axi_clk.c),
722 },
723};
724
725static struct branch_clk rot_axi_clk = {
726 .b = {
727 .ctl_reg = MAXI_EN2_REG,
728 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800729 .hwcg_reg = MAXI_EN2_REG,
730 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700731 .reset_reg = SW_RESET_AXI_REG,
732 .reset_mask = BIT(6),
733 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700734 .halt_bit = 2,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800735 .retain_reg = MAXI_EN3_REG,
736 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700737 },
738 .c = {
739 .dbg_name = "rot_axi_clk",
740 .ops = &clk_ops_branch,
741 CLK_INIT(rot_axi_clk.c),
742 },
743};
744
745static struct branch_clk vpe_axi_clk = {
746 .b = {
747 .ctl_reg = MAXI_EN2_REG,
748 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800749 .hwcg_reg = MAXI_EN2_REG,
750 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700751 .reset_reg = SW_RESET_AXI_REG,
752 .reset_mask = BIT(15),
753 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700754 .halt_bit = 1,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800755 .retain_reg = MAXI_EN3_REG,
756 .retain_mask = BIT(21),
757
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700758 },
759 .c = {
760 .dbg_name = "vpe_axi_clk",
761 .ops = &clk_ops_branch,
762 CLK_INIT(vpe_axi_clk.c),
763 },
764};
765
Tianyi Gou41515e22011-09-01 19:37:43 -0700766static struct branch_clk vcap_axi_clk = {
767 .b = {
768 .ctl_reg = MAXI_EN5_REG,
769 .en_mask = BIT(12),
770 .reset_reg = SW_RESET_AXI_REG,
771 .reset_mask = BIT(16),
772 .halt_reg = DBG_BUS_VEC_J_REG,
773 .halt_bit = 20,
774 },
775 .c = {
776 .dbg_name = "vcap_axi_clk",
777 .ops = &clk_ops_branch,
778 CLK_INIT(vcap_axi_clk.c),
779 },
780};
781
Tianyi Goue3d4f542012-03-15 17:06:45 -0700782/* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
783static struct branch_clk gfx3d_axi_clk_8064 = {
Tianyi Gou621f8742011-09-01 21:45:01 -0700784 .b = {
785 .ctl_reg = MAXI_EN5_REG,
786 .en_mask = BIT(25),
787 .reset_reg = SW_RESET_AXI_REG,
788 .reset_mask = BIT(17),
789 .halt_reg = DBG_BUS_VEC_J_REG,
790 .halt_bit = 30,
791 },
792 .c = {
793 .dbg_name = "gfx3d_axi_clk",
794 .ops = &clk_ops_branch,
Tianyi Goue3d4f542012-03-15 17:06:45 -0700795 CLK_INIT(gfx3d_axi_clk_8064.c),
796 },
797};
798
799static struct branch_clk gfx3d_axi_clk_8930 = {
800 .b = {
801 .ctl_reg = MAXI_EN5_REG,
802 .en_mask = BIT(12),
803 .reset_reg = SW_RESET_AXI_REG,
804 .reset_mask = BIT(16),
805 .halt_reg = DBG_BUS_VEC_J_REG,
806 .halt_bit = 12,
807 },
808 .c = {
809 .dbg_name = "gfx3d_axi_clk",
810 .ops = &clk_ops_branch,
811 CLK_INIT(gfx3d_axi_clk_8930.c),
Tianyi Gou621f8742011-09-01 21:45:01 -0700812 },
813};
814
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700815/* AHB Interfaces */
816static struct branch_clk amp_p_clk = {
817 .b = {
818 .ctl_reg = AHB_EN_REG,
819 .en_mask = BIT(24),
Matt Wagantalld40857a2012-04-10 19:15:43 -0700820 .reset_reg = SW_RESET_CORE_REG,
821 .reset_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822 .halt_reg = DBG_BUS_VEC_F_REG,
823 .halt_bit = 18,
824 },
825 .c = {
826 .dbg_name = "amp_p_clk",
827 .ops = &clk_ops_branch,
828 CLK_INIT(amp_p_clk.c),
829 },
830};
831
Matt Wagantallc23eee92011-08-16 23:06:52 -0700832static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700833 .b = {
834 .ctl_reg = AHB_EN_REG,
835 .en_mask = BIT(7),
836 .reset_reg = SW_RESET_AHB_REG,
837 .reset_mask = BIT(17),
838 .halt_reg = DBG_BUS_VEC_F_REG,
839 .halt_bit = 16,
840 },
841 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700842 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700843 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700844 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700845 },
846};
847
848static struct branch_clk dsi1_m_p_clk = {
849 .b = {
850 .ctl_reg = AHB_EN_REG,
851 .en_mask = BIT(9),
852 .reset_reg = SW_RESET_AHB_REG,
853 .reset_mask = BIT(6),
854 .halt_reg = DBG_BUS_VEC_F_REG,
855 .halt_bit = 19,
856 },
857 .c = {
858 .dbg_name = "dsi1_m_p_clk",
859 .ops = &clk_ops_branch,
860 CLK_INIT(dsi1_m_p_clk.c),
861 },
862};
863
864static struct branch_clk dsi1_s_p_clk = {
865 .b = {
866 .ctl_reg = AHB_EN_REG,
867 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800868 .hwcg_reg = AHB_EN2_REG,
869 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700870 .reset_reg = SW_RESET_AHB_REG,
871 .reset_mask = BIT(5),
872 .halt_reg = DBG_BUS_VEC_F_REG,
873 .halt_bit = 21,
874 },
875 .c = {
876 .dbg_name = "dsi1_s_p_clk",
877 .ops = &clk_ops_branch,
878 CLK_INIT(dsi1_s_p_clk.c),
879 },
880};
881
882static struct branch_clk dsi2_m_p_clk = {
883 .b = {
884 .ctl_reg = AHB_EN_REG,
885 .en_mask = BIT(17),
886 .reset_reg = SW_RESET_AHB2_REG,
887 .reset_mask = BIT(1),
888 .halt_reg = DBG_BUS_VEC_E_REG,
889 .halt_bit = 18,
890 },
891 .c = {
892 .dbg_name = "dsi2_m_p_clk",
893 .ops = &clk_ops_branch,
894 CLK_INIT(dsi2_m_p_clk.c),
895 },
896};
897
898static struct branch_clk dsi2_s_p_clk = {
899 .b = {
900 .ctl_reg = AHB_EN_REG,
901 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800902 .hwcg_reg = AHB_EN2_REG,
903 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700904 .reset_reg = SW_RESET_AHB2_REG,
905 .reset_mask = BIT(0),
906 .halt_reg = DBG_BUS_VEC_F_REG,
907 .halt_bit = 20,
908 },
909 .c = {
910 .dbg_name = "dsi2_s_p_clk",
911 .ops = &clk_ops_branch,
912 CLK_INIT(dsi2_s_p_clk.c),
913 },
914};
915
916static struct branch_clk gfx2d0_p_clk = {
917 .b = {
918 .ctl_reg = AHB_EN_REG,
919 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800920 .hwcg_reg = AHB_EN2_REG,
921 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700922 .reset_reg = SW_RESET_AHB_REG,
923 .reset_mask = BIT(12),
924 .halt_reg = DBG_BUS_VEC_F_REG,
925 .halt_bit = 2,
926 },
927 .c = {
928 .dbg_name = "gfx2d0_p_clk",
929 .ops = &clk_ops_branch,
930 CLK_INIT(gfx2d0_p_clk.c),
931 },
932};
933
934static struct branch_clk gfx2d1_p_clk = {
935 .b = {
936 .ctl_reg = AHB_EN_REG,
937 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800938 .hwcg_reg = AHB_EN2_REG,
939 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700940 .reset_reg = SW_RESET_AHB_REG,
941 .reset_mask = BIT(11),
942 .halt_reg = DBG_BUS_VEC_F_REG,
943 .halt_bit = 3,
944 },
945 .c = {
946 .dbg_name = "gfx2d1_p_clk",
947 .ops = &clk_ops_branch,
948 CLK_INIT(gfx2d1_p_clk.c),
949 },
950};
951
952static struct branch_clk gfx3d_p_clk = {
953 .b = {
954 .ctl_reg = AHB_EN_REG,
955 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800956 .hwcg_reg = AHB_EN2_REG,
957 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700958 .reset_reg = SW_RESET_AHB_REG,
959 .reset_mask = BIT(10),
960 .halt_reg = DBG_BUS_VEC_F_REG,
961 .halt_bit = 4,
962 },
963 .c = {
964 .dbg_name = "gfx3d_p_clk",
965 .ops = &clk_ops_branch,
966 CLK_INIT(gfx3d_p_clk.c),
967 },
968};
969
970static struct branch_clk hdmi_m_p_clk = {
971 .b = {
972 .ctl_reg = AHB_EN_REG,
973 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800974 .hwcg_reg = AHB_EN2_REG,
975 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700976 .reset_reg = SW_RESET_AHB_REG,
977 .reset_mask = BIT(9),
978 .halt_reg = DBG_BUS_VEC_F_REG,
979 .halt_bit = 5,
980 },
981 .c = {
982 .dbg_name = "hdmi_m_p_clk",
983 .ops = &clk_ops_branch,
984 CLK_INIT(hdmi_m_p_clk.c),
985 },
986};
987
988static struct branch_clk hdmi_s_p_clk = {
989 .b = {
990 .ctl_reg = AHB_EN_REG,
991 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800992 .hwcg_reg = AHB_EN2_REG,
993 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700994 .reset_reg = SW_RESET_AHB_REG,
995 .reset_mask = BIT(9),
996 .halt_reg = DBG_BUS_VEC_F_REG,
997 .halt_bit = 6,
998 },
999 .c = {
1000 .dbg_name = "hdmi_s_p_clk",
1001 .ops = &clk_ops_branch,
1002 CLK_INIT(hdmi_s_p_clk.c),
1003 },
1004};
1005
1006static struct branch_clk ijpeg_p_clk = {
1007 .b = {
1008 .ctl_reg = AHB_EN_REG,
1009 .en_mask = BIT(5),
1010 .reset_reg = SW_RESET_AHB_REG,
1011 .reset_mask = BIT(7),
1012 .halt_reg = DBG_BUS_VEC_F_REG,
1013 .halt_bit = 9,
1014 },
1015 .c = {
1016 .dbg_name = "ijpeg_p_clk",
1017 .ops = &clk_ops_branch,
1018 CLK_INIT(ijpeg_p_clk.c),
1019 },
1020};
1021
1022static struct branch_clk imem_p_clk = {
1023 .b = {
1024 .ctl_reg = AHB_EN_REG,
1025 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001026 .hwcg_reg = AHB_EN2_REG,
1027 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001028 .reset_reg = SW_RESET_AHB_REG,
1029 .reset_mask = BIT(8),
1030 .halt_reg = DBG_BUS_VEC_F_REG,
1031 .halt_bit = 10,
1032 },
1033 .c = {
1034 .dbg_name = "imem_p_clk",
1035 .ops = &clk_ops_branch,
1036 CLK_INIT(imem_p_clk.c),
1037 },
1038};
1039
1040static struct branch_clk jpegd_p_clk = {
1041 .b = {
1042 .ctl_reg = AHB_EN_REG,
1043 .en_mask = BIT(21),
1044 .reset_reg = SW_RESET_AHB_REG,
1045 .reset_mask = BIT(4),
1046 .halt_reg = DBG_BUS_VEC_F_REG,
1047 .halt_bit = 7,
1048 },
1049 .c = {
1050 .dbg_name = "jpegd_p_clk",
1051 .ops = &clk_ops_branch,
1052 CLK_INIT(jpegd_p_clk.c),
1053 },
1054};
1055
1056static struct branch_clk mdp_p_clk = {
1057 .b = {
1058 .ctl_reg = AHB_EN_REG,
1059 .en_mask = BIT(10),
1060 .reset_reg = SW_RESET_AHB_REG,
1061 .reset_mask = BIT(3),
1062 .halt_reg = DBG_BUS_VEC_F_REG,
1063 .halt_bit = 11,
1064 },
1065 .c = {
1066 .dbg_name = "mdp_p_clk",
1067 .ops = &clk_ops_branch,
1068 CLK_INIT(mdp_p_clk.c),
1069 },
1070};
1071
1072static struct branch_clk rot_p_clk = {
1073 .b = {
1074 .ctl_reg = AHB_EN_REG,
1075 .en_mask = BIT(12),
1076 .reset_reg = SW_RESET_AHB_REG,
1077 .reset_mask = BIT(2),
1078 .halt_reg = DBG_BUS_VEC_F_REG,
1079 .halt_bit = 13,
1080 },
1081 .c = {
1082 .dbg_name = "rot_p_clk",
1083 .ops = &clk_ops_branch,
1084 CLK_INIT(rot_p_clk.c),
1085 },
1086};
1087
1088static struct branch_clk smmu_p_clk = {
1089 .b = {
1090 .ctl_reg = AHB_EN_REG,
1091 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001092 .hwcg_reg = AHB_EN_REG,
1093 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001094 .halt_reg = DBG_BUS_VEC_F_REG,
1095 .halt_bit = 22,
1096 },
1097 .c = {
1098 .dbg_name = "smmu_p_clk",
1099 .ops = &clk_ops_branch,
1100 CLK_INIT(smmu_p_clk.c),
1101 },
1102};
1103
1104static struct branch_clk tv_enc_p_clk = {
1105 .b = {
1106 .ctl_reg = AHB_EN_REG,
1107 .en_mask = BIT(25),
1108 .reset_reg = SW_RESET_AHB_REG,
1109 .reset_mask = BIT(15),
1110 .halt_reg = DBG_BUS_VEC_F_REG,
1111 .halt_bit = 23,
1112 },
1113 .c = {
1114 .dbg_name = "tv_enc_p_clk",
1115 .ops = &clk_ops_branch,
1116 CLK_INIT(tv_enc_p_clk.c),
1117 },
1118};
1119
1120static struct branch_clk vcodec_p_clk = {
1121 .b = {
1122 .ctl_reg = AHB_EN_REG,
1123 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001124 .hwcg_reg = AHB_EN2_REG,
1125 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001126 .reset_reg = SW_RESET_AHB_REG,
1127 .reset_mask = BIT(1),
1128 .halt_reg = DBG_BUS_VEC_F_REG,
1129 .halt_bit = 12,
1130 },
1131 .c = {
1132 .dbg_name = "vcodec_p_clk",
1133 .ops = &clk_ops_branch,
1134 CLK_INIT(vcodec_p_clk.c),
1135 },
1136};
1137
1138static struct branch_clk vfe_p_clk = {
1139 .b = {
1140 .ctl_reg = AHB_EN_REG,
1141 .en_mask = BIT(13),
1142 .reset_reg = SW_RESET_AHB_REG,
1143 .reset_mask = BIT(0),
1144 .halt_reg = DBG_BUS_VEC_F_REG,
1145 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08001146 .retain_reg = AHB_EN2_REG,
1147 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001148 },
1149 .c = {
1150 .dbg_name = "vfe_p_clk",
1151 .ops = &clk_ops_branch,
1152 CLK_INIT(vfe_p_clk.c),
1153 },
1154};
1155
1156static struct branch_clk vpe_p_clk = {
1157 .b = {
1158 .ctl_reg = AHB_EN_REG,
1159 .en_mask = BIT(16),
1160 .reset_reg = SW_RESET_AHB_REG,
1161 .reset_mask = BIT(14),
1162 .halt_reg = DBG_BUS_VEC_F_REG,
1163 .halt_bit = 15,
1164 },
1165 .c = {
1166 .dbg_name = "vpe_p_clk",
1167 .ops = &clk_ops_branch,
1168 CLK_INIT(vpe_p_clk.c),
1169 },
1170};
1171
Tianyi Gou41515e22011-09-01 19:37:43 -07001172static struct branch_clk vcap_p_clk = {
1173 .b = {
1174 .ctl_reg = AHB_EN3_REG,
1175 .en_mask = BIT(1),
1176 .reset_reg = SW_RESET_AHB2_REG,
1177 .reset_mask = BIT(2),
1178 .halt_reg = DBG_BUS_VEC_J_REG,
1179 .halt_bit = 23,
1180 },
1181 .c = {
1182 .dbg_name = "vcap_p_clk",
1183 .ops = &clk_ops_branch,
1184 CLK_INIT(vcap_p_clk.c),
1185 },
1186};
1187
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001188/*
1189 * Peripheral Clocks
1190 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001191#define CLK_GP(i, n, h_r, h_b) \
1192 struct rcg_clk i##_clk = { \
1193 .b = { \
1194 .ctl_reg = GPn_NS_REG(n), \
1195 .en_mask = BIT(9), \
1196 .halt_reg = h_r, \
1197 .halt_bit = h_b, \
1198 }, \
1199 .ns_reg = GPn_NS_REG(n), \
1200 .md_reg = GPn_MD_REG(n), \
1201 .root_en_mask = BIT(11), \
1202 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001203 .mnd_en_mask = BIT(8), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001204 .set_rate = set_rate_mnd, \
1205 .freq_tbl = clk_tbl_gp, \
1206 .current_freq = &rcg_dummy_freq, \
1207 .c = { \
1208 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001209 .ops = &clk_ops_rcg, \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001210 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1211 CLK_INIT(i##_clk.c), \
1212 }, \
1213 }
1214#define F_GP(f, s, d, m, n) \
1215 { \
1216 .freq_hz = f, \
1217 .src_clk = &s##_clk.c, \
1218 .md_val = MD8(16, m, 0, n), \
1219 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001220 }
1221static struct clk_freq_tbl clk_tbl_gp[] = {
1222 F_GP( 0, gnd, 1, 0, 0),
1223 F_GP( 9600000, cxo, 2, 0, 0),
1224 F_GP( 13500000, pxo, 2, 0, 0),
1225 F_GP( 19200000, cxo, 1, 0, 0),
1226 F_GP( 27000000, pxo, 1, 0, 0),
1227 F_GP( 64000000, pll8, 2, 1, 3),
1228 F_GP( 76800000, pll8, 1, 1, 5),
1229 F_GP( 96000000, pll8, 4, 0, 0),
1230 F_GP(128000000, pll8, 3, 0, 0),
1231 F_GP(192000000, pll8, 2, 0, 0),
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001232 F_END
1233};
1234
1235static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1236static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1237static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1238
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001239#define CLK_GSBI_UART(i, n, h_r, h_b) \
1240 struct rcg_clk i##_clk = { \
1241 .b = { \
1242 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1243 .en_mask = BIT(9), \
1244 .reset_reg = GSBIn_RESET_REG(n), \
1245 .reset_mask = BIT(0), \
1246 .halt_reg = h_r, \
1247 .halt_bit = h_b, \
1248 }, \
1249 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1250 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1251 .root_en_mask = BIT(11), \
1252 .ns_mask = (BM(31, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001253 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001254 .set_rate = set_rate_mnd, \
1255 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001256 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001257 .c = { \
1258 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001259 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001260 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001261 CLK_INIT(i##_clk.c), \
1262 }, \
1263 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001264#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001265 { \
1266 .freq_hz = f, \
1267 .src_clk = &s##_clk.c, \
1268 .md_val = MD16(m, n), \
1269 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001270 }
1271static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001272 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001273 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1274 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1275 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1276 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001277 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1278 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1279 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1280 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1281 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1282 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1283 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1284 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1285 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1286 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001287 F_END
1288};
1289
1290static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1291static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1292static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1293static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1294static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1295static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1296static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1297static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1298static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1299static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1300static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1301static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1302
1303#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1304 struct rcg_clk i##_clk = { \
1305 .b = { \
1306 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1307 .en_mask = BIT(9), \
1308 .reset_reg = GSBIn_RESET_REG(n), \
1309 .reset_mask = BIT(0), \
1310 .halt_reg = h_r, \
1311 .halt_bit = h_b, \
1312 }, \
1313 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1314 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1315 .root_en_mask = BIT(11), \
1316 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001317 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001318 .set_rate = set_rate_mnd, \
1319 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001320 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001321 .c = { \
1322 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001323 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001324 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001325 CLK_INIT(i##_clk.c), \
1326 }, \
1327 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001328#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001329 { \
1330 .freq_hz = f, \
1331 .src_clk = &s##_clk.c, \
1332 .md_val = MD8(16, m, 0, n), \
1333 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001334 }
1335static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001336 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1337 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1338 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1339 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1340 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1341 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1342 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1343 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1344 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1345 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001346 F_END
1347};
1348
1349static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1350static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1351static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1352static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1353static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1354static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1355static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1356static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1357static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1358static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1359static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1360static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1361
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001362#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001363 { \
1364 .freq_hz = f, \
1365 .src_clk = &s##_clk.c, \
1366 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001367 }
1368static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001369 F_PDM( 0, gnd, 1),
1370 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001371 F_END
1372};
1373
1374static struct rcg_clk pdm_clk = {
1375 .b = {
1376 .ctl_reg = PDM_CLK_NS_REG,
1377 .en_mask = BIT(9),
1378 .reset_reg = PDM_CLK_NS_REG,
1379 .reset_mask = BIT(12),
1380 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1381 .halt_bit = 3,
1382 },
1383 .ns_reg = PDM_CLK_NS_REG,
1384 .root_en_mask = BIT(11),
1385 .ns_mask = BM(1, 0),
1386 .set_rate = set_rate_nop,
1387 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001388 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001389 .c = {
1390 .dbg_name = "pdm_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001391 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001392 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001393 CLK_INIT(pdm_clk.c),
1394 },
1395};
1396
1397static struct branch_clk pmem_clk = {
1398 .b = {
1399 .ctl_reg = PMEM_ACLK_CTL_REG,
1400 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001401 .hwcg_reg = PMEM_ACLK_CTL_REG,
1402 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001403 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1404 .halt_bit = 20,
1405 },
1406 .c = {
1407 .dbg_name = "pmem_clk",
1408 .ops = &clk_ops_branch,
1409 CLK_INIT(pmem_clk.c),
1410 },
1411};
1412
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001413#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001414 { \
1415 .freq_hz = f, \
1416 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001417 }
Stephen Boyd842a1f62012-04-26 19:07:38 -07001418static struct clk_freq_tbl clk_tbl_prng_32[] = {
1419 F_PRNG(32000000, pll8),
1420 F_END
1421};
1422
1423static struct clk_freq_tbl clk_tbl_prng_64[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001424 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001425 F_END
1426};
1427
1428static struct rcg_clk prng_clk = {
1429 .b = {
1430 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1431 .en_mask = BIT(10),
1432 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1433 .halt_check = HALT_VOTED,
1434 .halt_bit = 10,
1435 },
1436 .set_rate = set_rate_nop,
Stephen Boyd842a1f62012-04-26 19:07:38 -07001437 .freq_tbl = clk_tbl_prng_32,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001438 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001439 .c = {
1440 .dbg_name = "prng_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001441 .ops = &clk_ops_rcg,
Stephen Boyd842a1f62012-04-26 19:07:38 -07001442 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001443 CLK_INIT(prng_clk.c),
1444 },
1445};
1446
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001447#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001448 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001449 .b = { \
1450 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1451 .en_mask = BIT(9), \
1452 .reset_reg = SDCn_RESET_REG(n), \
1453 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001454 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001455 .halt_bit = h_b, \
1456 }, \
1457 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1458 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1459 .root_en_mask = BIT(11), \
1460 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001461 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001462 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001463 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001464 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001465 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001466 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001467 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001468 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001469 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001470 }, \
1471 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001472#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001473 { \
1474 .freq_hz = f, \
1475 .src_clk = &s##_clk.c, \
1476 .md_val = MD8(16, m, 0, n), \
1477 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001478 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001479static struct clk_freq_tbl clk_tbl_sdc[] = {
1480 F_SDC( 0, gnd, 1, 0, 0),
1481 F_SDC( 144000, pxo, 3, 2, 125),
1482 F_SDC( 400000, pll8, 4, 1, 240),
1483 F_SDC( 16000000, pll8, 4, 1, 6),
1484 F_SDC( 17070000, pll8, 1, 2, 45),
1485 F_SDC( 20210000, pll8, 1, 1, 19),
1486 F_SDC( 24000000, pll8, 4, 1, 4),
1487 F_SDC( 48000000, pll8, 4, 1, 2),
1488 F_SDC( 64000000, pll8, 3, 1, 2),
1489 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301490 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001491 F_END
1492};
1493
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001494static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1495static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1496static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1497static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1498static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001499
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001500#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001501 { \
1502 .freq_hz = f, \
1503 .src_clk = &s##_clk.c, \
1504 .md_val = MD16(m, n), \
1505 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001506 }
1507static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001508 F_TSIF_REF( 0, gnd, 1, 0, 0),
1509 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001510 F_END
1511};
1512
1513static struct rcg_clk tsif_ref_clk = {
1514 .b = {
1515 .ctl_reg = TSIF_REF_CLK_NS_REG,
1516 .en_mask = BIT(9),
1517 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1518 .halt_bit = 5,
1519 },
1520 .ns_reg = TSIF_REF_CLK_NS_REG,
1521 .md_reg = TSIF_REF_CLK_MD_REG,
1522 .root_en_mask = BIT(11),
1523 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001524 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001525 .set_rate = set_rate_mnd,
1526 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001527 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001528 .c = {
1529 .dbg_name = "tsif_ref_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001530 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001531 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001532 CLK_INIT(tsif_ref_clk.c),
1533 },
1534};
1535
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001536#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001537 { \
1538 .freq_hz = f, \
1539 .src_clk = &s##_clk.c, \
1540 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001541 }
1542static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001543 F_TSSC( 0, gnd),
1544 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001545 F_END
1546};
1547
1548static struct rcg_clk tssc_clk = {
1549 .b = {
1550 .ctl_reg = TSSC_CLK_CTL_REG,
1551 .en_mask = BIT(4),
1552 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1553 .halt_bit = 4,
1554 },
1555 .ns_reg = TSSC_CLK_CTL_REG,
1556 .ns_mask = BM(1, 0),
1557 .set_rate = set_rate_nop,
1558 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001559 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001560 .c = {
1561 .dbg_name = "tssc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001562 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001563 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001564 CLK_INIT(tssc_clk.c),
1565 },
1566};
1567
Tianyi Gou41515e22011-09-01 19:37:43 -07001568#define CLK_USB_HS(name, n, h_b) \
1569 static struct rcg_clk name = { \
1570 .b = { \
1571 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1572 .en_mask = BIT(9), \
1573 .reset_reg = USB_HS##n##_RESET_REG, \
1574 .reset_mask = BIT(0), \
1575 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1576 .halt_bit = h_b, \
1577 }, \
1578 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1579 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1580 .root_en_mask = BIT(11), \
1581 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001582 .mnd_en_mask = BIT(8), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001583 .set_rate = set_rate_mnd, \
1584 .freq_tbl = clk_tbl_usb, \
1585 .current_freq = &rcg_dummy_freq, \
1586 .c = { \
1587 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001588 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001589 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001590 CLK_INIT(name.c), \
1591 }, \
1592}
1593
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001594#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001595 { \
1596 .freq_hz = f, \
1597 .src_clk = &s##_clk.c, \
1598 .md_val = MD8(16, m, 0, n), \
1599 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001600 }
1601static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001602 F_USB( 0, gnd, 1, 0, 0),
1603 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001604 F_END
1605};
1606
Tianyi Gou41515e22011-09-01 19:37:43 -07001607CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1608CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1609CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001610
Stephen Boyd94625ef2011-07-12 17:06:01 -07001611static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001612 F_USB( 0, gnd, 1, 0, 0),
1613 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001614 F_END
1615};
1616
1617static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1618 .b = {
1619 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1620 .en_mask = BIT(9),
1621 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1622 .halt_bit = 26,
1623 },
1624 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1625 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1626 .root_en_mask = BIT(11),
1627 .ns_mask = (BM(23, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001628 .mnd_en_mask = BIT(8),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001629 .set_rate = set_rate_mnd,
1630 .freq_tbl = clk_tbl_usb_hsic,
1631 .current_freq = &rcg_dummy_freq,
1632 .c = {
1633 .dbg_name = "usb_hsic_xcvr_fs_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001634 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001635 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001636 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1637 },
1638};
1639
1640static struct branch_clk usb_hsic_system_clk = {
1641 .b = {
1642 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1643 .en_mask = BIT(4),
1644 .reset_reg = USB_HSIC_RESET_REG,
1645 .reset_mask = BIT(0),
1646 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1647 .halt_bit = 24,
1648 },
1649 .parent = &usb_hsic_xcvr_fs_clk.c,
1650 .c = {
1651 .dbg_name = "usb_hsic_system_clk",
1652 .ops = &clk_ops_branch,
1653 CLK_INIT(usb_hsic_system_clk.c),
1654 },
1655};
1656
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001657#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001658 { \
1659 .freq_hz = f, \
1660 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001661 }
1662static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001663 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001664 F_END
1665};
1666
1667static struct rcg_clk usb_hsic_hsic_src_clk = {
1668 .b = {
1669 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1670 .halt_check = NOCHECK,
1671 },
1672 .root_en_mask = BIT(0),
1673 .set_rate = set_rate_nop,
1674 .freq_tbl = clk_tbl_usb2_hsic,
1675 .current_freq = &rcg_dummy_freq,
1676 .c = {
1677 .dbg_name = "usb_hsic_hsic_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001678 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001679 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001680 CLK_INIT(usb_hsic_hsic_src_clk.c),
1681 },
1682};
1683
1684static struct branch_clk usb_hsic_hsic_clk = {
1685 .b = {
1686 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1687 .en_mask = BIT(0),
1688 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1689 .halt_bit = 19,
1690 },
1691 .parent = &usb_hsic_hsic_src_clk.c,
1692 .c = {
1693 .dbg_name = "usb_hsic_hsic_clk",
1694 .ops = &clk_ops_branch,
1695 CLK_INIT(usb_hsic_hsic_clk.c),
1696 },
1697};
1698
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001699#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001700 { \
1701 .freq_hz = f, \
1702 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001703 }
1704static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001705 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001706 F_END
1707};
1708
1709static struct rcg_clk usb_hsic_hsio_cal_clk = {
1710 .b = {
1711 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1712 .en_mask = BIT(0),
1713 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1714 .halt_bit = 23,
1715 },
1716 .set_rate = set_rate_nop,
1717 .freq_tbl = clk_tbl_usb_hsio_cal,
1718 .current_freq = &rcg_dummy_freq,
1719 .c = {
1720 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001721 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001722 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001723 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1724 },
1725};
1726
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001727static struct branch_clk usb_phy0_clk = {
1728 .b = {
1729 .reset_reg = USB_PHY0_RESET_REG,
1730 .reset_mask = BIT(0),
1731 },
1732 .c = {
1733 .dbg_name = "usb_phy0_clk",
1734 .ops = &clk_ops_reset,
1735 CLK_INIT(usb_phy0_clk.c),
1736 },
1737};
1738
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001739#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001740 struct rcg_clk i##_clk = { \
1741 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1742 .b = { \
1743 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1744 .halt_check = NOCHECK, \
1745 }, \
1746 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1747 .root_en_mask = BIT(11), \
1748 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001749 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001750 .set_rate = set_rate_mnd, \
1751 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001752 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001753 .c = { \
1754 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07001755 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001756 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001757 CLK_INIT(i##_clk.c), \
1758 }, \
1759 }
1760
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001761static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001762static struct branch_clk usb_fs1_xcvr_clk = {
1763 .b = {
1764 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1765 .en_mask = BIT(9),
1766 .reset_reg = USB_FSn_RESET_REG(1),
1767 .reset_mask = BIT(1),
1768 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1769 .halt_bit = 15,
1770 },
1771 .parent = &usb_fs1_src_clk.c,
1772 .c = {
1773 .dbg_name = "usb_fs1_xcvr_clk",
1774 .ops = &clk_ops_branch,
1775 CLK_INIT(usb_fs1_xcvr_clk.c),
1776 },
1777};
1778
1779static struct branch_clk usb_fs1_sys_clk = {
1780 .b = {
1781 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1782 .en_mask = BIT(4),
1783 .reset_reg = USB_FSn_RESET_REG(1),
1784 .reset_mask = BIT(0),
1785 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1786 .halt_bit = 16,
1787 },
1788 .parent = &usb_fs1_src_clk.c,
1789 .c = {
1790 .dbg_name = "usb_fs1_sys_clk",
1791 .ops = &clk_ops_branch,
1792 CLK_INIT(usb_fs1_sys_clk.c),
1793 },
1794};
1795
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001796static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001797static struct branch_clk usb_fs2_xcvr_clk = {
1798 .b = {
1799 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1800 .en_mask = BIT(9),
1801 .reset_reg = USB_FSn_RESET_REG(2),
1802 .reset_mask = BIT(1),
1803 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1804 .halt_bit = 12,
1805 },
1806 .parent = &usb_fs2_src_clk.c,
1807 .c = {
1808 .dbg_name = "usb_fs2_xcvr_clk",
1809 .ops = &clk_ops_branch,
1810 CLK_INIT(usb_fs2_xcvr_clk.c),
1811 },
1812};
1813
1814static struct branch_clk usb_fs2_sys_clk = {
1815 .b = {
1816 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1817 .en_mask = BIT(4),
1818 .reset_reg = USB_FSn_RESET_REG(2),
1819 .reset_mask = BIT(0),
1820 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1821 .halt_bit = 13,
1822 },
1823 .parent = &usb_fs2_src_clk.c,
1824 .c = {
1825 .dbg_name = "usb_fs2_sys_clk",
1826 .ops = &clk_ops_branch,
1827 CLK_INIT(usb_fs2_sys_clk.c),
1828 },
1829};
1830
1831/* Fast Peripheral Bus Clocks */
1832static struct branch_clk ce1_core_clk = {
1833 .b = {
1834 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1835 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001836 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1837 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001838 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1839 .halt_bit = 27,
1840 },
1841 .c = {
1842 .dbg_name = "ce1_core_clk",
1843 .ops = &clk_ops_branch,
1844 CLK_INIT(ce1_core_clk.c),
1845 },
1846};
Tianyi Gou41515e22011-09-01 19:37:43 -07001847
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001848static struct branch_clk ce1_p_clk = {
1849 .b = {
1850 .ctl_reg = CE1_HCLK_CTL_REG,
1851 .en_mask = BIT(4),
1852 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1853 .halt_bit = 1,
1854 },
1855 .c = {
1856 .dbg_name = "ce1_p_clk",
1857 .ops = &clk_ops_branch,
1858 CLK_INIT(ce1_p_clk.c),
1859 },
1860};
1861
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001862#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001863 { \
1864 .freq_hz = f, \
1865 .src_clk = &s##_clk.c, \
1866 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001867 }
1868
1869static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001870 F_CE3( 0, gnd, 1),
1871 F_CE3( 48000000, pll8, 8),
1872 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001873 F_END
1874};
1875
1876static struct rcg_clk ce3_src_clk = {
1877 .b = {
1878 .ctl_reg = CE3_CLK_SRC_NS_REG,
1879 .halt_check = NOCHECK,
1880 },
1881 .ns_reg = CE3_CLK_SRC_NS_REG,
1882 .root_en_mask = BIT(7),
1883 .ns_mask = BM(6, 0),
1884 .set_rate = set_rate_nop,
1885 .freq_tbl = clk_tbl_ce3,
1886 .current_freq = &rcg_dummy_freq,
1887 .c = {
1888 .dbg_name = "ce3_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07001889 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001890 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001891 CLK_INIT(ce3_src_clk.c),
1892 },
1893};
1894
1895static struct branch_clk ce3_core_clk = {
1896 .b = {
1897 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1898 .en_mask = BIT(4),
1899 .reset_reg = CE3_CORE_CLK_CTL_REG,
1900 .reset_mask = BIT(7),
1901 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1902 .halt_bit = 5,
1903 },
1904 .parent = &ce3_src_clk.c,
1905 .c = {
1906 .dbg_name = "ce3_core_clk",
1907 .ops = &clk_ops_branch,
1908 CLK_INIT(ce3_core_clk.c),
1909 }
1910};
1911
1912static struct branch_clk ce3_p_clk = {
1913 .b = {
1914 .ctl_reg = CE3_HCLK_CTL_REG,
1915 .en_mask = BIT(4),
1916 .reset_reg = CE3_HCLK_CTL_REG,
1917 .reset_mask = BIT(7),
1918 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1919 .halt_bit = 16,
1920 },
1921 .parent = &ce3_src_clk.c,
1922 .c = {
1923 .dbg_name = "ce3_p_clk",
1924 .ops = &clk_ops_branch,
1925 CLK_INIT(ce3_p_clk.c),
1926 }
1927};
1928
1929static struct branch_clk sata_phy_ref_clk = {
1930 .b = {
1931 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
1932 .en_mask = BIT(4),
1933 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1934 .halt_bit = 24,
1935 },
1936 .parent = &pxo_clk.c,
1937 .c = {
1938 .dbg_name = "sata_phy_ref_clk",
1939 .ops = &clk_ops_branch,
1940 CLK_INIT(sata_phy_ref_clk.c),
1941 },
1942};
1943
1944static struct branch_clk pcie_p_clk = {
1945 .b = {
1946 .ctl_reg = PCIE_HCLK_CTL_REG,
1947 .en_mask = BIT(4),
1948 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1949 .halt_bit = 8,
1950 },
1951 .c = {
1952 .dbg_name = "pcie_p_clk",
1953 .ops = &clk_ops_branch,
1954 CLK_INIT(pcie_p_clk.c),
1955 },
1956};
1957
Tianyi Gou6613de52012-01-27 17:57:53 -08001958static struct branch_clk pcie_phy_ref_clk = {
1959 .b = {
1960 .ctl_reg = PCIE_PCLK_CTL_REG,
1961 .en_mask = BIT(4),
1962 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1963 .halt_bit = 29,
1964 },
1965 .c = {
1966 .dbg_name = "pcie_phy_ref_clk",
1967 .ops = &clk_ops_branch,
1968 CLK_INIT(pcie_phy_ref_clk.c),
1969 },
1970};
1971
1972static struct branch_clk pcie_a_clk = {
1973 .b = {
1974 .ctl_reg = PCIE_ACLK_CTL_REG,
1975 .en_mask = BIT(4),
1976 .halt_reg = CLK_HALT_AFAB_SFAB_STATEA_REG,
1977 .halt_bit = 13,
1978 },
1979 .c = {
1980 .dbg_name = "pcie_a_clk",
1981 .ops = &clk_ops_branch,
1982 CLK_INIT(pcie_a_clk.c),
1983 },
1984};
1985
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001986static struct branch_clk dma_bam_p_clk = {
1987 .b = {
1988 .ctl_reg = DMA_BAM_HCLK_CTL,
1989 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001990 .hwcg_reg = DMA_BAM_HCLK_CTL,
1991 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001992 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1993 .halt_bit = 12,
1994 },
1995 .c = {
1996 .dbg_name = "dma_bam_p_clk",
1997 .ops = &clk_ops_branch,
1998 CLK_INIT(dma_bam_p_clk.c),
1999 },
2000};
2001
2002static struct branch_clk gsbi1_p_clk = {
2003 .b = {
2004 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2005 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002006 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
2007 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002008 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2009 .halt_bit = 11,
2010 },
2011 .c = {
2012 .dbg_name = "gsbi1_p_clk",
2013 .ops = &clk_ops_branch,
2014 CLK_INIT(gsbi1_p_clk.c),
2015 },
2016};
2017
2018static struct branch_clk gsbi2_p_clk = {
2019 .b = {
2020 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2021 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002022 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2023 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002024 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2025 .halt_bit = 7,
2026 },
2027 .c = {
2028 .dbg_name = "gsbi2_p_clk",
2029 .ops = &clk_ops_branch,
2030 CLK_INIT(gsbi2_p_clk.c),
2031 },
2032};
2033
2034static struct branch_clk gsbi3_p_clk = {
2035 .b = {
2036 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2037 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002038 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2039 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002040 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2041 .halt_bit = 3,
2042 },
2043 .c = {
2044 .dbg_name = "gsbi3_p_clk",
2045 .ops = &clk_ops_branch,
2046 CLK_INIT(gsbi3_p_clk.c),
2047 },
2048};
2049
2050static struct branch_clk gsbi4_p_clk = {
2051 .b = {
2052 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2053 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002054 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2055 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002056 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2057 .halt_bit = 27,
2058 },
2059 .c = {
2060 .dbg_name = "gsbi4_p_clk",
2061 .ops = &clk_ops_branch,
2062 CLK_INIT(gsbi4_p_clk.c),
2063 },
2064};
2065
2066static struct branch_clk gsbi5_p_clk = {
2067 .b = {
2068 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2069 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002070 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2071 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002072 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2073 .halt_bit = 23,
2074 },
2075 .c = {
2076 .dbg_name = "gsbi5_p_clk",
2077 .ops = &clk_ops_branch,
2078 CLK_INIT(gsbi5_p_clk.c),
2079 },
2080};
2081
2082static struct branch_clk gsbi6_p_clk = {
2083 .b = {
2084 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2085 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002086 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2087 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002088 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2089 .halt_bit = 19,
2090 },
2091 .c = {
2092 .dbg_name = "gsbi6_p_clk",
2093 .ops = &clk_ops_branch,
2094 CLK_INIT(gsbi6_p_clk.c),
2095 },
2096};
2097
2098static struct branch_clk gsbi7_p_clk = {
2099 .b = {
2100 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2101 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002102 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2103 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002104 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2105 .halt_bit = 15,
2106 },
2107 .c = {
2108 .dbg_name = "gsbi7_p_clk",
2109 .ops = &clk_ops_branch,
2110 CLK_INIT(gsbi7_p_clk.c),
2111 },
2112};
2113
2114static struct branch_clk gsbi8_p_clk = {
2115 .b = {
2116 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2117 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002118 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2119 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002120 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2121 .halt_bit = 11,
2122 },
2123 .c = {
2124 .dbg_name = "gsbi8_p_clk",
2125 .ops = &clk_ops_branch,
2126 CLK_INIT(gsbi8_p_clk.c),
2127 },
2128};
2129
2130static struct branch_clk gsbi9_p_clk = {
2131 .b = {
2132 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2133 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002134 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2135 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002136 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2137 .halt_bit = 7,
2138 },
2139 .c = {
2140 .dbg_name = "gsbi9_p_clk",
2141 .ops = &clk_ops_branch,
2142 CLK_INIT(gsbi9_p_clk.c),
2143 },
2144};
2145
2146static struct branch_clk gsbi10_p_clk = {
2147 .b = {
2148 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2149 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002150 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2151 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002152 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2153 .halt_bit = 3,
2154 },
2155 .c = {
2156 .dbg_name = "gsbi10_p_clk",
2157 .ops = &clk_ops_branch,
2158 CLK_INIT(gsbi10_p_clk.c),
2159 },
2160};
2161
2162static struct branch_clk gsbi11_p_clk = {
2163 .b = {
2164 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2165 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002166 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2167 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002168 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2169 .halt_bit = 18,
2170 },
2171 .c = {
2172 .dbg_name = "gsbi11_p_clk",
2173 .ops = &clk_ops_branch,
2174 CLK_INIT(gsbi11_p_clk.c),
2175 },
2176};
2177
2178static struct branch_clk gsbi12_p_clk = {
2179 .b = {
2180 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2181 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002182 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2183 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002184 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2185 .halt_bit = 14,
2186 },
2187 .c = {
2188 .dbg_name = "gsbi12_p_clk",
2189 .ops = &clk_ops_branch,
2190 CLK_INIT(gsbi12_p_clk.c),
2191 },
2192};
2193
Tianyi Gou41515e22011-09-01 19:37:43 -07002194static struct branch_clk sata_phy_cfg_clk = {
2195 .b = {
2196 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2197 .en_mask = BIT(4),
2198 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2199 .halt_bit = 12,
2200 },
2201 .c = {
2202 .dbg_name = "sata_phy_cfg_clk",
2203 .ops = &clk_ops_branch,
2204 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002205 },
2206};
2207
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002208static struct branch_clk tsif_p_clk = {
2209 .b = {
2210 .ctl_reg = TSIF_HCLK_CTL_REG,
2211 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002212 .hwcg_reg = TSIF_HCLK_CTL_REG,
2213 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002214 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2215 .halt_bit = 7,
2216 },
2217 .c = {
2218 .dbg_name = "tsif_p_clk",
2219 .ops = &clk_ops_branch,
2220 CLK_INIT(tsif_p_clk.c),
2221 },
2222};
2223
2224static struct branch_clk usb_fs1_p_clk = {
2225 .b = {
2226 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2227 .en_mask = BIT(4),
2228 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2229 .halt_bit = 17,
2230 },
2231 .c = {
2232 .dbg_name = "usb_fs1_p_clk",
2233 .ops = &clk_ops_branch,
2234 CLK_INIT(usb_fs1_p_clk.c),
2235 },
2236};
2237
2238static struct branch_clk usb_fs2_p_clk = {
2239 .b = {
2240 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2241 .en_mask = BIT(4),
2242 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2243 .halt_bit = 14,
2244 },
2245 .c = {
2246 .dbg_name = "usb_fs2_p_clk",
2247 .ops = &clk_ops_branch,
2248 CLK_INIT(usb_fs2_p_clk.c),
2249 },
2250};
2251
2252static struct branch_clk usb_hs1_p_clk = {
2253 .b = {
2254 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2255 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002256 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2257 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002258 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2259 .halt_bit = 1,
2260 },
2261 .c = {
2262 .dbg_name = "usb_hs1_p_clk",
2263 .ops = &clk_ops_branch,
2264 CLK_INIT(usb_hs1_p_clk.c),
2265 },
2266};
2267
Tianyi Gou41515e22011-09-01 19:37:43 -07002268static struct branch_clk usb_hs3_p_clk = {
2269 .b = {
2270 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2271 .en_mask = BIT(4),
2272 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2273 .halt_bit = 31,
2274 },
2275 .c = {
2276 .dbg_name = "usb_hs3_p_clk",
2277 .ops = &clk_ops_branch,
2278 CLK_INIT(usb_hs3_p_clk.c),
2279 },
2280};
2281
2282static struct branch_clk usb_hs4_p_clk = {
2283 .b = {
2284 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2285 .en_mask = BIT(4),
2286 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2287 .halt_bit = 7,
2288 },
2289 .c = {
2290 .dbg_name = "usb_hs4_p_clk",
2291 .ops = &clk_ops_branch,
2292 CLK_INIT(usb_hs4_p_clk.c),
2293 },
2294};
2295
Stephen Boyd94625ef2011-07-12 17:06:01 -07002296static struct branch_clk usb_hsic_p_clk = {
2297 .b = {
2298 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2299 .en_mask = BIT(4),
2300 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2301 .halt_bit = 28,
2302 },
2303 .c = {
2304 .dbg_name = "usb_hsic_p_clk",
2305 .ops = &clk_ops_branch,
2306 CLK_INIT(usb_hsic_p_clk.c),
2307 },
2308};
2309
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002310static struct branch_clk sdc1_p_clk = {
2311 .b = {
2312 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2313 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002314 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2315 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002316 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2317 .halt_bit = 11,
2318 },
2319 .c = {
2320 .dbg_name = "sdc1_p_clk",
2321 .ops = &clk_ops_branch,
2322 CLK_INIT(sdc1_p_clk.c),
2323 },
2324};
2325
2326static struct branch_clk sdc2_p_clk = {
2327 .b = {
2328 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2329 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002330 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2331 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002332 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2333 .halt_bit = 10,
2334 },
2335 .c = {
2336 .dbg_name = "sdc2_p_clk",
2337 .ops = &clk_ops_branch,
2338 CLK_INIT(sdc2_p_clk.c),
2339 },
2340};
2341
2342static struct branch_clk sdc3_p_clk = {
2343 .b = {
2344 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2345 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002346 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2347 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002348 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2349 .halt_bit = 9,
2350 },
2351 .c = {
2352 .dbg_name = "sdc3_p_clk",
2353 .ops = &clk_ops_branch,
2354 CLK_INIT(sdc3_p_clk.c),
2355 },
2356};
2357
2358static struct branch_clk sdc4_p_clk = {
2359 .b = {
2360 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2361 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002362 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2363 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002364 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2365 .halt_bit = 8,
2366 },
2367 .c = {
2368 .dbg_name = "sdc4_p_clk",
2369 .ops = &clk_ops_branch,
2370 CLK_INIT(sdc4_p_clk.c),
2371 },
2372};
2373
2374static struct branch_clk sdc5_p_clk = {
2375 .b = {
2376 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2377 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002378 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2379 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002380 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2381 .halt_bit = 7,
2382 },
2383 .c = {
2384 .dbg_name = "sdc5_p_clk",
2385 .ops = &clk_ops_branch,
2386 CLK_INIT(sdc5_p_clk.c),
2387 },
2388};
2389
2390/* HW-Voteable Clocks */
2391static struct branch_clk adm0_clk = {
2392 .b = {
2393 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2394 .en_mask = BIT(2),
2395 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2396 .halt_check = HALT_VOTED,
2397 .halt_bit = 14,
2398 },
2399 .c = {
2400 .dbg_name = "adm0_clk",
2401 .ops = &clk_ops_branch,
2402 CLK_INIT(adm0_clk.c),
2403 },
2404};
2405
2406static struct branch_clk adm0_p_clk = {
2407 .b = {
2408 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2409 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002410 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2411 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002412 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2413 .halt_check = HALT_VOTED,
2414 .halt_bit = 13,
2415 },
2416 .c = {
2417 .dbg_name = "adm0_p_clk",
2418 .ops = &clk_ops_branch,
2419 CLK_INIT(adm0_p_clk.c),
2420 },
2421};
2422
2423static struct branch_clk pmic_arb0_p_clk = {
2424 .b = {
2425 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2426 .en_mask = BIT(8),
2427 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2428 .halt_check = HALT_VOTED,
2429 .halt_bit = 22,
2430 },
2431 .c = {
2432 .dbg_name = "pmic_arb0_p_clk",
2433 .ops = &clk_ops_branch,
2434 CLK_INIT(pmic_arb0_p_clk.c),
2435 },
2436};
2437
2438static struct branch_clk pmic_arb1_p_clk = {
2439 .b = {
2440 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2441 .en_mask = BIT(9),
2442 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2443 .halt_check = HALT_VOTED,
2444 .halt_bit = 21,
2445 },
2446 .c = {
2447 .dbg_name = "pmic_arb1_p_clk",
2448 .ops = &clk_ops_branch,
2449 CLK_INIT(pmic_arb1_p_clk.c),
2450 },
2451};
2452
2453static struct branch_clk pmic_ssbi2_clk = {
2454 .b = {
2455 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2456 .en_mask = BIT(7),
2457 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2458 .halt_check = HALT_VOTED,
2459 .halt_bit = 23,
2460 },
2461 .c = {
2462 .dbg_name = "pmic_ssbi2_clk",
2463 .ops = &clk_ops_branch,
2464 CLK_INIT(pmic_ssbi2_clk.c),
2465 },
2466};
2467
2468static struct branch_clk rpm_msg_ram_p_clk = {
2469 .b = {
2470 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2471 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002472 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2473 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002474 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2475 .halt_check = HALT_VOTED,
2476 .halt_bit = 12,
2477 },
2478 .c = {
2479 .dbg_name = "rpm_msg_ram_p_clk",
2480 .ops = &clk_ops_branch,
2481 CLK_INIT(rpm_msg_ram_p_clk.c),
2482 },
2483};
2484
2485/*
2486 * Multimedia Clocks
2487 */
2488
Stephen Boyd94625ef2011-07-12 17:06:01 -07002489#define CLK_CAM(name, n, hb) \
2490 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002491 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002492 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002493 .en_mask = BIT(0), \
2494 .halt_reg = DBG_BUS_VEC_I_REG, \
2495 .halt_bit = hb, \
2496 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002497 .ns_reg = CAMCLK##n##_NS_REG, \
2498 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002499 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002500 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Matt Wagantall07c45472012-02-10 23:27:24 -08002501 .mnd_en_mask = BIT(5), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002502 .ctl_mask = BM(7, 6), \
2503 .set_rate = set_rate_mnd_8, \
2504 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002505 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002506 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002507 .dbg_name = #name, \
Stephen Boyd409b8b42012-04-10 12:12:56 -07002508 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002509 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002510 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002511 }, \
2512 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002513#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002514 { \
2515 .freq_hz = f, \
2516 .src_clk = &s##_clk.c, \
2517 .md_val = MD8(8, m, 0, n), \
2518 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2519 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002520 }
2521static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002522 F_CAM( 0, gnd, 1, 0, 0),
2523 F_CAM( 6000000, pll8, 4, 1, 16),
2524 F_CAM( 8000000, pll8, 4, 1, 12),
2525 F_CAM( 12000000, pll8, 4, 1, 8),
2526 F_CAM( 16000000, pll8, 4, 1, 6),
2527 F_CAM( 19200000, pll8, 4, 1, 5),
2528 F_CAM( 24000000, pll8, 4, 1, 4),
2529 F_CAM( 32000000, pll8, 4, 1, 3),
2530 F_CAM( 48000000, pll8, 4, 1, 2),
2531 F_CAM( 64000000, pll8, 3, 1, 2),
2532 F_CAM( 96000000, pll8, 4, 0, 0),
2533 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002534 F_END
2535};
2536
Stephen Boyd94625ef2011-07-12 17:06:01 -07002537static CLK_CAM(cam0_clk, 0, 15);
2538static CLK_CAM(cam1_clk, 1, 16);
2539static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002540
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002541#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002542 { \
2543 .freq_hz = f, \
2544 .src_clk = &s##_clk.c, \
2545 .md_val = MD8(8, m, 0, n), \
2546 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2547 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002548 }
2549static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002550 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002551 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002552 F_CSI( 85330000, pll8, 1, 2, 9),
2553 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002554 F_END
2555};
2556
2557static struct rcg_clk csi0_src_clk = {
2558 .ns_reg = CSI0_NS_REG,
2559 .b = {
2560 .ctl_reg = CSI0_CC_REG,
2561 .halt_check = NOCHECK,
2562 },
2563 .md_reg = CSI0_MD_REG,
2564 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002565 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002566 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002567 .ctl_mask = BM(7, 6),
2568 .set_rate = set_rate_mnd,
2569 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002570 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002571 .c = {
2572 .dbg_name = "csi0_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002573 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002574 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002575 CLK_INIT(csi0_src_clk.c),
2576 },
2577};
2578
2579static struct branch_clk csi0_clk = {
2580 .b = {
2581 .ctl_reg = CSI0_CC_REG,
2582 .en_mask = BIT(0),
2583 .reset_reg = SW_RESET_CORE_REG,
2584 .reset_mask = BIT(8),
2585 .halt_reg = DBG_BUS_VEC_B_REG,
2586 .halt_bit = 13,
2587 },
2588 .parent = &csi0_src_clk.c,
2589 .c = {
2590 .dbg_name = "csi0_clk",
2591 .ops = &clk_ops_branch,
2592 CLK_INIT(csi0_clk.c),
2593 },
2594};
2595
2596static struct branch_clk csi0_phy_clk = {
2597 .b = {
2598 .ctl_reg = CSI0_CC_REG,
2599 .en_mask = BIT(8),
2600 .reset_reg = SW_RESET_CORE_REG,
2601 .reset_mask = BIT(29),
2602 .halt_reg = DBG_BUS_VEC_I_REG,
2603 .halt_bit = 9,
2604 },
2605 .parent = &csi0_src_clk.c,
2606 .c = {
2607 .dbg_name = "csi0_phy_clk",
2608 .ops = &clk_ops_branch,
2609 CLK_INIT(csi0_phy_clk.c),
2610 },
2611};
2612
2613static struct rcg_clk csi1_src_clk = {
2614 .ns_reg = CSI1_NS_REG,
2615 .b = {
2616 .ctl_reg = CSI1_CC_REG,
2617 .halt_check = NOCHECK,
2618 },
2619 .md_reg = CSI1_MD_REG,
2620 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002621 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002622 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002623 .ctl_mask = BM(7, 6),
2624 .set_rate = set_rate_mnd,
2625 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002626 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002627 .c = {
2628 .dbg_name = "csi1_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002629 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002630 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002631 CLK_INIT(csi1_src_clk.c),
2632 },
2633};
2634
2635static struct branch_clk csi1_clk = {
2636 .b = {
2637 .ctl_reg = CSI1_CC_REG,
2638 .en_mask = BIT(0),
2639 .reset_reg = SW_RESET_CORE_REG,
2640 .reset_mask = BIT(18),
2641 .halt_reg = DBG_BUS_VEC_B_REG,
2642 .halt_bit = 14,
2643 },
2644 .parent = &csi1_src_clk.c,
2645 .c = {
2646 .dbg_name = "csi1_clk",
2647 .ops = &clk_ops_branch,
2648 CLK_INIT(csi1_clk.c),
2649 },
2650};
2651
2652static struct branch_clk csi1_phy_clk = {
2653 .b = {
2654 .ctl_reg = CSI1_CC_REG,
2655 .en_mask = BIT(8),
2656 .reset_reg = SW_RESET_CORE_REG,
2657 .reset_mask = BIT(28),
2658 .halt_reg = DBG_BUS_VEC_I_REG,
2659 .halt_bit = 10,
2660 },
2661 .parent = &csi1_src_clk.c,
2662 .c = {
2663 .dbg_name = "csi1_phy_clk",
2664 .ops = &clk_ops_branch,
2665 CLK_INIT(csi1_phy_clk.c),
2666 },
2667};
2668
Stephen Boyd94625ef2011-07-12 17:06:01 -07002669static struct rcg_clk csi2_src_clk = {
2670 .ns_reg = CSI2_NS_REG,
2671 .b = {
2672 .ctl_reg = CSI2_CC_REG,
2673 .halt_check = NOCHECK,
2674 },
2675 .md_reg = CSI2_MD_REG,
2676 .root_en_mask = BIT(2),
2677 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002678 .mnd_en_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002679 .ctl_mask = BM(7, 6),
2680 .set_rate = set_rate_mnd,
2681 .freq_tbl = clk_tbl_csi,
2682 .current_freq = &rcg_dummy_freq,
2683 .c = {
2684 .dbg_name = "csi2_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07002685 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002686 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002687 CLK_INIT(csi2_src_clk.c),
2688 },
2689};
2690
2691static struct branch_clk csi2_clk = {
2692 .b = {
2693 .ctl_reg = CSI2_CC_REG,
2694 .en_mask = BIT(0),
2695 .reset_reg = SW_RESET_CORE2_REG,
2696 .reset_mask = BIT(2),
2697 .halt_reg = DBG_BUS_VEC_B_REG,
2698 .halt_bit = 29,
2699 },
2700 .parent = &csi2_src_clk.c,
2701 .c = {
2702 .dbg_name = "csi2_clk",
2703 .ops = &clk_ops_branch,
2704 CLK_INIT(csi2_clk.c),
2705 },
2706};
2707
2708static struct branch_clk csi2_phy_clk = {
2709 .b = {
2710 .ctl_reg = CSI2_CC_REG,
2711 .en_mask = BIT(8),
2712 .reset_reg = SW_RESET_CORE_REG,
2713 .reset_mask = BIT(31),
2714 .halt_reg = DBG_BUS_VEC_I_REG,
2715 .halt_bit = 29,
2716 },
2717 .parent = &csi2_src_clk.c,
2718 .c = {
2719 .dbg_name = "csi2_phy_clk",
2720 .ops = &clk_ops_branch,
2721 CLK_INIT(csi2_phy_clk.c),
2722 },
2723};
2724
Stephen Boyd092fd182011-10-21 15:56:30 -07002725static struct clk *pix_rdi_mux_map[] = {
2726 [0] = &csi0_clk.c,
2727 [1] = &csi1_clk.c,
2728 [2] = &csi2_clk.c,
2729 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002730};
2731
Stephen Boyd092fd182011-10-21 15:56:30 -07002732struct pix_rdi_clk {
2733 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002734 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002735
2736 void __iomem *const s_reg;
2737 u32 s_mask;
2738
2739 void __iomem *const s2_reg;
2740 u32 s2_mask;
2741
2742 struct branch b;
2743 struct clk c;
2744};
2745
2746static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
2747{
2748 return container_of(clk, struct pix_rdi_clk, c);
2749}
2750
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002751static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002752{
2753 int ret, i;
2754 u32 reg;
2755 unsigned long flags;
2756 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2757 struct clk **mux_map = pix_rdi_mux_map;
2758
2759 /*
2760 * These clocks select three inputs via two muxes. One mux selects
2761 * between csi0 and csi1 and the second mux selects between that mux's
2762 * output and csi2. The source and destination selections for each
2763 * mux must be clocking for the switch to succeed so just turn on
2764 * all three sources because it's easier than figuring out what source
2765 * needs to be on at what time.
2766 */
2767 for (i = 0; mux_map[i]; i++) {
2768 ret = clk_enable(mux_map[i]);
2769 if (ret)
2770 goto err;
2771 }
2772 if (rate >= i) {
2773 ret = -EINVAL;
2774 goto err;
2775 }
2776 /* Keep the new source on when switching inputs of an enabled clock */
2777 if (clk->enabled) {
2778 clk_disable(mux_map[clk->cur_rate]);
2779 clk_enable(mux_map[rate]);
2780 }
2781 spin_lock_irqsave(&local_clock_reg_lock, flags);
2782 reg = readl_relaxed(clk->s2_reg);
2783 reg &= ~clk->s2_mask;
2784 reg |= rate == 2 ? clk->s2_mask : 0;
2785 writel_relaxed(reg, clk->s2_reg);
2786 /*
2787 * Wait at least 6 cycles of slowest clock
2788 * for the glitch-free MUX to fully switch sources.
2789 */
2790 mb();
2791 udelay(1);
2792 reg = readl_relaxed(clk->s_reg);
2793 reg &= ~clk->s_mask;
2794 reg |= rate == 1 ? clk->s_mask : 0;
2795 writel_relaxed(reg, clk->s_reg);
2796 /*
2797 * Wait at least 6 cycles of slowest clock
2798 * for the glitch-free MUX to fully switch sources.
2799 */
2800 mb();
2801 udelay(1);
2802 clk->cur_rate = rate;
2803 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2804err:
2805 for (i--; i >= 0; i--)
2806 clk_disable(mux_map[i]);
2807
2808 return 0;
2809}
2810
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002811static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002812{
2813 return to_pix_rdi_clk(c)->cur_rate;
2814}
2815
2816static int pix_rdi_clk_enable(struct clk *c)
2817{
2818 unsigned long flags;
2819 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2820
2821 spin_lock_irqsave(&local_clock_reg_lock, flags);
2822 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
2823 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2824 clk->enabled = true;
2825
2826 return 0;
2827}
2828
2829static void pix_rdi_clk_disable(struct clk *c)
2830{
2831 unsigned long flags;
2832 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2833
2834 spin_lock_irqsave(&local_clock_reg_lock, flags);
2835 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
2836 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2837 clk->enabled = false;
2838}
2839
2840static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
2841{
2842 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
2843}
2844
2845static struct clk *pix_rdi_clk_get_parent(struct clk *c)
2846{
2847 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2848
2849 return pix_rdi_mux_map[clk->cur_rate];
2850}
2851
2852static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
2853{
2854 if (pix_rdi_mux_map[n])
2855 return n;
2856 return -ENXIO;
2857}
2858
Matt Wagantalla15833b2012-04-03 11:00:56 -07002859static enum handoff pix_rdi_clk_handoff(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002860{
2861 u32 reg;
2862 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
Matt Wagantalla15833b2012-04-03 11:00:56 -07002863 enum handoff ret;
2864
2865 ret = branch_handoff(&clk->b, &clk->c);
2866 if (ret == HANDOFF_DISABLED_CLK)
2867 return ret;
Stephen Boyd092fd182011-10-21 15:56:30 -07002868
2869 reg = readl_relaxed(clk->s_reg);
2870 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
2871 reg = readl_relaxed(clk->s2_reg);
2872 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
Matt Wagantalla15833b2012-04-03 11:00:56 -07002873
2874 return HANDOFF_ENABLED_CLK;
Stephen Boyd092fd182011-10-21 15:56:30 -07002875}
2876
2877static struct clk_ops clk_ops_pix_rdi_8960 = {
2878 .enable = pix_rdi_clk_enable,
2879 .disable = pix_rdi_clk_disable,
2880 .auto_off = pix_rdi_clk_disable,
2881 .handoff = pix_rdi_clk_handoff,
2882 .set_rate = pix_rdi_clk_set_rate,
2883 .get_rate = pix_rdi_clk_get_rate,
2884 .list_rate = pix_rdi_clk_list_rate,
2885 .reset = pix_rdi_clk_reset,
Stephen Boyd092fd182011-10-21 15:56:30 -07002886 .get_parent = pix_rdi_clk_get_parent,
2887};
2888
2889static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002890 .b = {
2891 .ctl_reg = MISC_CC_REG,
2892 .en_mask = BIT(26),
2893 .halt_check = DELAY,
2894 .reset_reg = SW_RESET_CORE_REG,
2895 .reset_mask = BIT(26),
2896 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002897 .s_reg = MISC_CC_REG,
2898 .s_mask = BIT(25),
2899 .s2_reg = MISC_CC3_REG,
2900 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002901 .c = {
2902 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002903 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002904 CLK_INIT(csi_pix_clk.c),
2905 },
2906};
2907
Stephen Boyd092fd182011-10-21 15:56:30 -07002908static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002909 .b = {
2910 .ctl_reg = MISC_CC3_REG,
2911 .en_mask = BIT(10),
2912 .halt_check = DELAY,
2913 .reset_reg = SW_RESET_CORE_REG,
2914 .reset_mask = BIT(30),
2915 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002916 .s_reg = MISC_CC3_REG,
2917 .s_mask = BIT(8),
2918 .s2_reg = MISC_CC3_REG,
2919 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002920 .c = {
2921 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002922 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002923 CLK_INIT(csi_pix1_clk.c),
2924 },
2925};
2926
Stephen Boyd092fd182011-10-21 15:56:30 -07002927static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002928 .b = {
2929 .ctl_reg = MISC_CC_REG,
2930 .en_mask = BIT(13),
2931 .halt_check = DELAY,
2932 .reset_reg = SW_RESET_CORE_REG,
2933 .reset_mask = BIT(27),
2934 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002935 .s_reg = MISC_CC_REG,
2936 .s_mask = BIT(12),
2937 .s2_reg = MISC_CC3_REG,
2938 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002939 .c = {
2940 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002941 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002942 CLK_INIT(csi_rdi_clk.c),
2943 },
2944};
2945
Stephen Boyd092fd182011-10-21 15:56:30 -07002946static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002947 .b = {
2948 .ctl_reg = MISC_CC3_REG,
2949 .en_mask = BIT(2),
2950 .halt_check = DELAY,
2951 .reset_reg = SW_RESET_CORE2_REG,
2952 .reset_mask = BIT(1),
2953 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002954 .s_reg = MISC_CC3_REG,
2955 .s_mask = BIT(0),
2956 .s2_reg = MISC_CC3_REG,
2957 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002958 .c = {
2959 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002960 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002961 CLK_INIT(csi_rdi1_clk.c),
2962 },
2963};
2964
Stephen Boyd092fd182011-10-21 15:56:30 -07002965static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002966 .b = {
2967 .ctl_reg = MISC_CC3_REG,
2968 .en_mask = BIT(6),
2969 .halt_check = DELAY,
2970 .reset_reg = SW_RESET_CORE2_REG,
2971 .reset_mask = BIT(0),
2972 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002973 .s_reg = MISC_CC3_REG,
2974 .s_mask = BIT(4),
2975 .s2_reg = MISC_CC3_REG,
2976 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002977 .c = {
2978 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002979 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002980 CLK_INIT(csi_rdi2_clk.c),
2981 },
2982};
2983
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002984#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002985 { \
2986 .freq_hz = f, \
2987 .src_clk = &s##_clk.c, \
2988 .md_val = MD8(8, m, 0, n), \
2989 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2990 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002991 }
2992static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002993 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
2994 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
2995 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002996 F_END
2997};
2998
2999static struct rcg_clk csiphy_timer_src_clk = {
3000 .ns_reg = CSIPHYTIMER_NS_REG,
3001 .b = {
3002 .ctl_reg = CSIPHYTIMER_CC_REG,
3003 .halt_check = NOCHECK,
3004 },
3005 .md_reg = CSIPHYTIMER_MD_REG,
3006 .root_en_mask = BIT(2),
3007 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003008 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003009 .ctl_mask = BM(7, 6),
3010 .set_rate = set_rate_mnd_8,
3011 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003012 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003013 .c = {
3014 .dbg_name = "csiphy_timer_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003015 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003016 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003017 CLK_INIT(csiphy_timer_src_clk.c),
3018 },
3019};
3020
3021static struct branch_clk csi0phy_timer_clk = {
3022 .b = {
3023 .ctl_reg = CSIPHYTIMER_CC_REG,
3024 .en_mask = BIT(0),
3025 .halt_reg = DBG_BUS_VEC_I_REG,
3026 .halt_bit = 17,
3027 },
3028 .parent = &csiphy_timer_src_clk.c,
3029 .c = {
3030 .dbg_name = "csi0phy_timer_clk",
3031 .ops = &clk_ops_branch,
3032 CLK_INIT(csi0phy_timer_clk.c),
3033 },
3034};
3035
3036static struct branch_clk csi1phy_timer_clk = {
3037 .b = {
3038 .ctl_reg = CSIPHYTIMER_CC_REG,
3039 .en_mask = BIT(9),
3040 .halt_reg = DBG_BUS_VEC_I_REG,
3041 .halt_bit = 18,
3042 },
3043 .parent = &csiphy_timer_src_clk.c,
3044 .c = {
3045 .dbg_name = "csi1phy_timer_clk",
3046 .ops = &clk_ops_branch,
3047 CLK_INIT(csi1phy_timer_clk.c),
3048 },
3049};
3050
Stephen Boyd94625ef2011-07-12 17:06:01 -07003051static struct branch_clk csi2phy_timer_clk = {
3052 .b = {
3053 .ctl_reg = CSIPHYTIMER_CC_REG,
3054 .en_mask = BIT(11),
3055 .halt_reg = DBG_BUS_VEC_I_REG,
3056 .halt_bit = 30,
3057 },
3058 .parent = &csiphy_timer_src_clk.c,
3059 .c = {
3060 .dbg_name = "csi2phy_timer_clk",
3061 .ops = &clk_ops_branch,
3062 CLK_INIT(csi2phy_timer_clk.c),
3063 },
3064};
3065
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003066#define F_DSI(d) \
3067 { \
3068 .freq_hz = d, \
3069 .ns_val = BVAL(15, 12, (d-1)), \
3070 }
3071/*
3072 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3073 * without this clock driver knowing. So, overload the clk_set_rate() to set
3074 * the divider (1 to 16) of the clock with respect to the PLL rate.
3075 */
3076static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3077 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3078 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3079 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3080 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3081 F_END
3082};
3083
3084static struct rcg_clk dsi1_byte_clk = {
3085 .b = {
3086 .ctl_reg = DSI1_BYTE_CC_REG,
3087 .en_mask = BIT(0),
3088 .reset_reg = SW_RESET_CORE_REG,
3089 .reset_mask = BIT(7),
3090 .halt_reg = DBG_BUS_VEC_B_REG,
3091 .halt_bit = 21,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003092 .retain_reg = DSI1_BYTE_CC_REG,
3093 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003094 },
3095 .ns_reg = DSI1_BYTE_NS_REG,
3096 .root_en_mask = BIT(2),
3097 .ns_mask = BM(15, 12),
3098 .set_rate = set_rate_nop,
3099 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003100 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003101 .c = {
3102 .dbg_name = "dsi1_byte_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003103 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003104 CLK_INIT(dsi1_byte_clk.c),
3105 },
3106};
3107
3108static struct rcg_clk dsi2_byte_clk = {
3109 .b = {
3110 .ctl_reg = DSI2_BYTE_CC_REG,
3111 .en_mask = BIT(0),
3112 .reset_reg = SW_RESET_CORE_REG,
3113 .reset_mask = BIT(25),
3114 .halt_reg = DBG_BUS_VEC_B_REG,
3115 .halt_bit = 20,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003116 .retain_reg = DSI2_BYTE_CC_REG,
3117 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003118 },
3119 .ns_reg = DSI2_BYTE_NS_REG,
3120 .root_en_mask = BIT(2),
3121 .ns_mask = BM(15, 12),
3122 .set_rate = set_rate_nop,
3123 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003124 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003125 .c = {
3126 .dbg_name = "dsi2_byte_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003127 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003128 CLK_INIT(dsi2_byte_clk.c),
3129 },
3130};
3131
3132static struct rcg_clk dsi1_esc_clk = {
3133 .b = {
3134 .ctl_reg = DSI1_ESC_CC_REG,
3135 .en_mask = BIT(0),
3136 .reset_reg = SW_RESET_CORE_REG,
3137 .halt_reg = DBG_BUS_VEC_I_REG,
3138 .halt_bit = 1,
3139 },
3140 .ns_reg = DSI1_ESC_NS_REG,
3141 .root_en_mask = BIT(2),
3142 .ns_mask = BM(15, 12),
3143 .set_rate = set_rate_nop,
3144 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003145 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003146 .c = {
3147 .dbg_name = "dsi1_esc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003148 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003149 CLK_INIT(dsi1_esc_clk.c),
3150 },
3151};
3152
3153static struct rcg_clk dsi2_esc_clk = {
3154 .b = {
3155 .ctl_reg = DSI2_ESC_CC_REG,
3156 .en_mask = BIT(0),
3157 .halt_reg = DBG_BUS_VEC_I_REG,
3158 .halt_bit = 3,
3159 },
3160 .ns_reg = DSI2_ESC_NS_REG,
3161 .root_en_mask = BIT(2),
3162 .ns_mask = BM(15, 12),
3163 .set_rate = set_rate_nop,
3164 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003165 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003166 .c = {
3167 .dbg_name = "dsi2_esc_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003168 .ops = &clk_ops_rcg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003169 CLK_INIT(dsi2_esc_clk.c),
3170 },
3171};
3172
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003173#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003174 { \
3175 .freq_hz = f, \
3176 .src_clk = &s##_clk.c, \
3177 .md_val = MD4(4, m, 0, n), \
3178 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3179 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003180 }
3181static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003182 F_GFX2D( 0, gnd, 0, 0),
3183 F_GFX2D( 27000000, pxo, 0, 0),
3184 F_GFX2D( 48000000, pll8, 1, 8),
3185 F_GFX2D( 54857000, pll8, 1, 7),
3186 F_GFX2D( 64000000, pll8, 1, 6),
3187 F_GFX2D( 76800000, pll8, 1, 5),
3188 F_GFX2D( 96000000, pll8, 1, 4),
3189 F_GFX2D(128000000, pll8, 1, 3),
3190 F_GFX2D(145455000, pll2, 2, 11),
3191 F_GFX2D(160000000, pll2, 1, 5),
3192 F_GFX2D(177778000, pll2, 2, 9),
3193 F_GFX2D(200000000, pll2, 1, 4),
3194 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003195 F_END
3196};
3197
3198static struct bank_masks bmnd_info_gfx2d0 = {
3199 .bank_sel_mask = BIT(11),
3200 .bank0_mask = {
3201 .md_reg = GFX2D0_MD0_REG,
3202 .ns_mask = BM(23, 20) | BM(5, 3),
3203 .rst_mask = BIT(25),
3204 .mnd_en_mask = BIT(8),
3205 .mode_mask = BM(10, 9),
3206 },
3207 .bank1_mask = {
3208 .md_reg = GFX2D0_MD1_REG,
3209 .ns_mask = BM(19, 16) | BM(2, 0),
3210 .rst_mask = BIT(24),
3211 .mnd_en_mask = BIT(5),
3212 .mode_mask = BM(7, 6),
3213 },
3214};
3215
3216static struct rcg_clk gfx2d0_clk = {
3217 .b = {
3218 .ctl_reg = GFX2D0_CC_REG,
3219 .en_mask = BIT(0),
3220 .reset_reg = SW_RESET_CORE_REG,
3221 .reset_mask = BIT(14),
3222 .halt_reg = DBG_BUS_VEC_A_REG,
3223 .halt_bit = 9,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003224 .retain_reg = GFX2D0_CC_REG,
3225 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003226 },
3227 .ns_reg = GFX2D0_NS_REG,
3228 .root_en_mask = BIT(2),
3229 .set_rate = set_rate_mnd_banked,
3230 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003231 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003232 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003233 .c = {
3234 .dbg_name = "gfx2d0_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003235 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003236 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3237 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003238 CLK_INIT(gfx2d0_clk.c),
3239 },
3240};
3241
3242static struct bank_masks bmnd_info_gfx2d1 = {
3243 .bank_sel_mask = BIT(11),
3244 .bank0_mask = {
3245 .md_reg = GFX2D1_MD0_REG,
3246 .ns_mask = BM(23, 20) | BM(5, 3),
3247 .rst_mask = BIT(25),
3248 .mnd_en_mask = BIT(8),
3249 .mode_mask = BM(10, 9),
3250 },
3251 .bank1_mask = {
3252 .md_reg = GFX2D1_MD1_REG,
3253 .ns_mask = BM(19, 16) | BM(2, 0),
3254 .rst_mask = BIT(24),
3255 .mnd_en_mask = BIT(5),
3256 .mode_mask = BM(7, 6),
3257 },
3258};
3259
3260static struct rcg_clk gfx2d1_clk = {
3261 .b = {
3262 .ctl_reg = GFX2D1_CC_REG,
3263 .en_mask = BIT(0),
3264 .reset_reg = SW_RESET_CORE_REG,
3265 .reset_mask = BIT(13),
3266 .halt_reg = DBG_BUS_VEC_A_REG,
3267 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003268 .retain_reg = GFX2D1_CC_REG,
3269 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003270 },
3271 .ns_reg = GFX2D1_NS_REG,
3272 .root_en_mask = BIT(2),
3273 .set_rate = set_rate_mnd_banked,
3274 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003275 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003276 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003277 .c = {
3278 .dbg_name = "gfx2d1_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003279 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003280 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3281 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003282 CLK_INIT(gfx2d1_clk.c),
3283 },
3284};
3285
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003286#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003287 { \
3288 .freq_hz = f, \
3289 .src_clk = &s##_clk.c, \
3290 .md_val = MD4(4, m, 0, n), \
3291 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3292 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003293 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003294
3295static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003296 F_GFX3D( 0, gnd, 0, 0),
3297 F_GFX3D( 27000000, pxo, 0, 0),
3298 F_GFX3D( 48000000, pll8, 1, 8),
3299 F_GFX3D( 54857000, pll8, 1, 7),
3300 F_GFX3D( 64000000, pll8, 1, 6),
3301 F_GFX3D( 76800000, pll8, 1, 5),
3302 F_GFX3D( 96000000, pll8, 1, 4),
3303 F_GFX3D(128000000, pll8, 1, 3),
3304 F_GFX3D(145455000, pll2, 2, 11),
3305 F_GFX3D(160000000, pll2, 1, 5),
3306 F_GFX3D(177778000, pll2, 2, 9),
3307 F_GFX3D(200000000, pll2, 1, 4),
3308 F_GFX3D(228571000, pll2, 2, 7),
3309 F_GFX3D(266667000, pll2, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003310 F_GFX3D(300000000, pll3, 1, 4),
3311 F_GFX3D(320000000, pll2, 2, 5),
3312 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003313 F_END
3314};
3315
Tianyi Gou41515e22011-09-01 19:37:43 -07003316static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003317 F_GFX3D( 0, gnd, 0, 0),
3318 F_GFX3D( 27000000, pxo, 0, 0),
3319 F_GFX3D( 48000000, pll8, 1, 8),
3320 F_GFX3D( 54857000, pll8, 1, 7),
3321 F_GFX3D( 64000000, pll8, 1, 6),
3322 F_GFX3D( 76800000, pll8, 1, 5),
3323 F_GFX3D( 96000000, pll8, 1, 4),
3324 F_GFX3D(128000000, pll8, 1, 3),
3325 F_GFX3D(145455000, pll2, 2, 11),
3326 F_GFX3D(160000000, pll2, 1, 5),
3327 F_GFX3D(177778000, pll2, 2, 9),
3328 F_GFX3D(200000000, pll2, 1, 4),
3329 F_GFX3D(228571000, pll2, 2, 7),
3330 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003331 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003332 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003333 F_END
3334};
3335
Tianyi Goue3d4f542012-03-15 17:06:45 -07003336static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = {
3337 F_GFX3D( 0, gnd, 0, 0),
3338 F_GFX3D( 27000000, pxo, 0, 0),
3339 F_GFX3D( 48000000, pll8, 1, 8),
3340 F_GFX3D( 54857000, pll8, 1, 7),
3341 F_GFX3D( 64000000, pll8, 1, 6),
3342 F_GFX3D( 76800000, pll8, 1, 5),
3343 F_GFX3D( 96000000, pll8, 1, 4),
3344 F_GFX3D(128000000, pll8, 1, 3),
3345 F_GFX3D(145455000, pll2, 2, 11),
3346 F_GFX3D(160000000, pll2, 1, 5),
3347 F_GFX3D(177778000, pll2, 2, 9),
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003348 F_GFX3D(192000000, pll8, 1, 2),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003349 F_GFX3D(200000000, pll2, 1, 4),
3350 F_GFX3D(228571000, pll2, 2, 7),
3351 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003352 F_GFX3D(320000000, pll2, 2, 5),
3353 F_GFX3D(400000000, pll2, 1, 2),
3354 F_GFX3D(450000000, pll15, 1, 2),
3355 F_END
3356};
3357
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003358static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3359 [VDD_DIG_LOW] = 128000000,
3360 [VDD_DIG_NOMINAL] = 325000000,
3361 [VDD_DIG_HIGH] = 400000000
3362};
3363
Tianyi Goue3d4f542012-03-15 17:06:45 -07003364static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = {
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003365 [VDD_DIG_LOW] = 192000000,
Tianyi Goue3d4f542012-03-15 17:06:45 -07003366 [VDD_DIG_NOMINAL] = 320000000,
3367 [VDD_DIG_HIGH] = 450000000
3368};
3369
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003370static struct bank_masks bmnd_info_gfx3d = {
3371 .bank_sel_mask = BIT(11),
3372 .bank0_mask = {
3373 .md_reg = GFX3D_MD0_REG,
3374 .ns_mask = BM(21, 18) | BM(5, 3),
3375 .rst_mask = BIT(23),
3376 .mnd_en_mask = BIT(8),
3377 .mode_mask = BM(10, 9),
3378 },
3379 .bank1_mask = {
3380 .md_reg = GFX3D_MD1_REG,
3381 .ns_mask = BM(17, 14) | BM(2, 0),
3382 .rst_mask = BIT(22),
3383 .mnd_en_mask = BIT(5),
3384 .mode_mask = BM(7, 6),
3385 },
3386};
3387
3388static struct rcg_clk gfx3d_clk = {
3389 .b = {
3390 .ctl_reg = GFX3D_CC_REG,
3391 .en_mask = BIT(0),
3392 .reset_reg = SW_RESET_CORE_REG,
3393 .reset_mask = BIT(12),
3394 .halt_reg = DBG_BUS_VEC_A_REG,
3395 .halt_bit = 4,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003396 .retain_reg = GFX3D_CC_REG,
3397 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003398 },
3399 .ns_reg = GFX3D_NS_REG,
3400 .root_en_mask = BIT(2),
3401 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003402 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003403 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003404 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003405 .c = {
3406 .dbg_name = "gfx3d_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003407 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003408 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
3409 HIGH, 400000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003410 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003411 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003412 },
3413};
3414
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003415#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003416 { \
3417 .freq_hz = f, \
3418 .src_clk = &s##_clk.c, \
3419 .md_val = MD4(4, m, 0, n), \
3420 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3421 .ctl_val = CC_BANKED(9, 6, n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003422 }
3423
3424static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003425 F_VCAP( 0, gnd, 0, 0),
3426 F_VCAP( 27000000, pxo, 0, 0),
3427 F_VCAP( 54860000, pll8, 1, 7),
3428 F_VCAP( 64000000, pll8, 1, 6),
3429 F_VCAP( 76800000, pll8, 1, 5),
3430 F_VCAP(128000000, pll8, 1, 3),
3431 F_VCAP(160000000, pll2, 1, 5),
3432 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003433 F_END
3434};
3435
3436static struct bank_masks bmnd_info_vcap = {
3437 .bank_sel_mask = BIT(11),
3438 .bank0_mask = {
3439 .md_reg = VCAP_MD0_REG,
3440 .ns_mask = BM(21, 18) | BM(5, 3),
3441 .rst_mask = BIT(23),
3442 .mnd_en_mask = BIT(8),
3443 .mode_mask = BM(10, 9),
3444 },
3445 .bank1_mask = {
3446 .md_reg = VCAP_MD1_REG,
3447 .ns_mask = BM(17, 14) | BM(2, 0),
3448 .rst_mask = BIT(22),
3449 .mnd_en_mask = BIT(5),
3450 .mode_mask = BM(7, 6),
3451 },
3452};
3453
3454static struct rcg_clk vcap_clk = {
3455 .b = {
3456 .ctl_reg = VCAP_CC_REG,
3457 .en_mask = BIT(0),
3458 .halt_reg = DBG_BUS_VEC_J_REG,
3459 .halt_bit = 15,
3460 },
3461 .ns_reg = VCAP_NS_REG,
3462 .root_en_mask = BIT(2),
3463 .set_rate = set_rate_mnd_banked,
3464 .freq_tbl = clk_tbl_vcap,
3465 .bank_info = &bmnd_info_vcap,
3466 .current_freq = &rcg_dummy_freq,
3467 .c = {
3468 .dbg_name = "vcap_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003469 .ops = &clk_ops_rcg,
Tianyi Gou621f8742011-09-01 21:45:01 -07003470 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003471 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003472 CLK_INIT(vcap_clk.c),
3473 },
3474};
3475
3476static struct branch_clk vcap_npl_clk = {
3477 .b = {
3478 .ctl_reg = VCAP_CC_REG,
3479 .en_mask = BIT(13),
3480 .halt_reg = DBG_BUS_VEC_J_REG,
3481 .halt_bit = 25,
3482 },
3483 .parent = &vcap_clk.c,
3484 .c = {
3485 .dbg_name = "vcap_npl_clk",
3486 .ops = &clk_ops_branch,
3487 CLK_INIT(vcap_npl_clk.c),
3488 },
3489};
3490
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003491#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003492 { \
3493 .freq_hz = f, \
3494 .src_clk = &s##_clk.c, \
3495 .md_val = MD8(8, m, 0, n), \
3496 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3497 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003498 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003499
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003500static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3501 F_IJPEG( 0, gnd, 1, 0, 0),
3502 F_IJPEG( 27000000, pxo, 1, 0, 0),
3503 F_IJPEG( 36570000, pll8, 1, 2, 21),
3504 F_IJPEG( 54860000, pll8, 7, 0, 0),
3505 F_IJPEG( 96000000, pll8, 4, 0, 0),
3506 F_IJPEG(109710000, pll8, 1, 2, 7),
3507 F_IJPEG(128000000, pll8, 3, 0, 0),
3508 F_IJPEG(153600000, pll8, 1, 2, 5),
3509 F_IJPEG(200000000, pll2, 4, 0, 0),
3510 F_IJPEG(228571000, pll2, 1, 2, 7),
3511 F_IJPEG(266667000, pll2, 1, 1, 3),
3512 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003513 F_END
3514};
3515
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003516static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3517 [VDD_DIG_LOW] = 128000000,
3518 [VDD_DIG_NOMINAL] = 266667000,
3519 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003520};
3521
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003522static struct rcg_clk ijpeg_clk = {
3523 .b = {
3524 .ctl_reg = IJPEG_CC_REG,
3525 .en_mask = BIT(0),
3526 .reset_reg = SW_RESET_CORE_REG,
3527 .reset_mask = BIT(9),
3528 .halt_reg = DBG_BUS_VEC_A_REG,
3529 .halt_bit = 24,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003530 .retain_reg = IJPEG_CC_REG,
3531 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003532 },
3533 .ns_reg = IJPEG_NS_REG,
3534 .md_reg = IJPEG_MD_REG,
3535 .root_en_mask = BIT(2),
3536 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003537 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003538 .ctl_mask = BM(7, 6),
3539 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003540 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003541 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003542 .c = {
3543 .dbg_name = "ijpeg_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003544 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003545 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
3546 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003547 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003548 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003549 },
3550};
3551
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003552#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003553 { \
3554 .freq_hz = f, \
3555 .src_clk = &s##_clk.c, \
3556 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003557 }
3558static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003559 F_JPEGD( 0, gnd, 1),
3560 F_JPEGD( 64000000, pll8, 6),
3561 F_JPEGD( 76800000, pll8, 5),
3562 F_JPEGD( 96000000, pll8, 4),
3563 F_JPEGD(160000000, pll2, 5),
3564 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003565 F_END
3566};
3567
3568static struct rcg_clk jpegd_clk = {
3569 .b = {
3570 .ctl_reg = JPEGD_CC_REG,
3571 .en_mask = BIT(0),
3572 .reset_reg = SW_RESET_CORE_REG,
3573 .reset_mask = BIT(19),
3574 .halt_reg = DBG_BUS_VEC_A_REG,
3575 .halt_bit = 19,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003576 .retain_reg = JPEGD_CC_REG,
3577 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003578 },
3579 .ns_reg = JPEGD_NS_REG,
3580 .root_en_mask = BIT(2),
3581 .ns_mask = (BM(15, 12) | BM(2, 0)),
3582 .set_rate = set_rate_nop,
3583 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003584 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003585 .c = {
3586 .dbg_name = "jpegd_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003587 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003588 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003589 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003590 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003591 },
3592};
3593
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003594#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003595 { \
3596 .freq_hz = f, \
3597 .src_clk = &s##_clk.c, \
3598 .md_val = MD8(8, m, 0, n), \
3599 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3600 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003601 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003602static struct clk_freq_tbl clk_tbl_mdp[] = {
3603 F_MDP( 0, gnd, 0, 0),
3604 F_MDP( 9600000, pll8, 1, 40),
3605 F_MDP( 13710000, pll8, 1, 28),
3606 F_MDP( 27000000, pxo, 0, 0),
3607 F_MDP( 29540000, pll8, 1, 13),
3608 F_MDP( 34910000, pll8, 1, 11),
3609 F_MDP( 38400000, pll8, 1, 10),
3610 F_MDP( 59080000, pll8, 2, 13),
3611 F_MDP( 76800000, pll8, 1, 5),
3612 F_MDP( 85330000, pll8, 2, 9),
3613 F_MDP( 96000000, pll8, 1, 4),
3614 F_MDP(128000000, pll8, 1, 3),
3615 F_MDP(160000000, pll2, 1, 5),
3616 F_MDP(177780000, pll2, 2, 9),
3617 F_MDP(200000000, pll2, 1, 4),
3618 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003619 F_END
3620};
3621
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003622static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3623 [VDD_DIG_LOW] = 128000000,
3624 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003625};
3626
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003627static struct bank_masks bmnd_info_mdp = {
3628 .bank_sel_mask = BIT(11),
3629 .bank0_mask = {
3630 .md_reg = MDP_MD0_REG,
3631 .ns_mask = BM(29, 22) | BM(5, 3),
3632 .rst_mask = BIT(31),
3633 .mnd_en_mask = BIT(8),
3634 .mode_mask = BM(10, 9),
3635 },
3636 .bank1_mask = {
3637 .md_reg = MDP_MD1_REG,
3638 .ns_mask = BM(21, 14) | BM(2, 0),
3639 .rst_mask = BIT(30),
3640 .mnd_en_mask = BIT(5),
3641 .mode_mask = BM(7, 6),
3642 },
3643};
3644
3645static struct rcg_clk mdp_clk = {
3646 .b = {
3647 .ctl_reg = MDP_CC_REG,
3648 .en_mask = BIT(0),
3649 .reset_reg = SW_RESET_CORE_REG,
3650 .reset_mask = BIT(21),
3651 .halt_reg = DBG_BUS_VEC_C_REG,
3652 .halt_bit = 10,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003653 .retain_reg = MDP_CC_REG,
3654 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003655 },
3656 .ns_reg = MDP_NS_REG,
3657 .root_en_mask = BIT(2),
3658 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003659 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003660 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003661 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003662 .c = {
3663 .dbg_name = "mdp_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003664 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003665 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003666 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003667 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003668 },
3669};
3670
3671static struct branch_clk lut_mdp_clk = {
3672 .b = {
3673 .ctl_reg = MDP_LUT_CC_REG,
3674 .en_mask = BIT(0),
3675 .halt_reg = DBG_BUS_VEC_I_REG,
3676 .halt_bit = 13,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003677 .retain_reg = MDP_LUT_CC_REG,
3678 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003679 },
3680 .parent = &mdp_clk.c,
3681 .c = {
3682 .dbg_name = "lut_mdp_clk",
3683 .ops = &clk_ops_branch,
3684 CLK_INIT(lut_mdp_clk.c),
3685 },
3686};
3687
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003688#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003689 { \
3690 .freq_hz = f, \
3691 .src_clk = &s##_clk.c, \
3692 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003693 }
3694static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003695 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003696 F_END
3697};
3698
3699static struct rcg_clk mdp_vsync_clk = {
3700 .b = {
3701 .ctl_reg = MISC_CC_REG,
3702 .en_mask = BIT(6),
3703 .reset_reg = SW_RESET_CORE_REG,
3704 .reset_mask = BIT(3),
3705 .halt_reg = DBG_BUS_VEC_B_REG,
3706 .halt_bit = 22,
3707 },
3708 .ns_reg = MISC_CC2_REG,
3709 .ns_mask = BIT(13),
3710 .set_rate = set_rate_nop,
3711 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003712 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003713 .c = {
3714 .dbg_name = "mdp_vsync_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003715 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003716 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003717 CLK_INIT(mdp_vsync_clk.c),
3718 },
3719};
3720
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003721#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003722 { \
3723 .freq_hz = f, \
3724 .src_clk = &s##_clk.c, \
3725 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3726 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003727 }
3728static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003729 F_ROT( 0, gnd, 1),
3730 F_ROT( 27000000, pxo, 1),
3731 F_ROT( 29540000, pll8, 13),
3732 F_ROT( 32000000, pll8, 12),
3733 F_ROT( 38400000, pll8, 10),
3734 F_ROT( 48000000, pll8, 8),
3735 F_ROT( 54860000, pll8, 7),
3736 F_ROT( 64000000, pll8, 6),
3737 F_ROT( 76800000, pll8, 5),
3738 F_ROT( 96000000, pll8, 4),
3739 F_ROT(100000000, pll2, 8),
3740 F_ROT(114290000, pll2, 7),
3741 F_ROT(133330000, pll2, 6),
3742 F_ROT(160000000, pll2, 5),
3743 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003744 F_END
3745};
3746
3747static struct bank_masks bdiv_info_rot = {
3748 .bank_sel_mask = BIT(30),
3749 .bank0_mask = {
3750 .ns_mask = BM(25, 22) | BM(18, 16),
3751 },
3752 .bank1_mask = {
3753 .ns_mask = BM(29, 26) | BM(21, 19),
3754 },
3755};
3756
3757static struct rcg_clk rot_clk = {
3758 .b = {
3759 .ctl_reg = ROT_CC_REG,
3760 .en_mask = BIT(0),
3761 .reset_reg = SW_RESET_CORE_REG,
3762 .reset_mask = BIT(2),
3763 .halt_reg = DBG_BUS_VEC_C_REG,
3764 .halt_bit = 15,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003765 .retain_reg = ROT_CC_REG,
3766 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003767 },
3768 .ns_reg = ROT_NS_REG,
3769 .root_en_mask = BIT(2),
3770 .set_rate = set_rate_div_banked,
3771 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003772 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003773 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003774 .c = {
3775 .dbg_name = "rot_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003776 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003777 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003778 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003779 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003780 },
3781};
3782
3783static int hdmi_pll_clk_enable(struct clk *clk)
3784{
3785 int ret;
3786 unsigned long flags;
3787 spin_lock_irqsave(&local_clock_reg_lock, flags);
3788 ret = hdmi_pll_enable();
3789 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3790 return ret;
3791}
3792
3793static void hdmi_pll_clk_disable(struct clk *clk)
3794{
3795 unsigned long flags;
3796 spin_lock_irqsave(&local_clock_reg_lock, flags);
3797 hdmi_pll_disable();
3798 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3799}
3800
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003801static unsigned long hdmi_pll_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003802{
3803 return hdmi_pll_get_rate();
3804}
3805
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003806static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3807{
3808 return &pxo_clk.c;
3809}
3810
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003811static struct clk_ops clk_ops_hdmi_pll = {
3812 .enable = hdmi_pll_clk_enable,
3813 .disable = hdmi_pll_clk_disable,
3814 .get_rate = hdmi_pll_clk_get_rate,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003815 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003816};
3817
3818static struct clk hdmi_pll_clk = {
3819 .dbg_name = "hdmi_pll_clk",
3820 .ops = &clk_ops_hdmi_pll,
3821 CLK_INIT(hdmi_pll_clk),
3822};
3823
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003824#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003825 { \
3826 .freq_hz = f, \
3827 .src_clk = &s##_clk.c, \
3828 .md_val = MD8(8, m, 0, n), \
3829 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3830 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003831 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003832#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003833 { \
3834 .freq_hz = f, \
3835 .src_clk = &s##_clk, \
3836 .md_val = MD8(8, m, 0, n), \
3837 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3838 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003839 .extra_freq_data = (void *)p_r, \
3840 }
3841/* Switching TV freqs requires PLL reconfiguration. */
3842static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003843 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3844 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3845 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3846 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3847 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3848 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003849 F_END
3850};
3851
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003852static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
3853 [VDD_DIG_LOW] = 74250000,
3854 [VDD_DIG_NOMINAL] = 149000000
3855};
3856
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003857/*
3858 * Unlike other clocks, the TV rate is adjusted through PLL
3859 * re-programming. It is also routed through an MND divider.
3860 */
3861void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3862{
3863 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3864 if (pll_rate)
3865 hdmi_pll_set_rate(pll_rate);
3866 set_rate_mnd(clk, nf);
3867}
3868
3869static struct rcg_clk tv_src_clk = {
3870 .ns_reg = TV_NS_REG,
3871 .b = {
3872 .ctl_reg = TV_CC_REG,
3873 .halt_check = NOCHECK,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003874 .retain_reg = TV_CC_REG,
3875 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003876 },
3877 .md_reg = TV_MD_REG,
3878 .root_en_mask = BIT(2),
3879 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003880 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003881 .ctl_mask = BM(7, 6),
3882 .set_rate = set_rate_tv,
3883 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003884 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003885 .c = {
3886 .dbg_name = "tv_src_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07003887 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003888 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003889 CLK_INIT(tv_src_clk.c),
3890 },
3891};
3892
Tianyi Gou51918802012-01-26 14:05:43 -08003893static struct cdiv_clk tv_src_div_clk = {
3894 .b = {
3895 .ctl_reg = TV_NS_REG,
3896 .halt_check = NOCHECK,
3897 },
3898 .ns_reg = TV_NS_REG,
3899 .div_offset = 6,
3900 .max_div = 2,
3901 .c = {
3902 .dbg_name = "tv_src_div_clk",
3903 .ops = &clk_ops_cdiv,
3904 CLK_INIT(tv_src_div_clk.c),
3905 },
3906};
3907
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003908static struct branch_clk tv_enc_clk = {
3909 .b = {
3910 .ctl_reg = TV_CC_REG,
3911 .en_mask = BIT(8),
3912 .reset_reg = SW_RESET_CORE_REG,
3913 .reset_mask = BIT(0),
3914 .halt_reg = DBG_BUS_VEC_D_REG,
3915 .halt_bit = 9,
3916 },
3917 .parent = &tv_src_clk.c,
3918 .c = {
3919 .dbg_name = "tv_enc_clk",
3920 .ops = &clk_ops_branch,
3921 CLK_INIT(tv_enc_clk.c),
3922 },
3923};
3924
3925static struct branch_clk tv_dac_clk = {
3926 .b = {
3927 .ctl_reg = TV_CC_REG,
3928 .en_mask = BIT(10),
3929 .halt_reg = DBG_BUS_VEC_D_REG,
3930 .halt_bit = 10,
3931 },
3932 .parent = &tv_src_clk.c,
3933 .c = {
3934 .dbg_name = "tv_dac_clk",
3935 .ops = &clk_ops_branch,
3936 CLK_INIT(tv_dac_clk.c),
3937 },
3938};
3939
3940static struct branch_clk mdp_tv_clk = {
3941 .b = {
3942 .ctl_reg = TV_CC_REG,
3943 .en_mask = BIT(0),
3944 .reset_reg = SW_RESET_CORE_REG,
3945 .reset_mask = BIT(4),
3946 .halt_reg = DBG_BUS_VEC_D_REG,
3947 .halt_bit = 12,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003948 .retain_reg = TV_CC2_REG,
3949 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003950 },
3951 .parent = &tv_src_clk.c,
3952 .c = {
3953 .dbg_name = "mdp_tv_clk",
3954 .ops = &clk_ops_branch,
3955 CLK_INIT(mdp_tv_clk.c),
3956 },
3957};
3958
3959static struct branch_clk hdmi_tv_clk = {
3960 .b = {
3961 .ctl_reg = TV_CC_REG,
3962 .en_mask = BIT(12),
3963 .reset_reg = SW_RESET_CORE_REG,
3964 .reset_mask = BIT(1),
3965 .halt_reg = DBG_BUS_VEC_D_REG,
3966 .halt_bit = 11,
3967 },
3968 .parent = &tv_src_clk.c,
3969 .c = {
3970 .dbg_name = "hdmi_tv_clk",
3971 .ops = &clk_ops_branch,
3972 CLK_INIT(hdmi_tv_clk.c),
3973 },
3974};
3975
Tianyi Gou51918802012-01-26 14:05:43 -08003976static struct branch_clk rgb_tv_clk = {
3977 .b = {
3978 .ctl_reg = TV_CC2_REG,
3979 .en_mask = BIT(14),
3980 .halt_reg = DBG_BUS_VEC_J_REG,
3981 .halt_bit = 27,
3982 },
3983 .parent = &tv_src_clk.c,
3984 .c = {
3985 .dbg_name = "rgb_tv_clk",
3986 .ops = &clk_ops_branch,
3987 CLK_INIT(rgb_tv_clk.c),
3988 },
3989};
3990
3991static struct branch_clk npl_tv_clk = {
3992 .b = {
3993 .ctl_reg = TV_CC2_REG,
3994 .en_mask = BIT(16),
3995 .halt_reg = DBG_BUS_VEC_J_REG,
3996 .halt_bit = 26,
3997 },
3998 .parent = &tv_src_clk.c,
3999 .c = {
4000 .dbg_name = "npl_tv_clk",
4001 .ops = &clk_ops_branch,
4002 CLK_INIT(npl_tv_clk.c),
4003 },
4004};
4005
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004006static struct branch_clk hdmi_app_clk = {
4007 .b = {
4008 .ctl_reg = MISC_CC2_REG,
4009 .en_mask = BIT(11),
4010 .reset_reg = SW_RESET_CORE_REG,
4011 .reset_mask = BIT(11),
4012 .halt_reg = DBG_BUS_VEC_B_REG,
4013 .halt_bit = 25,
4014 },
4015 .c = {
4016 .dbg_name = "hdmi_app_clk",
4017 .ops = &clk_ops_branch,
4018 CLK_INIT(hdmi_app_clk.c),
4019 },
4020};
4021
4022static struct bank_masks bmnd_info_vcodec = {
4023 .bank_sel_mask = BIT(13),
4024 .bank0_mask = {
4025 .md_reg = VCODEC_MD0_REG,
4026 .ns_mask = BM(18, 11) | BM(2, 0),
4027 .rst_mask = BIT(31),
4028 .mnd_en_mask = BIT(5),
4029 .mode_mask = BM(7, 6),
4030 },
4031 .bank1_mask = {
4032 .md_reg = VCODEC_MD1_REG,
4033 .ns_mask = BM(26, 19) | BM(29, 27),
4034 .rst_mask = BIT(30),
4035 .mnd_en_mask = BIT(10),
4036 .mode_mask = BM(12, 11),
4037 },
4038};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004039#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004040 { \
4041 .freq_hz = f, \
4042 .src_clk = &s##_clk.c, \
4043 .md_val = MD8(8, m, 0, n), \
4044 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4045 .ctl_val = CC_BANKED(6, 11, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004046 }
4047static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004048 F_VCODEC( 0, gnd, 0, 0),
4049 F_VCODEC( 27000000, pxo, 0, 0),
4050 F_VCODEC( 32000000, pll8, 1, 12),
4051 F_VCODEC( 48000000, pll8, 1, 8),
4052 F_VCODEC( 54860000, pll8, 1, 7),
4053 F_VCODEC( 96000000, pll8, 1, 4),
4054 F_VCODEC(133330000, pll2, 1, 6),
4055 F_VCODEC(200000000, pll2, 1, 4),
4056 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004057 F_END
4058};
4059
4060static struct rcg_clk vcodec_clk = {
4061 .b = {
4062 .ctl_reg = VCODEC_CC_REG,
4063 .en_mask = BIT(0),
4064 .reset_reg = SW_RESET_CORE_REG,
4065 .reset_mask = BIT(6),
4066 .halt_reg = DBG_BUS_VEC_C_REG,
4067 .halt_bit = 29,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004068 .retain_reg = VCODEC_CC_REG,
4069 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004070 },
4071 .ns_reg = VCODEC_NS_REG,
4072 .root_en_mask = BIT(2),
4073 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004074 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004075 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004076 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004077 .c = {
4078 .dbg_name = "vcodec_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004079 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004080 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4081 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004082 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004083 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004084 },
4085};
4086
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004087#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004088 { \
4089 .freq_hz = f, \
4090 .src_clk = &s##_clk.c, \
4091 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004092 }
4093static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004094 F_VPE( 0, gnd, 1),
4095 F_VPE( 27000000, pxo, 1),
4096 F_VPE( 34909000, pll8, 11),
4097 F_VPE( 38400000, pll8, 10),
4098 F_VPE( 64000000, pll8, 6),
4099 F_VPE( 76800000, pll8, 5),
4100 F_VPE( 96000000, pll8, 4),
4101 F_VPE(100000000, pll2, 8),
4102 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004103 F_END
4104};
4105
4106static struct rcg_clk vpe_clk = {
4107 .b = {
4108 .ctl_reg = VPE_CC_REG,
4109 .en_mask = BIT(0),
4110 .reset_reg = SW_RESET_CORE_REG,
4111 .reset_mask = BIT(17),
4112 .halt_reg = DBG_BUS_VEC_A_REG,
4113 .halt_bit = 28,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004114 .retain_reg = VPE_CC_REG,
4115 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004116 },
4117 .ns_reg = VPE_NS_REG,
4118 .root_en_mask = BIT(2),
4119 .ns_mask = (BM(15, 12) | BM(2, 0)),
4120 .set_rate = set_rate_nop,
4121 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004122 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004123 .c = {
4124 .dbg_name = "vpe_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004125 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004126 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004127 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004128 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004129 },
4130};
4131
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004132#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004133 { \
4134 .freq_hz = f, \
4135 .src_clk = &s##_clk.c, \
4136 .md_val = MD8(8, m, 0, n), \
4137 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4138 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004139 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004140
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004141static struct clk_freq_tbl clk_tbl_vfe[] = {
4142 F_VFE( 0, gnd, 1, 0, 0),
4143 F_VFE( 13960000, pll8, 1, 2, 55),
4144 F_VFE( 27000000, pxo, 1, 0, 0),
4145 F_VFE( 36570000, pll8, 1, 2, 21),
4146 F_VFE( 38400000, pll8, 2, 1, 5),
4147 F_VFE( 45180000, pll8, 1, 2, 17),
4148 F_VFE( 48000000, pll8, 2, 1, 4),
4149 F_VFE( 54860000, pll8, 1, 1, 7),
4150 F_VFE( 64000000, pll8, 2, 1, 3),
4151 F_VFE( 76800000, pll8, 1, 1, 5),
4152 F_VFE( 96000000, pll8, 2, 1, 2),
4153 F_VFE(109710000, pll8, 1, 2, 7),
4154 F_VFE(128000000, pll8, 1, 1, 3),
4155 F_VFE(153600000, pll8, 1, 2, 5),
4156 F_VFE(200000000, pll2, 2, 1, 2),
4157 F_VFE(228570000, pll2, 1, 2, 7),
4158 F_VFE(266667000, pll2, 1, 1, 3),
4159 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004160 F_END
4161};
4162
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004163static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4164 [VDD_DIG_LOW] = 128000000,
4165 [VDD_DIG_NOMINAL] = 266667000,
4166 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004167};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004168
4169static struct rcg_clk vfe_clk = {
4170 .b = {
4171 .ctl_reg = VFE_CC_REG,
4172 .reset_reg = SW_RESET_CORE_REG,
4173 .reset_mask = BIT(15),
4174 .halt_reg = DBG_BUS_VEC_B_REG,
4175 .halt_bit = 6,
4176 .en_mask = BIT(0),
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004177 .retain_reg = VFE_CC2_REG,
4178 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004179 },
4180 .ns_reg = VFE_NS_REG,
4181 .md_reg = VFE_MD_REG,
4182 .root_en_mask = BIT(2),
4183 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004184 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004185 .ctl_mask = BM(7, 6),
4186 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004187 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004188 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004189 .c = {
4190 .dbg_name = "vfe_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004191 .ops = &clk_ops_rcg,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08004192 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
4193 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004194 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004195 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004196 },
4197};
4198
Matt Wagantallc23eee92011-08-16 23:06:52 -07004199static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004200 .b = {
4201 .ctl_reg = VFE_CC_REG,
4202 .en_mask = BIT(12),
4203 .reset_reg = SW_RESET_CORE_REG,
4204 .reset_mask = BIT(24),
4205 .halt_reg = DBG_BUS_VEC_B_REG,
4206 .halt_bit = 8,
4207 },
4208 .parent = &vfe_clk.c,
4209 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004210 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004211 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004212 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004213 },
4214};
4215
4216/*
4217 * Low Power Audio Clocks
4218 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004219#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004220 { \
4221 .freq_hz = f, \
4222 .src_clk = &s##_clk.c, \
4223 .md_val = MD8(8, m, 0, n), \
4224 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004225 }
4226static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004227 F_AIF_OSR( 0, gnd, 1, 0, 0),
4228 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4229 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4230 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4231 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4232 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4233 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4234 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4235 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4236 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4237 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4238 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004239 F_END
4240};
4241
4242#define CLK_AIF_OSR(i, ns, md, h_r) \
4243 struct rcg_clk i##_clk = { \
4244 .b = { \
4245 .ctl_reg = ns, \
4246 .en_mask = BIT(17), \
4247 .reset_reg = ns, \
4248 .reset_mask = BIT(19), \
4249 .halt_reg = h_r, \
4250 .halt_check = ENABLE, \
4251 .halt_bit = 1, \
4252 }, \
4253 .ns_reg = ns, \
4254 .md_reg = md, \
4255 .root_en_mask = BIT(9), \
4256 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004257 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004258 .set_rate = set_rate_mnd, \
4259 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004260 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004261 .c = { \
4262 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07004263 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004264 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004265 CLK_INIT(i##_clk.c), \
4266 }, \
4267 }
4268#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4269 struct rcg_clk i##_clk = { \
4270 .b = { \
4271 .ctl_reg = ns, \
4272 .en_mask = BIT(21), \
4273 .reset_reg = ns, \
4274 .reset_mask = BIT(23), \
4275 .halt_reg = h_r, \
4276 .halt_check = ENABLE, \
4277 .halt_bit = 1, \
4278 }, \
4279 .ns_reg = ns, \
4280 .md_reg = md, \
4281 .root_en_mask = BIT(9), \
4282 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004283 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004284 .set_rate = set_rate_mnd, \
4285 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004286 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004287 .c = { \
4288 .dbg_name = #i "_clk", \
Stephen Boyd409b8b42012-04-10 12:12:56 -07004289 .ops = &clk_ops_rcg, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004290 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004291 CLK_INIT(i##_clk.c), \
4292 }, \
4293 }
4294
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004295#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004296 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004297 .b = { \
4298 .ctl_reg = ns, \
4299 .en_mask = BIT(15), \
4300 .halt_reg = h_r, \
4301 .halt_check = DELAY, \
4302 }, \
4303 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004304 .ext_mask = BIT(14), \
4305 .div_offset = 10, \
4306 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004307 .c = { \
4308 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004309 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004310 CLK_INIT(i##_clk.c), \
4311 }, \
4312 }
4313
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004314#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004315 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004316 .b = { \
4317 .ctl_reg = ns, \
4318 .en_mask = BIT(19), \
4319 .halt_reg = h_r, \
Stephen Boyd7bb9cf82012-01-25 18:09:01 -08004320 .halt_check = DELAY, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004321 }, \
4322 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004323 .ext_mask = BIT(18), \
4324 .div_offset = 10, \
4325 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004326 .c = { \
4327 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004328 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004329 CLK_INIT(i##_clk.c), \
4330 }, \
4331 }
4332
4333static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4334 LCC_MI2S_STATUS_REG);
4335static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4336
4337static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4338 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4339static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4340 LCC_CODEC_I2S_MIC_STATUS_REG);
4341
4342static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4343 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4344static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4345 LCC_SPARE_I2S_MIC_STATUS_REG);
4346
4347static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4348 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4349static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4350 LCC_CODEC_I2S_SPKR_STATUS_REG);
4351
4352static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4353 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4354static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4355 LCC_SPARE_I2S_SPKR_STATUS_REG);
4356
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004357#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004358 { \
4359 .freq_hz = f, \
4360 .src_clk = &s##_clk.c, \
4361 .md_val = MD16(m, n), \
4362 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004363 }
4364static struct clk_freq_tbl clk_tbl_pcm[] = {
Stephen Boyd630f3252012-01-31 00:10:08 -08004365 { .ns_val = BIT(10) /* external input */ },
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004366 F_PCM( 512000, pll4, 4, 1, 192),
4367 F_PCM( 768000, pll4, 4, 1, 128),
4368 F_PCM( 1024000, pll4, 4, 1, 96),
4369 F_PCM( 1536000, pll4, 4, 1, 64),
4370 F_PCM( 2048000, pll4, 4, 1, 48),
4371 F_PCM( 3072000, pll4, 4, 1, 32),
4372 F_PCM( 4096000, pll4, 4, 1, 24),
4373 F_PCM( 6144000, pll4, 4, 1, 16),
4374 F_PCM( 8192000, pll4, 4, 1, 12),
4375 F_PCM(12288000, pll4, 4, 1, 8),
4376 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004377 F_END
4378};
4379
4380static struct rcg_clk pcm_clk = {
4381 .b = {
4382 .ctl_reg = LCC_PCM_NS_REG,
4383 .en_mask = BIT(11),
4384 .reset_reg = LCC_PCM_NS_REG,
4385 .reset_mask = BIT(13),
4386 .halt_reg = LCC_PCM_STATUS_REG,
4387 .halt_check = ENABLE,
4388 .halt_bit = 0,
4389 },
4390 .ns_reg = LCC_PCM_NS_REG,
4391 .md_reg = LCC_PCM_MD_REG,
4392 .root_en_mask = BIT(9),
Stephen Boyd630f3252012-01-31 00:10:08 -08004393 .ns_mask = BM(31, 16) | BIT(10) | BM(6, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08004394 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004395 .set_rate = set_rate_mnd,
4396 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004397 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004398 .c = {
4399 .dbg_name = "pcm_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004400 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004401 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004402 CLK_INIT(pcm_clk.c),
4403 },
4404};
4405
4406static struct rcg_clk audio_slimbus_clk = {
4407 .b = {
4408 .ctl_reg = LCC_SLIMBUS_NS_REG,
4409 .en_mask = BIT(10),
4410 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4411 .reset_mask = BIT(5),
4412 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4413 .halt_check = ENABLE,
4414 .halt_bit = 0,
4415 },
4416 .ns_reg = LCC_SLIMBUS_NS_REG,
4417 .md_reg = LCC_SLIMBUS_MD_REG,
4418 .root_en_mask = BIT(9),
4419 .ns_mask = (BM(31, 24) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004420 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004421 .set_rate = set_rate_mnd,
4422 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004423 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004424 .c = {
4425 .dbg_name = "audio_slimbus_clk",
Stephen Boyd409b8b42012-04-10 12:12:56 -07004426 .ops = &clk_ops_rcg,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004427 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004428 CLK_INIT(audio_slimbus_clk.c),
4429 },
4430};
4431
4432static struct branch_clk sps_slimbus_clk = {
4433 .b = {
4434 .ctl_reg = LCC_SLIMBUS_NS_REG,
4435 .en_mask = BIT(12),
4436 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4437 .halt_check = ENABLE,
4438 .halt_bit = 1,
4439 },
4440 .parent = &audio_slimbus_clk.c,
4441 .c = {
4442 .dbg_name = "sps_slimbus_clk",
4443 .ops = &clk_ops_branch,
4444 CLK_INIT(sps_slimbus_clk.c),
4445 },
4446};
4447
4448static struct branch_clk slimbus_xo_src_clk = {
4449 .b = {
4450 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4451 .en_mask = BIT(2),
4452 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004453 .halt_bit = 28,
4454 },
4455 .parent = &sps_slimbus_clk.c,
4456 .c = {
4457 .dbg_name = "slimbus_xo_src_clk",
4458 .ops = &clk_ops_branch,
4459 CLK_INIT(slimbus_xo_src_clk.c),
4460 },
4461};
4462
Matt Wagantall735f01a2011-08-12 12:40:28 -07004463DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4464DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4465DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4466DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4467DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4468DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4469DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4470DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004471
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004472static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c, 0);
4473static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c, 0);
Stephen Boydd7a143a2012-02-16 17:59:26 -08004474
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004475static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c, 0);
4476static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c, 0);
4477static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c, 0);
4478static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c, 0);
4479static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c, 0);
4480static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c, 0);
4481static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c, 0);
4482static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c, 0);
4483static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c, 0);
4484static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c, 0);
4485static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c, 0);
4486static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c, 0);
4487static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c, 0);
4488static DEFINE_CLK_VOTER(dfab_tzcom_clk, &dfab_clk.c, 0);
4489static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c, 0);
4490static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004491
Matt Wagantall42cd12a2012-03-30 18:02:40 -07004492static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c, LONG_MAX);
Matt Wagantall35e78fc2012-04-05 14:18:44 -07004493static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004494
4495#ifdef CONFIG_DEBUG_FS
4496struct measure_sel {
4497 u32 test_vector;
4498 struct clk *clk;
4499};
4500
Matt Wagantall8b38f942011-08-02 18:23:18 -07004501static DEFINE_CLK_MEASURE(l2_m_clk);
4502static DEFINE_CLK_MEASURE(krait0_m_clk);
4503static DEFINE_CLK_MEASURE(krait1_m_clk);
Tianyi Gou455c13c2012-02-02 16:33:24 -08004504static DEFINE_CLK_MEASURE(krait2_m_clk);
4505static DEFINE_CLK_MEASURE(krait3_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004506static DEFINE_CLK_MEASURE(q6sw_clk);
4507static DEFINE_CLK_MEASURE(q6fw_clk);
4508static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004509
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004510static struct measure_sel measure_mux[] = {
4511 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4512 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4513 { TEST_PER_LS(0x13), &sdc1_clk.c },
4514 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4515 { TEST_PER_LS(0x15), &sdc2_clk.c },
4516 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4517 { TEST_PER_LS(0x17), &sdc3_clk.c },
4518 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4519 { TEST_PER_LS(0x19), &sdc4_clk.c },
4520 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4521 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004522 { TEST_PER_LS(0x1F), &gp0_clk.c },
4523 { TEST_PER_LS(0x20), &gp1_clk.c },
4524 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004525 { TEST_PER_LS(0x25), &dfab_clk.c },
4526 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4527 { TEST_PER_LS(0x26), &pmem_clk.c },
4528 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4529 { TEST_PER_LS(0x33), &cfpb_clk.c },
4530 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4531 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4532 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4533 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4534 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4535 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4536 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4537 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4538 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4539 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4540 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4541 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4542 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4543 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4544 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4545 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4546 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4547 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4548 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4549 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4550 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4551 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4552 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4553 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4554 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4555 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4556 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4557 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4558 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4559 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4560 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4561 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4562 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4563 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4564 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4565 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4566 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004567 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4568 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4569 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4570 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4571 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4572 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4573 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4574 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4575 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004576 { TEST_PER_LS(0x78), &sfpb_clk.c },
4577 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4578 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4579 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4580 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4581 { TEST_PER_LS(0x7D), &prng_clk.c },
4582 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4583 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4584 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4585 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004586 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4587 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4588 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004589 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4590 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4591 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4592 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4593 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4594 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4595 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4596 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4597 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4598 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004599 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004600 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4601
4602 { TEST_PER_HS(0x07), &afab_clk.c },
4603 { TEST_PER_HS(0x07), &afab_a_clk.c },
4604 { TEST_PER_HS(0x18), &sfab_clk.c },
4605 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004606 { TEST_PER_HS(0x26), &q6sw_clk },
4607 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004608 { TEST_PER_HS(0x2A), &adm0_clk.c },
Tianyi Gou6613de52012-01-27 17:57:53 -08004609 { TEST_PER_HS(0x2D), &pcie_phy_ref_clk.c },
4610 { TEST_PER_HS(0x32), &pcie_a_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004611 { TEST_PER_HS(0x34), &ebi1_clk.c },
4612 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004613 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004614
4615 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4616 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4617 { TEST_MM_LS(0x02), &cam1_clk.c },
4618 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004619 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004620 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4621 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4622 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4623 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4624 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4625 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4626 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4627 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4628 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4629 { TEST_MM_LS(0x12), &imem_p_clk.c },
4630 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4631 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4632 { TEST_MM_LS(0x16), &rot_p_clk.c },
4633 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4634 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4635 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4636 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4637 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4638 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4639 { TEST_MM_LS(0x1D), &cam0_clk.c },
4640 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4641 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4642 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4643 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4644 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4645 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4646 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4647 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004648 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004649 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004650
4651 { TEST_MM_HS(0x00), &csi0_clk.c },
4652 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004653 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004654 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4655 { TEST_MM_HS(0x06), &vfe_clk.c },
4656 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4657 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4658 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4659 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4660 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4661 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4662 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4663 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4664 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4665 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4666 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4667 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4668 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4669 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4670 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4671 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4672 { TEST_MM_HS(0x1A), &mdp_clk.c },
4673 { TEST_MM_HS(0x1B), &rot_clk.c },
4674 { TEST_MM_HS(0x1C), &vpe_clk.c },
4675 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4676 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4677 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4678 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4679 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4680 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4681 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4682 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4683 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4684 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4685 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004686 { TEST_MM_HS(0x2D), &csi2_clk.c },
4687 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4688 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4689 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4690 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4691 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004692 { TEST_MM_HS(0x33), &vcap_clk.c },
4693 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004694 { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004695 { TEST_MM_HS(0x35), &vcap_axi_clk.c },
Tianyi Gou51918802012-01-26 14:05:43 -08004696 { TEST_MM_HS(0x36), &rgb_tv_clk.c },
4697 { TEST_MM_HS(0x37), &npl_tv_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004698 { TEST_MM_HS(0x38), &gfx3d_axi_clk_8064.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004699
4700 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4701 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4702 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4703 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4704 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4705 { TEST_LPA(0x14), &pcm_clk.c },
4706 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004707
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004708 { TEST_LPA_HS(0x00), &q6_func_clk },
4709
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004710 { TEST_CPUL2(0x2), &l2_m_clk },
4711 { TEST_CPUL2(0x0), &krait0_m_clk },
4712 { TEST_CPUL2(0x1), &krait1_m_clk },
Tianyi Gou455c13c2012-02-02 16:33:24 -08004713 { TEST_CPUL2(0x4), &krait2_m_clk },
4714 { TEST_CPUL2(0x5), &krait3_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004715};
4716
4717static struct measure_sel *find_measure_sel(struct clk *clk)
4718{
4719 int i;
4720
4721 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4722 if (measure_mux[i].clk == clk)
4723 return &measure_mux[i];
4724 return NULL;
4725}
4726
Matt Wagantall8b38f942011-08-02 18:23:18 -07004727static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004728{
4729 int ret = 0;
4730 u32 clk_sel;
4731 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004732 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004733 unsigned long flags;
4734
4735 if (!parent)
4736 return -EINVAL;
4737
4738 p = find_measure_sel(parent);
4739 if (!p)
4740 return -EINVAL;
4741
4742 spin_lock_irqsave(&local_clock_reg_lock, flags);
4743
Matt Wagantall8b38f942011-08-02 18:23:18 -07004744 /*
4745 * Program the test vector, measurement period (sample_ticks)
4746 * and scaling multiplier.
4747 */
4748 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004749 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004750 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004751 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4752 case TEST_TYPE_PER_LS:
4753 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4754 break;
4755 case TEST_TYPE_PER_HS:
4756 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4757 break;
4758 case TEST_TYPE_MM_LS:
4759 writel_relaxed(0x4030D97, CLK_TEST_REG);
4760 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4761 break;
4762 case TEST_TYPE_MM_HS:
4763 writel_relaxed(0x402B800, CLK_TEST_REG);
4764 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4765 break;
4766 case TEST_TYPE_LPA:
4767 writel_relaxed(0x4030D98, CLK_TEST_REG);
4768 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4769 LCC_CLK_LS_DEBUG_CFG_REG);
4770 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004771 case TEST_TYPE_LPA_HS:
4772 writel_relaxed(0x402BC00, CLK_TEST_REG);
4773 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4774 LCC_CLK_HS_DEBUG_CFG_REG);
4775 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004776 case TEST_TYPE_CPUL2:
4777 writel_relaxed(0x4030400, CLK_TEST_REG);
4778 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4779 clk->sample_ticks = 0x4000;
4780 clk->multiplier = 2;
4781 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004782 default:
4783 ret = -EPERM;
4784 }
4785 /* Make sure test vector is set before starting measurements. */
4786 mb();
4787
4788 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4789
4790 return ret;
4791}
4792
4793/* Sample clock for 'ticks' reference clock ticks. */
4794static u32 run_measurement(unsigned ticks)
4795{
4796 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004797 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4798
4799 /* Wait for timer to become ready. */
4800 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4801 cpu_relax();
4802
4803 /* Run measurement and wait for completion. */
4804 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4805 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4806 cpu_relax();
4807
4808 /* Stop counters. */
4809 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4810
4811 /* Return measured ticks. */
4812 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4813}
4814
4815
4816/* Perform a hardware rate measurement for a given clock.
4817 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004818static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004819{
4820 unsigned long flags;
4821 u32 pdm_reg_backup, ringosc_reg_backup;
4822 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004823 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004824 unsigned ret;
4825
Stephen Boyde334aeb2012-01-24 12:17:29 -08004826 ret = clk_prepare_enable(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004827 if (ret) {
4828 pr_warning("CXO clock failed to enable. Can't measure\n");
4829 return 0;
4830 }
4831
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004832 spin_lock_irqsave(&local_clock_reg_lock, flags);
4833
4834 /* Enable CXO/4 and RINGOSC branch and root. */
4835 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4836 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4837 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4838 writel_relaxed(0xA00, RINGOSC_NS_REG);
4839
4840 /*
4841 * The ring oscillator counter will not reset if the measured clock
4842 * is not running. To detect this, run a short measurement before
4843 * the full measurement. If the raw results of the two are the same
4844 * then the clock must be off.
4845 */
4846
4847 /* Run a short measurement. (~1 ms) */
4848 raw_count_short = run_measurement(0x1000);
4849 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004850 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004851
4852 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4853 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4854
4855 /* Return 0 if the clock is off. */
4856 if (raw_count_full == raw_count_short)
4857 ret = 0;
4858 else {
4859 /* Compute rate in Hz. */
4860 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004861 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4862 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004863 }
4864
4865 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004866 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004867 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4868
Stephen Boyde334aeb2012-01-24 12:17:29 -08004869 clk_disable_unprepare(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004870
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004871 return ret;
4872}
4873#else /* !CONFIG_DEBUG_FS */
4874static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4875{
4876 return -EINVAL;
4877}
4878
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004879static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004880{
4881 return 0;
4882}
4883#endif /* CONFIG_DEBUG_FS */
4884
4885static struct clk_ops measure_clk_ops = {
4886 .set_parent = measure_clk_set_parent,
4887 .get_rate = measure_clk_get_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004888};
4889
Matt Wagantall8b38f942011-08-02 18:23:18 -07004890static struct measure_clk measure_clk = {
4891 .c = {
4892 .dbg_name = "measure_clk",
4893 .ops = &measure_clk_ops,
4894 CLK_INIT(measure_clk.c),
4895 },
4896 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004897};
4898
Tianyi Goua8b3cce2011-11-08 14:37:26 -08004899static struct clk_lookup msm_clocks_8064[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08004900 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
4901 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyded630b02012-01-26 15:26:47 -08004902 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
4903 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
4904 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
4905 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
4906 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Matt Wagantall292aace2012-01-26 19:12:34 -08004907 CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08004908 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08004909 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Stephen Boyded630b02012-01-26 15:26:47 -08004910 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4911 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4912 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
4913 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004914
Tianyi Gou21a0e802012-02-04 22:34:10 -08004915 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
4916 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
4917 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
4918 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
4919 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08004920 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08004921 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
4922 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
4923 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
4924 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
4925 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
4926 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06004927 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
4928 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08004929
Tianyi Gou21a0e802012-02-04 22:34:10 -08004930 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08004931 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""),
4932 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
4933 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004934
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004935 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
4936 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
4937 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004938 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004939 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
4940 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
4941 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
4942 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""),
4943 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004944 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"),
David Keitel3c40fc52012-02-09 17:53:52 -08004945 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004946 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004947 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08004948 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004949 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"),
Joel King8f839b92012-04-01 14:37:46 -07004950 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "qup_i2c.5"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004951 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
4952 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
4953 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08004954 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Tianyi Gou05e01102012-02-08 22:15:49 -08004955 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004956 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4957 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4958 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4959 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004960 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
4961 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004962 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
4963 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
4964 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004965 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
4966 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
4967 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004968 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""),
4969 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07004970 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
4971 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
4972 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
4973 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
4974 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
4975 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004976 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004977 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"),
David Keitel3c40fc52012-02-09 17:53:52 -08004978 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004979 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004980 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08004981 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004982 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"),
Joel King8f839b92012-04-01 14:37:46 -07004983 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "qup_i2c.5"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004984 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004985 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004986 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
4987 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004988 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05304989 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
4990 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004991 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4992 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4993 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4994 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004995 CLK_LOOKUP("iface_clk", pcie_p_clk.c, ""),
Tianyi Gou6613de52012-01-27 17:57:53 -08004996 CLK_LOOKUP("ref_clk", pcie_phy_ref_clk.c, ""),
4997 CLK_LOOKUP("bus_clk", pcie_a_clk.c, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07004998 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
4999 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005000 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5001 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5002 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5003 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Kevin Chand07220e2012-02-13 15:52:22 -08005004 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005005 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Sreesudhan Ramakrish Ramkumar8002a792012-04-09 17:42:58 -07005006 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar6c6f57c2012-02-21 15:12:44 -08005007 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Kevin Chand07220e2012-02-13 15:52:22 -08005008 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
5009 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5010 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5011 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5012 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5013 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5014 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5015 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5016 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5017 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5018 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5019 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5020 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5021 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5022 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5023 CLK_LOOKUP("csiphy_timer_src_clk",
5024 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5025 CLK_LOOKUP("csiphy_timer_src_clk",
5026 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5027 CLK_LOOKUP("csiphy_timer_src_clk",
5028 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5029 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5030 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5031 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005032 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5033 CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"),
5034 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
5035 CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"),
Tianyi Gou51918802012-01-26 14:05:43 -08005036 CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""),
5037 CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""),
5038
Pu Chen86b4be92011-11-03 17:27:57 -07005039 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005040 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005041 CLK_LOOKUP("bus_clk",
5042 gfx3d_axi_clk_8064.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005043 CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005044 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005045 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
5046 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005047 CLK_LOOKUP("core_clk", vcap_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005048 CLK_LOOKUP("core_clk", vcap_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005049 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005050 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
Terence Hampson2e1705f2012-04-11 19:55:29 -04005051 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, "msm_vcap.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005052 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005053 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5054 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005055 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005056 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005057 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005058 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005059 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005060 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005061 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005062 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005063 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005064 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Matt Wagantall61286312012-02-22 15:55:09 -08005065 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005066 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5067 CLK_LOOKUP("div_clk", tv_src_div_clk.c, ""),
Greg Griscofa47b532011-11-11 10:32:06 -08005068 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005069 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005070 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
Tianyi Gou51918802012-01-26 14:05:43 -08005071 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005072 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005073 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Ujwal Pateld041f982012-03-27 19:51:44 -07005074 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005075 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chand07220e2012-02-13 15:52:22 -08005076 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005077 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chand07220e2012-02-13 15:52:22 -08005078 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005079 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5080 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5081 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5082 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5083 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5084 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5085 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005086 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
5087 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"),
Kevin Chand07220e2012-02-13 15:52:22 -08005088 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5089 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5090 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005091 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5092 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
5093 CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"),
5094 CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"),
Pu Chen86b4be92011-11-03 17:27:57 -07005095 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005096 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005097 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5098 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005099 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005100 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005101 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005102 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005103 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005104 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005105 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005106 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005107 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005108 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005109 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chand07220e2012-02-13 15:52:22 -08005110 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005111 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chanb20742b2012-02-27 15:47:35 -08005112 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall61286312012-02-22 15:55:09 -08005113 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005114
Patrick Lai04baee942012-05-01 14:38:47 -07005115 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c,
5116 "msm-dai-q6-mi2s"),
5117 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c,
5118 "msm-dai-q6-mi2s"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005119 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5120 "msm-dai-q6.1"),
5121 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5122 "msm-dai-q6.1"),
5123 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5124 "msm-dai-q6.5"),
5125 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5126 "msm-dai-q6.5"),
5127 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5128 "msm-dai-q6.16384"),
5129 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5130 "msm-dai-q6.16384"),
5131 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5132 "msm-dai-q6.4"),
5133 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5134 "msm-dai-q6.4"),
5135 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005136 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005137 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005138 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005139 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""),
5140 CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""),
5141 CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""),
5142 CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""),
5143 CLK_LOOKUP("core_clk", rot_axi_clk.c, ""),
5144 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""),
5145 CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
5146 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
5147 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005148 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005149
5150 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5151 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5152 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"),
5153 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"),
5154 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5155 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5156 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5157 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5158 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5159 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5160 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005161 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08005162 CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005163
Manu Gautam5143b252012-01-05 19:25:23 -08005164 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5165 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5166 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5167 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5168 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005169
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005170 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5171 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5172 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5173 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5174 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5175 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5176 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5177 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5178 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005179 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.9"),
5180 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.10"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005181 CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
5182
Deepak Kotur954b1782012-04-24 17:58:19 -07005183 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5184 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5185 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5186 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5187 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005188 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5189 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
5190
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005191 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005192
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005193 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5194 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5195 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
Tianyi Gou455c13c2012-02-02 16:33:24 -08005196 CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""),
5197 CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005198};
5199
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005200static struct clk_lookup msm_clocks_8960[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005201 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5202 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyded630b02012-01-26 15:26:47 -08005203 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5204 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5205 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5206 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5207 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005208 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08005209 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Stephen Boyded630b02012-01-26 15:26:47 -08005210 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5211 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5212 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5213 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005214
Matt Wagantallb2710b82011-11-16 19:55:17 -08005215 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5216 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5217 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5218 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5219 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005220 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005221 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5222 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5223 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5224 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5225 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5226 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005227 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5228 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005229
5230 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005231 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5232 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5233 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005234
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005235 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5236 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5237 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5238 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5239 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5240 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5241 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
Matt Wagantalle2522372011-08-17 14:52:21 -07005242 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5243 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005244 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
Stepan Moskovchenko2b4b1cd2012-03-29 18:21:04 -07005245 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, "msm_serial_hsl.1"),
Mayank Ranae009c922012-03-22 03:02:06 +05305246 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, "msm_serial_hs.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005247 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5248 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5249 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005250 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005251 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005252 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5253 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005254 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5255 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5256 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5257 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005258 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005259 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005260 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005261 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005262 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005263 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005264 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005265 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5266 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5267 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5268 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5269 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005270 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005271 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5272 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005273 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5274 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005275 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5276 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5277 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5278 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5279 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5280 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005281 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5282 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5283 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5284 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5285 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005286 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005287 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005288 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005289 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005290 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005291 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005292 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005293 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5294 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005295 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5296 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005297 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
Stepan Moskovchenko2b4b1cd2012-03-29 18:21:04 -07005298 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, "msm_serial_hsl.1"),
Mayank Ranae009c922012-03-22 03:02:06 +05305299 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "msm_serial_hs.1"),
Matt Wagantallac294852011-08-17 15:44:58 -07005300 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005301 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005302 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005303 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5304 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5305 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005306 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005307 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5308 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5309 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5310 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5311 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005312 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5313 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005314 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5315 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5316 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5317 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Kevin Chan09f4e662011-12-16 08:17:02 -08005318 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5319 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5320 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005321 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -08005322 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005323 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005324 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5325 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005326 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005327 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5328 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005329 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005330 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5331 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005332 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
Kevin Chane12c6672011-10-26 11:55:26 -07005333 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5334 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005335 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5336 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5337 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5338 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5339 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5340 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5341 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Kevin Chanf6216f22011-10-25 18:40:11 -07005342 CLK_LOOKUP("csiphy_timer_src_clk",
5343 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5344 CLK_LOOKUP("csiphy_timer_src_clk",
5345 csiphy_timer_src_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005346 CLK_LOOKUP("csiphy_timer_src_clk",
5347 csiphy_timer_src_clk.c, "msm_csiphy.2"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005348 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5349 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005350 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005351 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5352 CLK_LOOKUP("byte_clk", dsi2_byte_clk.c, "mipi_dsi.2"),
5353 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
5354 CLK_LOOKUP("esc_clk", dsi2_esc_clk.c, "mipi_dsi.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005355 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005356 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005357 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005358 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005359 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005360 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5361 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005362 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5363 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005364 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005365 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005366 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005367 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005368 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005369 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005370 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005371 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005372 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005373 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005374 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5375 CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005376 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005377 CLK_LOOKUP("enc_clk", tv_enc_clk.c, "tvenc.0"),
5378 CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005379 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005380 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005381 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
5382 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005383 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005384 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005385 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005386 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005387 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005388 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005389 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005390 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005391 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5392 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5393 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5394 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5395 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5396 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5397 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005398 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
5399 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005400 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5401 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005402 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005403 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5404 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
5405 CLK_LOOKUP("master_iface_clk", dsi2_m_p_clk.c, "mipi_dsi.2"),
5406 CLK_LOOKUP("slave_iface_clk", dsi2_s_p_clk.c, "mipi_dsi.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005407 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005408 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005409 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005410 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005411 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005412 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005413 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5414 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005415 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005416 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005417 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005418 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005419 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005420 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005421 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005422 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005423 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005424 CLK_LOOKUP("iface_clk", tv_enc_p_clk.c, "tvenc.0"),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005425 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005426 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005427 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005428 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005429 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005430 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Patrick Lai04baee942012-05-01 14:38:47 -07005431 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c,
5432 "msm-dai-q6-mi2s"),
5433 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c,
5434 "msm-dai-q6-mi2s"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005435 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5436 "msm-dai-q6.1"),
5437 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5438 "msm-dai-q6.1"),
5439 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5440 "msm-dai-q6.5"),
5441 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5442 "msm-dai-q6.5"),
5443 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5444 "msm-dai-q6.16384"),
5445 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5446 "msm-dai-q6.16384"),
5447 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5448 "msm-dai-q6.4"),
5449 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5450 "msm-dai-q6.4"),
5451 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005452 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005453 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005454 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005455 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5456 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5457 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5458 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5459 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5460 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5461 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5462 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5463 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5464 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5465 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5466 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005467
5468 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5469 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5470 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5471 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5472 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005473 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5474 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005475
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005476 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005477 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005478 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5479 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5480 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5481 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5482 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005483 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005484 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005485 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005486 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08005487 CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005488
Matt Wagantalle1a86062011-08-18 17:46:10 -07005489 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005490
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005491 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5492 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5493 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5494 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5495 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5496 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005497};
5498
Tianyi Goue3d4f542012-03-15 17:06:45 -07005499static struct clk_lookup msm_clocks_8930[] = {
Stephen Boydbe1a7392012-04-02 20:17:11 -07005500 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005501 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5502 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5503 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5504 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5505 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
5506 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
5507 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5508 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5509 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5510 CLK_LOOKUP("measure", measure_clk.c, "debug"),
5511
5512 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5513 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5514 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5515 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5516 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
5517 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
5518 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5519 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5520 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5521 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5522 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5523 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005524 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5525 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005526
5527 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005528 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5529 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5530 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
5531
5532 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5533 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5534 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5535 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5536 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5537 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5538 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
5539 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5540 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5541 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5542 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5543 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5544 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5545 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5546 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
5547 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
5548 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
5549 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5550 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
5551 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5552 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5553 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5554 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
5555 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
5556 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
5557 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
5558 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
5559 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
5560 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
5561 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
5562 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5563 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5564 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5565 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5566 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
5567 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5568 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
5569 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5570 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
5571 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5572 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5573 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5574 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5575 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5576 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
5577 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5578 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5579 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5580 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5581 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
5582 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
5583 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
5584 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
5585 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
5586 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
5587 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
5588 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
5589 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5590 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
5591 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5592 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
5593 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5594 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
5595 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
5596 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
5597 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
5598 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
5599 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5600 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5601 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
5602 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
5603 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5604 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5605 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5606 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5607 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
5608 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5609 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
5610 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5611 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5612 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5613 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005614 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Hody Hung994f4622012-04-24 10:27:45 -07005615 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
Sreesudhan Ramakrish Ramkumar981c82c2012-04-30 17:31:37 -07005616 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005617 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5618 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
5619 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5620 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5621 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5622 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5623 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5624 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5625 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5626 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5627 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5628 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5629 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5630 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5631 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5632 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5633 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5634 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5635 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5636 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
5637 CLK_LOOKUP("csiphy_timer_src_clk",
5638 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5639 CLK_LOOKUP("csiphy_timer_src_clk",
5640 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5641 CLK_LOOKUP("csiphy_timer_src_clk",
5642 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5643 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5644 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5645 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005646 CLK_LOOKUP("byte_clk", dsi1_byte_clk.c, "mipi_dsi.1"),
5647 CLK_LOOKUP("esc_clk", dsi1_esc_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005648 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
5649 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5650 CLK_LOOKUP("bus_clk",
5651 gfx3d_axi_clk_8930.c, "footswitch-8x60.2"),
5652 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005653 CLK_LOOKUP("mem_clk", imem_axi_clk.c, "msm_gemini.0"),
5654 CLK_LOOKUP("core_clk", ijpeg_clk.c, "msm_gemini.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005655 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005656 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005657 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005658 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005659 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005660 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005661 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
5662 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
5663 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005664 CLK_LOOKUP("src_clk", tv_src_clk.c, "dtv.0"),
5665 CLK_LOOKUP("src_clk", tv_src_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005666 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005667 CLK_LOOKUP("dac_clk", tv_dac_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005668 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
5669 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005670 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "dtv.0"),
5671 CLK_LOOKUP("mdp_clk", mdp_tv_clk.c, "tvenc.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005672 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005673 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, "dtv.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005674 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
5675 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
5676 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
5677 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
5678 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
5679 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
5680 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5681 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5682 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5683 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5684 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5685 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5686 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005687 CLK_LOOKUP("arb_clk", amp_p_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005688 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5689 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5690 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005691 CLK_LOOKUP("master_iface_clk", dsi1_m_p_clk.c, "mipi_dsi.1"),
5692 CLK_LOOKUP("slave_iface_clk", dsi1_s_p_clk.c, "mipi_dsi.1"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005693 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
5694 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
5695 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5696 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallf45cd362012-05-03 21:09:44 -07005697 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "msm_gemini.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005698 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
5699 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -07005700 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "mdp.0"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005701 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
5702 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
5703 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
5704 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
5705 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
5706 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
5707 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
5708 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
5709 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
5710 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
5711 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5712 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5713 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5714 "msm-dai-q6.1"),
5715 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5716 "msm-dai-q6.1"),
5717 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5718 "msm-dai-q6.5"),
5719 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5720 "msm-dai-q6.5"),
5721 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5722 "msm-dai-q6.16384"),
5723 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5724 "msm-dai-q6.16384"),
5725 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5726 "msm-dai-q6.4"),
5727 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5728 "msm-dai-q6.4"),
5729 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
5730 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5731 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
5732 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5733 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5734 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5735 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5736 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5737 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5738 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5739 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5740 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"),
5741 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"),
5742
5743 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5744 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5745 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5746 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5747 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
Stephen Boyd7b973de2012-03-09 12:26:16 -08005748 CLK_LOOKUP("core_clk", vcodec_axi_clk.c, "pil_vidc"),
5749 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "pil_vidc"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005750
5751 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5752 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5753 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5754 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5755 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5756 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5757 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
5758 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5759 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5760 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
5761 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
5762
5763 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
5764
5765 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5766 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5767 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5768 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5769 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5770 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
5771};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005772/*
5773 * Miscellaneous clock register initializations
5774 */
5775
5776/* Read, modify, then write-back a register. */
5777static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5778{
5779 uint32_t regval = readl_relaxed(reg);
5780 regval &= ~mask;
5781 regval |= val;
5782 writel_relaxed(regval, reg);
5783}
5784
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005785static struct pll_config_regs pll4_regs __initdata = {
5786 .l_reg = LCC_PLL0_L_VAL_REG,
5787 .m_reg = LCC_PLL0_M_VAL_REG,
5788 .n_reg = LCC_PLL0_N_VAL_REG,
5789 .config_reg = LCC_PLL0_CONFIG_REG,
5790 .mode_reg = LCC_PLL0_MODE_REG,
5791};
Tianyi Gou41515e22011-09-01 19:37:43 -07005792
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005793static struct pll_config pll4_config __initdata = {
5794 .l = 0xE,
5795 .m = 0x27A,
5796 .n = 0x465,
5797 .vco_val = 0x0,
5798 .vco_mask = BM(17, 16),
5799 .pre_div_val = 0x0,
5800 .pre_div_mask = BIT(19),
5801 .post_div_val = 0x0,
5802 .post_div_mask = BM(21, 20),
5803 .mn_ena_val = BIT(22),
5804 .mn_ena_mask = BIT(22),
5805 .main_output_val = BIT(23),
5806 .main_output_mask = BIT(23),
5807};
Tianyi Gou41515e22011-09-01 19:37:43 -07005808
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005809static struct pll_config_regs pll15_regs __initdata = {
5810 .l_reg = MM_PLL3_L_VAL_REG,
5811 .m_reg = MM_PLL3_M_VAL_REG,
5812 .n_reg = MM_PLL3_N_VAL_REG,
5813 .config_reg = MM_PLL3_CONFIG_REG,
5814 .mode_reg = MM_PLL3_MODE_REG,
5815};
Tianyi Gou358c3862011-10-18 17:03:41 -07005816
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005817static struct pll_config pll15_config __initdata = {
5818 .l = (0x24 | BVAL(31, 7, 0x620)),
5819 .m = 0x1,
5820 .n = 0x9,
5821 .vco_val = BVAL(17, 16, 0x2),
5822 .vco_mask = BM(17, 16),
5823 .pre_div_val = 0x0,
5824 .pre_div_mask = BIT(19),
5825 .post_div_val = 0x0,
5826 .post_div_mask = BM(21, 20),
5827 .mn_ena_val = BIT(22),
5828 .mn_ena_mask = BIT(22),
5829 .main_output_val = BIT(23),
5830 .main_output_mask = BIT(23),
5831};
Tianyi Gou41515e22011-09-01 19:37:43 -07005832
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005833static struct pll_config_regs pll14_regs __initdata = {
5834 .l_reg = BB_PLL14_L_VAL_REG,
5835 .m_reg = BB_PLL14_M_VAL_REG,
5836 .n_reg = BB_PLL14_N_VAL_REG,
5837 .config_reg = BB_PLL14_CONFIG_REG,
5838 .mode_reg = BB_PLL14_MODE_REG,
5839};
5840
5841static struct pll_config pll14_config __initdata = {
5842 .l = (0x11 | BVAL(31, 7, 0x620)),
5843 .m = 0x7,
5844 .n = 0x9,
5845 .vco_val = 0x0,
5846 .vco_mask = BM(17, 16),
5847 .pre_div_val = 0x0,
5848 .pre_div_mask = BIT(19),
5849 .post_div_val = 0x0,
5850 .post_div_mask = BM(21, 20),
5851 .mn_ena_val = BIT(22),
5852 .mn_ena_mask = BIT(22),
5853 .main_output_val = BIT(23),
5854 .main_output_mask = BIT(23),
5855};
Tianyi Gou41515e22011-09-01 19:37:43 -07005856
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005857static void __init reg_init(void)
5858{
Stephen Boydd471e7a2011-11-19 01:37:39 -08005859 void __iomem *imem_reg;
Vikram Mulukutla5b146722012-04-23 18:17:50 -07005860
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005861 /* Deassert MM SW_RESET_ALL signal. */
5862 writel_relaxed(0, SW_RESET_ALL_REG);
5863
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005864 /*
Tianyi Goue3d4f542012-03-15 17:06:45 -07005865 * Some bits are only used on 8960 or 8064 or 8930 and are marked as
5866 * reserved bits on the other SoCs. Writing to these reserved bits
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005867 * should have no effect.
5868 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005869 /*
5870 * Initialize MM AHB registers: Enable the FPB clock and disable HW
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005871 * gating on non-8960 for all clocks. Also set VFE_AHB's
Stephen Boydd471e7a2011-11-19 01:37:39 -08005872 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
5873 * the clock is halted. The sleep and wake-up delays are set to safe
5874 * values.
5875 */
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005876 if (cpu_is_msm8960()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08005877 rmwreg(0x44000000, AHB_EN_REG, 0x6C000103);
5878 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
5879 } else {
5880 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5881 writel_relaxed(0x000007F9, AHB_EN2_REG);
5882 }
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005883 if (cpu_is_apq8064())
5884 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005885
5886 /* Deassert all locally-owned MM AHB resets. */
5887 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005888 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005889
5890 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5891 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5892 * delays to safe values. */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005893 if (cpu_is_msm8960() &&
5894 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
5895 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
5896 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -08005897 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08005898 } else {
5899 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5900 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5901 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
5902 }
Matt Wagantall53d968f2011-07-19 13:22:53 -07005903 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005904 if (cpu_is_apq8064())
5905 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Tianyi Goue3d4f542012-03-15 17:06:45 -07005906 if (cpu_is_msm8930())
5907 rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005908 if (cpu_is_msm8960())
Stephen Boydd471e7a2011-11-19 01:37:39 -08005909 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
5910 else
5911 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
5912
5913 /* Enable IMEM's clk_on signal */
5914 imem_reg = ioremap(0x04b00040, 4);
5915 if (imem_reg) {
5916 writel_relaxed(0x3, imem_reg);
5917 iounmap(imem_reg);
5918 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005919
5920 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5921 * memories retain state even when not clocked. Also, set sleep and
5922 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005923 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5924 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5925 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005926 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07005927 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005928 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005929 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5930 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5931 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005932 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5933 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5934 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005935 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005936 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Tianyi Goue3d4f542012-03-15 17:06:45 -07005937 if (cpu_is_msm8960() || cpu_is_apq8064()) {
5938 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5939 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
5940 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5941 }
5942 if (cpu_is_msm8960() || cpu_is_msm8930())
5943 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5944
5945 if (cpu_is_msm8960()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005946 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5947 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005948 }
5949 if (cpu_is_apq8064()) {
5950 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005951 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005952 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005953
Tianyi Gou41515e22011-09-01 19:37:43 -07005954 /*
5955 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5956 * core remain active during halt state of the clk. Also, set sleep
5957 * and wake-up value to max.
5958 */
5959 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005960 if (cpu_is_apq8064()) {
5961 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5962 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5963 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005964
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005965 /* De-assert MM AXI resets to all hardware blocks. */
5966 writel_relaxed(0, SW_RESET_AXI_REG);
5967
5968 /* Deassert all MM core resets. */
5969 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005970 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005971
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005972 /* Enable TSSC and PDM PXO sources. */
5973 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5974 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5975
5976 /* Source SLIMBus xo src from slimbus reference clock */
Tianyi Goue3d4f542012-03-15 17:06:45 -07005977 if (cpu_is_msm8960())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005978 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005979
5980 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5981 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
Tianyi Goue3d4f542012-03-15 17:06:45 -07005982 if (cpu_is_msm8960() || cpu_is_apq8064())
5983 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005984
5985 /* Source the sata_phy_ref_clk from PXO */
5986 if (cpu_is_apq8064())
5987 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5988
5989 /*
Tianyi Gou05e01102012-02-08 22:15:49 -08005990 * TODO: Programming below PLLs and prng_clk is temporary and
5991 * needs to be removed after bootloaders program them.
Tianyi Gou41515e22011-09-01 19:37:43 -07005992 */
5993 if (cpu_is_apq8064()) {
Tianyi Gou317aa862012-02-06 14:31:07 -08005994 u32 is_pll_enabled;
Tianyi Gou41515e22011-09-01 19:37:43 -07005995
5996 /* Program pxo_src_clk to source from PXO */
5997 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5998
Tianyi Gou41515e22011-09-01 19:37:43 -07005999 /* Check if PLL14 is active */
6000 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006001 if (!is_pll_enabled)
Tianyi Goudf71f2e2011-10-24 22:25:04 -07006002 /* Ref clk = 27MHz and program pll14 to 480MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006003 configure_pll(&pll14_config, &pll14_regs, 1);
Tianyi Gou621f8742011-09-01 21:45:01 -07006004
Tianyi Gou621f8742011-09-01 21:45:01 -07006005 /* Program PLL15 to 975MHz with ref clk = 27MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006006 configure_pll(&pll15_config, &pll15_regs, 0);
Tianyi Gouc29c3242011-10-12 21:02:15 -07006007
6008 /* Check if PLL4 is active */
6009 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006010 if (!is_pll_enabled)
Tianyi Goudf71f2e2011-10-24 22:25:04 -07006011 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006012 configure_pll(&pll4_config, &pll4_regs, 1);
Tianyi Gouc29c3242011-10-12 21:02:15 -07006013
6014 /* Enable PLL4 source on the LPASS Primary PLL Mux */
6015 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou05e01102012-02-08 22:15:49 -08006016
6017 /* Program prng_clk to 64MHz if it isn't configured */
6018 if (!readl_relaxed(PRNG_CLK_NS_REG))
6019 writel_relaxed(0x2B, PRNG_CLK_NS_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07006020 }
Tianyi Gou65c536a2012-03-20 23:20:29 -07006021
6022 /*
6023 * Program PLL15 to 900MHz with ref clk = 27MHz and
6024 * only enable PLL main output.
6025 */
6026 if (cpu_is_msm8930()) {
Vikram Mulukutla5b146722012-04-23 18:17:50 -07006027 pll15_config.l = 0x21 | BVAL(31, 7, 0x600);
6028 pll15_config.m = 0x1;
6029 pll15_config.n = 0x3;
6030 configure_pll(&pll15_config, &pll15_regs, 0);
6031 /* Disable AUX and BIST outputs */
6032 writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
Tianyi Gou65c536a2012-03-20 23:20:29 -07006033 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006034}
6035
Matt Wagantallb64888f2012-04-02 21:35:07 -07006036static void __init msm8960_clock_pre_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006037{
Saravana Kannan298ec392012-02-08 19:21:47 -08006038 if (cpu_is_apq8064()) {
6039 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8064;
Tianyi Goue1faaf22012-01-24 16:07:19 -08006040 } else if (cpu_is_msm8930() || cpu_is_msm8627()) {
Saravana Kannan298ec392012-02-08 19:21:47 -08006041 vdd_dig.set_vdd = set_vdd_dig_8930;
6042 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8930;
Tianyi Goue1faaf22012-01-24 16:07:19 -08006043 }
Tianyi Goubf3d0b12012-01-23 14:37:28 -08006044
Tianyi Gou41515e22011-09-01 19:37:43 -07006045 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006046 * Change the freq tables for and voltage requirements for
6047 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07006048 */
6049 if (cpu_is_apq8064()) {
6050 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006051
6052 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
6053 sizeof(gfx3d_clk.c.fmax));
6054 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
6055 sizeof(ijpeg_clk.c.fmax));
6056 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
6057 sizeof(ijpeg_clk.c.fmax));
6058 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
6059 sizeof(tv_src_clk.c.fmax));
6060 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
6061 sizeof(vfe_clk.c.fmax));
6062
Tianyi Goue3d4f542012-03-15 17:06:45 -07006063 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8064.c;
6064 }
6065
6066 /*
6067 * Change the freq tables and voltage requirements for
6068 * clocks which differ between 8960 and 8930.
6069 */
6070 if (cpu_is_msm8930()) {
6071 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
6072
6073 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930,
6074 sizeof(gfx3d_clk.c.fmax));
6075
6076 pll15_clk.c.rate = 900000000;
6077 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07006078 }
Stephen Boyd842a1f62012-04-26 19:07:38 -07006079 if ((readl_relaxed(PRNG_CLK_NS_REG) & 0x7F) == 0x2B)
6080 prng_clk.freq_tbl = clk_tbl_prng_64;
Stephen Boyd94625ef2011-07-12 17:06:01 -07006081
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006082 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006083
Vikram Mulukutla681d8682012-03-09 23:56:20 -08006084 clk_ops_local_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006085
6086 /* Initialize clock registers. */
6087 reg_init();
Matt Wagantallb64888f2012-04-02 21:35:07 -07006088}
6089
6090static void __init msm8960_clock_post_init(void)
6091{
6092 /* Keep PXO on whenever APPS cpu is active */
6093 clk_prepare_enable(&pxo_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006094
Matt Wagantalle655cd72012-04-09 10:15:03 -07006095 /* Reset 3D core while clocked to ensure it resets completely. */
6096 clk_set_rate(&gfx3d_clk.c, 27000000);
6097 clk_prepare_enable(&gfx3d_clk.c);
6098 clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT);
6099 udelay(5);
6100 clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT);
6101 clk_disable_unprepare(&gfx3d_clk.c);
6102
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006103 /* Initialize rates for clocks that only support one. */
6104 clk_set_rate(&pdm_clk.c, 27000000);
Stephen Boyd842a1f62012-04-26 19:07:38 -07006105 clk_set_rate(&prng_clk.c, prng_clk.freq_tbl->freq_hz);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006106 clk_set_rate(&mdp_vsync_clk.c, 27000000);
6107 clk_set_rate(&tsif_ref_clk.c, 105000);
6108 clk_set_rate(&tssc_clk.c, 27000000);
6109 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07006110 if (cpu_is_apq8064()) {
6111 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
6112 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
6113 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006114 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07006115 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07006116 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07006117 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
6118 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
6119 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Lena Salman127823f2012-02-14 17:13:53 +02006120 clk_set_rate(&usb_hsic_system_clk.c, 60000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07006121 /*
6122 * Set the CSI rates to a safe default to avoid warnings when
6123 * switching csi pix and rdi clocks.
6124 */
6125 clk_set_rate(&csi0_src_clk.c, 27000000);
6126 clk_set_rate(&csi1_src_clk.c, 27000000);
6127 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006128
6129 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07006130 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006131 * Toggle these clocks on and off to refresh them.
6132 */
Stephen Boyd409b8b42012-04-10 12:12:56 -07006133 clk_prepare_enable(&pdm_clk.c);
6134 clk_disable_unprepare(&pdm_clk.c);
6135 clk_prepare_enable(&tssc_clk.c);
6136 clk_disable_unprepare(&tssc_clk.c);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006137 clk_prepare_enable(&usb_hsic_hsic_clk.c);
6138 clk_disable_unprepare(&usb_hsic_hsic_clk.c);
Stephen Boydd7a143a2012-02-16 17:59:26 -08006139
6140 /*
6141 * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all
6142 * times when Apps CPU is active. This ensures the timer's requirement
6143 * of Krait AHB running 4 times as fast as the timer itself.
6144 */
6145 clk_set_rate(&sfab_tmr_a_clk.c, 54000000);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006146 clk_prepare_enable(&sfab_tmr_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006147}
6148
Stephen Boydbb600ae2011-08-02 20:11:40 -07006149static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006150{
Stephen Boyda3787f32011-09-16 18:55:13 -07006151 int rc;
6152 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07006153 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07006154
6155 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
6156 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
6157 PTR_ERR(mmfpb_a_clk)))
6158 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006159 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07006160 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
6161 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006162 rc = clk_prepare_enable(mmfpb_a_clk);
Stephen Boyda3787f32011-09-16 18:55:13 -07006163 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
6164 return rc;
6165
Stephen Boyd85436132011-09-16 18:55:13 -07006166 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
6167 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
6168 PTR_ERR(cfpb_a_clk)))
6169 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006170 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07006171 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
6172 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006173 rc = clk_prepare_enable(cfpb_a_clk);
Stephen Boyd85436132011-09-16 18:55:13 -07006174 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
6175 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006176
6177 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006178}
Stephen Boydbb600ae2011-08-02 20:11:40 -07006179
6180struct clock_init_data msm8960_clock_init_data __initdata = {
6181 .table = msm_clocks_8960,
6182 .size = ARRAY_SIZE(msm_clocks_8960),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006183 .pre_init = msm8960_clock_pre_init,
6184 .post_init = msm8960_clock_post_init,
Stephen Boydbb600ae2011-08-02 20:11:40 -07006185 .late_init = msm8960_clock_late_init,
6186};
Tianyi Gou41515e22011-09-01 19:37:43 -07006187
6188struct clock_init_data apq8064_clock_init_data __initdata = {
6189 .table = msm_clocks_8064,
6190 .size = ARRAY_SIZE(msm_clocks_8064),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006191 .pre_init = msm8960_clock_pre_init,
6192 .post_init = msm8960_clock_post_init,
Tianyi Gou41515e22011-09-01 19:37:43 -07006193 .late_init = msm8960_clock_late_init,
6194};
Tianyi Goue3d4f542012-03-15 17:06:45 -07006195
6196struct clock_init_data msm8930_clock_init_data __initdata = {
6197 .table = msm_clocks_8930,
6198 .size = ARRAY_SIZE(msm_clocks_8930),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006199 .pre_init = msm8960_clock_pre_init,
6200 .post_init = msm8960_clock_post_init,
Tianyi Goue3d4f542012-03-15 17:06:45 -07006201 .late_init = msm8960_clock_late_init,
6202};