blob: b0a2e042aaf5d5149a67a10b7b1523c3cf410fa5 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
44#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou41515e22011-09-01 19:37:43 -070046#define CE3_HCLK_CTL_REG REG(0x36C4)
47#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
48#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070049#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070050#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
52#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
53#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
54#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070055/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
57#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070058#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070059#define CLK_TEST_REG REG(0x2FA0)
60#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
61#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
62#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
63#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
64#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
65#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070067/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070068#define BB_PLL_ENA_SC0_REG REG(0x34C0)
69#define BB_PLL0_STATUS_REG REG(0x30D8)
70#define BB_PLL5_STATUS_REG REG(0x30F8)
71#define BB_PLL6_STATUS_REG REG(0x3118)
72#define BB_PLL7_STATUS_REG REG(0x3138)
73#define BB_PLL8_L_VAL_REG REG(0x3144)
74#define BB_PLL8_M_VAL_REG REG(0x3148)
75#define BB_PLL8_MODE_REG REG(0x3140)
76#define BB_PLL8_N_VAL_REG REG(0x314C)
77#define BB_PLL8_STATUS_REG REG(0x3158)
78#define BB_PLL8_CONFIG_REG REG(0x3154)
79#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070080#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
81#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070082#define BB_PLL14_MODE_REG REG(0x31C0)
83#define BB_PLL14_L_VAL_REG REG(0x31C4)
84#define BB_PLL14_M_VAL_REG REG(0x31C8)
85#define BB_PLL14_N_VAL_REG REG(0x31CC)
86#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
87#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070088#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070089#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
90#define PMEM_ACLK_CTL_REG REG(0x25A0)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070091#define QDSS_AT_CLK_SRC0_NS_REG REG(0x2180)
92#define QDSS_AT_CLK_SRC1_NS_REG REG(0x2184)
93#define QDSS_AT_CLK_SRC_CTL_REG REG(0x2188)
94#define QDSS_AT_CLK_NS_REG REG(0x218C)
95#define QDSS_HCLK_CTL_REG REG(0x22A0)
96#define QDSS_RESETS_REG REG(0x2260)
97#define QDSS_STM_CLK_CTL_REG REG(0x2060)
98#define QDSS_TRACECLKIN_CLK_SRC0_NS_REG REG(0x21A0)
99#define QDSS_TRACECLKIN_CLK_SRC1_NS_REG REG(0x21A4)
100#define QDSS_TRACECLKIN_CLK_SRC_CTL_REG REG(0x21A8)
101#define QDSS_TRACECLKIN_CTL_REG REG(0x21AC)
102#define QDSS_TSCTR_CLK_SRC0_NS_REG REG(0x21C0)
103#define QDSS_TSCTR_CLK_SRC1_NS_REG REG(0x21C4)
104#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
105#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
106#define QDSS_TSCTR_CTL_REG REG(0x21CC)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700107#define RINGOSC_NS_REG REG(0x2DC0)
108#define RINGOSC_STATUS_REG REG(0x2DCC)
109#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
110#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
111#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
112#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
113#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
114#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
115#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
116#define TSIF_HCLK_CTL_REG REG(0x2700)
117#define TSIF_REF_CLK_MD_REG REG(0x270C)
118#define TSIF_REF_CLK_NS_REG REG(0x2710)
119#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700120#define SATA_CLK_SRC_NS_REG REG(0x2C08)
121#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
122#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
123#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
124#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700125#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
126#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
127#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
128#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
129#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
130#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700131#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700132#define USB_HS1_RESET_REG REG(0x2910)
133#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
134#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700135#define USB_HS3_HCLK_CTL_REG REG(0x3700)
136#define USB_HS3_HCLK_FS_REG REG(0x3704)
137#define USB_HS3_RESET_REG REG(0x3710)
138#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
139#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
140#define USB_HS4_HCLK_CTL_REG REG(0x3720)
141#define USB_HS4_HCLK_FS_REG REG(0x3724)
142#define USB_HS4_RESET_REG REG(0x3730)
143#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
144#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700145#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
146#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
147#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
148#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
149#define USB_HSIC_RESET_REG REG(0x2934)
150#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
151#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
152#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700153#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700154#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
155#define PCIE_HCLK_CTL_REG REG(0x22CC)
156#define GPLL1_MODE_REG REG(0x3160)
157#define GPLL1_L_VAL_REG REG(0x3164)
158#define GPLL1_M_VAL_REG REG(0x3168)
159#define GPLL1_N_VAL_REG REG(0x316C)
160#define GPLL1_CONFIG_REG REG(0x3174)
161#define GPLL1_STATUS_REG REG(0x3178)
162#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700163
164/* Multimedia clock registers. */
165#define AHB_EN_REG REG_MM(0x0008)
166#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700167#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700168#define AHB_NS_REG REG_MM(0x0004)
169#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700170#define CAMCLK0_NS_REG REG_MM(0x0148)
171#define CAMCLK0_CC_REG REG_MM(0x0140)
172#define CAMCLK0_MD_REG REG_MM(0x0144)
173#define CAMCLK1_NS_REG REG_MM(0x015C)
174#define CAMCLK1_CC_REG REG_MM(0x0154)
175#define CAMCLK1_MD_REG REG_MM(0x0158)
176#define CAMCLK2_NS_REG REG_MM(0x0228)
177#define CAMCLK2_CC_REG REG_MM(0x0220)
178#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700179#define CSI0_NS_REG REG_MM(0x0048)
180#define CSI0_CC_REG REG_MM(0x0040)
181#define CSI0_MD_REG REG_MM(0x0044)
182#define CSI1_NS_REG REG_MM(0x0010)
183#define CSI1_CC_REG REG_MM(0x0024)
184#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700185#define CSI2_NS_REG REG_MM(0x0234)
186#define CSI2_CC_REG REG_MM(0x022C)
187#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700188#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
189#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
190#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
191#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
192#define DSI1_BYTE_CC_REG REG_MM(0x0090)
193#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
194#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
195#define DSI1_ESC_NS_REG REG_MM(0x011C)
196#define DSI1_ESC_CC_REG REG_MM(0x00CC)
197#define DSI2_ESC_NS_REG REG_MM(0x0150)
198#define DSI2_ESC_CC_REG REG_MM(0x013C)
199#define DSI_PIXEL_CC_REG REG_MM(0x0130)
200#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
201#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
202#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
203#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
204#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
205#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
206#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
207#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
208#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
209#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700210#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700211#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
212#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
213#define GFX2D0_CC_REG REG_MM(0x0060)
214#define GFX2D0_MD0_REG REG_MM(0x0064)
215#define GFX2D0_MD1_REG REG_MM(0x0068)
216#define GFX2D0_NS_REG REG_MM(0x0070)
217#define GFX2D1_CC_REG REG_MM(0x0074)
218#define GFX2D1_MD0_REG REG_MM(0x0078)
219#define GFX2D1_MD1_REG REG_MM(0x006C)
220#define GFX2D1_NS_REG REG_MM(0x007C)
221#define GFX3D_CC_REG REG_MM(0x0080)
222#define GFX3D_MD0_REG REG_MM(0x0084)
223#define GFX3D_MD1_REG REG_MM(0x0088)
224#define GFX3D_NS_REG REG_MM(0x008C)
225#define IJPEG_CC_REG REG_MM(0x0098)
226#define IJPEG_MD_REG REG_MM(0x009C)
227#define IJPEG_NS_REG REG_MM(0x00A0)
228#define JPEGD_CC_REG REG_MM(0x00A4)
229#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700230#define VCAP_CC_REG REG_MM(0x0178)
231#define VCAP_NS_REG REG_MM(0x021C)
232#define VCAP_MD0_REG REG_MM(0x01EC)
233#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700234#define MAXI_EN_REG REG_MM(0x0018)
235#define MAXI_EN2_REG REG_MM(0x0020)
236#define MAXI_EN3_REG REG_MM(0x002C)
237#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700238#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700239#define MDP_CC_REG REG_MM(0x00C0)
240#define MDP_LUT_CC_REG REG_MM(0x016C)
241#define MDP_MD0_REG REG_MM(0x00C4)
242#define MDP_MD1_REG REG_MM(0x00C8)
243#define MDP_NS_REG REG_MM(0x00D0)
244#define MISC_CC_REG REG_MM(0x0058)
245#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700246#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700247#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700248#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
249#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
250#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
251#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
252#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
253#define MM_PLL1_STATUS_REG REG_MM(0x0334)
254#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700255#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
256#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
257#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
258#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
259#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
260#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700261#define ROT_CC_REG REG_MM(0x00E0)
262#define ROT_NS_REG REG_MM(0x00E8)
263#define SAXI_EN_REG REG_MM(0x0030)
264#define SW_RESET_AHB_REG REG_MM(0x020C)
265#define SW_RESET_AHB2_REG REG_MM(0x0200)
266#define SW_RESET_ALL_REG REG_MM(0x0204)
267#define SW_RESET_AXI_REG REG_MM(0x0208)
268#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700269#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700270#define TV_CC_REG REG_MM(0x00EC)
271#define TV_CC2_REG REG_MM(0x0124)
272#define TV_MD_REG REG_MM(0x00F0)
273#define TV_NS_REG REG_MM(0x00F4)
274#define VCODEC_CC_REG REG_MM(0x00F8)
275#define VCODEC_MD0_REG REG_MM(0x00FC)
276#define VCODEC_MD1_REG REG_MM(0x0128)
277#define VCODEC_NS_REG REG_MM(0x0100)
278#define VFE_CC_REG REG_MM(0x0104)
279#define VFE_MD_REG REG_MM(0x0108)
280#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700281#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700282#define VPE_CC_REG REG_MM(0x0110)
283#define VPE_NS_REG REG_MM(0x0118)
284
285/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700286#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700287#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
288#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
289#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
290#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
291#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
292#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
293#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
294#define LCC_MI2S_MD_REG REG_LPA(0x004C)
295#define LCC_MI2S_NS_REG REG_LPA(0x0048)
296#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
297#define LCC_PCM_MD_REG REG_LPA(0x0058)
298#define LCC_PCM_NS_REG REG_LPA(0x0054)
299#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700300#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
301#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
302#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
303#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
304#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700305#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700306#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
307#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
308#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
309#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
310#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
311#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
312#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
313#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
314#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
315#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700316#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700317
Matt Wagantall8b38f942011-08-02 18:23:18 -0700318#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
319
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700320/* MUX source input identifiers. */
321#define pxo_to_bb_mux 0
322#define cxo_to_bb_mux pxo_to_bb_mux
323#define pll0_to_bb_mux 2
324#define pll8_to_bb_mux 3
325#define pll6_to_bb_mux 4
326#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700327#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700328#define pxo_to_mm_mux 0
329#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700330#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
331#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700332#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700333#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700334#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700335#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700336#define hdmi_pll_to_mm_mux 3
337#define cxo_to_xo_mux 0
338#define pxo_to_xo_mux 1
339#define gnd_to_xo_mux 3
340#define pxo_to_lpa_mux 0
341#define cxo_to_lpa_mux 1
342#define pll4_to_lpa_mux 2
343#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700344#define pxo_to_pcie_mux 0
345#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700346
347/* Test Vector Macros */
348#define TEST_TYPE_PER_LS 1
349#define TEST_TYPE_PER_HS 2
350#define TEST_TYPE_MM_LS 3
351#define TEST_TYPE_MM_HS 4
352#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700353#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700354#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700355#define TEST_TYPE_SHIFT 24
356#define TEST_CLK_SEL_MASK BM(23, 0)
357#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
358#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
359#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
360#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
361#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
362#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700363#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700364#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700365
366#define MN_MODE_DUAL_EDGE 0x2
367
368/* MD Registers */
369#define MD4(m_lsb, m, n_lsb, n) \
370 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
371#define MD8(m_lsb, m, n_lsb, n) \
372 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
373#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
374
375/* NS Registers */
376#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
377 (BVAL(n_msb, n_lsb, ~(n-m)) \
378 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
379 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
380
381#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
382 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
383 | BVAL(s_msb, s_lsb, s))
384
385#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
386 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
387
388#define NS_DIV(d_msb , d_lsb, d) \
389 BVAL(d_msb, d_lsb, (d-1))
390
391#define NS_SRC_SEL(s_msb, s_lsb, s) \
392 BVAL(s_msb, s_lsb, s)
393
394#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
395 (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
396 | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
397 | BVAL((s0_lsb+2), s0_lsb, s) \
398 | BVAL((s1_lsb+2), s1_lsb, s))
399
400#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
401 (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
402 | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
403 | BVAL((s0_lsb+2), s0_lsb, s) \
404 | BVAL((s1_lsb+2), s1_lsb, s))
405
406#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
407 s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
408 (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
409 | BVAL(s0_msb, s0_lsb, s) \
410 | BVAL(s1_msb, s1_lsb, s))
411
412/* CC Registers */
413#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
414#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
415 ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
416 | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
417 * !!(n))
418
419struct pll_rate {
420 const uint32_t l_val;
421 const uint32_t m_val;
422 const uint32_t n_val;
423 const uint32_t vco;
424 const uint32_t post_div;
425 const uint32_t i_bits;
426};
427#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
428
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700429enum vdd_dig_levels {
430 VDD_DIG_NONE,
431 VDD_DIG_LOW,
432 VDD_DIG_NOMINAL,
433 VDD_DIG_HIGH
434};
435
436static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
437{
438 static const int vdd_uv[] = {
439 [VDD_DIG_NONE] = 0,
440 [VDD_DIG_LOW] = 945000,
441 [VDD_DIG_NOMINAL] = 1050000,
442 [VDD_DIG_HIGH] = 1150000
443 };
444
445 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
446 vdd_uv[level], 1150000, 1);
447}
448
449static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig);
450
451#define VDD_DIG_FMAX_MAP1(l1, f1) \
452 .vdd_class = &vdd_dig, \
453 .fmax[VDD_DIG_##l1] = (f1)
454#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
455 .vdd_class = &vdd_dig, \
456 .fmax[VDD_DIG_##l1] = (f1), \
457 .fmax[VDD_DIG_##l2] = (f2)
458#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
459 .vdd_class = &vdd_dig, \
460 .fmax[VDD_DIG_##l1] = (f1), \
461 .fmax[VDD_DIG_##l2] = (f2), \
462 .fmax[VDD_DIG_##l3] = (f3)
463
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700464/*
465 * Clock Descriptions
466 */
467
468static struct msm_xo_voter *xo_pxo, *xo_cxo;
469
470static int pxo_clk_enable(struct clk *clk)
471{
472 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
473}
474
475static void pxo_clk_disable(struct clk *clk)
476{
Tianyi Gou41515e22011-09-01 19:37:43 -0700477 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700478}
479
480static struct clk_ops clk_ops_pxo = {
481 .enable = pxo_clk_enable,
482 .disable = pxo_clk_disable,
483 .get_rate = fixed_clk_get_rate,
484 .is_local = local_clk_is_local,
485};
486
487static struct fixed_clk pxo_clk = {
488 .rate = 27000000,
489 .c = {
490 .dbg_name = "pxo_clk",
491 .ops = &clk_ops_pxo,
492 CLK_INIT(pxo_clk.c),
493 },
494};
495
496static int cxo_clk_enable(struct clk *clk)
497{
498 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
499}
500
501static void cxo_clk_disable(struct clk *clk)
502{
503 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
504}
505
506static struct clk_ops clk_ops_cxo = {
507 .enable = cxo_clk_enable,
508 .disable = cxo_clk_disable,
509 .get_rate = fixed_clk_get_rate,
510 .is_local = local_clk_is_local,
511};
512
513static struct fixed_clk cxo_clk = {
514 .rate = 19200000,
515 .c = {
516 .dbg_name = "cxo_clk",
517 .ops = &clk_ops_cxo,
518 CLK_INIT(cxo_clk.c),
519 },
520};
521
522static struct pll_clk pll2_clk = {
523 .rate = 800000000,
524 .mode_reg = MM_PLL1_MODE_REG,
525 .parent = &pxo_clk.c,
526 .c = {
527 .dbg_name = "pll2_clk",
528 .ops = &clk_ops_pll,
529 CLK_INIT(pll2_clk.c),
530 },
531};
532
Stephen Boyd94625ef2011-07-12 17:06:01 -0700533static struct pll_clk pll3_clk = {
534 .rate = 1200000000,
535 .mode_reg = BB_MMCC_PLL2_MODE_REG,
536 .parent = &pxo_clk.c,
537 .c = {
538 .dbg_name = "pll3_clk",
539 .ops = &clk_ops_pll,
540 CLK_INIT(pll3_clk.c),
541 },
542};
543
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700544static struct pll_vote_clk pll4_clk = {
545 .rate = 393216000,
546 .en_reg = BB_PLL_ENA_SC0_REG,
547 .en_mask = BIT(4),
548 .status_reg = LCC_PLL0_STATUS_REG,
549 .parent = &pxo_clk.c,
550 .c = {
551 .dbg_name = "pll4_clk",
552 .ops = &clk_ops_pll_vote,
553 CLK_INIT(pll4_clk.c),
554 },
555};
556
557static struct pll_vote_clk pll8_clk = {
558 .rate = 384000000,
559 .en_reg = BB_PLL_ENA_SC0_REG,
560 .en_mask = BIT(8),
561 .status_reg = BB_PLL8_STATUS_REG,
562 .parent = &pxo_clk.c,
563 .c = {
564 .dbg_name = "pll8_clk",
565 .ops = &clk_ops_pll_vote,
566 CLK_INIT(pll8_clk.c),
567 },
568};
569
Stephen Boyd94625ef2011-07-12 17:06:01 -0700570static struct pll_vote_clk pll14_clk = {
571 .rate = 480000000,
572 .en_reg = BB_PLL_ENA_SC0_REG,
573 .en_mask = BIT(14),
574 .status_reg = BB_PLL14_STATUS_REG,
575 .parent = &pxo_clk.c,
576 .c = {
577 .dbg_name = "pll14_clk",
578 .ops = &clk_ops_pll_vote,
579 CLK_INIT(pll14_clk.c),
580 },
581};
582
Tianyi Gou41515e22011-09-01 19:37:43 -0700583static struct pll_clk pll15_clk = {
584 .rate = 975000000,
585 .mode_reg = MM_PLL3_MODE_REG,
586 .parent = &pxo_clk.c,
587 .c = {
588 .dbg_name = "pll15_clk",
589 .ops = &clk_ops_pll,
590 CLK_INIT(pll15_clk.c),
591 },
592};
593
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700594static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
595{
596 return branch_reset(&to_rcg_clk(clk)->b, action);
597}
598
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700599static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700600 .enable = rcg_clk_enable,
601 .disable = rcg_clk_disable,
Matt Wagantall41af0772011-09-17 12:21:39 -0700602 .auto_off = rcg_clk_disable,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700603 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700604 .set_rate = rcg_clk_set_rate,
605 .set_min_rate = rcg_clk_set_min_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700606 .get_rate = rcg_clk_get_rate,
607 .list_rate = rcg_clk_list_rate,
608 .is_enabled = rcg_clk_is_enabled,
609 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700610 .reset = soc_clk_reset,
611 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700612 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700613};
614
615static struct clk_ops clk_ops_branch = {
616 .enable = branch_clk_enable,
617 .disable = branch_clk_disable,
Matt Wagantall41af0772011-09-17 12:21:39 -0700618 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700619 .is_enabled = branch_clk_is_enabled,
620 .reset = branch_clk_reset,
621 .is_local = local_clk_is_local,
622 .get_parent = branch_clk_get_parent,
623 .set_parent = branch_clk_set_parent,
624};
625
626static struct clk_ops clk_ops_reset = {
627 .reset = branch_clk_reset,
628 .is_local = local_clk_is_local,
629};
630
631/* AXI Interfaces */
632static struct branch_clk gmem_axi_clk = {
633 .b = {
634 .ctl_reg = MAXI_EN_REG,
635 .en_mask = BIT(24),
636 .halt_reg = DBG_BUS_VEC_E_REG,
637 .halt_bit = 6,
638 },
639 .c = {
640 .dbg_name = "gmem_axi_clk",
641 .ops = &clk_ops_branch,
642 CLK_INIT(gmem_axi_clk.c),
643 },
644};
645
646static struct branch_clk ijpeg_axi_clk = {
647 .b = {
648 .ctl_reg = MAXI_EN_REG,
649 .en_mask = BIT(21),
650 .reset_reg = SW_RESET_AXI_REG,
651 .reset_mask = BIT(14),
652 .halt_reg = DBG_BUS_VEC_E_REG,
653 .halt_bit = 4,
654 },
655 .c = {
656 .dbg_name = "ijpeg_axi_clk",
657 .ops = &clk_ops_branch,
658 CLK_INIT(ijpeg_axi_clk.c),
659 },
660};
661
662static struct branch_clk imem_axi_clk = {
663 .b = {
664 .ctl_reg = MAXI_EN_REG,
665 .en_mask = BIT(22),
666 .reset_reg = SW_RESET_CORE_REG,
667 .reset_mask = BIT(10),
668 .halt_reg = DBG_BUS_VEC_E_REG,
669 .halt_bit = 7,
670 },
671 .c = {
672 .dbg_name = "imem_axi_clk",
673 .ops = &clk_ops_branch,
674 CLK_INIT(imem_axi_clk.c),
675 },
676};
677
678static struct branch_clk jpegd_axi_clk = {
679 .b = {
680 .ctl_reg = MAXI_EN_REG,
681 .en_mask = BIT(25),
682 .halt_reg = DBG_BUS_VEC_E_REG,
683 .halt_bit = 5,
684 },
685 .c = {
686 .dbg_name = "jpegd_axi_clk",
687 .ops = &clk_ops_branch,
688 CLK_INIT(jpegd_axi_clk.c),
689 },
690};
691
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700692static struct branch_clk vcodec_axi_b_clk = {
693 .b = {
694 .ctl_reg = MAXI_EN4_REG,
695 .en_mask = BIT(23),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700696 .halt_reg = DBG_BUS_VEC_I_REG,
697 .halt_bit = 25,
698 },
699 .c = {
700 .dbg_name = "vcodec_axi_b_clk",
701 .ops = &clk_ops_branch,
702 CLK_INIT(vcodec_axi_b_clk.c),
703 },
704};
705
Matt Wagantall91f42702011-07-14 12:01:15 -0700706static struct branch_clk vcodec_axi_a_clk = {
707 .b = {
708 .ctl_reg = MAXI_EN4_REG,
709 .en_mask = BIT(25),
Matt Wagantall91f42702011-07-14 12:01:15 -0700710 .halt_reg = DBG_BUS_VEC_I_REG,
711 .halt_bit = 26,
712 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700713 .c = {
714 .dbg_name = "vcodec_axi_a_clk",
715 .ops = &clk_ops_branch,
716 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700717 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700718 },
719};
720
721static struct branch_clk vcodec_axi_clk = {
722 .b = {
723 .ctl_reg = MAXI_EN_REG,
724 .en_mask = BIT(19),
725 .reset_reg = SW_RESET_AXI_REG,
Matt Wagantallfe2ee052011-07-14 13:33:44 -0700726 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700727 .halt_reg = DBG_BUS_VEC_E_REG,
728 .halt_bit = 3,
729 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700730 .c = {
731 .dbg_name = "vcodec_axi_clk",
732 .ops = &clk_ops_branch,
733 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700734 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700735 },
736};
737
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700738static struct branch_clk vfe_axi_clk = {
739 .b = {
740 .ctl_reg = MAXI_EN_REG,
741 .en_mask = BIT(18),
742 .reset_reg = SW_RESET_AXI_REG,
743 .reset_mask = BIT(9),
744 .halt_reg = DBG_BUS_VEC_E_REG,
745 .halt_bit = 0,
746 },
747 .c = {
748 .dbg_name = "vfe_axi_clk",
749 .ops = &clk_ops_branch,
750 CLK_INIT(vfe_axi_clk.c),
751 },
752};
753
754static struct branch_clk mdp_axi_clk = {
755 .b = {
756 .ctl_reg = MAXI_EN_REG,
757 .en_mask = BIT(23),
758 .reset_reg = SW_RESET_AXI_REG,
759 .reset_mask = BIT(13),
760 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700761 .halt_bit = 8,
762 },
763 .c = {
764 .dbg_name = "mdp_axi_clk",
765 .ops = &clk_ops_branch,
766 CLK_INIT(mdp_axi_clk.c),
767 },
768};
769
770static struct branch_clk rot_axi_clk = {
771 .b = {
772 .ctl_reg = MAXI_EN2_REG,
773 .en_mask = BIT(24),
774 .reset_reg = SW_RESET_AXI_REG,
775 .reset_mask = BIT(6),
776 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700777 .halt_bit = 2,
778 },
779 .c = {
780 .dbg_name = "rot_axi_clk",
781 .ops = &clk_ops_branch,
782 CLK_INIT(rot_axi_clk.c),
783 },
784};
785
786static struct branch_clk vpe_axi_clk = {
787 .b = {
788 .ctl_reg = MAXI_EN2_REG,
789 .en_mask = BIT(26),
790 .reset_reg = SW_RESET_AXI_REG,
791 .reset_mask = BIT(15),
792 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700793 .halt_bit = 1,
794 },
795 .c = {
796 .dbg_name = "vpe_axi_clk",
797 .ops = &clk_ops_branch,
798 CLK_INIT(vpe_axi_clk.c),
799 },
800};
801
Tianyi Gou41515e22011-09-01 19:37:43 -0700802static struct branch_clk vcap_axi_clk = {
803 .b = {
804 .ctl_reg = MAXI_EN5_REG,
805 .en_mask = BIT(12),
806 .reset_reg = SW_RESET_AXI_REG,
807 .reset_mask = BIT(16),
808 .halt_reg = DBG_BUS_VEC_J_REG,
809 .halt_bit = 20,
810 },
811 .c = {
812 .dbg_name = "vcap_axi_clk",
813 .ops = &clk_ops_branch,
814 CLK_INIT(vcap_axi_clk.c),
815 },
816};
817
Tianyi Gou621f8742011-09-01 21:45:01 -0700818/* For 8064, gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
819static struct branch_clk gfx3d_axi_clk = {
820 .b = {
821 .ctl_reg = MAXI_EN5_REG,
822 .en_mask = BIT(25),
823 .reset_reg = SW_RESET_AXI_REG,
824 .reset_mask = BIT(17),
825 .halt_reg = DBG_BUS_VEC_J_REG,
826 .halt_bit = 30,
827 },
828 .c = {
829 .dbg_name = "gfx3d_axi_clk",
830 .ops = &clk_ops_branch,
831 CLK_INIT(gfx3d_axi_clk.c),
832 },
833};
834
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700835/* AHB Interfaces */
836static struct branch_clk amp_p_clk = {
837 .b = {
838 .ctl_reg = AHB_EN_REG,
839 .en_mask = BIT(24),
840 .halt_reg = DBG_BUS_VEC_F_REG,
841 .halt_bit = 18,
842 },
843 .c = {
844 .dbg_name = "amp_p_clk",
845 .ops = &clk_ops_branch,
846 CLK_INIT(amp_p_clk.c),
847 },
848};
849
Matt Wagantallc23eee92011-08-16 23:06:52 -0700850static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700851 .b = {
852 .ctl_reg = AHB_EN_REG,
853 .en_mask = BIT(7),
854 .reset_reg = SW_RESET_AHB_REG,
855 .reset_mask = BIT(17),
856 .halt_reg = DBG_BUS_VEC_F_REG,
857 .halt_bit = 16,
858 },
859 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700860 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700861 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700862 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700863 },
864};
865
866static struct branch_clk dsi1_m_p_clk = {
867 .b = {
868 .ctl_reg = AHB_EN_REG,
869 .en_mask = BIT(9),
870 .reset_reg = SW_RESET_AHB_REG,
871 .reset_mask = BIT(6),
872 .halt_reg = DBG_BUS_VEC_F_REG,
873 .halt_bit = 19,
874 },
875 .c = {
876 .dbg_name = "dsi1_m_p_clk",
877 .ops = &clk_ops_branch,
878 CLK_INIT(dsi1_m_p_clk.c),
879 },
880};
881
882static struct branch_clk dsi1_s_p_clk = {
883 .b = {
884 .ctl_reg = AHB_EN_REG,
885 .en_mask = BIT(18),
886 .reset_reg = SW_RESET_AHB_REG,
887 .reset_mask = BIT(5),
888 .halt_reg = DBG_BUS_VEC_F_REG,
889 .halt_bit = 21,
890 },
891 .c = {
892 .dbg_name = "dsi1_s_p_clk",
893 .ops = &clk_ops_branch,
894 CLK_INIT(dsi1_s_p_clk.c),
895 },
896};
897
898static struct branch_clk dsi2_m_p_clk = {
899 .b = {
900 .ctl_reg = AHB_EN_REG,
901 .en_mask = BIT(17),
902 .reset_reg = SW_RESET_AHB2_REG,
903 .reset_mask = BIT(1),
904 .halt_reg = DBG_BUS_VEC_E_REG,
905 .halt_bit = 18,
906 },
907 .c = {
908 .dbg_name = "dsi2_m_p_clk",
909 .ops = &clk_ops_branch,
910 CLK_INIT(dsi2_m_p_clk.c),
911 },
912};
913
914static struct branch_clk dsi2_s_p_clk = {
915 .b = {
916 .ctl_reg = AHB_EN_REG,
917 .en_mask = BIT(22),
918 .reset_reg = SW_RESET_AHB2_REG,
919 .reset_mask = BIT(0),
920 .halt_reg = DBG_BUS_VEC_F_REG,
921 .halt_bit = 20,
922 },
923 .c = {
924 .dbg_name = "dsi2_s_p_clk",
925 .ops = &clk_ops_branch,
926 CLK_INIT(dsi2_s_p_clk.c),
927 },
928};
929
930static struct branch_clk gfx2d0_p_clk = {
931 .b = {
932 .ctl_reg = AHB_EN_REG,
933 .en_mask = BIT(19),
934 .reset_reg = SW_RESET_AHB_REG,
935 .reset_mask = BIT(12),
936 .halt_reg = DBG_BUS_VEC_F_REG,
937 .halt_bit = 2,
938 },
939 .c = {
940 .dbg_name = "gfx2d0_p_clk",
941 .ops = &clk_ops_branch,
942 CLK_INIT(gfx2d0_p_clk.c),
943 },
944};
945
946static struct branch_clk gfx2d1_p_clk = {
947 .b = {
948 .ctl_reg = AHB_EN_REG,
949 .en_mask = BIT(2),
950 .reset_reg = SW_RESET_AHB_REG,
951 .reset_mask = BIT(11),
952 .halt_reg = DBG_BUS_VEC_F_REG,
953 .halt_bit = 3,
954 },
955 .c = {
956 .dbg_name = "gfx2d1_p_clk",
957 .ops = &clk_ops_branch,
958 CLK_INIT(gfx2d1_p_clk.c),
959 },
960};
961
962static struct branch_clk gfx3d_p_clk = {
963 .b = {
964 .ctl_reg = AHB_EN_REG,
965 .en_mask = BIT(3),
966 .reset_reg = SW_RESET_AHB_REG,
967 .reset_mask = BIT(10),
968 .halt_reg = DBG_BUS_VEC_F_REG,
969 .halt_bit = 4,
970 },
971 .c = {
972 .dbg_name = "gfx3d_p_clk",
973 .ops = &clk_ops_branch,
974 CLK_INIT(gfx3d_p_clk.c),
975 },
976};
977
978static struct branch_clk hdmi_m_p_clk = {
979 .b = {
980 .ctl_reg = AHB_EN_REG,
981 .en_mask = BIT(14),
982 .reset_reg = SW_RESET_AHB_REG,
983 .reset_mask = BIT(9),
984 .halt_reg = DBG_BUS_VEC_F_REG,
985 .halt_bit = 5,
986 },
987 .c = {
988 .dbg_name = "hdmi_m_p_clk",
989 .ops = &clk_ops_branch,
990 CLK_INIT(hdmi_m_p_clk.c),
991 },
992};
993
994static struct branch_clk hdmi_s_p_clk = {
995 .b = {
996 .ctl_reg = AHB_EN_REG,
997 .en_mask = BIT(4),
998 .reset_reg = SW_RESET_AHB_REG,
999 .reset_mask = BIT(9),
1000 .halt_reg = DBG_BUS_VEC_F_REG,
1001 .halt_bit = 6,
1002 },
1003 .c = {
1004 .dbg_name = "hdmi_s_p_clk",
1005 .ops = &clk_ops_branch,
1006 CLK_INIT(hdmi_s_p_clk.c),
1007 },
1008};
1009
1010static struct branch_clk ijpeg_p_clk = {
1011 .b = {
1012 .ctl_reg = AHB_EN_REG,
1013 .en_mask = BIT(5),
1014 .reset_reg = SW_RESET_AHB_REG,
1015 .reset_mask = BIT(7),
1016 .halt_reg = DBG_BUS_VEC_F_REG,
1017 .halt_bit = 9,
1018 },
1019 .c = {
1020 .dbg_name = "ijpeg_p_clk",
1021 .ops = &clk_ops_branch,
1022 CLK_INIT(ijpeg_p_clk.c),
1023 },
1024};
1025
1026static struct branch_clk imem_p_clk = {
1027 .b = {
1028 .ctl_reg = AHB_EN_REG,
1029 .en_mask = BIT(6),
1030 .reset_reg = SW_RESET_AHB_REG,
1031 .reset_mask = BIT(8),
1032 .halt_reg = DBG_BUS_VEC_F_REG,
1033 .halt_bit = 10,
1034 },
1035 .c = {
1036 .dbg_name = "imem_p_clk",
1037 .ops = &clk_ops_branch,
1038 CLK_INIT(imem_p_clk.c),
1039 },
1040};
1041
1042static struct branch_clk jpegd_p_clk = {
1043 .b = {
1044 .ctl_reg = AHB_EN_REG,
1045 .en_mask = BIT(21),
1046 .reset_reg = SW_RESET_AHB_REG,
1047 .reset_mask = BIT(4),
1048 .halt_reg = DBG_BUS_VEC_F_REG,
1049 .halt_bit = 7,
1050 },
1051 .c = {
1052 .dbg_name = "jpegd_p_clk",
1053 .ops = &clk_ops_branch,
1054 CLK_INIT(jpegd_p_clk.c),
1055 },
1056};
1057
1058static struct branch_clk mdp_p_clk = {
1059 .b = {
1060 .ctl_reg = AHB_EN_REG,
1061 .en_mask = BIT(10),
1062 .reset_reg = SW_RESET_AHB_REG,
1063 .reset_mask = BIT(3),
1064 .halt_reg = DBG_BUS_VEC_F_REG,
1065 .halt_bit = 11,
1066 },
1067 .c = {
1068 .dbg_name = "mdp_p_clk",
1069 .ops = &clk_ops_branch,
1070 CLK_INIT(mdp_p_clk.c),
1071 },
1072};
1073
1074static struct branch_clk rot_p_clk = {
1075 .b = {
1076 .ctl_reg = AHB_EN_REG,
1077 .en_mask = BIT(12),
1078 .reset_reg = SW_RESET_AHB_REG,
1079 .reset_mask = BIT(2),
1080 .halt_reg = DBG_BUS_VEC_F_REG,
1081 .halt_bit = 13,
1082 },
1083 .c = {
1084 .dbg_name = "rot_p_clk",
1085 .ops = &clk_ops_branch,
1086 CLK_INIT(rot_p_clk.c),
1087 },
1088};
1089
1090static struct branch_clk smmu_p_clk = {
1091 .b = {
1092 .ctl_reg = AHB_EN_REG,
1093 .en_mask = BIT(15),
1094 .halt_reg = DBG_BUS_VEC_F_REG,
1095 .halt_bit = 22,
1096 },
1097 .c = {
1098 .dbg_name = "smmu_p_clk",
1099 .ops = &clk_ops_branch,
1100 CLK_INIT(smmu_p_clk.c),
1101 },
1102};
1103
1104static struct branch_clk tv_enc_p_clk = {
1105 .b = {
1106 .ctl_reg = AHB_EN_REG,
1107 .en_mask = BIT(25),
1108 .reset_reg = SW_RESET_AHB_REG,
1109 .reset_mask = BIT(15),
1110 .halt_reg = DBG_BUS_VEC_F_REG,
1111 .halt_bit = 23,
1112 },
1113 .c = {
1114 .dbg_name = "tv_enc_p_clk",
1115 .ops = &clk_ops_branch,
1116 CLK_INIT(tv_enc_p_clk.c),
1117 },
1118};
1119
1120static struct branch_clk vcodec_p_clk = {
1121 .b = {
1122 .ctl_reg = AHB_EN_REG,
1123 .en_mask = BIT(11),
1124 .reset_reg = SW_RESET_AHB_REG,
1125 .reset_mask = BIT(1),
1126 .halt_reg = DBG_BUS_VEC_F_REG,
1127 .halt_bit = 12,
1128 },
1129 .c = {
1130 .dbg_name = "vcodec_p_clk",
1131 .ops = &clk_ops_branch,
1132 CLK_INIT(vcodec_p_clk.c),
1133 },
1134};
1135
1136static struct branch_clk vfe_p_clk = {
1137 .b = {
1138 .ctl_reg = AHB_EN_REG,
1139 .en_mask = BIT(13),
1140 .reset_reg = SW_RESET_AHB_REG,
1141 .reset_mask = BIT(0),
1142 .halt_reg = DBG_BUS_VEC_F_REG,
1143 .halt_bit = 14,
1144 },
1145 .c = {
1146 .dbg_name = "vfe_p_clk",
1147 .ops = &clk_ops_branch,
1148 CLK_INIT(vfe_p_clk.c),
1149 },
1150};
1151
1152static struct branch_clk vpe_p_clk = {
1153 .b = {
1154 .ctl_reg = AHB_EN_REG,
1155 .en_mask = BIT(16),
1156 .reset_reg = SW_RESET_AHB_REG,
1157 .reset_mask = BIT(14),
1158 .halt_reg = DBG_BUS_VEC_F_REG,
1159 .halt_bit = 15,
1160 },
1161 .c = {
1162 .dbg_name = "vpe_p_clk",
1163 .ops = &clk_ops_branch,
1164 CLK_INIT(vpe_p_clk.c),
1165 },
1166};
1167
Tianyi Gou41515e22011-09-01 19:37:43 -07001168static struct branch_clk vcap_p_clk = {
1169 .b = {
1170 .ctl_reg = AHB_EN3_REG,
1171 .en_mask = BIT(1),
1172 .reset_reg = SW_RESET_AHB2_REG,
1173 .reset_mask = BIT(2),
1174 .halt_reg = DBG_BUS_VEC_J_REG,
1175 .halt_bit = 23,
1176 },
1177 .c = {
1178 .dbg_name = "vcap_p_clk",
1179 .ops = &clk_ops_branch,
1180 CLK_INIT(vcap_p_clk.c),
1181 },
1182};
1183
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001184/*
1185 * Peripheral Clocks
1186 */
1187#define CLK_GSBI_UART(i, n, h_r, h_b) \
1188 struct rcg_clk i##_clk = { \
1189 .b = { \
1190 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1191 .en_mask = BIT(9), \
1192 .reset_reg = GSBIn_RESET_REG(n), \
1193 .reset_mask = BIT(0), \
1194 .halt_reg = h_r, \
1195 .halt_bit = h_b, \
1196 }, \
1197 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1198 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1199 .root_en_mask = BIT(11), \
1200 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1201 .set_rate = set_rate_mnd, \
1202 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001203 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001204 .c = { \
1205 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001206 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001207 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001208 CLK_INIT(i##_clk.c), \
1209 }, \
1210 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001211#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001212 { \
1213 .freq_hz = f, \
1214 .src_clk = &s##_clk.c, \
1215 .md_val = MD16(m, n), \
1216 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1217 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001218 }
1219static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001220 F_GSBI_UART( 0, gnd, 1, 0, 0),
1221 F_GSBI_UART( 1843200, pll8, 1, 3, 625),
1222 F_GSBI_UART( 3686400, pll8, 1, 6, 625),
1223 F_GSBI_UART( 7372800, pll8, 1, 12, 625),
1224 F_GSBI_UART(14745600, pll8, 1, 24, 625),
1225 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1226 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1227 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1228 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1229 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1230 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1231 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1232 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1233 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1234 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001235 F_END
1236};
1237
1238static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1239static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1240static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1241static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1242static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1243static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1244static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1245static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1246static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1247static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1248static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1249static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1250
1251#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1252 struct rcg_clk i##_clk = { \
1253 .b = { \
1254 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1255 .en_mask = BIT(9), \
1256 .reset_reg = GSBIn_RESET_REG(n), \
1257 .reset_mask = BIT(0), \
1258 .halt_reg = h_r, \
1259 .halt_bit = h_b, \
1260 }, \
1261 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1262 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1263 .root_en_mask = BIT(11), \
1264 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1265 .set_rate = set_rate_mnd, \
1266 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001267 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001268 .c = { \
1269 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001270 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001271 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001272 CLK_INIT(i##_clk.c), \
1273 }, \
1274 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001275#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001276 { \
1277 .freq_hz = f, \
1278 .src_clk = &s##_clk.c, \
1279 .md_val = MD8(16, m, 0, n), \
1280 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1281 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001282 }
1283static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001284 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1285 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1286 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1287 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1288 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1289 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1290 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1291 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1292 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1293 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001294 F_END
1295};
1296
1297static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1298static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1299static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1300static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1301static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1302static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1303static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1304static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1305static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1306static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1307static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1308static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1309
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001310#define F_QDSS(f, s, d) \
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001311 { \
1312 .freq_hz = f, \
1313 .src_clk = &s##_clk.c, \
1314 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001315 }
1316static struct clk_freq_tbl clk_tbl_qdss[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001317 F_QDSS( 27000000, pxo, 1),
1318 F_QDSS(128000000, pll8, 3),
1319 F_QDSS(300000000, pll3, 4),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001320 F_END
1321};
1322
1323struct qdss_bank {
1324 const u32 bank_sel_mask;
1325 void __iomem *const ns_reg;
1326 const u32 ns_mask;
1327};
1328
Stephen Boydd4de6d72011-09-13 13:01:40 -07001329#define QDSS_CLK_ROOT_ENA BIT(1)
1330
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001331static int qdss_clk_handoff(struct clk *c)
Stephen Boydd4de6d72011-09-13 13:01:40 -07001332{
1333 struct rcg_clk *clk = to_rcg_clk(c);
1334 const struct qdss_bank *bank = clk->bank_info;
1335 u32 reg, ns_val, bank_sel;
1336 struct clk_freq_tbl *freq;
1337
1338 reg = readl_relaxed(clk->ns_reg);
1339 if (!(reg & QDSS_CLK_ROOT_ENA))
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001340 return 0;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001341
1342 bank_sel = reg & bank->bank_sel_mask;
1343 /* Force bank 1 to PXO if bank 0 is in use */
1344 if (bank_sel == 0)
1345 writel_relaxed(0, bank->ns_reg);
1346 ns_val = readl_relaxed(bank->ns_reg) & bank->ns_mask;
1347 for (freq = clk->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
1348 if ((freq->ns_val & bank->ns_mask) == ns_val) {
1349 pr_info("%s rate=%d\n", clk->c.dbg_name, freq->freq_hz);
1350 break;
1351 }
1352 }
1353 if (freq->freq_hz == FREQ_END)
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001354 return 0;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001355
1356 clk->current_freq = freq;
Matt Wagantall271a6cd2011-09-20 16:06:31 -07001357
1358 return 1;
Stephen Boydd4de6d72011-09-13 13:01:40 -07001359}
1360
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001361static void set_rate_qdss(struct rcg_clk *clk, struct clk_freq_tbl *nf)
1362{
1363 const struct qdss_bank *bank = clk->bank_info;
1364 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1365
1366 /* Switch to bank 0 (always sourced from PXO) */
1367 reg = readl_relaxed(clk->ns_reg);
1368 reg &= ~bank_sel_mask;
1369 writel_relaxed(reg, clk->ns_reg);
1370 /*
1371 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1372 * MUX to fully switch sources.
1373 */
1374 mb();
1375 udelay(1);
1376
1377 /* Set source and divider */
1378 reg = readl_relaxed(bank->ns_reg);
1379 reg &= ~bank->ns_mask;
1380 reg |= nf->ns_val;
1381 writel_relaxed(reg, bank->ns_reg);
1382
1383 /* Switch to reprogrammed bank */
1384 reg = readl_relaxed(clk->ns_reg);
1385 reg |= bank_sel_mask;
1386 writel_relaxed(reg, clk->ns_reg);
1387 /*
1388 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1389 * MUX to fully switch sources.
1390 */
1391 mb();
1392 udelay(1);
1393}
1394
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001395static int qdss_clk_enable(struct clk *c)
1396{
1397 struct rcg_clk *clk = to_rcg_clk(c);
1398 const struct qdss_bank *bank = clk->bank_info;
1399 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1400 int ret;
1401
1402 /* Switch to bank 1 */
1403 reg = readl_relaxed(clk->ns_reg);
1404 reg |= bank_sel_mask;
1405 writel_relaxed(reg, clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001406
1407 ret = rcg_clk_enable(c);
1408 if (ret) {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001409 /* Switch to bank 0 */
1410 reg &= ~bank_sel_mask;
1411 writel_relaxed(reg, clk->ns_reg);
1412 }
1413 return ret;
1414}
1415
1416static void qdss_clk_disable(struct clk *c)
1417{
1418 struct rcg_clk *clk = to_rcg_clk(c);
1419 const struct qdss_bank *bank = clk->bank_info;
1420 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1421
1422 rcg_clk_disable(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001423 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001424 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001425 reg &= ~bank_sel_mask;
1426 writel_relaxed(reg, clk->ns_reg);
1427}
1428
1429static void qdss_clk_auto_off(struct clk *c)
1430{
1431 struct rcg_clk *clk = to_rcg_clk(c);
1432 const struct qdss_bank *bank = clk->bank_info;
1433 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1434
Matt Wagantall41af0772011-09-17 12:21:39 -07001435 rcg_clk_disable(c);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001436 /* Switch to bank 0 */
Stephen Boyddbeca472011-09-12 19:21:22 -07001437 reg = readl_relaxed(clk->ns_reg);
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001438 reg &= ~bank_sel_mask;
1439 writel_relaxed(reg, clk->ns_reg);
1440}
1441
1442static struct clk_ops clk_ops_qdss = {
1443 .enable = qdss_clk_enable,
1444 .disable = qdss_clk_disable,
1445 .auto_off = qdss_clk_auto_off,
Stephen Boydd4de6d72011-09-13 13:01:40 -07001446 .handoff = qdss_clk_handoff,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001447 .set_rate = rcg_clk_set_rate,
1448 .set_min_rate = rcg_clk_set_min_rate,
1449 .get_rate = rcg_clk_get_rate,
1450 .list_rate = rcg_clk_list_rate,
1451 .is_enabled = rcg_clk_is_enabled,
1452 .round_rate = rcg_clk_round_rate,
1453 .reset = soc_clk_reset,
1454 .is_local = local_clk_is_local,
1455 .get_parent = rcg_clk_get_parent,
1456};
1457
1458static struct qdss_bank bdiv_info_qdss = {
1459 .bank_sel_mask = BIT(0),
1460 .ns_reg = QDSS_AT_CLK_SRC1_NS_REG,
1461 .ns_mask = BM(6, 0),
1462};
1463
1464static struct rcg_clk qdss_at_clk = {
1465 .b = {
1466 .ctl_reg = QDSS_AT_CLK_NS_REG,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001467 .reset_reg = QDSS_RESETS_REG,
1468 .reset_mask = BIT(0),
Stephen Boydfcfd4dd2011-09-13 12:49:57 -07001469 .halt_check = NOCHECK,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001470 },
1471 .ns_reg = QDSS_AT_CLK_SRC_CTL_REG,
1472 .set_rate = set_rate_qdss,
1473 .freq_tbl = clk_tbl_qdss,
1474 .bank_info = &bdiv_info_qdss,
1475 .current_freq = &rcg_dummy_freq,
1476 .c = {
1477 .dbg_name = "qdss_at_clk",
1478 .ops = &clk_ops_qdss,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001479 VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001480 CLK_INIT(qdss_at_clk.c),
1481 },
1482};
1483
1484static struct branch_clk qdss_pclkdbg_clk = {
1485 .b = {
1486 .ctl_reg = QDSS_AT_CLK_NS_REG,
1487 .en_mask = BIT(4),
1488 .reset_reg = QDSS_RESETS_REG,
1489 .reset_mask = BIT(0),
1490 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1491 .halt_bit = 9,
1492 .halt_check = HALT_VOTED
1493 },
1494 .parent = &qdss_at_clk.c,
1495 .c = {
1496 .dbg_name = "qdss_pclkdbg_clk",
1497 .ops = &clk_ops_branch,
1498 CLK_INIT(qdss_pclkdbg_clk.c),
1499 },
1500};
1501
1502static struct qdss_bank bdiv_info_qdss_trace = {
1503 .bank_sel_mask = BIT(0),
1504 .ns_reg = QDSS_TRACECLKIN_CLK_SRC1_NS_REG,
1505 .ns_mask = BM(6, 0),
1506};
1507
1508static struct rcg_clk qdss_traceclkin_clk = {
1509 .b = {
1510 .ctl_reg = QDSS_TRACECLKIN_CTL_REG,
1511 .en_mask = BIT(4),
1512 .reset_reg = QDSS_RESETS_REG,
1513 .reset_mask = BIT(0),
1514 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1515 .halt_bit = 8,
1516 .halt_check = HALT_VOTED,
1517 },
1518 .ns_reg = QDSS_TRACECLKIN_CLK_SRC_CTL_REG,
1519 .set_rate = set_rate_qdss,
1520 .freq_tbl = clk_tbl_qdss,
1521 .bank_info = &bdiv_info_qdss_trace,
1522 .current_freq = &rcg_dummy_freq,
1523 .c = {
1524 .dbg_name = "qdss_traceclkin_clk",
1525 .ops = &clk_ops_qdss,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001526 VDD_DIG_FMAX_MAP2(LOW, 150000000, NOMINAL, 300000000),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001527 CLK_INIT(qdss_traceclkin_clk.c),
1528 },
1529};
1530
1531static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001532 F_QDSS( 27000000, pxo, 1),
1533 F_QDSS(200000000, pll3, 6),
1534 F_QDSS(400000000, pll3, 3),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001535 F_END
1536};
1537
1538static struct qdss_bank bdiv_info_qdss_tsctr = {
1539 .bank_sel_mask = BIT(0),
1540 .ns_reg = QDSS_TSCTR_CLK_SRC1_NS_REG,
1541 .ns_mask = BM(6, 0),
1542};
1543
1544static struct rcg_clk qdss_tsctr_clk = {
1545 .b = {
1546 .ctl_reg = QDSS_TSCTR_CTL_REG,
1547 .en_mask = BIT(4),
1548 .reset_reg = QDSS_RESETS_REG,
1549 .reset_mask = BIT(3),
1550 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1551 .halt_bit = 7,
1552 .halt_check = HALT_VOTED,
1553 },
1554 .ns_reg = QDSS_TSCTR_CLK_SRC_CTL_REG,
1555 .set_rate = set_rate_qdss,
1556 .freq_tbl = clk_tbl_qdss_tsctr,
1557 .bank_info = &bdiv_info_qdss_tsctr,
1558 .current_freq = &rcg_dummy_freq,
1559 .c = {
1560 .dbg_name = "qdss_tsctr_clk",
1561 .ops = &clk_ops_qdss,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001562 VDD_DIG_FMAX_MAP2(LOW, 200000000, NOMINAL, 400000000),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001563 CLK_INIT(qdss_tsctr_clk.c),
1564 },
1565};
1566
1567static struct branch_clk qdss_stm_clk = {
1568 .b = {
1569 .ctl_reg = QDSS_STM_CLK_CTL_REG,
1570 .en_mask = BIT(4),
1571 .reset_reg = QDSS_RESETS_REG,
1572 .reset_mask = BIT(1),
1573 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1574 .halt_bit = 20,
1575 .halt_check = HALT_VOTED,
1576 },
1577 .c = {
1578 .dbg_name = "qdss_stm_clk",
1579 .ops = &clk_ops_branch,
1580 CLK_INIT(qdss_stm_clk.c),
1581 },
1582};
1583
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001584#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001585 { \
1586 .freq_hz = f, \
1587 .src_clk = &s##_clk.c, \
1588 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001589 }
1590static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001591 F_PDM( 0, gnd, 1),
1592 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001593 F_END
1594};
1595
1596static struct rcg_clk pdm_clk = {
1597 .b = {
1598 .ctl_reg = PDM_CLK_NS_REG,
1599 .en_mask = BIT(9),
1600 .reset_reg = PDM_CLK_NS_REG,
1601 .reset_mask = BIT(12),
1602 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1603 .halt_bit = 3,
1604 },
1605 .ns_reg = PDM_CLK_NS_REG,
1606 .root_en_mask = BIT(11),
1607 .ns_mask = BM(1, 0),
1608 .set_rate = set_rate_nop,
1609 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001610 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001611 .c = {
1612 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001613 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001614 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001615 CLK_INIT(pdm_clk.c),
1616 },
1617};
1618
1619static struct branch_clk pmem_clk = {
1620 .b = {
1621 .ctl_reg = PMEM_ACLK_CTL_REG,
1622 .en_mask = BIT(4),
1623 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1624 .halt_bit = 20,
1625 },
1626 .c = {
1627 .dbg_name = "pmem_clk",
1628 .ops = &clk_ops_branch,
1629 CLK_INIT(pmem_clk.c),
1630 },
1631};
1632
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001633#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001634 { \
1635 .freq_hz = f, \
1636 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001637 }
1638static struct clk_freq_tbl clk_tbl_prng[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001639 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001640 F_END
1641};
1642
1643static struct rcg_clk prng_clk = {
1644 .b = {
1645 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1646 .en_mask = BIT(10),
1647 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1648 .halt_check = HALT_VOTED,
1649 .halt_bit = 10,
1650 },
1651 .set_rate = set_rate_nop,
1652 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001653 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001654 .c = {
1655 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001656 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001657 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001658 CLK_INIT(prng_clk.c),
1659 },
1660};
1661
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001662#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001663 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001664 .b = { \
1665 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1666 .en_mask = BIT(9), \
1667 .reset_reg = SDCn_RESET_REG(n), \
1668 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001669 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001670 .halt_bit = h_b, \
1671 }, \
1672 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1673 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1674 .root_en_mask = BIT(11), \
1675 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1676 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001677 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001678 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001679 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001680 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001681 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001682 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001683 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001684 }, \
1685 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001686#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001687 { \
1688 .freq_hz = f, \
1689 .src_clk = &s##_clk.c, \
1690 .md_val = MD8(16, m, 0, n), \
1691 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1692 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001693 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001694static struct clk_freq_tbl clk_tbl_sdc[] = {
1695 F_SDC( 0, gnd, 1, 0, 0),
1696 F_SDC( 144000, pxo, 3, 2, 125),
1697 F_SDC( 400000, pll8, 4, 1, 240),
1698 F_SDC( 16000000, pll8, 4, 1, 6),
1699 F_SDC( 17070000, pll8, 1, 2, 45),
1700 F_SDC( 20210000, pll8, 1, 1, 19),
1701 F_SDC( 24000000, pll8, 4, 1, 4),
1702 F_SDC( 48000000, pll8, 4, 1, 2),
1703 F_SDC( 64000000, pll8, 3, 1, 2),
1704 F_SDC( 96000000, pll8, 4, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001705 F_END
1706};
1707
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001708static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1709static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1710static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1711static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1712static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001713
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001714#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001715 { \
1716 .freq_hz = f, \
1717 .src_clk = &s##_clk.c, \
1718 .md_val = MD16(m, n), \
1719 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1720 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001721 }
1722static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001723 F_TSIF_REF( 0, gnd, 1, 0, 0),
1724 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001725 F_END
1726};
1727
1728static struct rcg_clk tsif_ref_clk = {
1729 .b = {
1730 .ctl_reg = TSIF_REF_CLK_NS_REG,
1731 .en_mask = BIT(9),
1732 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1733 .halt_bit = 5,
1734 },
1735 .ns_reg = TSIF_REF_CLK_NS_REG,
1736 .md_reg = TSIF_REF_CLK_MD_REG,
1737 .root_en_mask = BIT(11),
1738 .ns_mask = (BM(31, 16) | BM(6, 0)),
1739 .set_rate = set_rate_mnd,
1740 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001741 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001742 .c = {
1743 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001744 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001745 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001746 CLK_INIT(tsif_ref_clk.c),
1747 },
1748};
1749
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001750#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001751 { \
1752 .freq_hz = f, \
1753 .src_clk = &s##_clk.c, \
1754 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001755 }
1756static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001757 F_TSSC( 0, gnd),
1758 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001759 F_END
1760};
1761
1762static struct rcg_clk tssc_clk = {
1763 .b = {
1764 .ctl_reg = TSSC_CLK_CTL_REG,
1765 .en_mask = BIT(4),
1766 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1767 .halt_bit = 4,
1768 },
1769 .ns_reg = TSSC_CLK_CTL_REG,
1770 .ns_mask = BM(1, 0),
1771 .set_rate = set_rate_nop,
1772 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001773 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001774 .c = {
1775 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001776 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001777 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001778 CLK_INIT(tssc_clk.c),
1779 },
1780};
1781
Tianyi Gou41515e22011-09-01 19:37:43 -07001782#define CLK_USB_HS(name, n, h_b) \
1783 static struct rcg_clk name = { \
1784 .b = { \
1785 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1786 .en_mask = BIT(9), \
1787 .reset_reg = USB_HS##n##_RESET_REG, \
1788 .reset_mask = BIT(0), \
1789 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1790 .halt_bit = h_b, \
1791 }, \
1792 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1793 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1794 .root_en_mask = BIT(11), \
1795 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1796 .set_rate = set_rate_mnd, \
1797 .freq_tbl = clk_tbl_usb, \
1798 .current_freq = &rcg_dummy_freq, \
1799 .c = { \
1800 .dbg_name = #name, \
1801 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001802 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001803 CLK_INIT(name.c), \
1804 }, \
1805}
1806
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001807#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001808 { \
1809 .freq_hz = f, \
1810 .src_clk = &s##_clk.c, \
1811 .md_val = MD8(16, m, 0, n), \
1812 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1813 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001814 }
1815static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001816 F_USB( 0, gnd, 1, 0, 0),
1817 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001818 F_END
1819};
1820
Tianyi Gou41515e22011-09-01 19:37:43 -07001821CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1822CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1823CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001824
Stephen Boyd94625ef2011-07-12 17:06:01 -07001825static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001826 F_USB( 0, gnd, 1, 0, 0),
1827 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001828 F_END
1829};
1830
1831static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1832 .b = {
1833 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1834 .en_mask = BIT(9),
1835 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1836 .halt_bit = 26,
1837 },
1838 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1839 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1840 .root_en_mask = BIT(11),
1841 .ns_mask = (BM(23, 16) | BM(6, 0)),
1842 .set_rate = set_rate_mnd,
1843 .freq_tbl = clk_tbl_usb_hsic,
1844 .current_freq = &rcg_dummy_freq,
1845 .c = {
1846 .dbg_name = "usb_hsic_xcvr_fs_clk",
1847 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001848 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001849 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1850 },
1851};
1852
1853static struct branch_clk usb_hsic_system_clk = {
1854 .b = {
1855 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1856 .en_mask = BIT(4),
1857 .reset_reg = USB_HSIC_RESET_REG,
1858 .reset_mask = BIT(0),
1859 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1860 .halt_bit = 24,
1861 },
1862 .parent = &usb_hsic_xcvr_fs_clk.c,
1863 .c = {
1864 .dbg_name = "usb_hsic_system_clk",
1865 .ops = &clk_ops_branch,
1866 CLK_INIT(usb_hsic_system_clk.c),
1867 },
1868};
1869
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001870#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001871 { \
1872 .freq_hz = f, \
1873 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001874 }
1875static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001876 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001877 F_END
1878};
1879
1880static struct rcg_clk usb_hsic_hsic_src_clk = {
1881 .b = {
1882 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1883 .halt_check = NOCHECK,
1884 },
1885 .root_en_mask = BIT(0),
1886 .set_rate = set_rate_nop,
1887 .freq_tbl = clk_tbl_usb2_hsic,
1888 .current_freq = &rcg_dummy_freq,
1889 .c = {
1890 .dbg_name = "usb_hsic_hsic_src_clk",
1891 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001892 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001893 CLK_INIT(usb_hsic_hsic_src_clk.c),
1894 },
1895};
1896
1897static struct branch_clk usb_hsic_hsic_clk = {
1898 .b = {
1899 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1900 .en_mask = BIT(0),
1901 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1902 .halt_bit = 19,
1903 },
1904 .parent = &usb_hsic_hsic_src_clk.c,
1905 .c = {
1906 .dbg_name = "usb_hsic_hsic_clk",
1907 .ops = &clk_ops_branch,
1908 CLK_INIT(usb_hsic_hsic_clk.c),
1909 },
1910};
1911
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001912#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001913 { \
1914 .freq_hz = f, \
1915 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001916 }
1917static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001918 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001919 F_END
1920};
1921
1922static struct rcg_clk usb_hsic_hsio_cal_clk = {
1923 .b = {
1924 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1925 .en_mask = BIT(0),
1926 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1927 .halt_bit = 23,
1928 },
1929 .set_rate = set_rate_nop,
1930 .freq_tbl = clk_tbl_usb_hsio_cal,
1931 .current_freq = &rcg_dummy_freq,
1932 .c = {
1933 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07001934 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001935 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001936 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1937 },
1938};
1939
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001940static struct branch_clk usb_phy0_clk = {
1941 .b = {
1942 .reset_reg = USB_PHY0_RESET_REG,
1943 .reset_mask = BIT(0),
1944 },
1945 .c = {
1946 .dbg_name = "usb_phy0_clk",
1947 .ops = &clk_ops_reset,
1948 CLK_INIT(usb_phy0_clk.c),
1949 },
1950};
1951
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001952#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001953 struct rcg_clk i##_clk = { \
1954 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1955 .b = { \
1956 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1957 .halt_check = NOCHECK, \
1958 }, \
1959 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1960 .root_en_mask = BIT(11), \
1961 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1962 .set_rate = set_rate_mnd, \
1963 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001964 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001965 .c = { \
1966 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001967 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001968 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001969 CLK_INIT(i##_clk.c), \
1970 }, \
1971 }
1972
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001973static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001974static struct branch_clk usb_fs1_xcvr_clk = {
1975 .b = {
1976 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1977 .en_mask = BIT(9),
1978 .reset_reg = USB_FSn_RESET_REG(1),
1979 .reset_mask = BIT(1),
1980 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1981 .halt_bit = 15,
1982 },
1983 .parent = &usb_fs1_src_clk.c,
1984 .c = {
1985 .dbg_name = "usb_fs1_xcvr_clk",
1986 .ops = &clk_ops_branch,
1987 CLK_INIT(usb_fs1_xcvr_clk.c),
1988 },
1989};
1990
1991static struct branch_clk usb_fs1_sys_clk = {
1992 .b = {
1993 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1994 .en_mask = BIT(4),
1995 .reset_reg = USB_FSn_RESET_REG(1),
1996 .reset_mask = BIT(0),
1997 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1998 .halt_bit = 16,
1999 },
2000 .parent = &usb_fs1_src_clk.c,
2001 .c = {
2002 .dbg_name = "usb_fs1_sys_clk",
2003 .ops = &clk_ops_branch,
2004 CLK_INIT(usb_fs1_sys_clk.c),
2005 },
2006};
2007
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002008static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002009static struct branch_clk usb_fs2_xcvr_clk = {
2010 .b = {
2011 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
2012 .en_mask = BIT(9),
2013 .reset_reg = USB_FSn_RESET_REG(2),
2014 .reset_mask = BIT(1),
2015 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2016 .halt_bit = 12,
2017 },
2018 .parent = &usb_fs2_src_clk.c,
2019 .c = {
2020 .dbg_name = "usb_fs2_xcvr_clk",
2021 .ops = &clk_ops_branch,
2022 CLK_INIT(usb_fs2_xcvr_clk.c),
2023 },
2024};
2025
2026static struct branch_clk usb_fs2_sys_clk = {
2027 .b = {
2028 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
2029 .en_mask = BIT(4),
2030 .reset_reg = USB_FSn_RESET_REG(2),
2031 .reset_mask = BIT(0),
2032 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2033 .halt_bit = 13,
2034 },
2035 .parent = &usb_fs2_src_clk.c,
2036 .c = {
2037 .dbg_name = "usb_fs2_sys_clk",
2038 .ops = &clk_ops_branch,
2039 CLK_INIT(usb_fs2_sys_clk.c),
2040 },
2041};
2042
2043/* Fast Peripheral Bus Clocks */
2044static struct branch_clk ce1_core_clk = {
2045 .b = {
2046 .ctl_reg = CE1_CORE_CLK_CTL_REG,
2047 .en_mask = BIT(4),
2048 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2049 .halt_bit = 27,
2050 },
2051 .c = {
2052 .dbg_name = "ce1_core_clk",
2053 .ops = &clk_ops_branch,
2054 CLK_INIT(ce1_core_clk.c),
2055 },
2056};
Tianyi Gou41515e22011-09-01 19:37:43 -07002057
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002058static struct branch_clk ce1_p_clk = {
2059 .b = {
2060 .ctl_reg = CE1_HCLK_CTL_REG,
2061 .en_mask = BIT(4),
2062 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2063 .halt_bit = 1,
2064 },
2065 .c = {
2066 .dbg_name = "ce1_p_clk",
2067 .ops = &clk_ops_branch,
2068 CLK_INIT(ce1_p_clk.c),
2069 },
2070};
2071
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002072#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07002073 { \
2074 .freq_hz = f, \
2075 .src_clk = &s##_clk.c, \
2076 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07002077 }
2078
2079static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002080 F_CE3( 0, gnd, 1),
2081 F_CE3( 48000000, pll8, 8),
2082 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07002083 F_END
2084};
2085
2086static struct rcg_clk ce3_src_clk = {
2087 .b = {
2088 .ctl_reg = CE3_CLK_SRC_NS_REG,
2089 .halt_check = NOCHECK,
2090 },
2091 .ns_reg = CE3_CLK_SRC_NS_REG,
2092 .root_en_mask = BIT(7),
2093 .ns_mask = BM(6, 0),
2094 .set_rate = set_rate_nop,
2095 .freq_tbl = clk_tbl_ce3,
2096 .current_freq = &rcg_dummy_freq,
2097 .c = {
2098 .dbg_name = "ce3_src_clk",
2099 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002100 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07002101 CLK_INIT(ce3_src_clk.c),
2102 },
2103};
2104
2105static struct branch_clk ce3_core_clk = {
2106 .b = {
2107 .ctl_reg = CE3_CORE_CLK_CTL_REG,
2108 .en_mask = BIT(4),
2109 .reset_reg = CE3_CORE_CLK_CTL_REG,
2110 .reset_mask = BIT(7),
2111 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2112 .halt_bit = 5,
2113 },
2114 .parent = &ce3_src_clk.c,
2115 .c = {
2116 .dbg_name = "ce3_core_clk",
2117 .ops = &clk_ops_branch,
2118 CLK_INIT(ce3_core_clk.c),
2119 }
2120};
2121
2122static struct branch_clk ce3_p_clk = {
2123 .b = {
2124 .ctl_reg = CE3_HCLK_CTL_REG,
2125 .en_mask = BIT(4),
2126 .reset_reg = CE3_HCLK_CTL_REG,
2127 .reset_mask = BIT(7),
2128 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
2129 .halt_bit = 16,
2130 },
2131 .parent = &ce3_src_clk.c,
2132 .c = {
2133 .dbg_name = "ce3_p_clk",
2134 .ops = &clk_ops_branch,
2135 CLK_INIT(ce3_p_clk.c),
2136 }
2137};
2138
2139static struct branch_clk sata_phy_ref_clk = {
2140 .b = {
2141 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
2142 .en_mask = BIT(4),
2143 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2144 .halt_bit = 24,
2145 },
2146 .parent = &pxo_clk.c,
2147 .c = {
2148 .dbg_name = "sata_phy_ref_clk",
2149 .ops = &clk_ops_branch,
2150 CLK_INIT(sata_phy_ref_clk.c),
2151 },
2152};
2153
2154static struct branch_clk pcie_p_clk = {
2155 .b = {
2156 .ctl_reg = PCIE_HCLK_CTL_REG,
2157 .en_mask = BIT(4),
2158 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2159 .halt_bit = 8,
2160 },
2161 .c = {
2162 .dbg_name = "pcie_p_clk",
2163 .ops = &clk_ops_branch,
2164 CLK_INIT(pcie_p_clk.c),
2165 },
2166};
2167
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002168static struct branch_clk dma_bam_p_clk = {
2169 .b = {
2170 .ctl_reg = DMA_BAM_HCLK_CTL,
2171 .en_mask = BIT(4),
2172 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2173 .halt_bit = 12,
2174 },
2175 .c = {
2176 .dbg_name = "dma_bam_p_clk",
2177 .ops = &clk_ops_branch,
2178 CLK_INIT(dma_bam_p_clk.c),
2179 },
2180};
2181
2182static struct branch_clk gsbi1_p_clk = {
2183 .b = {
2184 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
2185 .en_mask = BIT(4),
2186 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2187 .halt_bit = 11,
2188 },
2189 .c = {
2190 .dbg_name = "gsbi1_p_clk",
2191 .ops = &clk_ops_branch,
2192 CLK_INIT(gsbi1_p_clk.c),
2193 },
2194};
2195
2196static struct branch_clk gsbi2_p_clk = {
2197 .b = {
2198 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2199 .en_mask = BIT(4),
2200 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2201 .halt_bit = 7,
2202 },
2203 .c = {
2204 .dbg_name = "gsbi2_p_clk",
2205 .ops = &clk_ops_branch,
2206 CLK_INIT(gsbi2_p_clk.c),
2207 },
2208};
2209
2210static struct branch_clk gsbi3_p_clk = {
2211 .b = {
2212 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2213 .en_mask = BIT(4),
2214 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2215 .halt_bit = 3,
2216 },
2217 .c = {
2218 .dbg_name = "gsbi3_p_clk",
2219 .ops = &clk_ops_branch,
2220 CLK_INIT(gsbi3_p_clk.c),
2221 },
2222};
2223
2224static struct branch_clk gsbi4_p_clk = {
2225 .b = {
2226 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2227 .en_mask = BIT(4),
2228 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2229 .halt_bit = 27,
2230 },
2231 .c = {
2232 .dbg_name = "gsbi4_p_clk",
2233 .ops = &clk_ops_branch,
2234 CLK_INIT(gsbi4_p_clk.c),
2235 },
2236};
2237
2238static struct branch_clk gsbi5_p_clk = {
2239 .b = {
2240 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2241 .en_mask = BIT(4),
2242 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2243 .halt_bit = 23,
2244 },
2245 .c = {
2246 .dbg_name = "gsbi5_p_clk",
2247 .ops = &clk_ops_branch,
2248 CLK_INIT(gsbi5_p_clk.c),
2249 },
2250};
2251
2252static struct branch_clk gsbi6_p_clk = {
2253 .b = {
2254 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2255 .en_mask = BIT(4),
2256 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2257 .halt_bit = 19,
2258 },
2259 .c = {
2260 .dbg_name = "gsbi6_p_clk",
2261 .ops = &clk_ops_branch,
2262 CLK_INIT(gsbi6_p_clk.c),
2263 },
2264};
2265
2266static struct branch_clk gsbi7_p_clk = {
2267 .b = {
2268 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2269 .en_mask = BIT(4),
2270 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2271 .halt_bit = 15,
2272 },
2273 .c = {
2274 .dbg_name = "gsbi7_p_clk",
2275 .ops = &clk_ops_branch,
2276 CLK_INIT(gsbi7_p_clk.c),
2277 },
2278};
2279
2280static struct branch_clk gsbi8_p_clk = {
2281 .b = {
2282 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2283 .en_mask = BIT(4),
2284 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2285 .halt_bit = 11,
2286 },
2287 .c = {
2288 .dbg_name = "gsbi8_p_clk",
2289 .ops = &clk_ops_branch,
2290 CLK_INIT(gsbi8_p_clk.c),
2291 },
2292};
2293
2294static struct branch_clk gsbi9_p_clk = {
2295 .b = {
2296 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2297 .en_mask = BIT(4),
2298 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2299 .halt_bit = 7,
2300 },
2301 .c = {
2302 .dbg_name = "gsbi9_p_clk",
2303 .ops = &clk_ops_branch,
2304 CLK_INIT(gsbi9_p_clk.c),
2305 },
2306};
2307
2308static struct branch_clk gsbi10_p_clk = {
2309 .b = {
2310 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2311 .en_mask = BIT(4),
2312 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2313 .halt_bit = 3,
2314 },
2315 .c = {
2316 .dbg_name = "gsbi10_p_clk",
2317 .ops = &clk_ops_branch,
2318 CLK_INIT(gsbi10_p_clk.c),
2319 },
2320};
2321
2322static struct branch_clk gsbi11_p_clk = {
2323 .b = {
2324 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2325 .en_mask = BIT(4),
2326 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2327 .halt_bit = 18,
2328 },
2329 .c = {
2330 .dbg_name = "gsbi11_p_clk",
2331 .ops = &clk_ops_branch,
2332 CLK_INIT(gsbi11_p_clk.c),
2333 },
2334};
2335
2336static struct branch_clk gsbi12_p_clk = {
2337 .b = {
2338 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2339 .en_mask = BIT(4),
2340 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2341 .halt_bit = 14,
2342 },
2343 .c = {
2344 .dbg_name = "gsbi12_p_clk",
2345 .ops = &clk_ops_branch,
2346 CLK_INIT(gsbi12_p_clk.c),
2347 },
2348};
2349
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002350static struct branch_clk qdss_p_clk = {
2351 .b = {
2352 .ctl_reg = QDSS_HCLK_CTL_REG,
2353 .en_mask = BIT(4),
2354 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2355 .halt_bit = 11,
2356 .halt_check = HALT_VOTED,
2357 .reset_reg = QDSS_RESETS_REG,
2358 .reset_mask = BIT(2),
2359 },
2360 .c = {
2361 .dbg_name = "qdss_p_clk",
2362 .ops = &clk_ops_branch,
2363 CLK_INIT(qdss_p_clk.c),
Tianyi Gou41515e22011-09-01 19:37:43 -07002364 }
2365};
2366
2367static struct branch_clk sata_phy_cfg_clk = {
2368 .b = {
2369 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2370 .en_mask = BIT(4),
2371 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2372 .halt_bit = 12,
2373 },
2374 .c = {
2375 .dbg_name = "sata_phy_cfg_clk",
2376 .ops = &clk_ops_branch,
2377 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002378 },
2379};
2380
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002381static struct branch_clk tsif_p_clk = {
2382 .b = {
2383 .ctl_reg = TSIF_HCLK_CTL_REG,
2384 .en_mask = BIT(4),
2385 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2386 .halt_bit = 7,
2387 },
2388 .c = {
2389 .dbg_name = "tsif_p_clk",
2390 .ops = &clk_ops_branch,
2391 CLK_INIT(tsif_p_clk.c),
2392 },
2393};
2394
2395static struct branch_clk usb_fs1_p_clk = {
2396 .b = {
2397 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2398 .en_mask = BIT(4),
2399 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2400 .halt_bit = 17,
2401 },
2402 .c = {
2403 .dbg_name = "usb_fs1_p_clk",
2404 .ops = &clk_ops_branch,
2405 CLK_INIT(usb_fs1_p_clk.c),
2406 },
2407};
2408
2409static struct branch_clk usb_fs2_p_clk = {
2410 .b = {
2411 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2412 .en_mask = BIT(4),
2413 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2414 .halt_bit = 14,
2415 },
2416 .c = {
2417 .dbg_name = "usb_fs2_p_clk",
2418 .ops = &clk_ops_branch,
2419 CLK_INIT(usb_fs2_p_clk.c),
2420 },
2421};
2422
2423static struct branch_clk usb_hs1_p_clk = {
2424 .b = {
2425 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2426 .en_mask = BIT(4),
2427 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2428 .halt_bit = 1,
2429 },
2430 .c = {
2431 .dbg_name = "usb_hs1_p_clk",
2432 .ops = &clk_ops_branch,
2433 CLK_INIT(usb_hs1_p_clk.c),
2434 },
2435};
2436
Tianyi Gou41515e22011-09-01 19:37:43 -07002437static struct branch_clk usb_hs3_p_clk = {
2438 .b = {
2439 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2440 .en_mask = BIT(4),
2441 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2442 .halt_bit = 31,
2443 },
2444 .c = {
2445 .dbg_name = "usb_hs3_p_clk",
2446 .ops = &clk_ops_branch,
2447 CLK_INIT(usb_hs3_p_clk.c),
2448 },
2449};
2450
2451static struct branch_clk usb_hs4_p_clk = {
2452 .b = {
2453 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2454 .en_mask = BIT(4),
2455 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2456 .halt_bit = 7,
2457 },
2458 .c = {
2459 .dbg_name = "usb_hs4_p_clk",
2460 .ops = &clk_ops_branch,
2461 CLK_INIT(usb_hs4_p_clk.c),
2462 },
2463};
2464
Stephen Boyd94625ef2011-07-12 17:06:01 -07002465static struct branch_clk usb_hsic_p_clk = {
2466 .b = {
2467 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2468 .en_mask = BIT(4),
2469 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2470 .halt_bit = 28,
2471 },
2472 .c = {
2473 .dbg_name = "usb_hsic_p_clk",
2474 .ops = &clk_ops_branch,
2475 CLK_INIT(usb_hsic_p_clk.c),
2476 },
2477};
2478
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002479static struct branch_clk sdc1_p_clk = {
2480 .b = {
2481 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2482 .en_mask = BIT(4),
2483 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2484 .halt_bit = 11,
2485 },
2486 .c = {
2487 .dbg_name = "sdc1_p_clk",
2488 .ops = &clk_ops_branch,
2489 CLK_INIT(sdc1_p_clk.c),
2490 },
2491};
2492
2493static struct branch_clk sdc2_p_clk = {
2494 .b = {
2495 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2496 .en_mask = BIT(4),
2497 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2498 .halt_bit = 10,
2499 },
2500 .c = {
2501 .dbg_name = "sdc2_p_clk",
2502 .ops = &clk_ops_branch,
2503 CLK_INIT(sdc2_p_clk.c),
2504 },
2505};
2506
2507static struct branch_clk sdc3_p_clk = {
2508 .b = {
2509 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2510 .en_mask = BIT(4),
2511 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2512 .halt_bit = 9,
2513 },
2514 .c = {
2515 .dbg_name = "sdc3_p_clk",
2516 .ops = &clk_ops_branch,
2517 CLK_INIT(sdc3_p_clk.c),
2518 },
2519};
2520
2521static struct branch_clk sdc4_p_clk = {
2522 .b = {
2523 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2524 .en_mask = BIT(4),
2525 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2526 .halt_bit = 8,
2527 },
2528 .c = {
2529 .dbg_name = "sdc4_p_clk",
2530 .ops = &clk_ops_branch,
2531 CLK_INIT(sdc4_p_clk.c),
2532 },
2533};
2534
2535static struct branch_clk sdc5_p_clk = {
2536 .b = {
2537 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2538 .en_mask = BIT(4),
2539 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2540 .halt_bit = 7,
2541 },
2542 .c = {
2543 .dbg_name = "sdc5_p_clk",
2544 .ops = &clk_ops_branch,
2545 CLK_INIT(sdc5_p_clk.c),
2546 },
2547};
2548
2549/* HW-Voteable Clocks */
2550static struct branch_clk adm0_clk = {
2551 .b = {
2552 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2553 .en_mask = BIT(2),
2554 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2555 .halt_check = HALT_VOTED,
2556 .halt_bit = 14,
2557 },
2558 .c = {
2559 .dbg_name = "adm0_clk",
2560 .ops = &clk_ops_branch,
2561 CLK_INIT(adm0_clk.c),
2562 },
2563};
2564
2565static struct branch_clk adm0_p_clk = {
2566 .b = {
2567 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2568 .en_mask = BIT(3),
2569 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2570 .halt_check = HALT_VOTED,
2571 .halt_bit = 13,
2572 },
2573 .c = {
2574 .dbg_name = "adm0_p_clk",
2575 .ops = &clk_ops_branch,
2576 CLK_INIT(adm0_p_clk.c),
2577 },
2578};
2579
2580static struct branch_clk pmic_arb0_p_clk = {
2581 .b = {
2582 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2583 .en_mask = BIT(8),
2584 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2585 .halt_check = HALT_VOTED,
2586 .halt_bit = 22,
2587 },
2588 .c = {
2589 .dbg_name = "pmic_arb0_p_clk",
2590 .ops = &clk_ops_branch,
2591 CLK_INIT(pmic_arb0_p_clk.c),
2592 },
2593};
2594
2595static struct branch_clk pmic_arb1_p_clk = {
2596 .b = {
2597 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2598 .en_mask = BIT(9),
2599 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2600 .halt_check = HALT_VOTED,
2601 .halt_bit = 21,
2602 },
2603 .c = {
2604 .dbg_name = "pmic_arb1_p_clk",
2605 .ops = &clk_ops_branch,
2606 CLK_INIT(pmic_arb1_p_clk.c),
2607 },
2608};
2609
2610static struct branch_clk pmic_ssbi2_clk = {
2611 .b = {
2612 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2613 .en_mask = BIT(7),
2614 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2615 .halt_check = HALT_VOTED,
2616 .halt_bit = 23,
2617 },
2618 .c = {
2619 .dbg_name = "pmic_ssbi2_clk",
2620 .ops = &clk_ops_branch,
2621 CLK_INIT(pmic_ssbi2_clk.c),
2622 },
2623};
2624
2625static struct branch_clk rpm_msg_ram_p_clk = {
2626 .b = {
2627 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2628 .en_mask = BIT(6),
2629 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2630 .halt_check = HALT_VOTED,
2631 .halt_bit = 12,
2632 },
2633 .c = {
2634 .dbg_name = "rpm_msg_ram_p_clk",
2635 .ops = &clk_ops_branch,
2636 CLK_INIT(rpm_msg_ram_p_clk.c),
2637 },
2638};
2639
2640/*
2641 * Multimedia Clocks
2642 */
2643
2644static struct branch_clk amp_clk = {
2645 .b = {
2646 .reset_reg = SW_RESET_CORE_REG,
2647 .reset_mask = BIT(20),
2648 },
2649 .c = {
2650 .dbg_name = "amp_clk",
2651 .ops = &clk_ops_reset,
2652 CLK_INIT(amp_clk.c),
2653 },
2654};
2655
Stephen Boyd94625ef2011-07-12 17:06:01 -07002656#define CLK_CAM(name, n, hb) \
2657 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002658 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002659 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002660 .en_mask = BIT(0), \
2661 .halt_reg = DBG_BUS_VEC_I_REG, \
2662 .halt_bit = hb, \
2663 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002664 .ns_reg = CAMCLK##n##_NS_REG, \
2665 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002666 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002667 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002668 .ctl_mask = BM(7, 6), \
2669 .set_rate = set_rate_mnd_8, \
2670 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002671 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002672 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002673 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002674 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002675 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002676 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002677 }, \
2678 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002679#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002680 { \
2681 .freq_hz = f, \
2682 .src_clk = &s##_clk.c, \
2683 .md_val = MD8(8, m, 0, n), \
2684 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2685 .ctl_val = CC(6, n), \
2686 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002687 }
2688static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002689 F_CAM( 0, gnd, 1, 0, 0),
2690 F_CAM( 6000000, pll8, 4, 1, 16),
2691 F_CAM( 8000000, pll8, 4, 1, 12),
2692 F_CAM( 12000000, pll8, 4, 1, 8),
2693 F_CAM( 16000000, pll8, 4, 1, 6),
2694 F_CAM( 19200000, pll8, 4, 1, 5),
2695 F_CAM( 24000000, pll8, 4, 1, 4),
2696 F_CAM( 32000000, pll8, 4, 1, 3),
2697 F_CAM( 48000000, pll8, 4, 1, 2),
2698 F_CAM( 64000000, pll8, 3, 1, 2),
2699 F_CAM( 96000000, pll8, 4, 0, 0),
2700 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002701 F_END
2702};
2703
Stephen Boyd94625ef2011-07-12 17:06:01 -07002704static CLK_CAM(cam0_clk, 0, 15);
2705static CLK_CAM(cam1_clk, 1, 16);
2706static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002707
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002708#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002709 { \
2710 .freq_hz = f, \
2711 .src_clk = &s##_clk.c, \
2712 .md_val = MD8(8, m, 0, n), \
2713 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2714 .ctl_val = CC(6, n), \
2715 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002716 }
2717static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002718 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002719 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002720 F_CSI( 85330000, pll8, 1, 2, 9),
2721 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002722 F_END
2723};
2724
2725static struct rcg_clk csi0_src_clk = {
2726 .ns_reg = CSI0_NS_REG,
2727 .b = {
2728 .ctl_reg = CSI0_CC_REG,
2729 .halt_check = NOCHECK,
2730 },
2731 .md_reg = CSI0_MD_REG,
2732 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002733 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002734 .ctl_mask = BM(7, 6),
2735 .set_rate = set_rate_mnd,
2736 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002737 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002738 .c = {
2739 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002740 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002741 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002742 CLK_INIT(csi0_src_clk.c),
2743 },
2744};
2745
2746static struct branch_clk csi0_clk = {
2747 .b = {
2748 .ctl_reg = CSI0_CC_REG,
2749 .en_mask = BIT(0),
2750 .reset_reg = SW_RESET_CORE_REG,
2751 .reset_mask = BIT(8),
2752 .halt_reg = DBG_BUS_VEC_B_REG,
2753 .halt_bit = 13,
2754 },
2755 .parent = &csi0_src_clk.c,
2756 .c = {
2757 .dbg_name = "csi0_clk",
2758 .ops = &clk_ops_branch,
2759 CLK_INIT(csi0_clk.c),
2760 },
2761};
2762
2763static struct branch_clk csi0_phy_clk = {
2764 .b = {
2765 .ctl_reg = CSI0_CC_REG,
2766 .en_mask = BIT(8),
2767 .reset_reg = SW_RESET_CORE_REG,
2768 .reset_mask = BIT(29),
2769 .halt_reg = DBG_BUS_VEC_I_REG,
2770 .halt_bit = 9,
2771 },
2772 .parent = &csi0_src_clk.c,
2773 .c = {
2774 .dbg_name = "csi0_phy_clk",
2775 .ops = &clk_ops_branch,
2776 CLK_INIT(csi0_phy_clk.c),
2777 },
2778};
2779
2780static struct rcg_clk csi1_src_clk = {
2781 .ns_reg = CSI1_NS_REG,
2782 .b = {
2783 .ctl_reg = CSI1_CC_REG,
2784 .halt_check = NOCHECK,
2785 },
2786 .md_reg = CSI1_MD_REG,
2787 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002788 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002789 .ctl_mask = BM(7, 6),
2790 .set_rate = set_rate_mnd,
2791 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002792 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002793 .c = {
2794 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002795 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002796 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002797 CLK_INIT(csi1_src_clk.c),
2798 },
2799};
2800
2801static struct branch_clk csi1_clk = {
2802 .b = {
2803 .ctl_reg = CSI1_CC_REG,
2804 .en_mask = BIT(0),
2805 .reset_reg = SW_RESET_CORE_REG,
2806 .reset_mask = BIT(18),
2807 .halt_reg = DBG_BUS_VEC_B_REG,
2808 .halt_bit = 14,
2809 },
2810 .parent = &csi1_src_clk.c,
2811 .c = {
2812 .dbg_name = "csi1_clk",
2813 .ops = &clk_ops_branch,
2814 CLK_INIT(csi1_clk.c),
2815 },
2816};
2817
2818static struct branch_clk csi1_phy_clk = {
2819 .b = {
2820 .ctl_reg = CSI1_CC_REG,
2821 .en_mask = BIT(8),
2822 .reset_reg = SW_RESET_CORE_REG,
2823 .reset_mask = BIT(28),
2824 .halt_reg = DBG_BUS_VEC_I_REG,
2825 .halt_bit = 10,
2826 },
2827 .parent = &csi1_src_clk.c,
2828 .c = {
2829 .dbg_name = "csi1_phy_clk",
2830 .ops = &clk_ops_branch,
2831 CLK_INIT(csi1_phy_clk.c),
2832 },
2833};
2834
Stephen Boyd94625ef2011-07-12 17:06:01 -07002835static struct rcg_clk csi2_src_clk = {
2836 .ns_reg = CSI2_NS_REG,
2837 .b = {
2838 .ctl_reg = CSI2_CC_REG,
2839 .halt_check = NOCHECK,
2840 },
2841 .md_reg = CSI2_MD_REG,
2842 .root_en_mask = BIT(2),
2843 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2844 .ctl_mask = BM(7, 6),
2845 .set_rate = set_rate_mnd,
2846 .freq_tbl = clk_tbl_csi,
2847 .current_freq = &rcg_dummy_freq,
2848 .c = {
2849 .dbg_name = "csi2_src_clk",
2850 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002851 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002852 CLK_INIT(csi2_src_clk.c),
2853 },
2854};
2855
2856static struct branch_clk csi2_clk = {
2857 .b = {
2858 .ctl_reg = CSI2_CC_REG,
2859 .en_mask = BIT(0),
2860 .reset_reg = SW_RESET_CORE2_REG,
2861 .reset_mask = BIT(2),
2862 .halt_reg = DBG_BUS_VEC_B_REG,
2863 .halt_bit = 29,
2864 },
2865 .parent = &csi2_src_clk.c,
2866 .c = {
2867 .dbg_name = "csi2_clk",
2868 .ops = &clk_ops_branch,
2869 CLK_INIT(csi2_clk.c),
2870 },
2871};
2872
2873static struct branch_clk csi2_phy_clk = {
2874 .b = {
2875 .ctl_reg = CSI2_CC_REG,
2876 .en_mask = BIT(8),
2877 .reset_reg = SW_RESET_CORE_REG,
2878 .reset_mask = BIT(31),
2879 .halt_reg = DBG_BUS_VEC_I_REG,
2880 .halt_bit = 29,
2881 },
2882 .parent = &csi2_src_clk.c,
2883 .c = {
2884 .dbg_name = "csi2_phy_clk",
2885 .ops = &clk_ops_branch,
2886 CLK_INIT(csi2_phy_clk.c),
2887 },
2888};
2889
Stephen Boyd092fd182011-10-21 15:56:30 -07002890static struct clk *pix_rdi_mux_map[] = {
2891 [0] = &csi0_clk.c,
2892 [1] = &csi1_clk.c,
2893 [2] = &csi2_clk.c,
2894 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002895};
2896
Stephen Boyd092fd182011-10-21 15:56:30 -07002897struct pix_rdi_clk {
2898 bool enabled;
2899 unsigned cur_rate;
2900
2901 void __iomem *const s_reg;
2902 u32 s_mask;
2903
2904 void __iomem *const s2_reg;
2905 u32 s2_mask;
2906
2907 struct branch b;
2908 struct clk c;
2909};
2910
2911static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
2912{
2913 return container_of(clk, struct pix_rdi_clk, c);
2914}
2915
2916static int pix_rdi_clk_set_rate(struct clk *c, unsigned rate)
2917{
2918 int ret, i;
2919 u32 reg;
2920 unsigned long flags;
2921 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2922 struct clk **mux_map = pix_rdi_mux_map;
2923
2924 /*
2925 * These clocks select three inputs via two muxes. One mux selects
2926 * between csi0 and csi1 and the second mux selects between that mux's
2927 * output and csi2. The source and destination selections for each
2928 * mux must be clocking for the switch to succeed so just turn on
2929 * all three sources because it's easier than figuring out what source
2930 * needs to be on at what time.
2931 */
2932 for (i = 0; mux_map[i]; i++) {
2933 ret = clk_enable(mux_map[i]);
2934 if (ret)
2935 goto err;
2936 }
2937 if (rate >= i) {
2938 ret = -EINVAL;
2939 goto err;
2940 }
2941 /* Keep the new source on when switching inputs of an enabled clock */
2942 if (clk->enabled) {
2943 clk_disable(mux_map[clk->cur_rate]);
2944 clk_enable(mux_map[rate]);
2945 }
2946 spin_lock_irqsave(&local_clock_reg_lock, flags);
2947 reg = readl_relaxed(clk->s2_reg);
2948 reg &= ~clk->s2_mask;
2949 reg |= rate == 2 ? clk->s2_mask : 0;
2950 writel_relaxed(reg, clk->s2_reg);
2951 /*
2952 * Wait at least 6 cycles of slowest clock
2953 * for the glitch-free MUX to fully switch sources.
2954 */
2955 mb();
2956 udelay(1);
2957 reg = readl_relaxed(clk->s_reg);
2958 reg &= ~clk->s_mask;
2959 reg |= rate == 1 ? clk->s_mask : 0;
2960 writel_relaxed(reg, clk->s_reg);
2961 /*
2962 * Wait at least 6 cycles of slowest clock
2963 * for the glitch-free MUX to fully switch sources.
2964 */
2965 mb();
2966 udelay(1);
2967 clk->cur_rate = rate;
2968 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2969err:
2970 for (i--; i >= 0; i--)
2971 clk_disable(mux_map[i]);
2972
2973 return 0;
2974}
2975
2976static unsigned pix_rdi_clk_get_rate(struct clk *c)
2977{
2978 return to_pix_rdi_clk(c)->cur_rate;
2979}
2980
2981static int pix_rdi_clk_enable(struct clk *c)
2982{
2983 unsigned long flags;
2984 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2985
2986 spin_lock_irqsave(&local_clock_reg_lock, flags);
2987 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
2988 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2989 clk->enabled = true;
2990
2991 return 0;
2992}
2993
2994static void pix_rdi_clk_disable(struct clk *c)
2995{
2996 unsigned long flags;
2997 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2998
2999 spin_lock_irqsave(&local_clock_reg_lock, flags);
3000 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
3001 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3002 clk->enabled = false;
3003}
3004
3005static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
3006{
3007 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
3008}
3009
3010static struct clk *pix_rdi_clk_get_parent(struct clk *c)
3011{
3012 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3013
3014 return pix_rdi_mux_map[clk->cur_rate];
3015}
3016
3017static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
3018{
3019 if (pix_rdi_mux_map[n])
3020 return n;
3021 return -ENXIO;
3022}
3023
3024static int pix_rdi_clk_handoff(struct clk *c)
3025{
3026 u32 reg;
3027 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
3028
3029 reg = readl_relaxed(clk->s_reg);
3030 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
3031 reg = readl_relaxed(clk->s2_reg);
3032 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
3033 return 0;
3034}
3035
3036static struct clk_ops clk_ops_pix_rdi_8960 = {
3037 .enable = pix_rdi_clk_enable,
3038 .disable = pix_rdi_clk_disable,
3039 .auto_off = pix_rdi_clk_disable,
3040 .handoff = pix_rdi_clk_handoff,
3041 .set_rate = pix_rdi_clk_set_rate,
3042 .get_rate = pix_rdi_clk_get_rate,
3043 .list_rate = pix_rdi_clk_list_rate,
3044 .reset = pix_rdi_clk_reset,
3045 .is_local = local_clk_is_local,
3046 .get_parent = pix_rdi_clk_get_parent,
3047};
3048
3049static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003050 .b = {
3051 .ctl_reg = MISC_CC_REG,
3052 .en_mask = BIT(26),
3053 .halt_check = DELAY,
3054 .reset_reg = SW_RESET_CORE_REG,
3055 .reset_mask = BIT(26),
3056 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003057 .s_reg = MISC_CC_REG,
3058 .s_mask = BIT(25),
3059 .s2_reg = MISC_CC3_REG,
3060 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003061 .c = {
3062 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003063 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003064 CLK_INIT(csi_pix_clk.c),
3065 },
3066};
3067
Stephen Boyd092fd182011-10-21 15:56:30 -07003068static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003069 .b = {
3070 .ctl_reg = MISC_CC3_REG,
3071 .en_mask = BIT(10),
3072 .halt_check = DELAY,
3073 .reset_reg = SW_RESET_CORE_REG,
3074 .reset_mask = BIT(30),
3075 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003076 .s_reg = MISC_CC3_REG,
3077 .s_mask = BIT(8),
3078 .s2_reg = MISC_CC3_REG,
3079 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003080 .c = {
3081 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003082 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003083 CLK_INIT(csi_pix1_clk.c),
3084 },
3085};
3086
Stephen Boyd092fd182011-10-21 15:56:30 -07003087static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003088 .b = {
3089 .ctl_reg = MISC_CC_REG,
3090 .en_mask = BIT(13),
3091 .halt_check = DELAY,
3092 .reset_reg = SW_RESET_CORE_REG,
3093 .reset_mask = BIT(27),
3094 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003095 .s_reg = MISC_CC_REG,
3096 .s_mask = BIT(12),
3097 .s2_reg = MISC_CC3_REG,
3098 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003099 .c = {
3100 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003101 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003102 CLK_INIT(csi_rdi_clk.c),
3103 },
3104};
3105
Stephen Boyd092fd182011-10-21 15:56:30 -07003106static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003107 .b = {
3108 .ctl_reg = MISC_CC3_REG,
3109 .en_mask = BIT(2),
3110 .halt_check = DELAY,
3111 .reset_reg = SW_RESET_CORE2_REG,
3112 .reset_mask = BIT(1),
3113 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003114 .s_reg = MISC_CC3_REG,
3115 .s_mask = BIT(0),
3116 .s2_reg = MISC_CC3_REG,
3117 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003118 .c = {
3119 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003120 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003121 CLK_INIT(csi_rdi1_clk.c),
3122 },
3123};
3124
Stephen Boyd092fd182011-10-21 15:56:30 -07003125static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07003126 .b = {
3127 .ctl_reg = MISC_CC3_REG,
3128 .en_mask = BIT(6),
3129 .halt_check = DELAY,
3130 .reset_reg = SW_RESET_CORE2_REG,
3131 .reset_mask = BIT(0),
3132 },
Stephen Boyd092fd182011-10-21 15:56:30 -07003133 .s_reg = MISC_CC3_REG,
3134 .s_mask = BIT(4),
3135 .s2_reg = MISC_CC3_REG,
3136 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003137 .c = {
3138 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07003139 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07003140 CLK_INIT(csi_rdi2_clk.c),
3141 },
3142};
3143
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003144#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003145 { \
3146 .freq_hz = f, \
3147 .src_clk = &s##_clk.c, \
3148 .md_val = MD8(8, m, 0, n), \
3149 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3150 .ctl_val = CC(6, n), \
3151 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003152 }
3153static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003154 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
3155 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
3156 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003157 F_END
3158};
3159
3160static struct rcg_clk csiphy_timer_src_clk = {
3161 .ns_reg = CSIPHYTIMER_NS_REG,
3162 .b = {
3163 .ctl_reg = CSIPHYTIMER_CC_REG,
3164 .halt_check = NOCHECK,
3165 },
3166 .md_reg = CSIPHYTIMER_MD_REG,
3167 .root_en_mask = BIT(2),
3168 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
3169 .ctl_mask = BM(7, 6),
3170 .set_rate = set_rate_mnd_8,
3171 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003172 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003173 .c = {
3174 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003175 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003176 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003177 CLK_INIT(csiphy_timer_src_clk.c),
3178 },
3179};
3180
3181static struct branch_clk csi0phy_timer_clk = {
3182 .b = {
3183 .ctl_reg = CSIPHYTIMER_CC_REG,
3184 .en_mask = BIT(0),
3185 .halt_reg = DBG_BUS_VEC_I_REG,
3186 .halt_bit = 17,
3187 },
3188 .parent = &csiphy_timer_src_clk.c,
3189 .c = {
3190 .dbg_name = "csi0phy_timer_clk",
3191 .ops = &clk_ops_branch,
3192 CLK_INIT(csi0phy_timer_clk.c),
3193 },
3194};
3195
3196static struct branch_clk csi1phy_timer_clk = {
3197 .b = {
3198 .ctl_reg = CSIPHYTIMER_CC_REG,
3199 .en_mask = BIT(9),
3200 .halt_reg = DBG_BUS_VEC_I_REG,
3201 .halt_bit = 18,
3202 },
3203 .parent = &csiphy_timer_src_clk.c,
3204 .c = {
3205 .dbg_name = "csi1phy_timer_clk",
3206 .ops = &clk_ops_branch,
3207 CLK_INIT(csi1phy_timer_clk.c),
3208 },
3209};
3210
Stephen Boyd94625ef2011-07-12 17:06:01 -07003211static struct branch_clk csi2phy_timer_clk = {
3212 .b = {
3213 .ctl_reg = CSIPHYTIMER_CC_REG,
3214 .en_mask = BIT(11),
3215 .halt_reg = DBG_BUS_VEC_I_REG,
3216 .halt_bit = 30,
3217 },
3218 .parent = &csiphy_timer_src_clk.c,
3219 .c = {
3220 .dbg_name = "csi2phy_timer_clk",
3221 .ops = &clk_ops_branch,
3222 CLK_INIT(csi2phy_timer_clk.c),
3223 },
3224};
3225
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003226#define F_DSI(d) \
3227 { \
3228 .freq_hz = d, \
3229 .ns_val = BVAL(15, 12, (d-1)), \
3230 }
3231/*
3232 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3233 * without this clock driver knowing. So, overload the clk_set_rate() to set
3234 * the divider (1 to 16) of the clock with respect to the PLL rate.
3235 */
3236static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3237 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3238 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3239 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3240 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3241 F_END
3242};
3243
3244static struct rcg_clk dsi1_byte_clk = {
3245 .b = {
3246 .ctl_reg = DSI1_BYTE_CC_REG,
3247 .en_mask = BIT(0),
3248 .reset_reg = SW_RESET_CORE_REG,
3249 .reset_mask = BIT(7),
3250 .halt_reg = DBG_BUS_VEC_B_REG,
3251 .halt_bit = 21,
3252 },
3253 .ns_reg = DSI1_BYTE_NS_REG,
3254 .root_en_mask = BIT(2),
3255 .ns_mask = BM(15, 12),
3256 .set_rate = set_rate_nop,
3257 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003258 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003259 .c = {
3260 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003261 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003262 CLK_INIT(dsi1_byte_clk.c),
3263 },
3264};
3265
3266static struct rcg_clk dsi2_byte_clk = {
3267 .b = {
3268 .ctl_reg = DSI2_BYTE_CC_REG,
3269 .en_mask = BIT(0),
3270 .reset_reg = SW_RESET_CORE_REG,
3271 .reset_mask = BIT(25),
3272 .halt_reg = DBG_BUS_VEC_B_REG,
3273 .halt_bit = 20,
3274 },
3275 .ns_reg = DSI2_BYTE_NS_REG,
3276 .root_en_mask = BIT(2),
3277 .ns_mask = BM(15, 12),
3278 .set_rate = set_rate_nop,
3279 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003280 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003281 .c = {
3282 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003283 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003284 CLK_INIT(dsi2_byte_clk.c),
3285 },
3286};
3287
3288static struct rcg_clk dsi1_esc_clk = {
3289 .b = {
3290 .ctl_reg = DSI1_ESC_CC_REG,
3291 .en_mask = BIT(0),
3292 .reset_reg = SW_RESET_CORE_REG,
3293 .halt_reg = DBG_BUS_VEC_I_REG,
3294 .halt_bit = 1,
3295 },
3296 .ns_reg = DSI1_ESC_NS_REG,
3297 .root_en_mask = BIT(2),
3298 .ns_mask = BM(15, 12),
3299 .set_rate = set_rate_nop,
3300 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003301 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003302 .c = {
3303 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003304 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003305 CLK_INIT(dsi1_esc_clk.c),
3306 },
3307};
3308
3309static struct rcg_clk dsi2_esc_clk = {
3310 .b = {
3311 .ctl_reg = DSI2_ESC_CC_REG,
3312 .en_mask = BIT(0),
3313 .halt_reg = DBG_BUS_VEC_I_REG,
3314 .halt_bit = 3,
3315 },
3316 .ns_reg = DSI2_ESC_NS_REG,
3317 .root_en_mask = BIT(2),
3318 .ns_mask = BM(15, 12),
3319 .set_rate = set_rate_nop,
3320 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003321 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003322 .c = {
3323 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003324 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003325 CLK_INIT(dsi2_esc_clk.c),
3326 },
3327};
3328
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003329#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003330 { \
3331 .freq_hz = f, \
3332 .src_clk = &s##_clk.c, \
3333 .md_val = MD4(4, m, 0, n), \
3334 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3335 .ctl_val = CC_BANKED(9, 6, n), \
3336 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003337 }
3338static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003339 F_GFX2D( 0, gnd, 0, 0),
3340 F_GFX2D( 27000000, pxo, 0, 0),
3341 F_GFX2D( 48000000, pll8, 1, 8),
3342 F_GFX2D( 54857000, pll8, 1, 7),
3343 F_GFX2D( 64000000, pll8, 1, 6),
3344 F_GFX2D( 76800000, pll8, 1, 5),
3345 F_GFX2D( 96000000, pll8, 1, 4),
3346 F_GFX2D(128000000, pll8, 1, 3),
3347 F_GFX2D(145455000, pll2, 2, 11),
3348 F_GFX2D(160000000, pll2, 1, 5),
3349 F_GFX2D(177778000, pll2, 2, 9),
3350 F_GFX2D(200000000, pll2, 1, 4),
3351 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003352 F_END
3353};
3354
3355static struct bank_masks bmnd_info_gfx2d0 = {
3356 .bank_sel_mask = BIT(11),
3357 .bank0_mask = {
3358 .md_reg = GFX2D0_MD0_REG,
3359 .ns_mask = BM(23, 20) | BM(5, 3),
3360 .rst_mask = BIT(25),
3361 .mnd_en_mask = BIT(8),
3362 .mode_mask = BM(10, 9),
3363 },
3364 .bank1_mask = {
3365 .md_reg = GFX2D0_MD1_REG,
3366 .ns_mask = BM(19, 16) | BM(2, 0),
3367 .rst_mask = BIT(24),
3368 .mnd_en_mask = BIT(5),
3369 .mode_mask = BM(7, 6),
3370 },
3371};
3372
3373static struct rcg_clk gfx2d0_clk = {
3374 .b = {
3375 .ctl_reg = GFX2D0_CC_REG,
3376 .en_mask = BIT(0),
3377 .reset_reg = SW_RESET_CORE_REG,
3378 .reset_mask = BIT(14),
3379 .halt_reg = DBG_BUS_VEC_A_REG,
3380 .halt_bit = 9,
3381 },
3382 .ns_reg = GFX2D0_NS_REG,
3383 .root_en_mask = BIT(2),
3384 .set_rate = set_rate_mnd_banked,
3385 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003386 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003387 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003388 .c = {
3389 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003390 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003391 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3392 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003393 CLK_INIT(gfx2d0_clk.c),
3394 },
3395};
3396
3397static struct bank_masks bmnd_info_gfx2d1 = {
3398 .bank_sel_mask = BIT(11),
3399 .bank0_mask = {
3400 .md_reg = GFX2D1_MD0_REG,
3401 .ns_mask = BM(23, 20) | BM(5, 3),
3402 .rst_mask = BIT(25),
3403 .mnd_en_mask = BIT(8),
3404 .mode_mask = BM(10, 9),
3405 },
3406 .bank1_mask = {
3407 .md_reg = GFX2D1_MD1_REG,
3408 .ns_mask = BM(19, 16) | BM(2, 0),
3409 .rst_mask = BIT(24),
3410 .mnd_en_mask = BIT(5),
3411 .mode_mask = BM(7, 6),
3412 },
3413};
3414
3415static struct rcg_clk gfx2d1_clk = {
3416 .b = {
3417 .ctl_reg = GFX2D1_CC_REG,
3418 .en_mask = BIT(0),
3419 .reset_reg = SW_RESET_CORE_REG,
3420 .reset_mask = BIT(13),
3421 .halt_reg = DBG_BUS_VEC_A_REG,
3422 .halt_bit = 14,
3423 },
3424 .ns_reg = GFX2D1_NS_REG,
3425 .root_en_mask = BIT(2),
3426 .set_rate = set_rate_mnd_banked,
3427 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003428 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003429 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003430 .c = {
3431 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003432 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003433 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3434 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003435 CLK_INIT(gfx2d1_clk.c),
3436 },
3437};
3438
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003439#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003440 { \
3441 .freq_hz = f, \
3442 .src_clk = &s##_clk.c, \
3443 .md_val = MD4(4, m, 0, n), \
3444 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3445 .ctl_val = CC_BANKED(9, 6, n), \
3446 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003447 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003448
3449static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003450 F_GFX3D( 0, gnd, 0, 0),
3451 F_GFX3D( 27000000, pxo, 0, 0),
3452 F_GFX3D( 48000000, pll8, 1, 8),
3453 F_GFX3D( 54857000, pll8, 1, 7),
3454 F_GFX3D( 64000000, pll8, 1, 6),
3455 F_GFX3D( 76800000, pll8, 1, 5),
3456 F_GFX3D( 96000000, pll8, 1, 4),
3457 F_GFX3D(128000000, pll8, 1, 3),
3458 F_GFX3D(145455000, pll2, 2, 11),
3459 F_GFX3D(160000000, pll2, 1, 5),
3460 F_GFX3D(177778000, pll2, 2, 9),
3461 F_GFX3D(200000000, pll2, 1, 4),
3462 F_GFX3D(228571000, pll2, 2, 7),
3463 F_GFX3D(266667000, pll2, 1, 3),
3464 F_GFX3D(320000000, pll2, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003465 F_END
3466};
3467
Tianyi Gou41515e22011-09-01 19:37:43 -07003468static struct clk_freq_tbl clk_tbl_gfx3d_8960_v2[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003469 F_GFX3D( 0, gnd, 0, 0),
3470 F_GFX3D( 27000000, pxo, 0, 0),
3471 F_GFX3D( 48000000, pll8, 1, 8),
3472 F_GFX3D( 54857000, pll8, 1, 7),
3473 F_GFX3D( 64000000, pll8, 1, 6),
3474 F_GFX3D( 76800000, pll8, 1, 5),
3475 F_GFX3D( 96000000, pll8, 1, 4),
3476 F_GFX3D(128000000, pll8, 1, 3),
3477 F_GFX3D(145455000, pll2, 2, 11),
3478 F_GFX3D(160000000, pll2, 1, 5),
3479 F_GFX3D(177778000, pll2, 2, 9),
3480 F_GFX3D(200000000, pll2, 1, 4),
3481 F_GFX3D(228571000, pll2, 2, 7),
3482 F_GFX3D(266667000, pll2, 1, 3),
3483 F_GFX3D(300000000, pll3, 1, 4),
3484 F_GFX3D(320000000, pll2, 2, 5),
3485 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003486 F_END
3487};
3488
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003489static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
3490 [VDD_DIG_LOW] = 128000000,
3491 [VDD_DIG_NOMINAL] = 300000000,
3492 [VDD_DIG_HIGH] = 400000000
3493};
3494
Tianyi Gou621f8742011-09-01 21:45:01 -07003495/* TODO: need to add 325MHz back once it is fixed in the simulation model */
Tianyi Gou41515e22011-09-01 19:37:43 -07003496static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003497 F_GFX3D( 0, gnd, 0, 0),
3498 F_GFX3D( 27000000, pxo, 0, 0),
3499 F_GFX3D( 48000000, pll8, 1, 8),
3500 F_GFX3D( 54857000, pll8, 1, 7),
3501 F_GFX3D( 64000000, pll8, 1, 6),
3502 F_GFX3D( 76800000, pll8, 1, 5),
3503 F_GFX3D( 96000000, pll8, 1, 4),
3504 F_GFX3D(128000000, pll8, 1, 3),
3505 F_GFX3D(145455000, pll2, 2, 11),
3506 F_GFX3D(160000000, pll2, 1, 5),
3507 F_GFX3D(177778000, pll2, 2, 9),
3508 F_GFX3D(200000000, pll2, 1, 4),
3509 F_GFX3D(228571000, pll2, 2, 7),
3510 F_GFX3D(266667000, pll2, 1, 3),
3511 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003512 F_END
3513};
3514
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003515static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3516 [VDD_DIG_LOW] = 128000000,
3517 [VDD_DIG_NOMINAL] = 325000000,
3518 [VDD_DIG_HIGH] = 400000000
3519};
3520
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003521static struct bank_masks bmnd_info_gfx3d = {
3522 .bank_sel_mask = BIT(11),
3523 .bank0_mask = {
3524 .md_reg = GFX3D_MD0_REG,
3525 .ns_mask = BM(21, 18) | BM(5, 3),
3526 .rst_mask = BIT(23),
3527 .mnd_en_mask = BIT(8),
3528 .mode_mask = BM(10, 9),
3529 },
3530 .bank1_mask = {
3531 .md_reg = GFX3D_MD1_REG,
3532 .ns_mask = BM(17, 14) | BM(2, 0),
3533 .rst_mask = BIT(22),
3534 .mnd_en_mask = BIT(5),
3535 .mode_mask = BM(7, 6),
3536 },
3537};
3538
3539static struct rcg_clk gfx3d_clk = {
3540 .b = {
3541 .ctl_reg = GFX3D_CC_REG,
3542 .en_mask = BIT(0),
3543 .reset_reg = SW_RESET_CORE_REG,
3544 .reset_mask = BIT(12),
3545 .halt_reg = DBG_BUS_VEC_A_REG,
3546 .halt_bit = 4,
3547 },
3548 .ns_reg = GFX3D_NS_REG,
3549 .root_en_mask = BIT(2),
3550 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003551 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003552 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003553 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003554 .c = {
3555 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003556 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003557 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
3558 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003559 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003560 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003561 },
3562};
3563
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003564#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003565 { \
3566 .freq_hz = f, \
3567 .src_clk = &s##_clk.c, \
3568 .md_val = MD4(4, m, 0, n), \
3569 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3570 .ctl_val = CC_BANKED(9, 6, n), \
3571 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003572 }
3573
3574static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003575 F_VCAP( 0, gnd, 0, 0),
3576 F_VCAP( 27000000, pxo, 0, 0),
3577 F_VCAP( 54860000, pll8, 1, 7),
3578 F_VCAP( 64000000, pll8, 1, 6),
3579 F_VCAP( 76800000, pll8, 1, 5),
3580 F_VCAP(128000000, pll8, 1, 3),
3581 F_VCAP(160000000, pll2, 1, 5),
3582 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003583 F_END
3584};
3585
3586static struct bank_masks bmnd_info_vcap = {
3587 .bank_sel_mask = BIT(11),
3588 .bank0_mask = {
3589 .md_reg = VCAP_MD0_REG,
3590 .ns_mask = BM(21, 18) | BM(5, 3),
3591 .rst_mask = BIT(23),
3592 .mnd_en_mask = BIT(8),
3593 .mode_mask = BM(10, 9),
3594 },
3595 .bank1_mask = {
3596 .md_reg = VCAP_MD1_REG,
3597 .ns_mask = BM(17, 14) | BM(2, 0),
3598 .rst_mask = BIT(22),
3599 .mnd_en_mask = BIT(5),
3600 .mode_mask = BM(7, 6),
3601 },
3602};
3603
3604static struct rcg_clk vcap_clk = {
3605 .b = {
3606 .ctl_reg = VCAP_CC_REG,
3607 .en_mask = BIT(0),
3608 .halt_reg = DBG_BUS_VEC_J_REG,
3609 .halt_bit = 15,
3610 },
3611 .ns_reg = VCAP_NS_REG,
3612 .root_en_mask = BIT(2),
3613 .set_rate = set_rate_mnd_banked,
3614 .freq_tbl = clk_tbl_vcap,
3615 .bank_info = &bmnd_info_vcap,
3616 .current_freq = &rcg_dummy_freq,
3617 .c = {
3618 .dbg_name = "vcap_clk",
3619 .ops = &clk_ops_rcg_8960,
3620 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003621 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003622 CLK_INIT(vcap_clk.c),
3623 },
3624};
3625
3626static struct branch_clk vcap_npl_clk = {
3627 .b = {
3628 .ctl_reg = VCAP_CC_REG,
3629 .en_mask = BIT(13),
3630 .halt_reg = DBG_BUS_VEC_J_REG,
3631 .halt_bit = 25,
3632 },
3633 .parent = &vcap_clk.c,
3634 .c = {
3635 .dbg_name = "vcap_npl_clk",
3636 .ops = &clk_ops_branch,
3637 CLK_INIT(vcap_npl_clk.c),
3638 },
3639};
3640
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003641#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003642 { \
3643 .freq_hz = f, \
3644 .src_clk = &s##_clk.c, \
3645 .md_val = MD8(8, m, 0, n), \
3646 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3647 .ctl_val = CC(6, n), \
3648 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003649 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003650
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003651static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3652 F_IJPEG( 0, gnd, 1, 0, 0),
3653 F_IJPEG( 27000000, pxo, 1, 0, 0),
3654 F_IJPEG( 36570000, pll8, 1, 2, 21),
3655 F_IJPEG( 54860000, pll8, 7, 0, 0),
3656 F_IJPEG( 96000000, pll8, 4, 0, 0),
3657 F_IJPEG(109710000, pll8, 1, 2, 7),
3658 F_IJPEG(128000000, pll8, 3, 0, 0),
3659 F_IJPEG(153600000, pll8, 1, 2, 5),
3660 F_IJPEG(200000000, pll2, 4, 0, 0),
3661 F_IJPEG(228571000, pll2, 1, 2, 7),
3662 F_IJPEG(266667000, pll2, 1, 1, 3),
3663 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003664 F_END
3665};
3666
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003667static unsigned long fmax_ijpeg_8960_v2[MAX_VDD_LEVELS] __initdata = {
3668 [VDD_DIG_LOW] = 110000000,
3669 [VDD_DIG_NOMINAL] = 266667000,
3670 [VDD_DIG_HIGH] = 320000000
3671};
3672
3673static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3674 [VDD_DIG_LOW] = 128000000,
3675 [VDD_DIG_NOMINAL] = 266667000,
3676 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003677};
3678
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003679static struct rcg_clk ijpeg_clk = {
3680 .b = {
3681 .ctl_reg = IJPEG_CC_REG,
3682 .en_mask = BIT(0),
3683 .reset_reg = SW_RESET_CORE_REG,
3684 .reset_mask = BIT(9),
3685 .halt_reg = DBG_BUS_VEC_A_REG,
3686 .halt_bit = 24,
3687 },
3688 .ns_reg = IJPEG_NS_REG,
3689 .md_reg = IJPEG_MD_REG,
3690 .root_en_mask = BIT(2),
3691 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3692 .ctl_mask = BM(7, 6),
3693 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003694 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003695 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003696 .c = {
3697 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003698 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003699 VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003700 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003701 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003702 },
3703};
3704
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003705#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003706 { \
3707 .freq_hz = f, \
3708 .src_clk = &s##_clk.c, \
3709 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003710 }
3711static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003712 F_JPEGD( 0, gnd, 1),
3713 F_JPEGD( 64000000, pll8, 6),
3714 F_JPEGD( 76800000, pll8, 5),
3715 F_JPEGD( 96000000, pll8, 4),
3716 F_JPEGD(160000000, pll2, 5),
3717 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003718 F_END
3719};
3720
3721static struct rcg_clk jpegd_clk = {
3722 .b = {
3723 .ctl_reg = JPEGD_CC_REG,
3724 .en_mask = BIT(0),
3725 .reset_reg = SW_RESET_CORE_REG,
3726 .reset_mask = BIT(19),
3727 .halt_reg = DBG_BUS_VEC_A_REG,
3728 .halt_bit = 19,
3729 },
3730 .ns_reg = JPEGD_NS_REG,
3731 .root_en_mask = BIT(2),
3732 .ns_mask = (BM(15, 12) | BM(2, 0)),
3733 .set_rate = set_rate_nop,
3734 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003735 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003736 .c = {
3737 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003738 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003739 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003740 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003741 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003742 },
3743};
3744
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003745#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003746 { \
3747 .freq_hz = f, \
3748 .src_clk = &s##_clk.c, \
3749 .md_val = MD8(8, m, 0, n), \
3750 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3751 .ctl_val = CC_BANKED(9, 6, n), \
3752 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003753 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003754static struct clk_freq_tbl clk_tbl_mdp[] = {
3755 F_MDP( 0, gnd, 0, 0),
3756 F_MDP( 9600000, pll8, 1, 40),
3757 F_MDP( 13710000, pll8, 1, 28),
3758 F_MDP( 27000000, pxo, 0, 0),
3759 F_MDP( 29540000, pll8, 1, 13),
3760 F_MDP( 34910000, pll8, 1, 11),
3761 F_MDP( 38400000, pll8, 1, 10),
3762 F_MDP( 59080000, pll8, 2, 13),
3763 F_MDP( 76800000, pll8, 1, 5),
3764 F_MDP( 85330000, pll8, 2, 9),
3765 F_MDP( 96000000, pll8, 1, 4),
3766 F_MDP(128000000, pll8, 1, 3),
3767 F_MDP(160000000, pll2, 1, 5),
3768 F_MDP(177780000, pll2, 2, 9),
3769 F_MDP(200000000, pll2, 1, 4),
3770 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003771 F_END
3772};
3773
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003774static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3775 [VDD_DIG_LOW] = 128000000,
3776 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003777};
3778
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003779static struct bank_masks bmnd_info_mdp = {
3780 .bank_sel_mask = BIT(11),
3781 .bank0_mask = {
3782 .md_reg = MDP_MD0_REG,
3783 .ns_mask = BM(29, 22) | BM(5, 3),
3784 .rst_mask = BIT(31),
3785 .mnd_en_mask = BIT(8),
3786 .mode_mask = BM(10, 9),
3787 },
3788 .bank1_mask = {
3789 .md_reg = MDP_MD1_REG,
3790 .ns_mask = BM(21, 14) | BM(2, 0),
3791 .rst_mask = BIT(30),
3792 .mnd_en_mask = BIT(5),
3793 .mode_mask = BM(7, 6),
3794 },
3795};
3796
3797static struct rcg_clk mdp_clk = {
3798 .b = {
3799 .ctl_reg = MDP_CC_REG,
3800 .en_mask = BIT(0),
3801 .reset_reg = SW_RESET_CORE_REG,
3802 .reset_mask = BIT(21),
3803 .halt_reg = DBG_BUS_VEC_C_REG,
3804 .halt_bit = 10,
3805 },
3806 .ns_reg = MDP_NS_REG,
3807 .root_en_mask = BIT(2),
3808 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003809 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003810 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003811 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003812 .c = {
3813 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003814 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003815 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003816 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003817 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003818 },
3819};
3820
3821static struct branch_clk lut_mdp_clk = {
3822 .b = {
3823 .ctl_reg = MDP_LUT_CC_REG,
3824 .en_mask = BIT(0),
3825 .halt_reg = DBG_BUS_VEC_I_REG,
3826 .halt_bit = 13,
3827 },
3828 .parent = &mdp_clk.c,
3829 .c = {
3830 .dbg_name = "lut_mdp_clk",
3831 .ops = &clk_ops_branch,
3832 CLK_INIT(lut_mdp_clk.c),
3833 },
3834};
3835
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003836#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003837 { \
3838 .freq_hz = f, \
3839 .src_clk = &s##_clk.c, \
3840 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003841 }
3842static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003843 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003844 F_END
3845};
3846
3847static struct rcg_clk mdp_vsync_clk = {
3848 .b = {
3849 .ctl_reg = MISC_CC_REG,
3850 .en_mask = BIT(6),
3851 .reset_reg = SW_RESET_CORE_REG,
3852 .reset_mask = BIT(3),
3853 .halt_reg = DBG_BUS_VEC_B_REG,
3854 .halt_bit = 22,
3855 },
3856 .ns_reg = MISC_CC2_REG,
3857 .ns_mask = BIT(13),
3858 .set_rate = set_rate_nop,
3859 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003860 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003861 .c = {
3862 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003863 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003864 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003865 CLK_INIT(mdp_vsync_clk.c),
3866 },
3867};
3868
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003869#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003870 { \
3871 .freq_hz = f, \
3872 .src_clk = &s##_clk.c, \
3873 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3874 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003875 }
3876static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003877 F_ROT( 0, gnd, 1),
3878 F_ROT( 27000000, pxo, 1),
3879 F_ROT( 29540000, pll8, 13),
3880 F_ROT( 32000000, pll8, 12),
3881 F_ROT( 38400000, pll8, 10),
3882 F_ROT( 48000000, pll8, 8),
3883 F_ROT( 54860000, pll8, 7),
3884 F_ROT( 64000000, pll8, 6),
3885 F_ROT( 76800000, pll8, 5),
3886 F_ROT( 96000000, pll8, 4),
3887 F_ROT(100000000, pll2, 8),
3888 F_ROT(114290000, pll2, 7),
3889 F_ROT(133330000, pll2, 6),
3890 F_ROT(160000000, pll2, 5),
3891 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003892 F_END
3893};
3894
3895static struct bank_masks bdiv_info_rot = {
3896 .bank_sel_mask = BIT(30),
3897 .bank0_mask = {
3898 .ns_mask = BM(25, 22) | BM(18, 16),
3899 },
3900 .bank1_mask = {
3901 .ns_mask = BM(29, 26) | BM(21, 19),
3902 },
3903};
3904
3905static struct rcg_clk rot_clk = {
3906 .b = {
3907 .ctl_reg = ROT_CC_REG,
3908 .en_mask = BIT(0),
3909 .reset_reg = SW_RESET_CORE_REG,
3910 .reset_mask = BIT(2),
3911 .halt_reg = DBG_BUS_VEC_C_REG,
3912 .halt_bit = 15,
3913 },
3914 .ns_reg = ROT_NS_REG,
3915 .root_en_mask = BIT(2),
3916 .set_rate = set_rate_div_banked,
3917 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003918 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003919 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003920 .c = {
3921 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003922 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003923 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003924 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003925 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003926 },
3927};
3928
3929static int hdmi_pll_clk_enable(struct clk *clk)
3930{
3931 int ret;
3932 unsigned long flags;
3933 spin_lock_irqsave(&local_clock_reg_lock, flags);
3934 ret = hdmi_pll_enable();
3935 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3936 return ret;
3937}
3938
3939static void hdmi_pll_clk_disable(struct clk *clk)
3940{
3941 unsigned long flags;
3942 spin_lock_irqsave(&local_clock_reg_lock, flags);
3943 hdmi_pll_disable();
3944 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3945}
3946
3947static unsigned hdmi_pll_clk_get_rate(struct clk *clk)
3948{
3949 return hdmi_pll_get_rate();
3950}
3951
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003952static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3953{
3954 return &pxo_clk.c;
3955}
3956
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003957static struct clk_ops clk_ops_hdmi_pll = {
3958 .enable = hdmi_pll_clk_enable,
3959 .disable = hdmi_pll_clk_disable,
3960 .get_rate = hdmi_pll_clk_get_rate,
3961 .is_local = local_clk_is_local,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003962 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003963};
3964
3965static struct clk hdmi_pll_clk = {
3966 .dbg_name = "hdmi_pll_clk",
3967 .ops = &clk_ops_hdmi_pll,
3968 CLK_INIT(hdmi_pll_clk),
3969};
3970
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003971#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003972 { \
3973 .freq_hz = f, \
3974 .src_clk = &s##_clk.c, \
3975 .md_val = MD8(8, m, 0, n), \
3976 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3977 .ctl_val = CC(6, n), \
3978 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003979 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003980#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003981 { \
3982 .freq_hz = f, \
3983 .src_clk = &s##_clk, \
3984 .md_val = MD8(8, m, 0, n), \
3985 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3986 .ctl_val = CC(6, n), \
3987 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003988 .extra_freq_data = (void *)p_r, \
3989 }
3990/* Switching TV freqs requires PLL reconfiguration. */
3991static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003992 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3993 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3994 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3995 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3996 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3997 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003998 F_END
3999};
4000
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004001static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
4002 [VDD_DIG_LOW] = 74250000,
4003 [VDD_DIG_NOMINAL] = 149000000
4004};
4005
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004006/*
4007 * Unlike other clocks, the TV rate is adjusted through PLL
4008 * re-programming. It is also routed through an MND divider.
4009 */
4010void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
4011{
4012 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
4013 if (pll_rate)
4014 hdmi_pll_set_rate(pll_rate);
4015 set_rate_mnd(clk, nf);
4016}
4017
4018static struct rcg_clk tv_src_clk = {
4019 .ns_reg = TV_NS_REG,
4020 .b = {
4021 .ctl_reg = TV_CC_REG,
4022 .halt_check = NOCHECK,
4023 },
4024 .md_reg = TV_MD_REG,
4025 .root_en_mask = BIT(2),
4026 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
4027 .ctl_mask = BM(7, 6),
4028 .set_rate = set_rate_tv,
4029 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004030 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004031 .c = {
4032 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004033 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004034 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004035 CLK_INIT(tv_src_clk.c),
4036 },
4037};
4038
4039static struct branch_clk tv_enc_clk = {
4040 .b = {
4041 .ctl_reg = TV_CC_REG,
4042 .en_mask = BIT(8),
4043 .reset_reg = SW_RESET_CORE_REG,
4044 .reset_mask = BIT(0),
4045 .halt_reg = DBG_BUS_VEC_D_REG,
4046 .halt_bit = 9,
4047 },
4048 .parent = &tv_src_clk.c,
4049 .c = {
4050 .dbg_name = "tv_enc_clk",
4051 .ops = &clk_ops_branch,
4052 CLK_INIT(tv_enc_clk.c),
4053 },
4054};
4055
4056static struct branch_clk tv_dac_clk = {
4057 .b = {
4058 .ctl_reg = TV_CC_REG,
4059 .en_mask = BIT(10),
4060 .halt_reg = DBG_BUS_VEC_D_REG,
4061 .halt_bit = 10,
4062 },
4063 .parent = &tv_src_clk.c,
4064 .c = {
4065 .dbg_name = "tv_dac_clk",
4066 .ops = &clk_ops_branch,
4067 CLK_INIT(tv_dac_clk.c),
4068 },
4069};
4070
4071static struct branch_clk mdp_tv_clk = {
4072 .b = {
4073 .ctl_reg = TV_CC_REG,
4074 .en_mask = BIT(0),
4075 .reset_reg = SW_RESET_CORE_REG,
4076 .reset_mask = BIT(4),
4077 .halt_reg = DBG_BUS_VEC_D_REG,
4078 .halt_bit = 12,
4079 },
4080 .parent = &tv_src_clk.c,
4081 .c = {
4082 .dbg_name = "mdp_tv_clk",
4083 .ops = &clk_ops_branch,
4084 CLK_INIT(mdp_tv_clk.c),
4085 },
4086};
4087
4088static struct branch_clk hdmi_tv_clk = {
4089 .b = {
4090 .ctl_reg = TV_CC_REG,
4091 .en_mask = BIT(12),
4092 .reset_reg = SW_RESET_CORE_REG,
4093 .reset_mask = BIT(1),
4094 .halt_reg = DBG_BUS_VEC_D_REG,
4095 .halt_bit = 11,
4096 },
4097 .parent = &tv_src_clk.c,
4098 .c = {
4099 .dbg_name = "hdmi_tv_clk",
4100 .ops = &clk_ops_branch,
4101 CLK_INIT(hdmi_tv_clk.c),
4102 },
4103};
4104
4105static struct branch_clk hdmi_app_clk = {
4106 .b = {
4107 .ctl_reg = MISC_CC2_REG,
4108 .en_mask = BIT(11),
4109 .reset_reg = SW_RESET_CORE_REG,
4110 .reset_mask = BIT(11),
4111 .halt_reg = DBG_BUS_VEC_B_REG,
4112 .halt_bit = 25,
4113 },
4114 .c = {
4115 .dbg_name = "hdmi_app_clk",
4116 .ops = &clk_ops_branch,
4117 CLK_INIT(hdmi_app_clk.c),
4118 },
4119};
4120
4121static struct bank_masks bmnd_info_vcodec = {
4122 .bank_sel_mask = BIT(13),
4123 .bank0_mask = {
4124 .md_reg = VCODEC_MD0_REG,
4125 .ns_mask = BM(18, 11) | BM(2, 0),
4126 .rst_mask = BIT(31),
4127 .mnd_en_mask = BIT(5),
4128 .mode_mask = BM(7, 6),
4129 },
4130 .bank1_mask = {
4131 .md_reg = VCODEC_MD1_REG,
4132 .ns_mask = BM(26, 19) | BM(29, 27),
4133 .rst_mask = BIT(30),
4134 .mnd_en_mask = BIT(10),
4135 .mode_mask = BM(12, 11),
4136 },
4137};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004138#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004139 { \
4140 .freq_hz = f, \
4141 .src_clk = &s##_clk.c, \
4142 .md_val = MD8(8, m, 0, n), \
4143 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4144 .ctl_val = CC_BANKED(6, 11, n), \
4145 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004146 }
4147static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004148 F_VCODEC( 0, gnd, 0, 0),
4149 F_VCODEC( 27000000, pxo, 0, 0),
4150 F_VCODEC( 32000000, pll8, 1, 12),
4151 F_VCODEC( 48000000, pll8, 1, 8),
4152 F_VCODEC( 54860000, pll8, 1, 7),
4153 F_VCODEC( 96000000, pll8, 1, 4),
4154 F_VCODEC(133330000, pll2, 1, 6),
4155 F_VCODEC(200000000, pll2, 1, 4),
4156 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004157 F_END
4158};
4159
4160static struct rcg_clk vcodec_clk = {
4161 .b = {
4162 .ctl_reg = VCODEC_CC_REG,
4163 .en_mask = BIT(0),
4164 .reset_reg = SW_RESET_CORE_REG,
4165 .reset_mask = BIT(6),
4166 .halt_reg = DBG_BUS_VEC_C_REG,
4167 .halt_bit = 29,
4168 },
4169 .ns_reg = VCODEC_NS_REG,
4170 .root_en_mask = BIT(2),
4171 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004172 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004173 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004174 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004175 .c = {
4176 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004177 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004178 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4179 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004180 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004181 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004182 },
4183};
4184
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004185#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004186 { \
4187 .freq_hz = f, \
4188 .src_clk = &s##_clk.c, \
4189 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004190 }
4191static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004192 F_VPE( 0, gnd, 1),
4193 F_VPE( 27000000, pxo, 1),
4194 F_VPE( 34909000, pll8, 11),
4195 F_VPE( 38400000, pll8, 10),
4196 F_VPE( 64000000, pll8, 6),
4197 F_VPE( 76800000, pll8, 5),
4198 F_VPE( 96000000, pll8, 4),
4199 F_VPE(100000000, pll2, 8),
4200 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004201 F_END
4202};
4203
4204static struct rcg_clk vpe_clk = {
4205 .b = {
4206 .ctl_reg = VPE_CC_REG,
4207 .en_mask = BIT(0),
4208 .reset_reg = SW_RESET_CORE_REG,
4209 .reset_mask = BIT(17),
4210 .halt_reg = DBG_BUS_VEC_A_REG,
4211 .halt_bit = 28,
4212 },
4213 .ns_reg = VPE_NS_REG,
4214 .root_en_mask = BIT(2),
4215 .ns_mask = (BM(15, 12) | BM(2, 0)),
4216 .set_rate = set_rate_nop,
4217 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004218 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004219 .c = {
4220 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004221 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004222 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004223 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004224 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004225 },
4226};
4227
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004228#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004229 { \
4230 .freq_hz = f, \
4231 .src_clk = &s##_clk.c, \
4232 .md_val = MD8(8, m, 0, n), \
4233 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4234 .ctl_val = CC(6, n), \
4235 .mnd_en_mask = BIT(5) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004236 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004237
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004238static struct clk_freq_tbl clk_tbl_vfe[] = {
4239 F_VFE( 0, gnd, 1, 0, 0),
4240 F_VFE( 13960000, pll8, 1, 2, 55),
4241 F_VFE( 27000000, pxo, 1, 0, 0),
4242 F_VFE( 36570000, pll8, 1, 2, 21),
4243 F_VFE( 38400000, pll8, 2, 1, 5),
4244 F_VFE( 45180000, pll8, 1, 2, 17),
4245 F_VFE( 48000000, pll8, 2, 1, 4),
4246 F_VFE( 54860000, pll8, 1, 1, 7),
4247 F_VFE( 64000000, pll8, 2, 1, 3),
4248 F_VFE( 76800000, pll8, 1, 1, 5),
4249 F_VFE( 96000000, pll8, 2, 1, 2),
4250 F_VFE(109710000, pll8, 1, 2, 7),
4251 F_VFE(128000000, pll8, 1, 1, 3),
4252 F_VFE(153600000, pll8, 1, 2, 5),
4253 F_VFE(200000000, pll2, 2, 1, 2),
4254 F_VFE(228570000, pll2, 1, 2, 7),
4255 F_VFE(266667000, pll2, 1, 1, 3),
4256 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004257 F_END
4258};
4259
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004260static unsigned long fmax_vfe_8960_v2[MAX_VDD_LEVELS] __initdata = {
4261 [VDD_DIG_LOW] = 110000000,
4262 [VDD_DIG_NOMINAL] = 266667000,
4263 [VDD_DIG_HIGH] = 320000000
4264};
4265
4266static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4267 [VDD_DIG_LOW] = 128000000,
4268 [VDD_DIG_NOMINAL] = 266667000,
4269 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004270};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004271
4272static struct rcg_clk vfe_clk = {
4273 .b = {
4274 .ctl_reg = VFE_CC_REG,
4275 .reset_reg = SW_RESET_CORE_REG,
4276 .reset_mask = BIT(15),
4277 .halt_reg = DBG_BUS_VEC_B_REG,
4278 .halt_bit = 6,
4279 .en_mask = BIT(0),
4280 },
4281 .ns_reg = VFE_NS_REG,
4282 .md_reg = VFE_MD_REG,
4283 .root_en_mask = BIT(2),
4284 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
4285 .ctl_mask = BM(7, 6),
4286 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004287 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004288 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004289 .c = {
4290 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004291 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004292 VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 266667000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004293 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004294 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004295 },
4296};
4297
Matt Wagantallc23eee92011-08-16 23:06:52 -07004298static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004299 .b = {
4300 .ctl_reg = VFE_CC_REG,
4301 .en_mask = BIT(12),
4302 .reset_reg = SW_RESET_CORE_REG,
4303 .reset_mask = BIT(24),
4304 .halt_reg = DBG_BUS_VEC_B_REG,
4305 .halt_bit = 8,
4306 },
4307 .parent = &vfe_clk.c,
4308 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004309 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004310 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004311 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004312 },
4313};
4314
4315/*
4316 * Low Power Audio Clocks
4317 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004318#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004319 { \
4320 .freq_hz = f, \
4321 .src_clk = &s##_clk.c, \
4322 .md_val = MD8(8, m, 0, n), \
4323 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4324 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004325 }
4326static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004327 F_AIF_OSR( 0, gnd, 1, 0, 0),
4328 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4329 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4330 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4331 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4332 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4333 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4334 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4335 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4336 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4337 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4338 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004339 F_END
4340};
4341
4342#define CLK_AIF_OSR(i, ns, md, h_r) \
4343 struct rcg_clk i##_clk = { \
4344 .b = { \
4345 .ctl_reg = ns, \
4346 .en_mask = BIT(17), \
4347 .reset_reg = ns, \
4348 .reset_mask = BIT(19), \
4349 .halt_reg = h_r, \
4350 .halt_check = ENABLE, \
4351 .halt_bit = 1, \
4352 }, \
4353 .ns_reg = ns, \
4354 .md_reg = md, \
4355 .root_en_mask = BIT(9), \
4356 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4357 .set_rate = set_rate_mnd, \
4358 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004359 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004360 .c = { \
4361 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004362 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004363 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004364 CLK_INIT(i##_clk.c), \
4365 }, \
4366 }
4367#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4368 struct rcg_clk i##_clk = { \
4369 .b = { \
4370 .ctl_reg = ns, \
4371 .en_mask = BIT(21), \
4372 .reset_reg = ns, \
4373 .reset_mask = BIT(23), \
4374 .halt_reg = h_r, \
4375 .halt_check = ENABLE, \
4376 .halt_bit = 1, \
4377 }, \
4378 .ns_reg = ns, \
4379 .md_reg = md, \
4380 .root_en_mask = BIT(9), \
4381 .ns_mask = (BM(31, 24) | BM(6, 0)), \
4382 .set_rate = set_rate_mnd, \
4383 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004384 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004385 .c = { \
4386 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004387 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004388 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004389 CLK_INIT(i##_clk.c), \
4390 }, \
4391 }
4392
4393#define F_AIF_BIT(d, s) \
4394 { \
4395 .freq_hz = d, \
4396 .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
4397 }
4398static struct clk_freq_tbl clk_tbl_aif_bit[] = {
4399 F_AIF_BIT(0, 1), /* Use external clock. */
4400 F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
4401 F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
4402 F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
4403 F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
4404 F_END
4405};
4406
4407#define CLK_AIF_BIT(i, ns, h_r) \
4408 struct rcg_clk i##_clk = { \
4409 .b = { \
4410 .ctl_reg = ns, \
4411 .en_mask = BIT(15), \
4412 .halt_reg = h_r, \
4413 .halt_check = DELAY, \
4414 }, \
4415 .ns_reg = ns, \
4416 .ns_mask = BM(14, 10), \
4417 .set_rate = set_rate_nop, \
4418 .freq_tbl = clk_tbl_aif_bit, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004419 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004420 .c = { \
4421 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004422 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004423 CLK_INIT(i##_clk.c), \
4424 }, \
4425 }
4426
4427#define F_AIF_BIT_D(d, s) \
4428 { \
4429 .freq_hz = d, \
4430 .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
4431 }
4432static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
4433 F_AIF_BIT_D(0, 1), /* Use external clock. */
4434 F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
4435 F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
4436 F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
4437 F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
4438 F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
4439 F_AIF_BIT_D(16, 0),
4440 F_END
4441};
4442
4443#define CLK_AIF_BIT_DIV(i, ns, h_r) \
4444 struct rcg_clk i##_clk = { \
4445 .b = { \
4446 .ctl_reg = ns, \
4447 .en_mask = BIT(19), \
4448 .halt_reg = h_r, \
4449 .halt_check = ENABLE, \
4450 }, \
4451 .ns_reg = ns, \
4452 .ns_mask = BM(18, 10), \
4453 .set_rate = set_rate_nop, \
4454 .freq_tbl = clk_tbl_aif_bit_div, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004455 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004456 .c = { \
4457 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004458 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004459 CLK_INIT(i##_clk.c), \
4460 }, \
4461 }
4462
4463static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4464 LCC_MI2S_STATUS_REG);
4465static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4466
4467static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4468 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4469static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4470 LCC_CODEC_I2S_MIC_STATUS_REG);
4471
4472static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4473 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4474static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4475 LCC_SPARE_I2S_MIC_STATUS_REG);
4476
4477static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4478 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4479static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4480 LCC_CODEC_I2S_SPKR_STATUS_REG);
4481
4482static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4483 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4484static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4485 LCC_SPARE_I2S_SPKR_STATUS_REG);
4486
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004487#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004488 { \
4489 .freq_hz = f, \
4490 .src_clk = &s##_clk.c, \
4491 .md_val = MD16(m, n), \
4492 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
4493 .mnd_en_mask = BIT(8) * !!(n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004494 }
4495static struct clk_freq_tbl clk_tbl_pcm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004496 F_PCM( 0, gnd, 1, 0, 0),
4497 F_PCM( 512000, pll4, 4, 1, 192),
4498 F_PCM( 768000, pll4, 4, 1, 128),
4499 F_PCM( 1024000, pll4, 4, 1, 96),
4500 F_PCM( 1536000, pll4, 4, 1, 64),
4501 F_PCM( 2048000, pll4, 4, 1, 48),
4502 F_PCM( 3072000, pll4, 4, 1, 32),
4503 F_PCM( 4096000, pll4, 4, 1, 24),
4504 F_PCM( 6144000, pll4, 4, 1, 16),
4505 F_PCM( 8192000, pll4, 4, 1, 12),
4506 F_PCM(12288000, pll4, 4, 1, 8),
4507 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004508 F_END
4509};
4510
4511static struct rcg_clk pcm_clk = {
4512 .b = {
4513 .ctl_reg = LCC_PCM_NS_REG,
4514 .en_mask = BIT(11),
4515 .reset_reg = LCC_PCM_NS_REG,
4516 .reset_mask = BIT(13),
4517 .halt_reg = LCC_PCM_STATUS_REG,
4518 .halt_check = ENABLE,
4519 .halt_bit = 0,
4520 },
4521 .ns_reg = LCC_PCM_NS_REG,
4522 .md_reg = LCC_PCM_MD_REG,
4523 .root_en_mask = BIT(9),
4524 .ns_mask = (BM(31, 16) | BM(6, 0)),
4525 .set_rate = set_rate_mnd,
4526 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004527 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004528 .c = {
4529 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004530 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004531 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004532 CLK_INIT(pcm_clk.c),
4533 },
4534};
4535
4536static struct rcg_clk audio_slimbus_clk = {
4537 .b = {
4538 .ctl_reg = LCC_SLIMBUS_NS_REG,
4539 .en_mask = BIT(10),
4540 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4541 .reset_mask = BIT(5),
4542 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4543 .halt_check = ENABLE,
4544 .halt_bit = 0,
4545 },
4546 .ns_reg = LCC_SLIMBUS_NS_REG,
4547 .md_reg = LCC_SLIMBUS_MD_REG,
4548 .root_en_mask = BIT(9),
4549 .ns_mask = (BM(31, 24) | BM(6, 0)),
4550 .set_rate = set_rate_mnd,
4551 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004552 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004553 .c = {
4554 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004555 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004556 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004557 CLK_INIT(audio_slimbus_clk.c),
4558 },
4559};
4560
4561static struct branch_clk sps_slimbus_clk = {
4562 .b = {
4563 .ctl_reg = LCC_SLIMBUS_NS_REG,
4564 .en_mask = BIT(12),
4565 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4566 .halt_check = ENABLE,
4567 .halt_bit = 1,
4568 },
4569 .parent = &audio_slimbus_clk.c,
4570 .c = {
4571 .dbg_name = "sps_slimbus_clk",
4572 .ops = &clk_ops_branch,
4573 CLK_INIT(sps_slimbus_clk.c),
4574 },
4575};
4576
4577static struct branch_clk slimbus_xo_src_clk = {
4578 .b = {
4579 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4580 .en_mask = BIT(2),
4581 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004582 .halt_bit = 28,
4583 },
4584 .parent = &sps_slimbus_clk.c,
4585 .c = {
4586 .dbg_name = "slimbus_xo_src_clk",
4587 .ops = &clk_ops_branch,
4588 CLK_INIT(slimbus_xo_src_clk.c),
4589 },
4590};
4591
Matt Wagantall735f01a2011-08-12 12:40:28 -07004592DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4593DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4594DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4595DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4596DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4597DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4598DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4599DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004600
4601static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4602static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
4603static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4604static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4605static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4606static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4607static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4608static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
Stephen Boyd1c51a492011-10-26 12:11:47 -07004609static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004610
4611static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
4612/*
4613 * TODO: replace dummy_clk below with ebi1_clk.c once the
4614 * bus driver starts voting on ebi1 rates.
4615 */
4616static DEFINE_CLK_VOTER(ebi1_adm_clk, &dummy_clk);
4617
4618#ifdef CONFIG_DEBUG_FS
4619struct measure_sel {
4620 u32 test_vector;
4621 struct clk *clk;
4622};
4623
Matt Wagantall8b38f942011-08-02 18:23:18 -07004624static DEFINE_CLK_MEASURE(l2_m_clk);
4625static DEFINE_CLK_MEASURE(krait0_m_clk);
4626static DEFINE_CLK_MEASURE(krait1_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004627static DEFINE_CLK_MEASURE(q6sw_clk);
4628static DEFINE_CLK_MEASURE(q6fw_clk);
4629static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004630
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004631static struct measure_sel measure_mux[] = {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004632 { TEST_PER_LS(0x05), &qdss_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004633 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4634 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4635 { TEST_PER_LS(0x13), &sdc1_clk.c },
4636 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4637 { TEST_PER_LS(0x15), &sdc2_clk.c },
4638 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4639 { TEST_PER_LS(0x17), &sdc3_clk.c },
4640 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4641 { TEST_PER_LS(0x19), &sdc4_clk.c },
4642 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4643 { TEST_PER_LS(0x1B), &sdc5_clk.c },
4644 { TEST_PER_LS(0x25), &dfab_clk.c },
4645 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4646 { TEST_PER_LS(0x26), &pmem_clk.c },
4647 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4648 { TEST_PER_LS(0x33), &cfpb_clk.c },
4649 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4650 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4651 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4652 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4653 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4654 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4655 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4656 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4657 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4658 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4659 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4660 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4661 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4662 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4663 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4664 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4665 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4666 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4667 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4668 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4669 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4670 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4671 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4672 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4673 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4674 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4675 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4676 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4677 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4678 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4679 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4680 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4681 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4682 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4683 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4684 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4685 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004686 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4687 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4688 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4689 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4690 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4691 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4692 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4693 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4694 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004695 { TEST_PER_LS(0x78), &sfpb_clk.c },
4696 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4697 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4698 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4699 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4700 { TEST_PER_LS(0x7D), &prng_clk.c },
4701 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4702 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4703 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4704 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004705 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4706 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4707 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004708 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4709 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4710 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4711 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4712 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4713 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4714 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4715 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4716 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4717 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004718 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004719 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4720
4721 { TEST_PER_HS(0x07), &afab_clk.c },
4722 { TEST_PER_HS(0x07), &afab_a_clk.c },
4723 { TEST_PER_HS(0x18), &sfab_clk.c },
4724 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004725 { TEST_PER_HS(0x26), &q6sw_clk },
4726 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004727 { TEST_PER_HS(0x2A), &adm0_clk.c },
4728 { TEST_PER_HS(0x34), &ebi1_clk.c },
4729 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004730 { TEST_PER_HS(0x48), &qdss_at_clk.c },
4731 { TEST_PER_HS(0x49), &qdss_pclkdbg_clk.c },
4732 { TEST_PER_HS(0x4A), &qdss_traceclkin_clk.c },
4733 { TEST_PER_HS(0x4B), &qdss_tsctr_clk.c },
4734 { TEST_PER_HS(0x4F), &qdss_stm_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004735 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004736
4737 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4738 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4739 { TEST_MM_LS(0x02), &cam1_clk.c },
4740 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004741 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004742 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4743 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4744 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4745 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4746 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4747 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4748 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4749 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4750 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4751 { TEST_MM_LS(0x12), &imem_p_clk.c },
4752 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4753 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4754 { TEST_MM_LS(0x16), &rot_p_clk.c },
4755 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4756 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4757 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4758 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4759 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4760 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4761 { TEST_MM_LS(0x1D), &cam0_clk.c },
4762 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4763 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4764 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4765 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4766 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4767 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4768 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4769 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004770 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004771 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004772
4773 { TEST_MM_HS(0x00), &csi0_clk.c },
4774 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004775 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004776 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4777 { TEST_MM_HS(0x06), &vfe_clk.c },
4778 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4779 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4780 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4781 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4782 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4783 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4784 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4785 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4786 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4787 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4788 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4789 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4790 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4791 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4792 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4793 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4794 { TEST_MM_HS(0x1A), &mdp_clk.c },
4795 { TEST_MM_HS(0x1B), &rot_clk.c },
4796 { TEST_MM_HS(0x1C), &vpe_clk.c },
4797 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4798 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4799 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4800 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4801 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4802 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4803 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4804 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4805 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4806 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4807 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004808 { TEST_MM_HS(0x2D), &csi2_clk.c },
4809 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4810 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4811 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4812 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4813 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004814 { TEST_MM_HS(0x33), &vcap_clk.c },
4815 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004816 { TEST_MM_HS(0x36), &vcap_axi_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004817 { TEST_MM_HS(0x39), &gfx3d_axi_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004818
4819 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4820 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4821 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4822 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4823 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4824 { TEST_LPA(0x14), &pcm_clk.c },
4825 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004826
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004827 { TEST_LPA_HS(0x00), &q6_func_clk },
4828
Matt Wagantall8b38f942011-08-02 18:23:18 -07004829 { TEST_CPUL2(0x1), &l2_m_clk },
4830 { TEST_CPUL2(0x2), &krait0_m_clk },
4831 { TEST_CPUL2(0x3), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004832};
4833
4834static struct measure_sel *find_measure_sel(struct clk *clk)
4835{
4836 int i;
4837
4838 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4839 if (measure_mux[i].clk == clk)
4840 return &measure_mux[i];
4841 return NULL;
4842}
4843
Matt Wagantall8b38f942011-08-02 18:23:18 -07004844static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004845{
4846 int ret = 0;
4847 u32 clk_sel;
4848 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004849 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004850 unsigned long flags;
4851
4852 if (!parent)
4853 return -EINVAL;
4854
4855 p = find_measure_sel(parent);
4856 if (!p)
4857 return -EINVAL;
4858
4859 spin_lock_irqsave(&local_clock_reg_lock, flags);
4860
Matt Wagantall8b38f942011-08-02 18:23:18 -07004861 /*
4862 * Program the test vector, measurement period (sample_ticks)
4863 * and scaling multiplier.
4864 */
4865 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004866 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004867 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004868 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4869 case TEST_TYPE_PER_LS:
4870 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4871 break;
4872 case TEST_TYPE_PER_HS:
4873 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4874 break;
4875 case TEST_TYPE_MM_LS:
4876 writel_relaxed(0x4030D97, CLK_TEST_REG);
4877 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4878 break;
4879 case TEST_TYPE_MM_HS:
4880 writel_relaxed(0x402B800, CLK_TEST_REG);
4881 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4882 break;
4883 case TEST_TYPE_LPA:
4884 writel_relaxed(0x4030D98, CLK_TEST_REG);
4885 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4886 LCC_CLK_LS_DEBUG_CFG_REG);
4887 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004888 case TEST_TYPE_LPA_HS:
4889 writel_relaxed(0x402BC00, CLK_TEST_REG);
4890 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4891 LCC_CLK_HS_DEBUG_CFG_REG);
4892 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004893 case TEST_TYPE_CPUL2:
4894 writel_relaxed(0x4030400, CLK_TEST_REG);
4895 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4896 clk->sample_ticks = 0x4000;
4897 clk->multiplier = 2;
4898 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004899 default:
4900 ret = -EPERM;
4901 }
4902 /* Make sure test vector is set before starting measurements. */
4903 mb();
4904
4905 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4906
4907 return ret;
4908}
4909
4910/* Sample clock for 'ticks' reference clock ticks. */
4911static u32 run_measurement(unsigned ticks)
4912{
4913 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004914 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4915
4916 /* Wait for timer to become ready. */
4917 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4918 cpu_relax();
4919
4920 /* Run measurement and wait for completion. */
4921 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4922 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4923 cpu_relax();
4924
4925 /* Stop counters. */
4926 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4927
4928 /* Return measured ticks. */
4929 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4930}
4931
4932
4933/* Perform a hardware rate measurement for a given clock.
4934 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004935static unsigned measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004936{
4937 unsigned long flags;
4938 u32 pdm_reg_backup, ringosc_reg_backup;
4939 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004940 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004941 unsigned ret;
4942
4943 spin_lock_irqsave(&local_clock_reg_lock, flags);
4944
4945 /* Enable CXO/4 and RINGOSC branch and root. */
4946 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4947 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4948 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4949 writel_relaxed(0xA00, RINGOSC_NS_REG);
4950
4951 /*
4952 * The ring oscillator counter will not reset if the measured clock
4953 * is not running. To detect this, run a short measurement before
4954 * the full measurement. If the raw results of the two are the same
4955 * then the clock must be off.
4956 */
4957
4958 /* Run a short measurement. (~1 ms) */
4959 raw_count_short = run_measurement(0x1000);
4960 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004961 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004962
4963 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4964 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4965
4966 /* Return 0 if the clock is off. */
4967 if (raw_count_full == raw_count_short)
4968 ret = 0;
4969 else {
4970 /* Compute rate in Hz. */
4971 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004972 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4973 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004974 }
4975
4976 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004977 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004978 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4979
4980 return ret;
4981}
4982#else /* !CONFIG_DEBUG_FS */
4983static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4984{
4985 return -EINVAL;
4986}
4987
4988static unsigned measure_clk_get_rate(struct clk *clk)
4989{
4990 return 0;
4991}
4992#endif /* CONFIG_DEBUG_FS */
4993
4994static struct clk_ops measure_clk_ops = {
4995 .set_parent = measure_clk_set_parent,
4996 .get_rate = measure_clk_get_rate,
4997 .is_local = local_clk_is_local,
4998};
4999
Matt Wagantall8b38f942011-08-02 18:23:18 -07005000static struct measure_clk measure_clk = {
5001 .c = {
5002 .dbg_name = "measure_clk",
5003 .ops = &measure_clk_ops,
5004 CLK_INIT(measure_clk.c),
5005 },
5006 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005007};
5008
Tianyi Gou41515e22011-09-01 19:37:43 -07005009static struct clk_lookup msm_clocks_8064[] __initdata = {
5010 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005011 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005012 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
Tianyi Gouc29c3242011-10-12 21:02:15 -07005013 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005014 CLK_LOOKUP("measure", measure_clk.c, "debug"),
5015
5016 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
5017 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
5018 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
5019 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
5020 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
5021 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
5022 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
5023 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
5024 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
5025 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
5026 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
5027 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
5028 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
5029 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
5030 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
5031 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
5032
5033 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
5034 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
5035 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
5036 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
5037 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, NULL),
5038 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, NULL),
5039 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
5040 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, NULL),
5041 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
5042 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, NULL),
5043 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, NULL),
5044 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
5045 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
5046 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005047 CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005048 CLK_LOOKUP("pmem_clk", pmem_clk.c, NULL),
5049 CLK_DUMMY("core_clk", PRNG_CLK, NULL, OFF),
Tianyi Gou43208a02011-09-27 15:35:13 -07005050 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5051 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5052 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5053 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005054 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
5055 CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005056 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005057 CLK_LOOKUP("core_clk", usb_hs3_xcvr_clk.c, NULL),
5058 CLK_LOOKUP("core_clk", usb_hs4_xcvr_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005059 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
5060 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
5061 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005062 CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
5063 CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
5064 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
5065 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005066 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
5067 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
5068 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
5069 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, NULL),
5070 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, NULL),
5071 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, NULL),
5072 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, NULL),
5073 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005074 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Tianyi Gou4496fba2011-10-12 11:40:15 -07005075 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
5076 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005077 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, NULL),
5078 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, NULL),
Tianyi Gou43208a02011-09-27 15:35:13 -07005079 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5080 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5081 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5082 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005083 CLK_LOOKUP("iface_clk", pcie_p_clk.c, NULL),
5084 CLK_LOOKUP("core_src_clk", ce3_src_clk.c, NULL),
5085 CLK_LOOKUP("core_clk", ce3_core_clk.c, NULL),
5086 CLK_LOOKUP("iface_clk", ce3_p_clk.c, NULL),
5087 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5088 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005089 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
5090 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
5091 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
5092 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
5093 CLK_LOOKUP("core_clk", amp_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005094 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5095 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
5096 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5097 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5098 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005099 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005100 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5101 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5102 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005103 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005104 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5105 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5106 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5107 CLK_DUMMY("csi_phy_clk", CSI0_PHY_CLK, NULL, OFF),
5108 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5109 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5110 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005111 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
5112 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005113 CLK_DUMMY("csi_pix_clk", CSI_PIX1_CLK, NULL, OFF),
5114 CLK_DUMMY("csi_rdi_clk", CSI_RDI1_CLK, NULL, OFF),
5115 CLK_DUMMY("csi_rdi_clk", CSI_RDI2_CLK, NULL, OFF),
5116 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
5117 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, NULL),
5118 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, NULL),
5119 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, NULL),
5120 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5121 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5122 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5123 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
5124 CLK_DUMMY("rgb_tv_clk", RGB_TV_CLK, NULL, OFF),
5125 CLK_DUMMY("npl_tv_clk", NPL_TV_CLK, NULL, OFF),
5126 CLK_LOOKUP("core_clk", gfx3d_clk.c, NULL),
5127 CLK_LOOKUP("iface_clk", vcap_p_clk.c, NULL),
5128 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, NULL),
5129 CLK_LOOKUP("core_clk", vcap_clk.c, NULL),
5130 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, NULL),
5131 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, NULL),
5132 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
5133 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005134 CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005135 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
5136 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5137 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
5138 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005139 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005140 CLK_LOOKUP("core_clk", vcodec_clk.c, NULL),
Tianyi Gou41515e22011-09-01 19:37:43 -07005141 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
5142 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
Tianyi Gou621f8742011-09-01 21:45:01 -07005143 CLK_LOOKUP("core_clk", hdmi_app_clk.c, NULL),
5144 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
5145 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
5146 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
5147 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
5148 CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005149 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, NULL),
5150 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, NULL),
5151 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, NULL),
5152 CLK_LOOKUP("vpe_axi_clk", vpe_axi_clk.c, NULL),
5153 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
5154 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
5155 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5156 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5157 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5158 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
5159 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, NULL),
5160 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, NULL),
5161 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, NULL),
5162 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005163 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
5164 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005165 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
5166 CLK_LOOKUP("iface_clk", smmu_p_clk.c, NULL),
5167 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
5168 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, NULL),
5169 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
5170 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
Tianyi Gouc29c3242011-10-12 21:02:15 -07005171 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5172 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5173 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5174 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5175 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5176 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5177 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5178 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5179 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5180 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5181 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
Tianyi Goudd8138a2011-10-20 15:46:00 -07005182 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5183 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Tianyi Gou621f8742011-09-01 21:45:01 -07005184 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, NULL),
5185 CLK_LOOKUP("core_clk", vpe_axi_clk.c, NULL),
5186 CLK_LOOKUP("core_clk", mdp_axi_clk.c, NULL),
5187 CLK_LOOKUP("core_clk", vcap_axi_clk.c, NULL),
5188 CLK_LOOKUP("core_clk", rot_axi_clk.c, NULL),
5189 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, NULL),
5190 CLK_LOOKUP("core_clk", vfe_axi_clk.c, NULL),
5191 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, NULL),
5192 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, NULL),
5193 CLK_DUMMY("core_clk", GFX3D_AXI_CLK, NULL, 0),
Tianyi Gou41515e22011-09-01 19:37:43 -07005194 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
5195 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
5196 CLK_DUMMY("bus_clk", DFAB_SDC1_CLK, NULL, 0),
5197 CLK_DUMMY("bus_clk", DFAB_SDC2_CLK, NULL, 0),
5198 CLK_DUMMY("bus_clk", DFAB_SDC3_CLK, NULL, 0),
5199 CLK_DUMMY("bus_clk", DFAB_SDC4_CLK, NULL, 0),
5200 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
5201 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
5202 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
5203 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
5204 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
5205 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
5206
5207 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
5208 CLK_LOOKUP("ebi1_clk", ebi1_adm_clk.c, "msm_dmov"),
5209
5210 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5211 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5212 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
5213};
5214
Stephen Boyd94625ef2011-07-12 17:06:01 -07005215static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005216 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
5217 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5218 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5219 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005220 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005221
5222 CLK_LOOKUP("afab_clk", afab_clk.c, NULL),
5223 CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
5224 CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
5225 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
Stephen Boyd85436132011-09-16 18:55:13 -07005226 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005227 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
5228 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
5229 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
5230 CLK_LOOKUP("ebi1_a_clk", ebi1_a_clk.c, NULL),
5231 CLK_LOOKUP("mmfab_clk", mmfab_clk.c, NULL),
5232 CLK_LOOKUP("mmfab_a_clk", mmfab_a_clk.c, NULL),
5233 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5234 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, NULL),
Stephen Boyda3787f32011-09-16 18:55:13 -07005235 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005236 CLK_LOOKUP("sfab_clk", sfab_clk.c, NULL),
5237 CLK_LOOKUP("sfab_a_clk", sfab_a_clk.c, NULL),
5238 CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
5239 CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
5240
Matt Wagantalle2522372011-08-17 14:52:21 -07005241 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
5242 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
5243 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
5244 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
5245 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5246 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5247 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
5248 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
5249 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
5250 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
5251 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
5252 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005253 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005254 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005255 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5256 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005257 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
5258 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
5259 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
5260 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
5261 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005262 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005263 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005264 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005265 CLK_LOOKUP("core_clk", pdm_clk.c, NULL),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005266 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005267 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005268 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5269 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5270 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5271 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5272 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005273 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005274 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005275 CLK_LOOKUP("core_clk", tssc_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005276 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
5277 CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
5278 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
5279 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
5280 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
5281 CLK_LOOKUP("usb_fs_clk", usb_fs2_xcvr_clk.c, NULL),
5282 CLK_LOOKUP("usb_fs_sys_clk", usb_fs2_sys_clk.c, NULL),
5283 CLK_LOOKUP("usb_fs_src_clk", usb_fs2_src_clk.c, NULL),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005284 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005285 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005286 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005287 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005288 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005289 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005290 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005291 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5292 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005293 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5294 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005295 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
5296 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
5297 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005298 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07005299 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005300 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07005301 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005302 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
5303 CLK_LOOKUP("usb_fs_pclk", usb_fs2_p_clk.c, NULL),
5304 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005305 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5306 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5307 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5308 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5309 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005310 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5311 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005312 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),
5313 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, NULL),
5314 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, NULL),
5315 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, NULL),
5316 CLK_LOOKUP("core_clk", amp_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005317 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
5318 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
5319 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
5320 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_ov2720.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005321 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005322 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
5323 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
5324 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005325 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005326 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_camera_ov2720.0"),
5327 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
5328 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
5329 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005330 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005331 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov2720.0"),
5332 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
5333 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
5334 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07005335 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005336 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_camera_ov2720.0"),
5337 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
5338 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
5339 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
5340 CLK_LOOKUP("csi0phy_timer_clk", csi0phy_timer_clk.c, NULL),
5341 CLK_LOOKUP("csi1phy_timer_clk", csi1phy_timer_clk.c, NULL),
5342 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5343 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5344 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5345 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005346 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005347 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005348 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005349 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005350 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005351 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5352 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005353 CLK_LOOKUP("mem_clk", imem_axi_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005354 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005355 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005356 CLK_LOOKUP("core_clk", jpegd_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005357 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005358 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005359 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5360 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07005361 CLK_LOOKUP("qdss_pclk", qdss_p_clk.c, NULL),
5362 CLK_LOOKUP("qdss_at_clk", qdss_at_clk.c, NULL),
5363 CLK_LOOKUP("qdss_pclkdbg_clk", qdss_pclkdbg_clk.c, NULL),
5364 CLK_LOOKUP("qdss_traceclkin_clk", qdss_traceclkin_clk.c, NULL),
5365 CLK_LOOKUP("qdss_tsctr_clk", qdss_tsctr_clk.c, NULL),
5366 CLK_LOOKUP("qdss_stm_clk", qdss_stm_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005367 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005368 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005369 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
5370 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5371 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005372 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005373 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005374 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
5375 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005376 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005377 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005378 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005379 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005380 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Matt Wagantallc23eee92011-08-16 23:06:52 -07005381 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005382 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5383 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5384 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5385 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5386 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5387 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5388 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005389 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07005390 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005391 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5392 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5393 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5394 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005395 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005396 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005397 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005398 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005399 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005400 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005401 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5402 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005403 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005404 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallb86ad262011-10-24 19:50:29 -07005405 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005406 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005407 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005408 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005409 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005410 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005411 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005412 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005413 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005414 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005415 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005416 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005417 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005418 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005419 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
5420 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
5421 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
5422 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
5423 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
5424 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
5425 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
5426 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
5427 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
5428 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
5429 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
5430 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5431 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
Matt Wagantalle604d712011-10-21 15:38:18 -07005432 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5433 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5434 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5435 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5436 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5437 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5438 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5439 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5440 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5441 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5442 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5443 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005444 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5445 CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005446 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5447 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5448 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5449 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5450 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005451 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005452 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005453
5454 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005455 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005456
5457 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
5458 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
5459 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Stephen Boyd3939c8d2011-08-29 17:36:22 -07005460 CLK_LOOKUP("q6sw_clk", q6sw_clk, NULL),
5461 CLK_LOOKUP("q6fw_clk", q6fw_clk, NULL),
5462 CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005463};
5464
Stephen Boyd94625ef2011-07-12 17:06:01 -07005465static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
5466 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5467 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5468 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5469 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, NULL),
5470 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, NULL),
5471 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, NULL),
5472 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5473 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
5474 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
5475 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
5476 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
5477 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
5478 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
5479};
5480
5481/* Add v2 clocks dynamically at runtime */
5482static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
5483 ARRAY_SIZE(msm_clocks_8960_v2)];
5484
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005485/*
5486 * Miscellaneous clock register initializations
5487 */
5488
5489/* Read, modify, then write-back a register. */
5490static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5491{
5492 uint32_t regval = readl_relaxed(reg);
5493 regval &= ~mask;
5494 regval |= val;
5495 writel_relaxed(regval, reg);
5496}
5497
Tianyi Gou41515e22011-09-01 19:37:43 -07005498static void __init set_fsm_mode(void __iomem *mode_reg)
5499{
5500 u32 regval = readl_relaxed(mode_reg);
5501
5502 /*De-assert reset to FSM */
5503 regval &= ~BIT(21);
5504 writel_relaxed(regval, mode_reg);
5505
5506 /* Program bias count */
Tianyi Gou358c3862011-10-18 17:03:41 -07005507 regval &= ~BM(19, 14);
5508 regval |= BVAL(19, 14, 0x1);
5509 writel_relaxed(regval, mode_reg);
5510
5511 /* Program lock count */
Tianyi Gou41515e22011-09-01 19:37:43 -07005512 regval &= ~BM(13, 8);
5513 regval |= BVAL(13, 8, 0x8);
5514 writel_relaxed(regval, mode_reg);
5515
5516 /*Enable PLL FSM voting */
5517 regval |= BIT(20);
5518 writel_relaxed(regval, mode_reg);
5519}
5520
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005521static void __init reg_init(void)
5522{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005523 /* Deassert MM SW_RESET_ALL signal. */
5524 writel_relaxed(0, SW_RESET_ALL_REG);
5525
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005526 /*
5527 * Some bits are only used on either 8960 or 8064 and are marked as
5528 * reserved bits on the other SoC. Writing to these reserved bits
5529 * should have no effect.
5530 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005531 /* Initialize MM AHB registers: Enable the FPB clock and disable HW
5532 * gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
5533 * prevent its memory from being collapsed when the clock is halted.
5534 * The sleep and wake-up delays are set to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005535 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5536 writel_relaxed(0x000007F9, AHB_EN2_REG);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005537 if (cpu_is_apq8064())
5538 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005539
5540 /* Deassert all locally-owned MM AHB resets. */
5541 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005542 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005543
5544 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5545 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5546 * delays to safe values. */
5547 /* TODO: Enable HW Gating */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005548 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5549 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5550 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
5551 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005552 if (cpu_is_apq8064())
5553 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005554 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005555
5556 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5557 * memories retain state even when not clocked. Also, set sleep and
5558 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005559 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5560 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5561 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
5562 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5563 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
5564 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005565 rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
5566 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
5567 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5568 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5569 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5570 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005571 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5572 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5573 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005574 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005575 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005576 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005577 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5578 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
5579 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5580 }
5581 if (cpu_is_apq8064()) {
5582 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005583 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005584 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005585
Tianyi Gou41515e22011-09-01 19:37:43 -07005586 /*
5587 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5588 * core remain active during halt state of the clk. Also, set sleep
5589 * and wake-up value to max.
5590 */
5591 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005592 if (cpu_is_apq8064()) {
5593 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5594 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5595 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005596
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005597 /* De-assert MM AXI resets to all hardware blocks. */
5598 writel_relaxed(0, SW_RESET_AXI_REG);
5599
5600 /* Deassert all MM core resets. */
5601 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005602 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005603
5604 /* Reset 3D core once more, with its clock enabled. This can
5605 * eventually be done as part of the GDFS footswitch driver. */
5606 clk_set_rate(&gfx3d_clk.c, 27000000);
5607 clk_enable(&gfx3d_clk.c);
5608 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
5609 mb();
5610 udelay(5);
5611 writel_relaxed(0, SW_RESET_CORE_REG);
5612 /* Make sure reset is de-asserted before clock is disabled. */
5613 mb();
5614 clk_disable(&gfx3d_clk.c);
5615
5616 /* Enable TSSC and PDM PXO sources. */
5617 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5618 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5619
5620 /* Source SLIMBus xo src from slimbus reference clock */
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005621 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005622 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005623
5624 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5625 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
5626 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005627
5628 /* Source the sata_phy_ref_clk from PXO */
5629 if (cpu_is_apq8064())
5630 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5631
5632 /*
5633 * TODO: Programming below PLLs is temporary and needs to be removed
5634 * after bootloaders program them.
5635 */
5636 if (cpu_is_apq8064()) {
5637 u32 regval, is_pll_enabled;
5638
5639 /* Program pxo_src_clk to source from PXO */
5640 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5641
5642 /* Check if PLL8 is active */
5643 is_pll_enabled = readl_relaxed(BB_PLL8_STATUS_REG) & BIT(16);
5644 if (!is_pll_enabled) {
5645 /* Ref clk = 24.5MHz and program pll8 to 384MHz */
5646 writel_relaxed(0xF, BB_PLL8_L_VAL_REG);
5647 writel_relaxed(0x21, BB_PLL8_M_VAL_REG);
5648 writel_relaxed(0x31, BB_PLL8_N_VAL_REG);
5649
5650 regval = readl_relaxed(BB_PLL8_CONFIG_REG);
5651
5652 /* Enable the main output and the MN accumulator */
5653 regval |= BIT(23) | BIT(22);
5654
5655 /* Set pre-divider and post-divider values to 1 and 1 */
5656 regval &= ~BIT(19);
5657 regval &= ~BM(21, 20);
5658
5659 writel_relaxed(regval, BB_PLL8_CONFIG_REG);
5660
5661 /* Set VCO frequency */
5662 rmwreg(0x10000, BB_PLL8_CONFIG_REG, 0x30000);
5663
5664 /* Enable AUX output */
5665 regval = readl_relaxed(BB_PLL8_TEST_CTL_REG);
5666 regval |= BIT(12);
5667 writel_relaxed(regval, BB_PLL8_TEST_CTL_REG);
5668
5669 set_fsm_mode(BB_PLL8_MODE_REG);
5670 }
5671 /* Check if PLL3 is active */
5672 is_pll_enabled = readl_relaxed(GPLL1_STATUS_REG) & BIT(16);
5673 if (!is_pll_enabled) {
5674 /* Ref clk = 24.5MHz and program pll3 to 1200MHz */
5675 writel_relaxed(0x30, GPLL1_L_VAL_REG);
5676 writel_relaxed(0x30, GPLL1_M_VAL_REG);
5677 writel_relaxed(0x31, GPLL1_N_VAL_REG);
5678
5679 regval = readl_relaxed(GPLL1_CONFIG_REG);
5680
5681 /* Set pre-divider and post-divider values to 1 and 1 */
5682 regval &= ~BIT(15);
5683 regval |= BIT(16);
5684
5685 writel_relaxed(regval, GPLL1_CONFIG_REG);
5686
5687 /* Set VCO frequency */
5688 rmwreg(0x180, GPLL1_CONFIG_REG, 0x180);
5689 }
5690 /* Check if PLL14 is active */
5691 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5692 if (!is_pll_enabled) {
5693 /* Ref clk = 24.5MHz and program pll14 to 480MHz */
5694 writel_relaxed(0x13, BB_PLL14_L_VAL_REG);
5695 writel_relaxed(0x1D, BB_PLL14_M_VAL_REG);
5696 writel_relaxed(0x31, BB_PLL14_N_VAL_REG);
5697
5698 regval = readl_relaxed(BB_PLL14_CONFIG_REG);
5699
5700 /* Enable the main output and the MN accumulator */
5701 regval |= BIT(23) | BIT(22);
5702
5703 /* Set pre-divider and post-divider values to 1 and 1 */
5704 regval &= ~BIT(19);
5705 regval &= ~BM(21, 20);
5706
5707 writel_relaxed(regval, BB_PLL14_CONFIG_REG);
5708
5709 /* Set VCO frequency */
5710 rmwreg(0x10000, BB_PLL14_CONFIG_REG, 0x30000);
5711
Tianyi Gou41515e22011-09-01 19:37:43 -07005712 set_fsm_mode(BB_PLL14_MODE_REG);
5713 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005714 /* Program PLL2 to 800MHz with ref clk = 27MHz */
5715 writel_relaxed(0x1D, MM_PLL1_L_VAL_REG);
5716 writel_relaxed(0x11, MM_PLL1_M_VAL_REG);
5717 writel_relaxed(0x1B, MM_PLL1_N_VAL_REG);
5718
5719 regval = readl_relaxed(MM_PLL1_CONFIG_REG);
5720
5721 /* Enable the main output and the MN accumulator */
5722 regval |= BIT(23) | BIT(22);
5723
5724 /* Set pre-divider and post-divider values to 1 and 1 */
5725 regval &= ~BIT(19);
5726 regval &= ~BM(21, 20);
5727
5728 writel_relaxed(regval, MM_PLL1_CONFIG_REG);
5729
5730 /* Set VCO frequency */
5731 rmwreg(0x20000, MM_PLL1_CONFIG_REG, 0x30000);
5732
Tianyi Gou621f8742011-09-01 21:45:01 -07005733 /* Program PLL15 to 975MHz with ref clk = 27MHz */
5734 writel_relaxed(0x24, MM_PLL3_L_VAL_REG);
5735 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5736 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
5737
5738 regval = readl_relaxed(MM_PLL3_CONFIG_REG);
5739
5740 /* Enable the main output and the MN accumulator */
5741 regval |= BIT(23) | BIT(22);
5742
5743 /* Set pre-divider and post-divider values to 1 and 1 */
5744 regval &= ~BIT(19);
5745 regval &= ~BM(21, 20);
5746
5747 writel_relaxed(regval, MM_PLL3_CONFIG_REG);
5748
5749 /* Set VCO frequency */
5750 rmwreg(0x20000, MM_PLL3_CONFIG_REG, 0x30000);
5751
5752 /* Enable AUX output */
5753 regval = readl_relaxed(MM_PLL3_TEST_CTL_REG);
5754 regval |= BIT(12);
5755 writel_relaxed(regval, MM_PLL3_TEST_CTL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005756
5757 /* Check if PLL4 is active */
5758 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
5759 if (!is_pll_enabled) {
5760 /* Ref clk = 24.5MHz and program pll4 to 393.2160MHz */
5761 writel_relaxed(0x10, LCC_PLL0_L_VAL_REG);
5762 writel_relaxed(0x130, LCC_PLL0_M_VAL_REG);
5763 writel_relaxed(0x17ED, LCC_PLL0_N_VAL_REG);
5764
5765 regval = readl_relaxed(LCC_PLL0_CONFIG_REG);
5766
5767 /* Enable the main output and the MN accumulator */
5768 regval |= BIT(23) | BIT(22);
5769
5770 /* Set pre-divider and post-divider values to 1 and 1 */
5771 regval &= ~BIT(19);
5772 regval &= ~BM(21, 20);
5773
5774 /* Set VCO frequency */
5775 regval &= ~BM(17, 16);
5776 writel_relaxed(regval, LCC_PLL0_CONFIG_REG);
5777
5778 set_fsm_mode(LCC_PLL0_MODE_REG);
5779 }
5780
5781 /* Enable PLL4 source on the LPASS Primary PLL Mux */
5782 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005783 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005784}
5785
Stephen Boyd94625ef2011-07-12 17:06:01 -07005786struct clock_init_data msm8960_clock_init_data __initdata;
5787
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005788/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07005789static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005790{
Stephen Boyd94625ef2011-07-12 17:06:01 -07005791 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Tianyi Gou41515e22011-09-01 19:37:43 -07005792
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005793 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
5794 if (IS_ERR(xo_pxo)) {
5795 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
5796 BUG();
5797 }
5798 xo_cxo = msm_xo_get(MSM_XO_TCXO_D0, "clock-8960");
5799 if (IS_ERR(xo_cxo)) {
5800 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
5801 BUG();
5802 }
5803
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005804 if (cpu_is_msm8960() || cpu_is_msm8930()) {
Tianyi Gou41515e22011-09-01 19:37:43 -07005805 memcpy(msm_clocks_8960, msm_clocks_8960_v1,
5806 sizeof(msm_clocks_8960_v1));
5807 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5808 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960_v2;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005809
5810 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8960_v2,
5811 sizeof(gfx3d_clk.c.fmax));
5812 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8960_v2,
5813 sizeof(ijpeg_clk.c.fmax));
5814 memcpy(vfe_clk.c.fmax, fmax_vfe_8960_v2,
5815 sizeof(vfe_clk.c.fmax));
5816
Tianyi Gou41515e22011-09-01 19:37:43 -07005817 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07005818 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
Tianyi Gou41515e22011-09-01 19:37:43 -07005819 num_lookups = ARRAY_SIZE(msm_clocks_8960);
5820 }
5821 msm8960_clock_init_data.size = num_lookups;
Stephen Boyd94625ef2011-07-12 17:06:01 -07005822 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005823
5824 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005825 * Change the freq tables for and voltage requirements for
5826 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07005827 */
5828 if (cpu_is_apq8064()) {
5829 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005830
5831 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
5832 sizeof(gfx3d_clk.c.fmax));
5833 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
5834 sizeof(ijpeg_clk.c.fmax));
5835 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
5836 sizeof(ijpeg_clk.c.fmax));
5837 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
5838 sizeof(tv_src_clk.c.fmax));
5839 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
5840 sizeof(vfe_clk.c.fmax));
5841
Tianyi Gou621f8742011-09-01 21:45:01 -07005842 gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07005843 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07005844
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005845 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005846
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07005847 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005848
5849 /* Initialize clock registers. */
5850 reg_init();
5851
5852 /* Initialize rates for clocks that only support one. */
5853 clk_set_rate(&pdm_clk.c, 27000000);
5854 clk_set_rate(&prng_clk.c, 64000000);
5855 clk_set_rate(&mdp_vsync_clk.c, 27000000);
5856 clk_set_rate(&tsif_ref_clk.c, 105000);
5857 clk_set_rate(&tssc_clk.c, 27000000);
5858 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07005859 if (cpu_is_apq8064()) {
5860 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
5861 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
5862 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005863 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07005864 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07005865 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005866 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
5867 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
5868 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07005869 /*
5870 * Set the CSI rates to a safe default to avoid warnings when
5871 * switching csi pix and rdi clocks.
5872 */
5873 clk_set_rate(&csi0_src_clk.c, 27000000);
5874 clk_set_rate(&csi1_src_clk.c, 27000000);
5875 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005876
5877 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07005878 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005879 * Toggle these clocks on and off to refresh them.
5880 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07005881 rcg_clk_enable(&pdm_clk.c);
5882 rcg_clk_disable(&pdm_clk.c);
5883 rcg_clk_enable(&tssc_clk.c);
5884 rcg_clk_disable(&tssc_clk.c);
Stephen Boyd60496bb2011-10-17 13:51:37 -07005885 if (cpu_is_msm8960() &&
5886 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
5887 clk_enable(&usb_hsic_hsic_clk.c);
5888 clk_disable(&usb_hsic_hsic_clk.c);
Stephen Boyd092fd182011-10-21 15:56:30 -07005889 } else
5890 /* CSI2 hardware not present on 8960v1 devices */
5891 pix_rdi_mux_map[2] = NULL;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005892
5893 if (machine_is_msm8960_sim()) {
5894 clk_set_rate(&sdc1_clk.c, 48000000);
5895 clk_enable(&sdc1_clk.c);
5896 clk_enable(&sdc1_p_clk.c);
5897 clk_set_rate(&sdc3_clk.c, 48000000);
5898 clk_enable(&sdc3_clk.c);
5899 clk_enable(&sdc3_p_clk.c);
5900 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005901}
5902
Stephen Boydbb600ae2011-08-02 20:11:40 -07005903static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005904{
Stephen Boyda3787f32011-09-16 18:55:13 -07005905 int rc;
5906 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07005907 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07005908
5909 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
5910 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
5911 PTR_ERR(mmfpb_a_clk)))
5912 return PTR_ERR(mmfpb_a_clk);
5913 rc = clk_set_min_rate(mmfpb_a_clk, 76800000);
5914 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
5915 return rc;
5916 rc = clk_enable(mmfpb_a_clk);
5917 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
5918 return rc;
5919
Stephen Boyd85436132011-09-16 18:55:13 -07005920 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
5921 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
5922 PTR_ERR(cfpb_a_clk)))
5923 return PTR_ERR(cfpb_a_clk);
5924 rc = clk_set_min_rate(cfpb_a_clk, 64000000);
5925 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
5926 return rc;
5927 rc = clk_enable(cfpb_a_clk);
5928 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
5929 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005930
5931 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005932}
Stephen Boydbb600ae2011-08-02 20:11:40 -07005933
5934struct clock_init_data msm8960_clock_init_data __initdata = {
5935 .table = msm_clocks_8960,
5936 .size = ARRAY_SIZE(msm_clocks_8960),
5937 .init = msm8960_clock_init,
5938 .late_init = msm8960_clock_late_init,
5939};
Tianyi Gou41515e22011-09-01 19:37:43 -07005940
5941struct clock_init_data apq8064_clock_init_data __initdata = {
5942 .table = msm_clocks_8064,
5943 .size = ARRAY_SIZE(msm_clocks_8064),
5944 .init = msm8960_clock_init,
5945 .late_init = msm8960_clock_late_init,
5946};