blob: 9f5189c700bb00bedbe598e14d7eef47f967c26d [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov265b7212009-04-14 18:39:14 +040011 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 * TODO
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME "pata_hpt37x"
Sergei Shtylyov265b7212009-04-14 18:39:14 +040027#define DRV_VERSION "0.6.12"
Jeff Garzik669a5db2006-08-29 18:12:40 -040028
29struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32};
33
34struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38};
39
40/* key for bus clock timings
41 * bit
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
47 * register access.
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
49 * register access.
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
53 * xfer.
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * register access.
56 * 28 UDMA enable
57 * 29 DMA enable
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
59 * PIO.
60 * 31 FIFO enable.
61 */
62
Alan Coxfcc2f692007-03-08 23:28:52 +000063static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040071
Alan Coxfcc2f692007-03-08 23:28:52 +000072 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040075
Alan Coxfcc2f692007-03-08 23:28:52 +000076 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
Jeff Garzik669a5db2006-08-29 18:12:40 -040081};
82
Alan Coxfcc2f692007-03-08 23:28:52 +000083static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040091
Alan Coxfcc2f692007-03-08 23:28:52 +000092 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040095
Alan Coxfcc2f692007-03-08 23:28:52 +000096 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101};
102
Alan Coxfcc2f692007-03-08 23:28:52 +0000103static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400111
Alan Coxfcc2f692007-03-08 23:28:52 +0000112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115
Alan Coxfcc2f692007-03-08 23:28:52 +0000116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400121};
122
Jeff Garzik669a5db2006-08-29 18:12:40 -0400123
124static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000128 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129 NULL,
130 NULL,
Alan Coxa4734462007-04-26 00:19:25 -0700131 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 }
133};
134
135static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000139 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000141 hpt37x_timings_50,
Alan Coxa4734462007-04-26 00:19:25 -0700142 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400143 }
144};
145
146static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000150 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400151 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000152 hpt37x_timings_50,
153 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 }
155};
156
157static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000161 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000163 hpt37x_timings_50,
164 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 }
166};
167
168static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000172 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400173 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000174 hpt37x_timings_50,
175 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400176 }
177};
178
179static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000183 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000185 hpt37x_timings_50,
186 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400187 }
188};
189
190static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000194 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195 NULL,
196 NULL,
197 NULL
198 }
199};
200
201/**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400209
Jeff Garzik669a5db2006-08-29 18:12:40 -0400210static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
222
223static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400226 int i = 0;
227
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400229
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239}
240
241static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250};
251
252static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269};
270
271/**
272 * hpt370_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400273 * @adev: ATA device
274 *
275 * Block UDMA on devices that cause trouble with this controller.
276 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400277
Alan Coxa76b62c2007-03-09 09:34:07 -0500278static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279{
Alan6929da42007-01-05 16:37:01 -0800280 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400285 }
Tejun Heo9363c382008-04-07 22:47:16 +0900286 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287}
288
289/**
290 * hpt370a_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400291 * @adev: ATA device
292 *
293 * Block UDMA on devices that cause trouble with this controller.
294 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400295
Alan Coxa76b62c2007-03-09 09:34:07 -0500296static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297{
Alan Cox73946f92007-11-05 22:53:38 +0000298 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400301 }
Tejun Heo9363c382008-04-07 22:47:16 +0900302 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400303}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400304
Jeff Garzik669a5db2006-08-29 18:12:40 -0400305/**
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100306 * hpt37x_cable_detect - Detect the cable type
307 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400308 *
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100309 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400311
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100312static int hpt37x_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400313{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100315 u8 scr2, ata66;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500316
Jeff Garzik669a5db2006-08-29 18:12:40 -0400317 pci_read_config_byte(pdev, 0x5B, &scr2);
318 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
Bartlomiej Zolnierkiewicz10a9c962009-11-19 20:31:31 +0100319
320 udelay(10); /* debounce */
321
Jeff Garzik669a5db2006-08-29 18:12:40 -0400322 /* Cable register now active */
323 pci_read_config_byte(pdev, 0x5A, &ata66);
324 /* Restore state */
325 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400326
Alan Cox22d5c762007-11-19 14:39:13 +0000327 if (ata66 & (2 >> ap->port_no))
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100328 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400329 else
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100330 return ATA_CBL_PATA80;
331}
332
333/**
334 * hpt374_fn1_cable_detect - Detect the cable type
335 * @ap: ATA port to detect on
336 *
337 * Return the cable type attached to this port
338 */
339
340static int hpt374_fn1_cable_detect(struct ata_port *ap)
341{
342 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
343 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
344 u16 mcr3;
345 u8 ata66;
346
347 /* Do the extra channel work */
348 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
349 /* Set bit 15 of 0x52 to enable TCBLID as input */
350 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
351 pci_read_config_byte(pdev, 0x5A, &ata66);
352 /* Reset TCBLID/FCBLID to output */
353 pci_write_config_word(pdev, mcrbase + 2, mcr3);
354
355 if (ata66 & (2 >> ap->port_no))
356 return ATA_CBL_PATA40;
357 else
358 return ATA_CBL_PATA80;
359}
360
361/**
362 * hpt37x_pre_reset - reset the hpt37x bus
363 * @link: ATA link to reset
364 * @deadline: deadline jiffies for the operation
365 *
Bartlomiej Zolnierkiewiczab81a502009-11-19 19:12:24 +0100366 * Perform the initial reset handling for the HPT37x.
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100367 */
368
369static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
370{
371 struct ata_port *ap = link->ap;
372 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
373 static const struct pci_bits hpt37x_enable_bits[] = {
374 { 0x50, 1, 0x04, 0x04 },
375 { 0x54, 1, 0x04, 0x04 }
376 };
377 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
378 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400379
380 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000381 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400382 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400383
Tejun Heo9363c382008-04-07 22:47:16 +0900384 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400385}
386
Jeff Garzik669a5db2006-08-29 18:12:40 -0400387/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400388 * hpt370_set_piomode - PIO setup
389 * @ap: ATA interface
390 * @adev: device on the interface
391 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400392 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400393 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400394
Jeff Garzik669a5db2006-08-29 18:12:40 -0400395static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
396{
397 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
398 u32 addr1, addr2;
399 u32 reg;
400 u32 mode;
401 u8 fast;
402
403 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
404 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400405
Jeff Garzik669a5db2006-08-29 18:12:40 -0400406 /* Fast interrupt prediction disable, hold off interrupt disable */
407 pci_read_config_byte(pdev, addr2, &fast);
408 fast &= ~0x02;
409 fast |= 0x01;
410 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400411
Jeff Garzik669a5db2006-08-29 18:12:40 -0400412 pci_read_config_dword(pdev, addr1, &reg);
413 mode = hpt37x_find_mode(ap, adev->pio_mode);
414 mode &= ~0x8000000; /* No FIFO in PIO */
415 mode &= ~0x30070000; /* Leave config bits alone */
416 reg &= 0x30070000; /* Strip timing bits */
417 pci_write_config_dword(pdev, addr1, reg | mode);
418}
419
420/**
421 * hpt370_set_dmamode - DMA timing setup
422 * @ap: ATA interface
423 * @adev: Device being configured
424 *
425 * Set up the channel for MWDMA or UDMA modes. Much the same as with
426 * PIO, load the mode number and then set MWDMA or UDMA flag.
427 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400428
Jeff Garzik669a5db2006-08-29 18:12:40 -0400429static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
430{
431 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
432 u32 addr1, addr2;
433 u32 reg;
434 u32 mode;
435 u8 fast;
436
437 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
438 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400439
Jeff Garzik669a5db2006-08-29 18:12:40 -0400440 /* Fast interrupt prediction disable, hold off interrupt disable */
441 pci_read_config_byte(pdev, addr2, &fast);
442 fast &= ~0x02;
443 fast |= 0x01;
444 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400445
Jeff Garzik669a5db2006-08-29 18:12:40 -0400446 pci_read_config_dword(pdev, addr1, &reg);
447 mode = hpt37x_find_mode(ap, adev->dma_mode);
448 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
449 mode &= ~0xC0000000; /* Leave config bits alone */
450 reg &= 0xC0000000; /* Strip timing bits */
451 pci_write_config_dword(pdev, addr1, reg | mode);
452}
453
454/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400455 * hpt370_bmdma_end - DMA engine stop
456 * @qc: ATA command
457 *
458 * Work around the HPT370 DMA engine.
459 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400460
Jeff Garzik669a5db2006-08-29 18:12:40 -0400461static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
462{
463 struct ata_port *ap = qc->ap;
464 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900465 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400466 u8 dma_cmd;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900467 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400468
Jeff Garzik669a5db2006-08-29 18:12:40 -0400469 if (dma_stat & 0x01) {
470 udelay(20);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900471 dma_stat = ioread8(bmdma + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400472 }
473 if (dma_stat & 0x01) {
474 /* Clear the engine */
475 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
476 udelay(10);
477 /* Stop DMA */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900478 dma_cmd = ioread8(bmdma );
479 iowrite8(dma_cmd & 0xFE, bmdma);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400480 /* Clear Error */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900481 dma_stat = ioread8(bmdma + 2);
482 iowrite8(dma_stat | 0x06 , bmdma + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400483 /* Clear the engine */
484 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
485 udelay(10);
486 }
487 ata_bmdma_stop(qc);
488}
489
490/**
491 * hpt372_set_piomode - PIO setup
492 * @ap: ATA interface
493 * @adev: device on the interface
494 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400495 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400496 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400497
Jeff Garzik669a5db2006-08-29 18:12:40 -0400498static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
499{
500 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
501 u32 addr1, addr2;
502 u32 reg;
503 u32 mode;
504 u8 fast;
505
506 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
507 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400508
Jeff Garzik669a5db2006-08-29 18:12:40 -0400509 /* Fast interrupt prediction disable, hold off interrupt disable */
510 pci_read_config_byte(pdev, addr2, &fast);
511 fast &= ~0x07;
512 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400513
Jeff Garzik669a5db2006-08-29 18:12:40 -0400514 pci_read_config_dword(pdev, addr1, &reg);
515 mode = hpt37x_find_mode(ap, adev->pio_mode);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400516
Jeff Garzik669a5db2006-08-29 18:12:40 -0400517 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
518 mode &= ~0x80000000; /* No FIFO in PIO */
519 mode &= ~0x30070000; /* Leave config bits alone */
520 reg &= 0x30070000; /* Strip timing bits */
521 pci_write_config_dword(pdev, addr1, reg | mode);
522}
523
524/**
525 * hpt372_set_dmamode - DMA timing setup
526 * @ap: ATA interface
527 * @adev: Device being configured
528 *
529 * Set up the channel for MWDMA or UDMA modes. Much the same as with
530 * PIO, load the mode number and then set MWDMA or UDMA flag.
531 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400532
Jeff Garzik669a5db2006-08-29 18:12:40 -0400533static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
534{
535 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
536 u32 addr1, addr2;
537 u32 reg;
538 u32 mode;
539 u8 fast;
540
541 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
542 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400543
Jeff Garzik669a5db2006-08-29 18:12:40 -0400544 /* Fast interrupt prediction disable, hold off interrupt disable */
545 pci_read_config_byte(pdev, addr2, &fast);
546 fast &= ~0x07;
547 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400548
Jeff Garzik669a5db2006-08-29 18:12:40 -0400549 pci_read_config_dword(pdev, addr1, &reg);
550 mode = hpt37x_find_mode(ap, adev->dma_mode);
551 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
552 mode &= ~0xC0000000; /* Leave config bits alone */
553 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
554 reg &= 0xC0000000; /* Strip timing bits */
555 pci_write_config_dword(pdev, addr1, reg | mode);
556}
557
558/**
559 * hpt37x_bmdma_end - DMA engine stop
560 * @qc: ATA command
561 *
562 * Clean up after the HPT372 and later DMA engine
563 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400564
Jeff Garzik669a5db2006-08-29 18:12:40 -0400565static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
566{
567 struct ata_port *ap = qc->ap;
568 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan6929da42007-01-05 16:37:01 -0800569 int mscreg = 0x50 + 4 * ap->port_no;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400570 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400571
Jeff Garzik669a5db2006-08-29 18:12:40 -0400572 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
573 pci_read_config_byte(pdev, mscreg, &msc_stat);
574 if (bwsr_stat & (1 << ap->port_no))
575 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
576 ata_bmdma_stop(qc);
577}
578
579
580static struct scsi_host_template hpt37x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900581 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400582};
583
584/*
585 * Configuration for HPT370
586 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400587
Jeff Garzik669a5db2006-08-29 18:12:40 -0400588static struct ata_port_operations hpt370_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900589 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400590
Jeff Garzik669a5db2006-08-29 18:12:40 -0400591 .bmdma_stop = hpt370_bmdma_stop,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400592
Tejun Heo029cfd62008-03-25 12:22:49 +0900593 .mode_filter = hpt370_filter,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100594 .cable_detect = hpt37x_cable_detect,
Tejun Heo029cfd62008-03-25 12:22:49 +0900595 .set_piomode = hpt370_set_piomode,
596 .set_dmamode = hpt370_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900597 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400598};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400599
600/*
601 * Configuration for HPT370A. Close to 370 but less filters
602 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400603
Jeff Garzik669a5db2006-08-29 18:12:40 -0400604static struct ata_port_operations hpt370a_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900605 .inherits = &hpt370_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400606 .mode_filter = hpt370a_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400607};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400608
609/*
610 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
611 * and DMA mode setting functionality.
612 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400613
Jeff Garzik669a5db2006-08-29 18:12:40 -0400614static struct ata_port_operations hpt372_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900615 .inherits = &ata_bmdma_port_ops,
616
617 .bmdma_stop = hpt37x_bmdma_stop,
618
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100619 .cable_detect = hpt37x_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400620 .set_piomode = hpt372_set_piomode,
621 .set_dmamode = hpt372_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900622 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400623};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400624
625/*
626 * Configuration for HPT374. Mode setting works like 372 and friends
Tejun Heoa1efdab2008-03-25 12:22:50 +0900627 * but we have a different cable detection procedure for function 1.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400628 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400629
Tejun Heoa1efdab2008-03-25 12:22:50 +0900630static struct ata_port_operations hpt374_fn1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900631 .inherits = &hpt372_port_ops,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100632 .cable_detect = hpt374_fn1_cable_detect,
Bartlomiej Zolnierkiewiczab81a502009-11-19 19:12:24 +0100633 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400634};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400635
636/**
Krzysztof Halasaad452d62009-09-20 16:22:51 +0200637 * hpt37x_clock_slot - Turn timing to PC clock entry
Jeff Garzik669a5db2006-08-29 18:12:40 -0400638 * @freq: Reported frequency timing
639 * @base: Base timing
640 *
641 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
642 * and 3 for 66Mhz)
643 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400644
Jeff Garzik669a5db2006-08-29 18:12:40 -0400645static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
646{
647 unsigned int f = (base * freq) / 192; /* Mhz */
648 if (f < 40)
649 return 0; /* 33Mhz slot */
650 if (f < 45)
651 return 1; /* 40Mhz slot */
652 if (f < 55)
653 return 2; /* 50Mhz slot */
654 return 3; /* 60Mhz slot */
655}
656
657/**
658 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400659 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400660 *
661 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
662 * succeeds
663 */
664
665static int hpt37x_calibrate_dpll(struct pci_dev *dev)
666{
667 u8 reg5b;
668 u32 reg5c;
669 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400670
Jeff Garzik669a5db2006-08-29 18:12:40 -0400671 for(tries = 0; tries < 0x5000; tries++) {
672 udelay(50);
673 pci_read_config_byte(dev, 0x5b, &reg5b);
674 if (reg5b & 0x80) {
675 /* See if it stays set */
676 for(tries = 0; tries < 0x1000; tries ++) {
677 pci_read_config_byte(dev, 0x5b, &reg5b);
678 /* Failed ? */
679 if ((reg5b & 0x80) == 0)
680 return 0;
681 }
682 /* Turn off tuning, we have the DPLL set */
683 pci_read_config_dword(dev, 0x5c, &reg5c);
684 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
685 return 1;
686 }
687 }
688 /* Never went stable */
689 return 0;
690}
Alan Cox73946f92007-11-05 22:53:38 +0000691
692static u32 hpt374_read_freq(struct pci_dev *pdev)
693{
694 u32 freq;
695 unsigned long io_base = pci_resource_start(pdev, 4);
696 if (PCI_FUNC(pdev->devfn) & 1) {
Andrew Morton40f46f12007-12-13 16:01:38 -0800697 struct pci_dev *pdev_0;
698
699 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
Alan Cox73946f92007-11-05 22:53:38 +0000700 /* Someone hot plugged the controller on us ? */
701 if (pdev_0 == NULL)
702 return 0;
703 io_base = pci_resource_start(pdev_0, 4);
704 freq = inl(io_base + 0x90);
705 pci_dev_put(pdev_0);
Andrew Morton40f46f12007-12-13 16:01:38 -0800706 } else
Alan Cox73946f92007-11-05 22:53:38 +0000707 freq = inl(io_base + 0x90);
708 return freq;
709}
710
Jeff Garzik669a5db2006-08-29 18:12:40 -0400711/**
712 * hpt37x_init_one - Initialise an HPT37X/302
713 * @dev: PCI device
714 * @id: Entry in match table
715 *
716 * Initialise an HPT37x device. There are some interesting complications
717 * here. Firstly the chip may report 366 and be one of several variants.
718 * Secondly all the timings depend on the clock for the chip which we must
719 * detect and look up
720 *
721 * This is the known chip mappings. It may be missing a couple of later
722 * releases.
723 *
724 * Chip version PCI Rev Notes
725 * HPT366 4 (HPT366) 0 Other driver
726 * HPT366 4 (HPT366) 1 Other driver
727 * HPT368 4 (HPT366) 2 Other driver
728 * HPT370 4 (HPT366) 3 UDMA100
729 * HPT370A 4 (HPT366) 4 UDMA100
730 * HPT372 4 (HPT366) 5 UDMA133 (1)
731 * HPT372N 4 (HPT366) 6 Other driver
732 * HPT372A 5 (HPT372) 1 UDMA133 (1)
733 * HPT372N 5 (HPT372) 2 Other driver
734 * HPT302 6 (HPT302) 1 UDMA133
735 * HPT302N 6 (HPT302) 2 Other driver
736 * HPT371 7 (HPT371) * UDMA133
737 * HPT374 8 (HPT374) * UDMA133 4 channel
738 * HPT372N 9 (HPT372N) * Other driver
739 *
740 * (1) UDMA133 support depends on the bus clock
741 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400742
Jeff Garzik669a5db2006-08-29 18:12:40 -0400743static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
744{
745 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200746 static const struct ata_port_info info_hpt370 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400747 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100748 .pio_mask = ATA_PIO4,
749 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400750 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400751 .port_ops = &hpt370_port_ops
752 };
753 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200754 static const struct ata_port_info info_hpt370a = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400755 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100756 .pio_mask = ATA_PIO4,
757 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400758 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400759 .port_ops = &hpt370a_port_ops
760 };
Alan Coxfcc2f692007-03-08 23:28:52 +0000761 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200762 static const struct ata_port_info info_hpt370_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400763 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100764 .pio_mask = ATA_PIO4,
765 .mwdma_mask = ATA_MWDMA2,
Alan Cox73946f92007-11-05 22:53:38 +0000766 .udma_mask = ATA_UDMA5,
Alan Coxfcc2f692007-03-08 23:28:52 +0000767 .port_ops = &hpt370_port_ops
768 };
769 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200770 static const struct ata_port_info info_hpt370a_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400771 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100772 .pio_mask = ATA_PIO4,
773 .mwdma_mask = ATA_MWDMA2,
Alan Cox73946f92007-11-05 22:53:38 +0000774 .udma_mask = ATA_UDMA5,
Alan Coxfcc2f692007-03-08 23:28:52 +0000775 .port_ops = &hpt370a_port_ops
776 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400777 /* HPT371, 372 and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200778 static const struct ata_port_info info_hpt372 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400779 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100780 .pio_mask = ATA_PIO4,
781 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400782 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400783 .port_ops = &hpt372_port_ops
784 };
Tejun Heoa1efdab2008-03-25 12:22:50 +0900785 /* HPT374 - UDMA100, function 1 uses different prereset method */
786 static const struct ata_port_info info_hpt374_fn0 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400787 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100788 .pio_mask = ATA_PIO4,
789 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400790 .udma_mask = ATA_UDMA5,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900791 .port_ops = &hpt372_port_ops
792 };
793 static const struct ata_port_info info_hpt374_fn1 = {
794 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100795 .pio_mask = ATA_PIO4,
796 .mwdma_mask = ATA_MWDMA2,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900797 .udma_mask = ATA_UDMA5,
798 .port_ops = &hpt374_fn1_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400799 };
800
801 static const int MHz[4] = { 33, 40, 50, 66 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200802 void *private_data = NULL;
Tejun Heo887125e2008-03-25 12:22:49 +0900803 const struct ata_port_info *ppi[] = { NULL, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400804
805 u8 irqmask;
806 u32 class_rev;
Alan Coxfcc2f692007-03-08 23:28:52 +0000807 u8 mcr1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400808 u32 freq;
Alan Coxfcc2f692007-03-08 23:28:52 +0000809 int prefer_dpll = 1;
Jeff Garzika617c092007-05-21 20:14:23 -0400810
Alan Coxfcc2f692007-03-08 23:28:52 +0000811 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400812
813 const struct hpt_chip *chip_table;
814 int clock_slot;
Tejun Heof08048e2008-03-25 12:22:47 +0900815 int rc;
816
817 rc = pcim_enable_device(dev);
818 if (rc)
819 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400820
821 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
822 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400823
Jeff Garzik669a5db2006-08-29 18:12:40 -0400824 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
825 /* May be a later chip in disguise. Check */
826 /* Older chips are in the HPT366 driver. Ignore them */
827 if (class_rev < 3)
828 return -ENODEV;
829 /* N series chips have their own driver. Ignore */
830 if (class_rev == 6)
831 return -ENODEV;
832
Jeff Garzik85cd7252006-08-31 00:03:49 -0400833 switch(class_rev) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400834 case 3:
Tejun Heo887125e2008-03-25 12:22:49 +0900835 ppi[0] = &info_hpt370;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400836 chip_table = &hpt370;
Alan Coxfcc2f692007-03-08 23:28:52 +0000837 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400838 break;
839 case 4:
Tejun Heo887125e2008-03-25 12:22:49 +0900840 ppi[0] = &info_hpt370a;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400841 chip_table = &hpt370a;
Alan Coxfcc2f692007-03-08 23:28:52 +0000842 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400843 break;
844 case 5:
Tejun Heo887125e2008-03-25 12:22:49 +0900845 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400846 chip_table = &hpt372;
847 break;
848 default:
849 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
850 return -ENODEV;
851 }
852 } else {
853 switch(dev->device) {
854 case PCI_DEVICE_ID_TTI_HPT372:
855 /* 372N if rev >= 2*/
856 if (class_rev >= 2)
857 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900858 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400859 chip_table = &hpt372a;
860 break;
861 case PCI_DEVICE_ID_TTI_HPT302:
862 /* 302N if rev > 1 */
863 if (class_rev > 1)
864 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900865 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400866 /* Check this */
867 chip_table = &hpt302;
868 break;
869 case PCI_DEVICE_ID_TTI_HPT371:
Alan Coxfcc2f692007-03-08 23:28:52 +0000870 if (class_rev > 1)
871 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900872 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400873 chip_table = &hpt371;
Alan Coxa4734462007-04-26 00:19:25 -0700874 /* Single channel device, master is not present
875 but the BIOS (or us for non x86) must mark it
Alan Coxfcc2f692007-03-08 23:28:52 +0000876 absent */
877 pci_read_config_byte(dev, 0x50, &mcr1);
878 mcr1 &= ~0x04;
879 pci_write_config_byte(dev, 0x50, mcr1);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400880 break;
881 case PCI_DEVICE_ID_TTI_HPT374:
882 chip_table = &hpt374;
Tejun Heoa1efdab2008-03-25 12:22:50 +0900883 if (!(PCI_FUNC(dev->devfn) & 1))
884 *ppi = &info_hpt374_fn0;
885 else
886 *ppi = &info_hpt374_fn1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400887 break;
888 default:
889 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
890 return -ENODEV;
891 }
892 }
893 /* Ok so this is a chip we support */
894
895 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
896 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
897 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
898 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
899
900 pci_read_config_byte(dev, 0x5A, &irqmask);
901 irqmask &= ~0x10;
902 pci_write_config_byte(dev, 0x5a, irqmask);
903
904 /*
905 * default to pci clock. make sure MA15/16 are set to output
906 * to prevent drives having problems with 40-pin cables. Needed
907 * for some drives such as IBM-DTLA which will not enter ready
908 * state on reset when PDIAG is a input.
909 */
910
Jeff Garzik85cd7252006-08-31 00:03:49 -0400911 pci_write_config_byte(dev, 0x5b, 0x23);
Jeff Garzika617c092007-05-21 20:14:23 -0400912
Alan Coxfcc2f692007-03-08 23:28:52 +0000913 /*
914 * HighPoint does this for HPT372A.
915 * NOTE: This register is only writeable via I/O space.
916 */
917 if (chip_table == &hpt372a)
918 outb(0x0e, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400919
Alan Coxfcc2f692007-03-08 23:28:52 +0000920 /* Some devices do not let this value be accessed via PCI space
Alan Cox73946f92007-11-05 22:53:38 +0000921 according to the old driver. In addition we must use the value
922 from FN 0 on the HPT374 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000923
Alan Cox73946f92007-11-05 22:53:38 +0000924 if (chip_table == &hpt374) {
925 freq = hpt374_read_freq(dev);
926 if (freq == 0)
927 return -ENODEV;
928 } else
929 freq = inl(iobase + 0x90);
930
Jeff Garzik669a5db2006-08-29 18:12:40 -0400931 if ((freq >> 12) != 0xABCDE) {
932 int i;
933 u8 sr;
934 u32 total = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400935
Jeff Garzik669a5db2006-08-29 18:12:40 -0400936 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
Jeff Garzik85cd7252006-08-31 00:03:49 -0400937
Jeff Garzik669a5db2006-08-29 18:12:40 -0400938 /* This is the process the HPT371 BIOS is reported to use */
939 for(i = 0; i < 128; i++) {
940 pci_read_config_byte(dev, 0x78, &sr);
Alan Coxfcc2f692007-03-08 23:28:52 +0000941 total += sr & 0x1FF;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400942 udelay(15);
943 }
944 freq = total / 128;
945 }
946 freq &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400947
Jeff Garzik669a5db2006-08-29 18:12:40 -0400948 /*
949 * Turn the frequency check into a band and then find a timing
950 * table to match it.
951 */
Jeff Garzika617c092007-05-21 20:14:23 -0400952
Jeff Garzik669a5db2006-08-29 18:12:40 -0400953 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
Alan Coxfcc2f692007-03-08 23:28:52 +0000954 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400955 /*
956 * We need to try PLL mode instead
Alan Coxfcc2f692007-03-08 23:28:52 +0000957 *
958 * For non UDMA133 capable devices we should
959 * use a 50MHz DPLL by choice
Jeff Garzik669a5db2006-08-29 18:12:40 -0400960 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000961 unsigned int f_low, f_high;
Alan Cox960c8a12007-05-25 20:48:55 +0100962 int dpll, adjust;
Jeff Garzika617c092007-05-21 20:14:23 -0400963
Alan Cox960c8a12007-05-25 20:48:55 +0100964 /* Compute DPLL */
Tejun Heo887125e2008-03-25 12:22:49 +0900965 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
Jeff Garzika617c092007-05-21 20:14:23 -0400966
Alan Cox960c8a12007-05-25 20:48:55 +0100967 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
Alan Coxfcc2f692007-03-08 23:28:52 +0000968 f_high = f_low + 2;
Alan Cox960c8a12007-05-25 20:48:55 +0100969 if (clock_slot > 1)
970 f_high += 2;
Alan Coxfcc2f692007-03-08 23:28:52 +0000971
972 /* Select the DPLL clock. */
973 pci_write_config_byte(dev, 0x5b, 0x21);
Alan Cox64a81702007-07-24 15:17:48 +0100974 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400975
Jeff Garzik669a5db2006-08-29 18:12:40 -0400976 for(adjust = 0; adjust < 8; adjust++) {
977 if (hpt37x_calibrate_dpll(dev))
978 break;
979 /* See if it'll settle at a fractionally different clock */
Alan Cox64a81702007-07-24 15:17:48 +0100980 if (adjust & 1)
981 f_low -= adjust >> 1;
982 else
983 f_high += adjust >> 1;
984 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400985 }
986 if (adjust == 8) {
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400987 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -0400988 return -ENODEV;
989 }
Alan Cox960c8a12007-05-25 20:48:55 +0100990 if (dpll == 3)
Tejun Heo1626aeb2007-05-04 12:43:58 +0200991 private_data = (void *)hpt37x_timings_66;
Alan Coxfcc2f692007-03-08 23:28:52 +0000992 else
Tejun Heo1626aeb2007-05-04 12:43:58 +0200993 private_data = (void *)hpt37x_timings_50;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400994
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400995 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
996 MHz[clock_slot], MHz[dpll]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400997 } else {
Tejun Heo1626aeb2007-05-04 12:43:58 +0200998 private_data = (void *)chip_table->clocks[clock_slot];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400999 /*
Alan Coxa4734462007-04-26 00:19:25 -07001000 * Perform a final fixup. Note that we will have used the
1001 * DPLL on the HPT372 which means we don't have to worry
1002 * about lack of UDMA133 support on lower clocks
1003 */
Jeff Garzik85cd7252006-08-31 00:03:49 -04001004
Tejun Heo887125e2008-03-25 12:22:49 +09001005 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1006 ppi[0] = &info_hpt370_33;
1007 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1008 ppi[0] = &info_hpt370a_33;
Sergei Shtylyov80b89872007-08-10 21:02:15 +04001009 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1010 chip_table->name, MHz[clock_slot]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001011 }
Alan Coxfcc2f692007-03-08 23:28:52 +00001012
Jeff Garzik669a5db2006-08-29 18:12:40 -04001013 /* Now kick off ATA set up */
Tejun Heo9363c382008-04-07 22:47:16 +09001014 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001015}
1016
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001017static const struct pci_device_id hpt37x[] = {
1018 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1019 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1020 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1021 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1022 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1023
1024 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -04001025};
1026
1027static struct pci_driver hpt37x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001028 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001029 .id_table = hpt37x,
1030 .probe = hpt37x_init_one,
1031 .remove = ata_pci_remove_one
1032};
1033
1034static int __init hpt37x_init(void)
1035{
1036 return pci_register_driver(&hpt37x_pci_driver);
1037}
1038
Jeff Garzik669a5db2006-08-29 18:12:40 -04001039static void __exit hpt37x_exit(void)
1040{
1041 pci_unregister_driver(&hpt37x_pci_driver);
1042}
1043
Jeff Garzik669a5db2006-08-29 18:12:40 -04001044MODULE_AUTHOR("Alan Cox");
1045MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1046MODULE_LICENSE("GPL");
1047MODULE_DEVICE_TABLE(pci, hpt37x);
1048MODULE_VERSION(DRV_VERSION);
1049
1050module_init(hpt37x_init);
1051module_exit(hpt37x_exit);