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gerrit-public.fairphone.software / kernel / msm / 1fa9be72b558c39459f98835eb86dbb4ef4da30b / . / arch / blackfin / mach-bf548 / Kconfig
blob: a09623dfd5504b063199c72b9f76d4df43ffaee7 [file] [log] [blame]
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]1if (BF54x)
2
Mike Frysinger4f25eb82007-11-15 20:49:44 +0800[diff] [blame]3source "arch/blackfin/mach-bf548/boards/Kconfig"
4
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]5menu "BF548 Specific Configuration"
6
Michael Hennericha924db72007-08-03 17:43:29 +0800[diff] [blame]7config DEB_DMA_URGENT
8 bool "DMA has priority over core for ext. accesses"
9 depends on BF54x
Cliff Caib8aab6f2007-12-24 12:33:20 +0800[diff] [blame]10 default y
Michael Hennericha924db72007-08-03 17:43:29 +0800[diff] [blame]11 help
12 Treat any DEB1, DEB2 and DEB3 request as Urgent
13
Sonic Zhang8d5c2f02009-03-30 09:07:26 +0000[diff] [blame]14config BF548_ATAPI_ALTERNATIVE_PORT
15 bool "BF548 ATAPI alternative port via GPIO"
16 help
17 BF548 ATAPI data and address PINs can be routed through
18 async address or GPIO port F and G. Select y to route it
19 to GPIO.
20
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]21comment "Interrupt Priority Assignment"
22menu "Priority"
23
24config IRQ_PLL_WAKEUP
25 int "IRQ_PLL_WAKEUP"
26 default 7
27config IRQ_DMAC0_ERR
28 int "IRQ_DMAC0_ERR"
29 default 7
30config IRQ_EPPI0_ERR
31 int "IRQ_EPPI0_ERR"
32 default 7
33config IRQ_SPORT0_ERR
34 int "IRQ_SPORT0_ERR"
35 default 7
36config IRQ_SPORT1_ERR
37 int "IRQ_SPORT1_ERR"
38 default 7
39config IRQ_SPI0_ERR
40 int "IRQ_SPI0_ERR"
41 default 7
42config IRQ_UART0_ERR
43 int "IRQ_UART0_ERR"
44 default 7
45config IRQ_RTC
46 int "IRQ_RTC"
47 default 8
48config IRQ_EPPI0
49 int "IRQ_EPPI0"
50 default 8
51config IRQ_SPORT0_RX
52 int "IRQ_SPORT0_RX"
53 default 9
54config IRQ_SPORT0_TX
55 int "IRQ_SPORT0_TX"
56 default 9
57config IRQ_SPORT1_RX
58 int "IRQ_SPORT1_RX"
59 default 9
60config IRQ_SPORT1_TX
61 int "IRQ_SPORT1_TX"
62 default 9
63config IRQ_SPI0
64 int "IRQ_SPI0"
65 default 10
66config IRQ_UART0_RX
67 int "IRQ_UART0_RX"
68 default 10
69config IRQ_UART0_TX
70 int "IRQ_UART0_TX"
71 default 10
72config IRQ_TIMER8
73 int "IRQ_TIMER8"
74 default 11
75config IRQ_TIMER9
76 int "IRQ_TIMER9"
77 default 11
78config IRQ_TIMER10
79 int "IRQ_TIMER10"
80 default 11
81config IRQ_PINT0
82 int "IRQ_PINT0"
83 default 12
84config IRQ_PINT1
85 int "IRQ_PINT0"
86 default 12
87config IRQ_MDMAS0
88 int "IRQ_MDMAS0"
89 default 13
90config IRQ_MDMAS1
91 int "IRQ_DMDMAS1"
92 default 13
93config IRQ_WATCHDOG
94 int "IRQ_WATCHDOG"
95 default 13
96config IRQ_DMAC1_ERR
97 int "IRQ_DMAC1_ERR"
98 default 7
99config IRQ_SPORT2_ERR
100 int "IRQ_SPORT2_ERR"
101 default 7
102config IRQ_SPORT3_ERR
103 int "IRQ_SPORT3_ERR"
104 default 7
105config IRQ_MXVR_DATA
106 int "IRQ MXVR Data"
107 default 7
108config IRQ_SPI1_ERR
109 int "IRQ_SPI1_ERR"
110 default 7
111config IRQ_SPI2_ERR
112 int "IRQ_SPI2_ERR"
113 default 7
114config IRQ_UART1_ERR
115 int "IRQ_UART1_ERR"
116 default 7
117config IRQ_UART2_ERR
118 int "IRQ_UART2_ERR"
119 default 7
120config IRQ_CAN0_ERR
121 int "IRQ_CAN0_ERR"
122 default 7
123config IRQ_SPORT2_RX
124 int "IRQ_SPORT2_RX"
125 default 9
126config IRQ_SPORT2_TX
127 int "IRQ_SPORT2_TX"
128 default 9
129config IRQ_SPORT3_RX
130 int "IRQ_SPORT3_RX"
131 default 9
132config IRQ_SPORT3_TX
133 int "IRQ_SPORT3_TX"
134 default 9
135config IRQ_EPPI1
136 int "IRQ_EPPI1"
137 default 9
138config IRQ_EPPI2
139 int "IRQ_EPPI2"
140 default 9
141config IRQ_SPI1
142 int "IRQ_SPI1"
143 default 10
144config IRQ_SPI2
145 int "IRQ_SPI2"
146 default 10
147config IRQ_UART1_RX
148 int "IRQ_UART1_RX"
149 default 10
150config IRQ_UART1_TX
151 int "IRQ_UART1_TX"
152 default 10
153config IRQ_ATAPI_RX
154 int "IRQ_ATAPI_RX"
155 default 10
156config IRQ_ATAPI_TX
157 int "IRQ_ATAPI_TX"
158 default 10
159config IRQ_TWI0
160 int "IRQ_TWI0"
161 default 11
162config IRQ_TWI1
163 int "IRQ_TWI1"
164 default 11
165config IRQ_CAN0_RX
166 int "IRQ_CAN_RX"
167 default 11
168config IRQ_CAN0_TX
169 int "IRQ_CAN_TX"
170 default 11
171config IRQ_MDMAS2
172 int "IRQ_MDMAS2"
173 default 13
174config IRQ_MDMAS3
175 int "IRQ_DMMAS3"
176 default 13
177config IRQ_MXVR_ERR
178 int "IRQ_MXVR_ERR"
179 default 11
180config IRQ_MXVR_MSG
181 int "IRQ_MXVR_MSG"
182 default 11
183config IRQ_MXVR_PKT
184 int "IRQ_MXVR_PKT"
185 default 11
186config IRQ_EPPI1_ERR
187 int "IRQ_EPPI1_ERR"
188 default 7
189config IRQ_EPPI2_ERR
190 int "IRQ_EPPI2_ERR"
191 default 7
192config IRQ_UART3_ERR
193 int "IRQ_UART3_ERR"
194 default 7
195config IRQ_HOST_ERR
196 int "IRQ_HOST_ERR"
197 default 7
198config IRQ_PIXC_ERR
199 int "IRQ_PIXC_ERR"
200 default 7
201config IRQ_NFC_ERR
202 int "IRQ_NFC_ERR"
203 default 7
204config IRQ_ATAPI_ERR
205 int "IRQ_ATAPI_ERR"
206 default 7
207config IRQ_CAN1_ERR
208 int "IRQ_CAN1_ERR"
209 default 7
210config IRQ_HS_DMA_ERR
211 int "IRQ Handshake DMA Status"
212 default 7
213config IRQ_PIXC_IN0
214 int "IRQ PIXC IN0"
215 default 8
216config IRQ_PIXC_IN1
217 int "IRQ PIXC IN1"
218 default 8
219config IRQ_PIXC_OUT
220 int "IRQ PIXC OUT"
221 default 8
222config IRQ_SDH
223 int "IRQ SDH"
224 default 8
225config IRQ_CNT
226 int "IRQ CNT"
227 default 8
228config IRQ_KEY
229 int "IRQ KEY"
230 default 8
231config IRQ_CAN1_RX
232 int "IRQ CAN1 RX"
233 default 11
234config IRQ_CAN1_TX
235 int "IRQ_CAN1_TX"
236 default 11
237config IRQ_SDH_MASK0
238 int "IRQ_SDH_MASK0"
239 default 11
240config IRQ_SDH_MASK1
241 int "IRQ_SDH_MASK1"
242 default 11
243config IRQ_USB_INT0
244 int "IRQ USB INT0"
245 default 11
246config IRQ_USB_INT1
247 int "IRQ USB INT1"
248 default 11
249config IRQ_USB_INT2
250 int "IRQ USB INT2"
251 default 11
252config IRQ_USB_DMA
253 int "IRQ USB DMA"
254 default 11
255config IRQ_OTPSEC
256 int "IRQ OPTSEC"
257 default 11
258config IRQ_TIMER0
259 int "IRQ_TIMER0"
Graf Yang1fa9be72009-05-15 11:01:59 +0000[diff] [blame^]260 default 7 if TICKSOURCE_GPTMR0
Yi Li6a01f232009-01-07 23:14:39 +0800[diff] [blame]261 default 8
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]262config IRQ_TIMER1
263 int "IRQ_TIMER1"
264 default 11
265config IRQ_TIMER2
266 int "IRQ_TIMER2"
267 default 11
268config IRQ_TIMER3
269 int "IRQ_TIMER3"
270 default 11
271config IRQ_TIMER4
272 int "IRQ_TIMER4"
273 default 11
274config IRQ_TIMER5
275 int "IRQ_TIMER5"
276 default 11
277config IRQ_TIMER6
278 int "IRQ_TIMER6"
279 default 11
280config IRQ_TIMER7
281 int "IRQ_TIMER7"
282 default 11
283config IRQ_PINT2
284 int "IRQ_PIN2"
285 default 11
286config IRQ_PINT3
287 int "IRQ_PIN3"
288 default 11
289
290 help
291 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
292 This applies to all the above. It is not recommended to assign the
293 highest priority number 7 to UART or any other device.
294
295endmenu
296
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]297comment "Pin Interrupt to Port Assignment"
298menu "Assignment"
299
300config PINTx_REASSIGN
301 bool "Reprogram PINT Assignment"
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]302 default y
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]303 help
304 The interrupt assignment registers controls the pin-to-interrupt
305 assignment in a byte-wide manner. Each option allows you to select
306 a set of pins (High/Low Byte) of an specific Port being mapped
307 to one of the four PIN Interrupts IRQ_PINTx.
308
309 You shouldn't change any of these unless you know exactly what you're doing.
310 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
311
312config PINT0_ASSIGN
313 hex "PINT0_ASSIGN"
314 depends on PINTx_REASSIGN
315 default 0x00000101
316config PINT1_ASSIGN
317 hex "PINT1_ASSIGN"
318 depends on PINTx_REASSIGN
319 default 0x01010000
320config PINT2_ASSIGN
321 hex "PINT2_ASSIGN"
322 depends on PINTx_REASSIGN
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]323 default 0x07000101
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]324config PINT3_ASSIGN
325 hex "PINT3_ASSIGN"
326 depends on PINTx_REASSIGN
327 default 0x02020303
328
329endmenu
330
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]331endmenu
332
333endif