Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/spinlock.h> |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame^] | 21 | #include <linux/delay.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 22 | #include <linux/mfd/pm8xxx/core.h> |
| 23 | #include <linux/mfd/pm8xxx/misc.h> |
| 24 | |
| 25 | /* PON CTRL 1 register */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 26 | #define REG_PM8XXX_PON_CTRL_1 0x01C |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 27 | |
| 28 | #define PON_CTRL_1_PULL_UP_MASK 0xE0 |
| 29 | #define PON_CTRL_1_USB_PWR_EN 0x10 |
| 30 | |
| 31 | #define PON_CTRL_1_WD_EN_MASK 0x08 |
| 32 | #define PON_CTRL_1_WD_EN_RESET 0x08 |
| 33 | #define PON_CTRL_1_WD_EN_PWR_OFF 0x00 |
| 34 | |
Anirudh Ghayal | a4262a3 | 2011-11-10 00:02:18 +0530 | [diff] [blame] | 35 | /* PON CNTL registers */ |
| 36 | #define REG_PM8058_PON_CNTL_4 0x098 |
| 37 | #define REG_PM8901_PON_CNTL_4 0x099 |
| 38 | #define REG_PM8018_PON_CNTL_4 0x01E |
| 39 | #define REG_PM8921_PON_CNTL_4 0x01E |
| 40 | #define REG_PM8058_PON_CNTL_5 0x07B |
| 41 | #define REG_PM8901_PON_CNTL_5 0x09A |
| 42 | #define REG_PM8018_PON_CNTL_5 0x01F |
| 43 | #define REG_PM8921_PON_CNTL_5 0x01F |
| 44 | |
| 45 | #define PON_CTRL_4_RESET_EN_MASK 0x01 |
| 46 | #define PON_CTRL_4_SHUTDOWN_ON_RESET 0x0 |
| 47 | #define PON_CTRL_4_RESTART_ON_RESET 0x1 |
| 48 | #define PON_CTRL_5_HARD_RESET_EN_MASK 0x08 |
| 49 | #define PON_CTRL_5_HARD_RESET_EN 0x08 |
| 50 | #define PON_CTRL_5_HARD_RESET_DIS 0x00 |
| 51 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 52 | /* Regulator master enable addresses */ |
| 53 | #define REG_PM8058_VREG_EN_MSM 0x018 |
| 54 | #define REG_PM8058_VREG_EN_GRP_5_4 0x1C8 |
| 55 | |
| 56 | /* Regulator control registers for shutdown/reset */ |
| 57 | #define REG_PM8058_S0_CTRL 0x004 |
| 58 | #define REG_PM8058_S1_CTRL 0x005 |
| 59 | #define REG_PM8058_S3_CTRL 0x111 |
| 60 | #define REG_PM8058_L21_CTRL 0x120 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 61 | #define REG_PM8058_L22_CTRL 0x121 |
| 62 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 63 | #define PM8058_REGULATOR_ENABLE_MASK 0x80 |
| 64 | #define PM8058_REGULATOR_ENABLE 0x80 |
| 65 | #define PM8058_REGULATOR_DISABLE 0x00 |
| 66 | #define PM8058_REGULATOR_PULL_DOWN_MASK 0x40 |
| 67 | #define PM8058_REGULATOR_PULL_DOWN_EN 0x40 |
| 68 | |
| 69 | /* Buck CTRL register */ |
| 70 | #define PM8058_SMPS_LEGACY_VREF_SEL 0x20 |
| 71 | #define PM8058_SMPS_LEGACY_VPROG_MASK 0x1F |
| 72 | #define PM8058_SMPS_ADVANCED_BAND_MASK 0xC0 |
| 73 | #define PM8058_SMPS_ADVANCED_BAND_SHIFT 6 |
| 74 | #define PM8058_SMPS_ADVANCED_VPROG_MASK 0x3F |
| 75 | |
| 76 | /* Buck TEST2 registers for shutdown/reset */ |
| 77 | #define REG_PM8058_S0_TEST2 0x084 |
| 78 | #define REG_PM8058_S1_TEST2 0x085 |
| 79 | #define REG_PM8058_S3_TEST2 0x11A |
| 80 | |
| 81 | #define PM8058_REGULATOR_BANK_WRITE 0x80 |
| 82 | #define PM8058_REGULATOR_BANK_MASK 0x70 |
| 83 | #define PM8058_REGULATOR_BANK_SHIFT 4 |
| 84 | #define PM8058_REGULATOR_BANK_SEL(n) ((n) << PM8058_REGULATOR_BANK_SHIFT) |
| 85 | |
| 86 | /* Buck TEST2 register bank 1 */ |
| 87 | #define PM8058_SMPS_LEGACY_VLOW_SEL 0x01 |
| 88 | |
| 89 | /* Buck TEST2 register bank 7 */ |
| 90 | #define PM8058_SMPS_ADVANCED_MODE_MASK 0x02 |
| 91 | #define PM8058_SMPS_ADVANCED_MODE 0x02 |
| 92 | #define PM8058_SMPS_LEGACY_MODE 0x00 |
| 93 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 94 | /* SLEEP CTRL register */ |
| 95 | #define REG_PM8058_SLEEP_CTRL 0x02B |
| 96 | #define REG_PM8921_SLEEP_CTRL 0x10A |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 97 | #define REG_PM8018_SLEEP_CTRL 0x10A |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 98 | |
| 99 | #define SLEEP_CTRL_SMPL_EN_MASK 0x04 |
| 100 | #define SLEEP_CTRL_SMPL_EN_RESET 0x04 |
| 101 | #define SLEEP_CTRL_SMPL_EN_PWR_OFF 0x00 |
| 102 | |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame] | 103 | #define SLEEP_CTRL_SMPL_SEL_MASK 0x03 |
| 104 | #define SLEEP_CTRL_SMPL_SEL_MIN 0 |
| 105 | #define SLEEP_CTRL_SMPL_SEL_MAX 3 |
| 106 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 107 | /* FTS regulator PMR registers */ |
| 108 | #define REG_PM8901_REGULATOR_S1_PMR 0xA7 |
| 109 | #define REG_PM8901_REGULATOR_S2_PMR 0xA8 |
| 110 | #define REG_PM8901_REGULATOR_S3_PMR 0xA9 |
| 111 | #define REG_PM8901_REGULATOR_S4_PMR 0xAA |
| 112 | |
| 113 | #define PM8901_REGULATOR_PMR_STATE_MASK 0x60 |
| 114 | #define PM8901_REGULATOR_PMR_STATE_OFF 0x20 |
| 115 | |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 116 | /* COINCELL CHG registers */ |
| 117 | #define REG_PM8058_COIN_CHG 0x02F |
| 118 | #define REG_PM8921_COIN_CHG 0x09C |
| 119 | #define REG_PM8018_COIN_CHG 0x09C |
| 120 | |
| 121 | #define COINCELL_RESISTOR_SHIFT 0x2 |
| 122 | |
Anirudh Ghayal | 51e947f | 2011-11-01 14:49:45 +0530 | [diff] [blame] | 123 | /* GP TEST register */ |
| 124 | #define REG_PM8XXX_GP_TEST_1 0x07A |
| 125 | |
| 126 | /* Stay on configuration */ |
| 127 | #define PM8XXX_STAY_ON_CFG 0x92 |
| 128 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 129 | /* GPIO UART MUX CTRL registers */ |
| 130 | #define REG_PM8XXX_GPIO_MUX_CTRL 0x1CC |
| 131 | |
| 132 | #define UART_PATH_SEL_MASK 0x60 |
| 133 | #define UART_PATH_SEL_SHIFT 0x5 |
| 134 | |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame^] | 135 | /* Shutdown/restart delays to allow for LDO 7/dVdd regulator load settling. */ |
| 136 | #define PM8901_DELAY_AFTER_REG_DISABLE_MS 4 |
| 137 | #define PM8901_DELAY_BEFORE_SHUTDOWN_MS 8 |
| 138 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 139 | struct pm8xxx_misc_chip { |
| 140 | struct list_head link; |
| 141 | struct pm8xxx_misc_platform_data pdata; |
| 142 | struct device *dev; |
| 143 | enum pm8xxx_version version; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 144 | u64 osc_halt_count; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 145 | }; |
| 146 | |
| 147 | static LIST_HEAD(pm8xxx_misc_chips); |
| 148 | static DEFINE_SPINLOCK(pm8xxx_misc_chips_lock); |
| 149 | |
| 150 | static int pm8xxx_misc_masked_write(struct pm8xxx_misc_chip *chip, u16 addr, |
| 151 | u8 mask, u8 val) |
| 152 | { |
| 153 | int rc; |
| 154 | u8 reg; |
| 155 | |
| 156 | rc = pm8xxx_readb(chip->dev->parent, addr, ®); |
| 157 | if (rc) { |
| 158 | pr_err("pm8xxx_readb(0x%03X) failed, rc=%d\n", addr, rc); |
| 159 | return rc; |
| 160 | } |
| 161 | reg &= ~mask; |
| 162 | reg |= val & mask; |
| 163 | rc = pm8xxx_writeb(chip->dev->parent, addr, reg); |
| 164 | if (rc) |
| 165 | pr_err("pm8xxx_writeb(0x%03X)=0x%02X failed, rc=%d\n", addr, |
| 166 | reg, rc); |
| 167 | return rc; |
| 168 | } |
| 169 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 170 | /* |
| 171 | * Set an SMPS regulator to be disabled in its CTRL register, but enabled |
| 172 | * in the master enable register. Also set it's pull down enable bit. |
| 173 | * Take care to make sure that the output voltage doesn't change if switching |
| 174 | * from advanced mode to legacy mode. |
| 175 | */ |
| 176 | static int |
| 177 | __pm8058_disable_smps_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 178 | u16 ctrl_addr, u16 test2_addr, u16 master_enable_addr, |
| 179 | u8 master_enable_bit) |
| 180 | { |
| 181 | int rc = 0; |
| 182 | u8 vref_sel, vlow_sel, band, vprog, bank, reg; |
| 183 | |
| 184 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 185 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 186 | if (rc) { |
| 187 | pr_err("%s: pm8xxx_writeb(0x%03X) failed: rc=%d\n", __func__, |
| 188 | test2_addr, rc); |
| 189 | goto done; |
| 190 | } |
| 191 | |
| 192 | rc = pm8xxx_readb(chip->dev->parent, test2_addr, ®); |
| 193 | if (rc) { |
| 194 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 195 | __func__, test2_addr, rc); |
| 196 | goto done; |
| 197 | } |
| 198 | |
| 199 | /* Check if in advanced mode. */ |
| 200 | if ((reg & PM8058_SMPS_ADVANCED_MODE_MASK) == |
| 201 | PM8058_SMPS_ADVANCED_MODE) { |
| 202 | /* Determine current output voltage. */ |
| 203 | rc = pm8xxx_readb(chip->dev->parent, ctrl_addr, ®); |
| 204 | if (rc) { |
| 205 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 206 | __func__, ctrl_addr, rc); |
| 207 | goto done; |
| 208 | } |
| 209 | |
| 210 | band = (reg & PM8058_SMPS_ADVANCED_BAND_MASK) |
| 211 | >> PM8058_SMPS_ADVANCED_BAND_SHIFT; |
| 212 | switch (band) { |
| 213 | case 3: |
| 214 | vref_sel = 0; |
| 215 | vlow_sel = 0; |
| 216 | break; |
| 217 | case 2: |
| 218 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 219 | vlow_sel = 0; |
| 220 | break; |
| 221 | case 1: |
| 222 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 223 | vlow_sel = PM8058_SMPS_LEGACY_VLOW_SEL; |
| 224 | break; |
| 225 | default: |
| 226 | pr_err("%s: regulator already disabled\n", __func__); |
| 227 | return -EPERM; |
| 228 | } |
| 229 | vprog = (reg & PM8058_SMPS_ADVANCED_VPROG_MASK); |
| 230 | /* Round up if fine step is in use. */ |
| 231 | vprog = (vprog + 1) >> 1; |
| 232 | if (vprog > PM8058_SMPS_LEGACY_VPROG_MASK) |
| 233 | vprog = PM8058_SMPS_LEGACY_VPROG_MASK; |
| 234 | |
| 235 | /* Set VLOW_SEL bit. */ |
| 236 | bank = PM8058_REGULATOR_BANK_SEL(1); |
| 237 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 238 | if (rc) { |
| 239 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 240 | __func__, test2_addr, rc); |
| 241 | goto done; |
| 242 | } |
| 243 | |
| 244 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 245 | PM8058_REGULATOR_BANK_WRITE | PM8058_REGULATOR_BANK_MASK |
| 246 | | PM8058_SMPS_LEGACY_VLOW_SEL, |
| 247 | PM8058_REGULATOR_BANK_WRITE | |
| 248 | PM8058_REGULATOR_BANK_SEL(1) | vlow_sel); |
| 249 | if (rc) |
| 250 | goto done; |
| 251 | |
| 252 | /* Switch to legacy mode */ |
| 253 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 254 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 255 | if (rc) { |
| 256 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 257 | __func__, test2_addr, rc); |
| 258 | goto done; |
| 259 | } |
| 260 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 261 | PM8058_REGULATOR_BANK_WRITE | |
| 262 | PM8058_REGULATOR_BANK_MASK | |
| 263 | PM8058_SMPS_ADVANCED_MODE_MASK, |
| 264 | PM8058_REGULATOR_BANK_WRITE | |
| 265 | PM8058_REGULATOR_BANK_SEL(7) | |
| 266 | PM8058_SMPS_LEGACY_MODE); |
| 267 | if (rc) |
| 268 | goto done; |
| 269 | |
| 270 | /* Enable locally, enable pull down, keep voltage the same. */ |
| 271 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 272 | PM8058_REGULATOR_ENABLE_MASK | |
| 273 | PM8058_REGULATOR_PULL_DOWN_MASK | |
| 274 | PM8058_SMPS_LEGACY_VREF_SEL | |
| 275 | PM8058_SMPS_LEGACY_VPROG_MASK, |
| 276 | PM8058_REGULATOR_ENABLE | PM8058_REGULATOR_PULL_DOWN_EN |
| 277 | | vref_sel | vprog); |
| 278 | if (rc) |
| 279 | goto done; |
| 280 | } |
| 281 | |
| 282 | /* Enable in master control register. */ |
| 283 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 284 | master_enable_bit, master_enable_bit); |
| 285 | if (rc) |
| 286 | goto done; |
| 287 | |
| 288 | /* Disable locally and enable pull down. */ |
| 289 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 290 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 291 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 292 | |
| 293 | done: |
| 294 | return rc; |
| 295 | } |
| 296 | |
| 297 | static int |
| 298 | __pm8058_disable_ldo_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 299 | u16 ctrl_addr, u16 master_enable_addr, u8 master_enable_bit) |
| 300 | { |
| 301 | int rc; |
| 302 | |
| 303 | /* Enable LDO in master control register. */ |
| 304 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 305 | master_enable_bit, master_enable_bit); |
| 306 | if (rc) |
| 307 | goto done; |
| 308 | |
| 309 | /* Disable LDO in CTRL register and set pull down */ |
| 310 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 311 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 312 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 313 | |
| 314 | done: |
| 315 | return rc; |
| 316 | } |
| 317 | |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 318 | static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 319 | { |
| 320 | int rc; |
| 321 | |
| 322 | /* Enable SMPL if resetting is desired. */ |
| 323 | rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL, |
| 324 | SLEEP_CTRL_SMPL_EN_MASK, |
| 325 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 326 | if (rc) { |
| 327 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 328 | return rc; |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 333 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 334 | * USB charging is enabled. |
| 335 | */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 336 | rc = pm8xxx_misc_masked_write(chip, REG_PM8XXX_PON_CTRL_1, |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 337 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 338 | | PON_CTRL_1_WD_EN_MASK, |
| 339 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 340 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 341 | if (rc) |
| 342 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 343 | |
| 344 | return rc; |
| 345 | } |
| 346 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 347 | static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 348 | { |
| 349 | int rc; |
| 350 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 351 | /* When shutting down, enable active pulldowns on important rails. */ |
| 352 | if (!reset) { |
| 353 | /* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */ |
| 354 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 355 | REG_PM8058_S0_CTRL, REG_PM8058_S0_TEST2, |
| 356 | REG_PM8058_VREG_EN_MSM, BIT(7)); |
| 357 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 358 | REG_PM8058_S1_CTRL, REG_PM8058_S1_TEST2, |
| 359 | REG_PM8058_VREG_EN_MSM, BIT(6)); |
| 360 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 361 | REG_PM8058_S3_CTRL, REG_PM8058_S3_TEST2, |
| 362 | REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4)); |
| 363 | /* Disable LDO 21 locally and set pulldown enable bit. */ |
| 364 | __pm8058_disable_ldo_locally_set_pull_down(chip, |
| 365 | REG_PM8058_L21_CTRL, REG_PM8058_VREG_EN_GRP_5_4, |
| 366 | BIT(1)); |
| 367 | } |
| 368 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 369 | /* |
| 370 | * Fix-up: Set regulator LDO22 to 1.225 V in high power mode. Leave its |
| 371 | * pull-down state intact. This ensures a safe shutdown. |
| 372 | */ |
| 373 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_L22_CTRL, 0xBF, 0x93); |
| 374 | if (rc) { |
| 375 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 376 | goto read_write_err; |
| 377 | } |
| 378 | |
| 379 | /* Enable SMPL if resetting is desired. */ |
| 380 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_SLEEP_CTRL, |
| 381 | SLEEP_CTRL_SMPL_EN_MASK, |
| 382 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 383 | if (rc) { |
| 384 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 385 | goto read_write_err; |
| 386 | } |
| 387 | |
| 388 | /* |
| 389 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 390 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 391 | * USB charging is enabled. |
| 392 | */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 393 | rc = pm8xxx_misc_masked_write(chip, REG_PM8XXX_PON_CTRL_1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 394 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 395 | | PON_CTRL_1_WD_EN_MASK, |
| 396 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 397 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 398 | if (rc) { |
| 399 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 400 | goto read_write_err; |
| 401 | } |
| 402 | |
| 403 | read_write_err: |
| 404 | return rc; |
| 405 | } |
| 406 | |
| 407 | static int __pm8901_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 408 | { |
| 409 | int rc = 0, i; |
| 410 | u8 pmr_addr[4] = { |
| 411 | REG_PM8901_REGULATOR_S2_PMR, |
| 412 | REG_PM8901_REGULATOR_S3_PMR, |
| 413 | REG_PM8901_REGULATOR_S4_PMR, |
| 414 | REG_PM8901_REGULATOR_S1_PMR, |
| 415 | }; |
| 416 | |
| 417 | /* Fix-up: Turn off regulators S1, S2, S3, S4 when shutting down. */ |
| 418 | if (!reset) { |
| 419 | for (i = 0; i < 4; i++) { |
| 420 | rc = pm8xxx_misc_masked_write(chip, pmr_addr[i], |
| 421 | PM8901_REGULATOR_PMR_STATE_MASK, |
| 422 | PM8901_REGULATOR_PMR_STATE_OFF); |
| 423 | if (rc) { |
| 424 | pr_err("pm8xxx_misc_masked_write failed, " |
| 425 | "rc=%d\n", rc); |
| 426 | goto read_write_err; |
| 427 | } |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame^] | 428 | mdelay(PM8901_DELAY_AFTER_REG_DISABLE_MS); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 429 | } |
| 430 | } |
| 431 | |
| 432 | read_write_err: |
Anirudh Ghayal | 1fd48c6 | 2011-12-13 12:39:43 +0530 | [diff] [blame^] | 433 | mdelay(PM8901_DELAY_BEFORE_SHUTDOWN_MS); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 434 | return rc; |
| 435 | } |
| 436 | |
| 437 | static int __pm8921_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 438 | { |
| 439 | int rc; |
| 440 | |
| 441 | /* Enable SMPL if resetting is desired. */ |
| 442 | rc = pm8xxx_misc_masked_write(chip, REG_PM8921_SLEEP_CTRL, |
| 443 | SLEEP_CTRL_SMPL_EN_MASK, |
| 444 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 445 | if (rc) { |
| 446 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 447 | goto read_write_err; |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 452 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 453 | * USB charging is enabled. |
| 454 | */ |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 455 | rc = pm8xxx_misc_masked_write(chip, REG_PM8XXX_PON_CTRL_1, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 456 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 457 | | PON_CTRL_1_WD_EN_MASK, |
| 458 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 459 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 460 | if (rc) { |
| 461 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 462 | goto read_write_err; |
| 463 | } |
| 464 | |
| 465 | read_write_err: |
| 466 | return rc; |
| 467 | } |
| 468 | |
| 469 | /** |
| 470 | * pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to |
| 471 | * either reset or shutdown when they are turned off |
| 472 | * @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs |
| 473 | * |
| 474 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 475 | */ |
| 476 | int pm8xxx_reset_pwr_off(int reset) |
| 477 | { |
| 478 | struct pm8xxx_misc_chip *chip; |
| 479 | unsigned long flags; |
| 480 | int rc = 0; |
| 481 | |
| 482 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 483 | |
| 484 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 485 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 486 | switch (chip->version) { |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 487 | case PM8XXX_VERSION_8018: |
| 488 | rc = __pm8018_reset_pwr_off(chip, reset); |
| 489 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 490 | case PM8XXX_VERSION_8058: |
| 491 | rc = __pm8058_reset_pwr_off(chip, reset); |
| 492 | break; |
| 493 | case PM8XXX_VERSION_8901: |
| 494 | rc = __pm8901_reset_pwr_off(chip, reset); |
| 495 | break; |
| 496 | case PM8XXX_VERSION_8921: |
| 497 | rc = __pm8921_reset_pwr_off(chip, reset); |
| 498 | break; |
| 499 | default: |
| 500 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 501 | break; |
| 502 | } |
| 503 | if (rc) { |
| 504 | pr_err("reset_pwr_off failed, rc=%d\n", rc); |
| 505 | break; |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 510 | |
| 511 | return rc; |
| 512 | } |
| 513 | EXPORT_SYMBOL_GPL(pm8xxx_reset_pwr_off); |
| 514 | |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 515 | /** |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame] | 516 | * pm8xxx_smpl_control - enables/disables SMPL detection |
| 517 | * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss |
| 518 | * |
| 519 | * This function enables or disables the Sudden Momentary Power Loss detection |
| 520 | * module. If SMPL detection is enabled, then when a sufficiently long power |
| 521 | * loss event occurs, the PMIC will automatically reset itself. If SMPL |
| 522 | * detection is disabled, then the PMIC will shutdown when power loss occurs. |
| 523 | * |
| 524 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 525 | */ |
| 526 | int pm8xxx_smpl_control(int enable) |
| 527 | { |
| 528 | struct pm8xxx_misc_chip *chip; |
| 529 | unsigned long flags; |
| 530 | int rc = 0; |
| 531 | |
| 532 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 533 | |
| 534 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 535 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 536 | switch (chip->version) { |
| 537 | case PM8XXX_VERSION_8018: |
| 538 | rc = pm8xxx_misc_masked_write(chip, |
| 539 | REG_PM8018_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 540 | (enable ? SLEEP_CTRL_SMPL_EN_PWR_OFF |
| 541 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 542 | break; |
| 543 | case PM8XXX_VERSION_8058: |
| 544 | rc = pm8xxx_misc_masked_write(chip, |
| 545 | REG_PM8058_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 546 | (enable ? SLEEP_CTRL_SMPL_EN_RESET |
| 547 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 548 | break; |
| 549 | case PM8XXX_VERSION_8921: |
| 550 | rc = pm8xxx_misc_masked_write(chip, |
| 551 | REG_PM8921_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 552 | (enable ? SLEEP_CTRL_SMPL_EN_PWR_OFF |
| 553 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 554 | break; |
| 555 | default: |
| 556 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 557 | break; |
| 558 | } |
| 559 | if (rc) { |
| 560 | pr_err("setting smpl control failed, rc=%d\n", rc); |
| 561 | break; |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 566 | |
| 567 | return rc; |
| 568 | } |
| 569 | EXPORT_SYMBOL(pm8xxx_smpl_control); |
| 570 | |
| 571 | |
| 572 | /** |
| 573 | * pm8xxx_smpl_set_delay - sets the SMPL detection time delay |
| 574 | * @delay: enum value corresponding to delay time |
| 575 | * |
| 576 | * This function sets the time delay of the SMPL detection module. If power |
| 577 | * is reapplied within this interval, then the PMIC reset automatically. The |
| 578 | * SMPL detection module must be enabled for this delay time to take effect. |
| 579 | * |
| 580 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 581 | */ |
| 582 | int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay) |
| 583 | { |
| 584 | struct pm8xxx_misc_chip *chip; |
| 585 | unsigned long flags; |
| 586 | int rc = 0; |
| 587 | |
| 588 | if (delay < SLEEP_CTRL_SMPL_SEL_MIN |
| 589 | || delay > SLEEP_CTRL_SMPL_SEL_MAX) { |
| 590 | pr_err("%s: invalid delay specified: %d\n", __func__, delay); |
| 591 | return -EINVAL; |
| 592 | } |
| 593 | |
| 594 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 595 | |
| 596 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 597 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 598 | switch (chip->version) { |
| 599 | case PM8XXX_VERSION_8018: |
| 600 | rc = pm8xxx_misc_masked_write(chip, |
| 601 | REG_PM8018_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 602 | delay); |
| 603 | break; |
| 604 | case PM8XXX_VERSION_8058: |
| 605 | rc = pm8xxx_misc_masked_write(chip, |
| 606 | REG_PM8058_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 607 | delay); |
| 608 | break; |
| 609 | case PM8XXX_VERSION_8921: |
| 610 | rc = pm8xxx_misc_masked_write(chip, |
| 611 | REG_PM8921_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 612 | delay); |
| 613 | break; |
| 614 | default: |
| 615 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 616 | break; |
| 617 | } |
| 618 | if (rc) { |
| 619 | pr_err("setting smpl delay failed, rc=%d\n", rc); |
| 620 | break; |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 625 | |
| 626 | return rc; |
| 627 | } |
| 628 | EXPORT_SYMBOL(pm8xxx_smpl_set_delay); |
| 629 | |
| 630 | /** |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 631 | * pm8xxx_coincell_chg_config - Disables or enables the coincell charger, and |
| 632 | * configures its voltage and resistor settings. |
| 633 | * @chg_config: Holds both voltage and resistor values, and a |
| 634 | * switch to change the state of charger. |
| 635 | * If state is to disable the charger then |
| 636 | * both voltage and resistor are disregarded. |
| 637 | * |
| 638 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 639 | */ |
| 640 | int pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config) |
| 641 | { |
| 642 | struct pm8xxx_misc_chip *chip; |
| 643 | unsigned long flags; |
| 644 | u8 reg = 0, voltage, resistor; |
| 645 | int rc = 0; |
| 646 | |
| 647 | if (chg_config == NULL) { |
| 648 | pr_err("chg_config is NULL\n"); |
| 649 | return -EINVAL; |
| 650 | } |
| 651 | |
| 652 | voltage = chg_config->voltage; |
| 653 | resistor = chg_config->resistor; |
| 654 | |
| 655 | if (resistor < PM8XXX_COINCELL_RESISTOR_2100_OHMS || |
| 656 | resistor > PM8XXX_COINCELL_RESISTOR_800_OHMS) { |
| 657 | pr_err("Invalid resistor value provided\n"); |
| 658 | return -EINVAL; |
| 659 | } |
| 660 | |
| 661 | if (voltage < PM8XXX_COINCELL_VOLTAGE_3p2V || |
| 662 | (voltage > PM8XXX_COINCELL_VOLTAGE_3p0V && |
| 663 | voltage != PM8XXX_COINCELL_VOLTAGE_2p5V)) { |
| 664 | pr_err("Invalid voltage value provided\n"); |
| 665 | return -EINVAL; |
| 666 | } |
| 667 | |
| 668 | if (chg_config->state == PM8XXX_COINCELL_CHG_DISABLE) { |
| 669 | reg = 0; |
| 670 | } else { |
| 671 | reg |= voltage; |
| 672 | reg |= (resistor << COINCELL_RESISTOR_SHIFT); |
| 673 | } |
| 674 | |
| 675 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 676 | |
| 677 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 678 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 679 | switch (chip->version) { |
| 680 | case PM8XXX_VERSION_8018: |
| 681 | rc = pm8xxx_writeb(chip->dev->parent, |
| 682 | REG_PM8018_COIN_CHG, reg); |
| 683 | break; |
| 684 | case PM8XXX_VERSION_8058: |
| 685 | rc = pm8xxx_writeb(chip->dev->parent, |
| 686 | REG_PM8058_COIN_CHG, reg); |
| 687 | break; |
| 688 | case PM8XXX_VERSION_8921: |
| 689 | rc = pm8xxx_writeb(chip->dev->parent, |
| 690 | REG_PM8921_COIN_CHG, reg); |
| 691 | break; |
| 692 | default: |
| 693 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 694 | break; |
| 695 | } |
| 696 | if (rc) { |
| 697 | pr_err("coincell chg. config failed, rc=%d\n", rc); |
| 698 | break; |
| 699 | } |
| 700 | } |
| 701 | |
| 702 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 703 | |
| 704 | return rc; |
| 705 | } |
| 706 | EXPORT_SYMBOL(pm8xxx_coincell_chg_config); |
| 707 | |
Anirudh Ghayal | a23c1ca | 2011-11-01 14:36:24 +0530 | [diff] [blame] | 708 | /** |
| 709 | * pm8xxx_watchdog_reset_control - enables/disables watchdog reset detection |
| 710 | * @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low |
| 711 | * |
| 712 | * This function enables or disables the PMIC watchdog reset detection feature. |
| 713 | * If watchdog reset detection is enabled, then the PMIC will reset itself |
| 714 | * when PS_HOLD goes low. If it is not enabled, then the PMIC will shutdown |
| 715 | * when PS_HOLD goes low. |
| 716 | * |
| 717 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 718 | */ |
| 719 | int pm8xxx_watchdog_reset_control(int enable) |
| 720 | { |
| 721 | struct pm8xxx_misc_chip *chip; |
| 722 | unsigned long flags; |
| 723 | int rc = 0; |
| 724 | |
| 725 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 726 | |
| 727 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 728 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 729 | switch (chip->version) { |
| 730 | case PM8XXX_VERSION_8018: |
| 731 | case PM8XXX_VERSION_8058: |
| 732 | case PM8XXX_VERSION_8921: |
| 733 | rc = pm8xxx_misc_masked_write(chip, |
| 734 | REG_PM8XXX_PON_CTRL_1, PON_CTRL_1_WD_EN_MASK, |
| 735 | (enable ? PON_CTRL_1_WD_EN_RESET |
| 736 | : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 737 | break; |
| 738 | default: |
| 739 | /* WD reset control not supported */ |
| 740 | break; |
| 741 | } |
| 742 | if (rc) { |
| 743 | pr_err("setting WD reset control failed, rc=%d\n", rc); |
| 744 | break; |
| 745 | } |
| 746 | } |
| 747 | |
| 748 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 749 | |
| 750 | return rc; |
| 751 | } |
| 752 | EXPORT_SYMBOL(pm8xxx_watchdog_reset_control); |
| 753 | |
Anirudh Ghayal | 51e947f | 2011-11-01 14:49:45 +0530 | [diff] [blame] | 754 | /** |
| 755 | * pm8xxx_stay_on - enables stay_on feature |
| 756 | * |
| 757 | * PMIC stay-on feature allows PMIC to ignore MSM PS_HOLD=low |
| 758 | * signal so that some special functions like debugging could be |
| 759 | * performed. |
| 760 | * |
| 761 | * This feature should not be used in any product release. |
| 762 | * |
| 763 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 764 | */ |
| 765 | int pm8xxx_stay_on(void) |
| 766 | { |
| 767 | struct pm8xxx_misc_chip *chip; |
| 768 | unsigned long flags; |
| 769 | int rc = 0; |
| 770 | |
| 771 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 772 | |
| 773 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 774 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 775 | switch (chip->version) { |
| 776 | case PM8XXX_VERSION_8018: |
| 777 | case PM8XXX_VERSION_8058: |
| 778 | case PM8XXX_VERSION_8921: |
| 779 | rc = pm8xxx_writeb(chip->dev->parent, |
| 780 | REG_PM8XXX_GP_TEST_1, PM8XXX_STAY_ON_CFG); |
| 781 | break; |
| 782 | default: |
| 783 | /* stay on not supported */ |
| 784 | break; |
| 785 | } |
| 786 | if (rc) { |
| 787 | pr_err("stay_on failed failed, rc=%d\n", rc); |
| 788 | break; |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 793 | |
| 794 | return rc; |
| 795 | } |
| 796 | EXPORT_SYMBOL(pm8xxx_stay_on); |
| 797 | |
Anirudh Ghayal | a4262a3 | 2011-11-10 00:02:18 +0530 | [diff] [blame] | 798 | static int |
| 799 | __pm8xxx_hard_reset_config(struct pm8xxx_misc_chip *chip, |
| 800 | enum pm8xxx_pon_config config, u16 pon4_addr, u16 pon5_addr) |
| 801 | { |
| 802 | int rc = 0; |
| 803 | |
| 804 | switch (config) { |
| 805 | case PM8XXX_DISABLE_HARD_RESET: |
| 806 | rc = pm8xxx_misc_masked_write(chip, pon5_addr, |
| 807 | PON_CTRL_5_HARD_RESET_EN_MASK, |
| 808 | PON_CTRL_5_HARD_RESET_DIS); |
| 809 | break; |
| 810 | case PM8XXX_SHUTDOWN_ON_HARD_RESET: |
| 811 | rc = pm8xxx_misc_masked_write(chip, pon5_addr, |
| 812 | PON_CTRL_5_HARD_RESET_EN_MASK, |
| 813 | PON_CTRL_5_HARD_RESET_EN); |
| 814 | if (!rc) { |
| 815 | rc = pm8xxx_misc_masked_write(chip, pon4_addr, |
| 816 | PON_CTRL_4_RESET_EN_MASK, |
| 817 | PON_CTRL_4_SHUTDOWN_ON_RESET); |
| 818 | } |
| 819 | break; |
| 820 | case PM8XXX_RESTART_ON_HARD_RESET: |
| 821 | rc = pm8xxx_misc_masked_write(chip, pon5_addr, |
| 822 | PON_CTRL_5_HARD_RESET_EN_MASK, |
| 823 | PON_CTRL_5_HARD_RESET_EN); |
| 824 | if (!rc) { |
| 825 | rc = pm8xxx_misc_masked_write(chip, pon4_addr, |
| 826 | PON_CTRL_4_RESET_EN_MASK, |
| 827 | PON_CTRL_4_RESTART_ON_RESET); |
| 828 | } |
| 829 | break; |
| 830 | default: |
| 831 | rc = -EINVAL; |
| 832 | break; |
| 833 | } |
| 834 | return rc; |
| 835 | } |
| 836 | |
| 837 | /** |
| 838 | * pm8xxx_hard_reset_config - Allows different reset configurations |
| 839 | * |
| 840 | * config = PM8XXX_DISABLE_HARD_RESET to disable hard reset |
| 841 | * = PM8XXX_SHUTDOWN_ON_HARD_RESET to turn off the system on hard reset |
| 842 | * = PM8XXX_RESTART_ON_HARD_RESET to restart the system on hard reset |
| 843 | * |
| 844 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 845 | */ |
| 846 | int pm8xxx_hard_reset_config(enum pm8xxx_pon_config config) |
| 847 | { |
| 848 | struct pm8xxx_misc_chip *chip; |
| 849 | unsigned long flags; |
| 850 | int rc = 0; |
| 851 | |
| 852 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 853 | |
| 854 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 855 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 856 | switch (chip->version) { |
| 857 | case PM8XXX_VERSION_8018: |
| 858 | __pm8xxx_hard_reset_config(chip, config, |
| 859 | REG_PM8018_PON_CNTL_4, REG_PM8018_PON_CNTL_5); |
| 860 | break; |
| 861 | case PM8XXX_VERSION_8058: |
| 862 | __pm8xxx_hard_reset_config(chip, config, |
| 863 | REG_PM8058_PON_CNTL_4, REG_PM8058_PON_CNTL_5); |
| 864 | break; |
| 865 | case PM8XXX_VERSION_8901: |
| 866 | __pm8xxx_hard_reset_config(chip, config, |
| 867 | REG_PM8901_PON_CNTL_4, REG_PM8901_PON_CNTL_5); |
| 868 | break; |
| 869 | case PM8XXX_VERSION_8921: |
| 870 | __pm8xxx_hard_reset_config(chip, config, |
| 871 | REG_PM8921_PON_CNTL_4, REG_PM8921_PON_CNTL_5); |
| 872 | break; |
| 873 | default: |
| 874 | /* hard reset config. no supported */ |
| 875 | break; |
| 876 | } |
| 877 | if (rc) { |
| 878 | pr_err("hard reset config. failed, rc=%d\n", rc); |
| 879 | break; |
| 880 | } |
| 881 | } |
| 882 | |
| 883 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 884 | |
| 885 | return rc; |
| 886 | } |
| 887 | EXPORT_SYMBOL(pm8xxx_hard_reset_config); |
| 888 | |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 889 | /* Handle the OSC_HALT interrupt: 32 kHz XTAL oscillator has stopped. */ |
| 890 | static irqreturn_t pm8xxx_osc_halt_isr(int irq, void *data) |
| 891 | { |
| 892 | struct pm8xxx_misc_chip *chip = data; |
| 893 | u64 count = 0; |
| 894 | |
| 895 | if (chip) { |
| 896 | chip->osc_halt_count++; |
| 897 | count = chip->osc_halt_count; |
| 898 | } |
| 899 | |
| 900 | pr_crit("%s: OSC_HALT interrupt has triggered, 32 kHz XTAL oscillator" |
| 901 | " has halted (%llu)!\n", __func__, count); |
| 902 | |
| 903 | return IRQ_HANDLED; |
| 904 | } |
| 905 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 906 | /** |
| 907 | * pm8xxx_uart_gpio_mux_ctrl - Mux configuration to select the UART |
| 908 | * |
| 909 | * @uart_path_sel: Input argument to select either UART1/2/3 |
| 910 | * |
| 911 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 912 | */ |
| 913 | int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel) |
| 914 | { |
| 915 | struct pm8xxx_misc_chip *chip; |
| 916 | unsigned long flags; |
| 917 | int rc = 0; |
| 918 | |
| 919 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 920 | |
| 921 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 922 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 923 | switch (chip->version) { |
| 924 | case PM8XXX_VERSION_8018: |
| 925 | case PM8XXX_VERSION_8058: |
| 926 | case PM8XXX_VERSION_8921: |
| 927 | rc = pm8xxx_misc_masked_write(chip, |
| 928 | REG_PM8XXX_GPIO_MUX_CTRL, UART_PATH_SEL_MASK, |
| 929 | uart_path_sel << UART_PATH_SEL_SHIFT); |
| 930 | break; |
| 931 | default: |
| 932 | /* Functionality not supported */ |
| 933 | break; |
| 934 | } |
| 935 | if (rc) { |
| 936 | pr_err("uart_gpio_mux_ctrl failed, rc=%d\n", rc); |
| 937 | break; |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 942 | |
| 943 | return rc; |
| 944 | } |
| 945 | EXPORT_SYMBOL(pm8xxx_uart_gpio_mux_ctrl); |
| 946 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 947 | static int __devinit pm8xxx_misc_probe(struct platform_device *pdev) |
| 948 | { |
| 949 | const struct pm8xxx_misc_platform_data *pdata = pdev->dev.platform_data; |
| 950 | struct pm8xxx_misc_chip *chip; |
| 951 | struct pm8xxx_misc_chip *sibling; |
| 952 | struct list_head *prev; |
| 953 | unsigned long flags; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 954 | int rc = 0, irq; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 955 | |
| 956 | if (!pdata) { |
| 957 | pr_err("missing platform data\n"); |
| 958 | return -EINVAL; |
| 959 | } |
| 960 | |
| 961 | chip = kzalloc(sizeof(struct pm8xxx_misc_chip), GFP_KERNEL); |
| 962 | if (!chip) { |
| 963 | pr_err("Cannot allocate %d bytes\n", |
| 964 | sizeof(struct pm8xxx_misc_chip)); |
| 965 | return -ENOMEM; |
| 966 | } |
| 967 | |
| 968 | chip->dev = &pdev->dev; |
| 969 | chip->version = pm8xxx_get_version(chip->dev->parent); |
| 970 | memcpy(&(chip->pdata), pdata, sizeof(struct pm8xxx_misc_platform_data)); |
| 971 | |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 972 | irq = platform_get_irq_byname(pdev, "pm8xxx_osc_halt_irq"); |
| 973 | if (irq > 0) { |
| 974 | rc = request_any_context_irq(irq, pm8xxx_osc_halt_isr, |
| 975 | IRQF_TRIGGER_RISING | IRQF_DISABLED, |
| 976 | "pm8xxx_osc_halt_irq", chip); |
| 977 | if (rc < 0) { |
| 978 | pr_err("%s: request_any_context_irq(%d) FAIL: %d\n", |
| 979 | __func__, irq, rc); |
| 980 | goto fail_irq; |
| 981 | } |
| 982 | } |
| 983 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 984 | /* Insert PMICs in priority order (lowest value first). */ |
| 985 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 986 | prev = &pm8xxx_misc_chips; |
| 987 | list_for_each_entry(sibling, &pm8xxx_misc_chips, link) { |
| 988 | if (chip->pdata.priority < sibling->pdata.priority) |
| 989 | break; |
| 990 | else |
| 991 | prev = &sibling->link; |
| 992 | } |
| 993 | list_add(&chip->link, prev); |
| 994 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 995 | |
| 996 | platform_set_drvdata(pdev, chip); |
| 997 | |
| 998 | return rc; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 999 | |
| 1000 | fail_irq: |
| 1001 | platform_set_drvdata(pdev, NULL); |
| 1002 | kfree(chip); |
| 1003 | return rc; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | static int __devexit pm8xxx_misc_remove(struct platform_device *pdev) |
| 1007 | { |
| 1008 | struct pm8xxx_misc_chip *chip = platform_get_drvdata(pdev); |
| 1009 | unsigned long flags; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 1010 | int irq = platform_get_irq_byname(pdev, "pm8xxx_osc_halt_irq"); |
| 1011 | if (irq > 0) |
| 1012 | free_irq(irq, chip); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1013 | |
| 1014 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 1015 | list_del(&chip->link); |
| 1016 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 1017 | |
| 1018 | platform_set_drvdata(pdev, NULL); |
| 1019 | kfree(chip); |
| 1020 | |
| 1021 | return 0; |
| 1022 | } |
| 1023 | |
| 1024 | static struct platform_driver pm8xxx_misc_driver = { |
| 1025 | .probe = pm8xxx_misc_probe, |
| 1026 | .remove = __devexit_p(pm8xxx_misc_remove), |
| 1027 | .driver = { |
| 1028 | .name = PM8XXX_MISC_DEV_NAME, |
| 1029 | .owner = THIS_MODULE, |
| 1030 | }, |
| 1031 | }; |
| 1032 | |
| 1033 | static int __init pm8xxx_misc_init(void) |
| 1034 | { |
| 1035 | return platform_driver_register(&pm8xxx_misc_driver); |
| 1036 | } |
| 1037 | postcore_initcall(pm8xxx_misc_init); |
| 1038 | |
| 1039 | static void __exit pm8xxx_misc_exit(void) |
| 1040 | { |
| 1041 | platform_driver_unregister(&pm8xxx_misc_driver); |
| 1042 | } |
| 1043 | module_exit(pm8xxx_misc_exit); |
| 1044 | |
| 1045 | MODULE_LICENSE("GPL v2"); |
| 1046 | MODULE_DESCRIPTION("PMIC 8XXX misc driver"); |
| 1047 | MODULE_VERSION("1.0"); |
| 1048 | MODULE_ALIAS("platform:" PM8XXX_MISC_DEV_NAME); |