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Paul Mundtcad82442006-01-16 22:14:19 -08001menu "Memory management options"
2
Paul Mundt5f8c9902007-05-08 11:55:21 +09003config QUICKLIST
4 def_bool y
5
Paul Mundtcad82442006-01-16 22:14:19 -08006config MMU
7 bool "Support for memory management hardware"
8 depends on !CPU_SH2
9 default y
10 help
11 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 boot on these systems, this option must not be set.
13
14 On other systems (such as the SH-3 and 4) where an MMU exists,
15 turning this off will boot the kernel on these machines with the
16 MMU implicitly switched off.
17
Paul Mundte7f93a32006-09-27 17:19:13 +090018config PAGE_OFFSET
19 hex
Paul Mundt36763b22007-11-21 15:34:33 +090020 default "0x80000000" if MMU && SUPERH32
21 default "0x20000000" if MMU && SUPERH64
Paul Mundte7f93a32006-09-27 17:19:13 +090022 default "0x00000000"
23
24config MEMORY_START
25 hex "Physical memory start address"
26 default "0x08000000"
27 ---help---
28 Computers built with Hitachi SuperH processors always
29 map the ROM starting at address zero. But the processor
30 does not specify the range that RAM takes.
31
32 The physical memory (RAM) start address will be automatically
33 set to 08000000. Other platforms, such as the Solution Engine
34 boards typically map RAM at 0C000000.
35
36 Tweak this only when porting to a new machine which does not
37 already have a defconfig. Changing it from the known correct
38 value on any of the known systems will only lead to disaster.
39
40config MEMORY_SIZE
41 hex "Physical memory size"
42 default "0x00400000"
43 help
44 This sets the default memory size assumed by your SH kernel. It can
45 be overridden as normal by the 'mem=' argument on the kernel command
46 line. If unsure, consult your board specifications or just leave it
47 as 0x00400000 which was the default value before this became
48 configurable.
49
Paul Mundt36bcd392007-11-10 19:16:55 +090050# Physical addressing modes
51
52config 29BIT
53 def_bool !32BIT
54 depends on SUPERH32
55
Paul Mundtcad82442006-01-16 22:14:19 -080056config 32BIT
Paul Mundt36bcd392007-11-10 19:16:55 +090057 bool
58 default y if CPU_SH5
59
60config PMB
Paul Mundtcad82442006-01-16 22:14:19 -080061 bool "Support 32-bit physical addressing through PMB"
Paul Mundt50f63f22007-06-15 18:30:42 +090062 depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
Paul Mundt36bcd392007-11-10 19:16:55 +090063 select 32BIT
Paul Mundtcad82442006-01-16 22:14:19 -080064 default y
65 help
66 If you say Y here, physical addressing will be extended to
67 32-bits through the SH-4A PMB. If this is not set, legacy
68 29-bit physical addressing will be used.
69
Paul Mundt21440cf2006-11-20 14:30:26 +090070config X2TLB
71 bool "Enable extended TLB mode"
Paul Mundtc3af3972007-09-27 18:08:46 +090072 depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
Paul Mundt21440cf2006-11-20 14:30:26 +090073 help
74 Selecting this option will enable the extended mode of the SH-X2
75 TLB. For legacy SH-X behaviour and interoperability, say N. For
76 all of the fun new features and a willingless to submit bug reports,
77 say Y.
78
Paul Mundt19f9a342006-09-27 18:33:49 +090079config VSYSCALL
80 bool "Support vsyscall page"
Paul Mundta09063d2007-11-08 18:54:16 +090081 depends on MMU && (CPU_SH3 || CPU_SH4)
Paul Mundt19f9a342006-09-27 18:33:49 +090082 default y
83 help
84 This will enable support for the kernel mapping a vDSO page
85 in process space, and subsequently handing down the entry point
86 to the libc through the ELF auxiliary vector.
87
88 From the kernel side this is used for the signal trampoline.
89 For systems with an MMU that can afford to give up a page,
90 (the default value) say Y.
91
Paul Mundtb241cb02007-06-06 17:52:19 +090092config NUMA
93 bool "Non Uniform Memory Access (NUMA) Support"
Paul Mundt357d5942007-06-11 15:32:07 +090094 depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
Paul Mundtb241cb02007-06-06 17:52:19 +090095 default n
96 help
97 Some SH systems have many various memories scattered around
98 the address space, each with varying latencies. This enables
99 support for these blocks by binding them to nodes and allowing
100 memory policies to be used for prioritizing and controlling
101 allocation behaviour.
102
Paul Mundt01066622007-03-28 16:38:13 +0900103config NODES_SHIFT
104 int
Paul Mundt99044942007-08-08 16:45:07 +0900105 default "3" if CPU_SUBTYPE_SHX3
Paul Mundt01066622007-03-28 16:38:13 +0900106 default "1"
107 depends on NEED_MULTIPLE_NODES
108
109config ARCH_FLATMEM_ENABLE
110 def_bool y
Paul Mundt357d5942007-06-11 15:32:07 +0900111 depends on !NUMA
Paul Mundt01066622007-03-28 16:38:13 +0900112
Paul Mundtdfbb9042007-05-23 17:48:36 +0900113config ARCH_SPARSEMEM_ENABLE
114 def_bool y
115 select SPARSEMEM_STATIC
116
117config ARCH_SPARSEMEM_DEFAULT
118 def_bool y
119
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900120config MAX_ACTIVE_REGIONS
121 int
Paul Mundt7da3b8e2007-08-01 17:52:47 +0900122 default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
Paul Mundtdc47e9d2007-09-27 16:48:00 +0900123 default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
124 CPU_SUBTYPE_SH7785)
Paul Mundt1ce7ddd2007-05-09 13:20:52 +0900125 default "1"
126
Paul Mundt01066622007-03-28 16:38:13 +0900127config ARCH_POPULATES_NODE_MAP
128 def_bool y
129
Paul Mundtdfbb9042007-05-23 17:48:36 +0900130config ARCH_SELECT_MEMORY_MODEL
131 def_bool y
132
Paul Mundt33d63bd2007-06-07 11:32:52 +0900133config ARCH_ENABLE_MEMORY_HOTPLUG
134 def_bool y
135 depends on SPARSEMEM
136
137config ARCH_MEMORY_PROBE
138 def_bool y
139 depends on MEMORY_HOTPLUG
140
Paul Mundtcad82442006-01-16 22:14:19 -0800141choice
Paul Mundt21440cf2006-11-20 14:30:26 +0900142 prompt "Kernel page size"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900143 default PAGE_SIZE_8KB if X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900144 default PAGE_SIZE_4KB
145
146config PAGE_SIZE_4KB
147 bool "4kB"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900148 depends on !X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900149 help
150 This is the default page size used by all SuperH CPUs.
151
152config PAGE_SIZE_8KB
153 bool "8kB"
Paul Mundt4d2cab72007-09-27 10:47:00 +0900154 depends on X2TLB
Paul Mundt21440cf2006-11-20 14:30:26 +0900155 help
156 This enables 8kB pages as supported by SH-X2 and later MMUs.
157
158config PAGE_SIZE_64KB
159 bool "64kB"
Paul Mundt079060c2007-11-11 17:25:10 +0900160 depends on CPU_SH4 || CPU_SH5
Paul Mundt21440cf2006-11-20 14:30:26 +0900161 help
162 This enables support for 64kB pages, possible on all SH-4
Paul Mundt4d2cab72007-09-27 10:47:00 +0900163 CPUs and later.
Paul Mundt21440cf2006-11-20 14:30:26 +0900164
165endchoice
166
167choice
Paul Mundtcad82442006-01-16 22:14:19 -0800168 prompt "HugeTLB page size"
Paul Mundt079060c2007-11-11 17:25:10 +0900169 depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
Paul Mundtcad82442006-01-16 22:14:19 -0800170 default HUGETLB_PAGE_SIZE_64K
171
172config HUGETLB_PAGE_SIZE_64K
Paul Mundt21440cf2006-11-20 14:30:26 +0900173 bool "64kB"
174
175config HUGETLB_PAGE_SIZE_256K
176 bool "256kB"
177 depends on X2TLB
Paul Mundtcad82442006-01-16 22:14:19 -0800178
179config HUGETLB_PAGE_SIZE_1MB
180 bool "1MB"
181
Paul Mundt21440cf2006-11-20 14:30:26 +0900182config HUGETLB_PAGE_SIZE_4MB
183 bool "4MB"
184 depends on X2TLB
185
186config HUGETLB_PAGE_SIZE_64MB
187 bool "64MB"
188 depends on X2TLB
189
Paul Mundta09063d2007-11-08 18:54:16 +0900190config HUGETLB_PAGE_SIZE_512MB
191 bool "512MB"
192 depends on CPU_SH5
193
Paul Mundtcad82442006-01-16 22:14:19 -0800194endchoice
195
196source "mm/Kconfig"
197
198endmenu
199
200menu "Cache configuration"
201
202config SH7705_CACHE_32KB
203 bool "Enable 32KB cache size for SH7705"
204 depends on CPU_SUBTYPE_SH7705
205 default y
206
207config SH_DIRECT_MAPPED
208 bool "Use direct-mapped caching"
209 default n
210 help
211 Selecting this option will configure the caches to be direct-mapped,
212 even if the cache supports a 2 or 4-way mode. This is useful primarily
213 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
214 SH4-202, SH4-501, etc.)
215
216 Turn this option off for platforms that do not have a direct-mapped
217 cache, and you have no need to run the caches in such a configuration.
218
Paul Mundte7bd34a2007-07-31 17:07:28 +0900219choice
220 prompt "Cache mode"
Paul Mundta09063d2007-11-08 18:54:16 +0900221 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
Paul Mundte7bd34a2007-07-31 17:07:28 +0900222 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
223
224config CACHE_WRITEBACK
225 bool "Write-back"
Paul Mundta09063d2007-11-08 18:54:16 +0900226 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
Paul Mundte7bd34a2007-07-31 17:07:28 +0900227
228config CACHE_WRITETHROUGH
229 bool "Write-through"
Paul Mundtcad82442006-01-16 22:14:19 -0800230 help
231 Selecting this option will configure the caches in write-through
232 mode, as opposed to the default write-back configuration.
233
234 Since there's sill some aliasing issues on SH-4, this option will
235 unfortunately still require the majority of flushing functions to
236 be implemented to deal with aliasing.
237
238 If unsure, say N.
239
Paul Mundte7bd34a2007-07-31 17:07:28 +0900240config CACHE_OFF
241 bool "Off"
242
243endchoice
244
Paul Mundtcad82442006-01-16 22:14:19 -0800245endmenu