blob: 77b3a6b62b38c712cd40015bf212d59875b9d8cf [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
29#include <mach/msm_xo.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070030#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "clock-local.h"
33#include "clock-rpm.h"
34#include "clock-voter.h"
35#include "clock-dss-8960.h"
36#include "devices.h"
37
38#define REG(off) (MSM_CLK_CTL_BASE + (off))
39#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
40#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070041#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070042
43/* Peripheral clock registers. */
44#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
46#define DMA_BAM_HCLK_CTL REG(0x25C0)
47#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
48#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
49#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
50#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
51#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
52#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070053#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054#define CLK_TEST_REG REG(0x2FA0)
55#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
56#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
57#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
58#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
59#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
60#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070061#define PDM_CLK_NS_REG REG(0x2CC0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070062#define BB_PLL_ENA_SC0_REG REG(0x34C0)
63#define BB_PLL0_STATUS_REG REG(0x30D8)
64#define BB_PLL5_STATUS_REG REG(0x30F8)
65#define BB_PLL6_STATUS_REG REG(0x3118)
66#define BB_PLL7_STATUS_REG REG(0x3138)
67#define BB_PLL8_L_VAL_REG REG(0x3144)
68#define BB_PLL8_M_VAL_REG REG(0x3148)
69#define BB_PLL8_MODE_REG REG(0x3140)
70#define BB_PLL8_N_VAL_REG REG(0x314C)
71#define BB_PLL8_STATUS_REG REG(0x3158)
72#define BB_PLL8_CONFIG_REG REG(0x3154)
73#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070074#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
75#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
76#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070077#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
78#define PMEM_ACLK_CTL_REG REG(0x25A0)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070079#define QDSS_AT_CLK_SRC0_NS_REG REG(0x2180)
80#define QDSS_AT_CLK_SRC1_NS_REG REG(0x2184)
81#define QDSS_AT_CLK_SRC_CTL_REG REG(0x2188)
82#define QDSS_AT_CLK_NS_REG REG(0x218C)
83#define QDSS_HCLK_CTL_REG REG(0x22A0)
84#define QDSS_RESETS_REG REG(0x2260)
85#define QDSS_STM_CLK_CTL_REG REG(0x2060)
86#define QDSS_TRACECLKIN_CLK_SRC0_NS_REG REG(0x21A0)
87#define QDSS_TRACECLKIN_CLK_SRC1_NS_REG REG(0x21A4)
88#define QDSS_TRACECLKIN_CLK_SRC_CTL_REG REG(0x21A8)
89#define QDSS_TRACECLKIN_CTL_REG REG(0x21AC)
90#define QDSS_TSCTR_CLK_SRC0_NS_REG REG(0x21C0)
91#define QDSS_TSCTR_CLK_SRC1_NS_REG REG(0x21C4)
92#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
93#define QDSS_TSCTR_CLK_SRC_CTL_REG REG(0x21C8)
94#define QDSS_TSCTR_CTL_REG REG(0x21CC)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070095#define RINGOSC_NS_REG REG(0x2DC0)
96#define RINGOSC_STATUS_REG REG(0x2DCC)
97#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
98#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
99#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
100#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
101#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
102#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
103#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
104#define TSIF_HCLK_CTL_REG REG(0x2700)
105#define TSIF_REF_CLK_MD_REG REG(0x270C)
106#define TSIF_REF_CLK_NS_REG REG(0x2710)
107#define TSSC_CLK_CTL_REG REG(0x2CA0)
108#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
109#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
110#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
111#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
112#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
113#define USB_HS1_HCLK_CTL_REG REG(0x2900)
114#define USB_HS1_RESET_REG REG(0x2910)
115#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
116#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700117#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
118#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
119#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
120#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
121#define USB_HSIC_RESET_REG REG(0x2934)
122#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
123#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
124#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700125#define USB_PHY0_RESET_REG REG(0x2E20)
126
127/* Multimedia clock registers. */
128#define AHB_EN_REG REG_MM(0x0008)
129#define AHB_EN2_REG REG_MM(0x0038)
130#define AHB_NS_REG REG_MM(0x0004)
131#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700132#define CAMCLK0_NS_REG REG_MM(0x0148)
133#define CAMCLK0_CC_REG REG_MM(0x0140)
134#define CAMCLK0_MD_REG REG_MM(0x0144)
135#define CAMCLK1_NS_REG REG_MM(0x015C)
136#define CAMCLK1_CC_REG REG_MM(0x0154)
137#define CAMCLK1_MD_REG REG_MM(0x0158)
138#define CAMCLK2_NS_REG REG_MM(0x0228)
139#define CAMCLK2_CC_REG REG_MM(0x0220)
140#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141#define CSI0_NS_REG REG_MM(0x0048)
142#define CSI0_CC_REG REG_MM(0x0040)
143#define CSI0_MD_REG REG_MM(0x0044)
144#define CSI1_NS_REG REG_MM(0x0010)
145#define CSI1_CC_REG REG_MM(0x0024)
146#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700147#define CSI2_NS_REG REG_MM(0x0234)
148#define CSI2_CC_REG REG_MM(0x022C)
149#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700150#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
151#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
152#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
153#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
154#define DSI1_BYTE_CC_REG REG_MM(0x0090)
155#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
156#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
157#define DSI1_ESC_NS_REG REG_MM(0x011C)
158#define DSI1_ESC_CC_REG REG_MM(0x00CC)
159#define DSI2_ESC_NS_REG REG_MM(0x0150)
160#define DSI2_ESC_CC_REG REG_MM(0x013C)
161#define DSI_PIXEL_CC_REG REG_MM(0x0130)
162#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
163#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
164#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
165#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
166#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
167#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
168#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
169#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
170#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
171#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
172#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
173#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
174#define GFX2D0_CC_REG REG_MM(0x0060)
175#define GFX2D0_MD0_REG REG_MM(0x0064)
176#define GFX2D0_MD1_REG REG_MM(0x0068)
177#define GFX2D0_NS_REG REG_MM(0x0070)
178#define GFX2D1_CC_REG REG_MM(0x0074)
179#define GFX2D1_MD0_REG REG_MM(0x0078)
180#define GFX2D1_MD1_REG REG_MM(0x006C)
181#define GFX2D1_NS_REG REG_MM(0x007C)
182#define GFX3D_CC_REG REG_MM(0x0080)
183#define GFX3D_MD0_REG REG_MM(0x0084)
184#define GFX3D_MD1_REG REG_MM(0x0088)
185#define GFX3D_NS_REG REG_MM(0x008C)
186#define IJPEG_CC_REG REG_MM(0x0098)
187#define IJPEG_MD_REG REG_MM(0x009C)
188#define IJPEG_NS_REG REG_MM(0x00A0)
189#define JPEGD_CC_REG REG_MM(0x00A4)
190#define JPEGD_NS_REG REG_MM(0x00AC)
191#define MAXI_EN_REG REG_MM(0x0018)
192#define MAXI_EN2_REG REG_MM(0x0020)
193#define MAXI_EN3_REG REG_MM(0x002C)
194#define MAXI_EN4_REG REG_MM(0x0114)
195#define MDP_CC_REG REG_MM(0x00C0)
196#define MDP_LUT_CC_REG REG_MM(0x016C)
197#define MDP_MD0_REG REG_MM(0x00C4)
198#define MDP_MD1_REG REG_MM(0x00C8)
199#define MDP_NS_REG REG_MM(0x00D0)
200#define MISC_CC_REG REG_MM(0x0058)
201#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700202#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700203#define MM_PLL1_MODE_REG REG_MM(0x031C)
204#define ROT_CC_REG REG_MM(0x00E0)
205#define ROT_NS_REG REG_MM(0x00E8)
206#define SAXI_EN_REG REG_MM(0x0030)
207#define SW_RESET_AHB_REG REG_MM(0x020C)
208#define SW_RESET_AHB2_REG REG_MM(0x0200)
209#define SW_RESET_ALL_REG REG_MM(0x0204)
210#define SW_RESET_AXI_REG REG_MM(0x0208)
211#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700212#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700213#define TV_CC_REG REG_MM(0x00EC)
214#define TV_CC2_REG REG_MM(0x0124)
215#define TV_MD_REG REG_MM(0x00F0)
216#define TV_NS_REG REG_MM(0x00F4)
217#define VCODEC_CC_REG REG_MM(0x00F8)
218#define VCODEC_MD0_REG REG_MM(0x00FC)
219#define VCODEC_MD1_REG REG_MM(0x0128)
220#define VCODEC_NS_REG REG_MM(0x0100)
221#define VFE_CC_REG REG_MM(0x0104)
222#define VFE_MD_REG REG_MM(0x0108)
223#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700224#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700225#define VPE_CC_REG REG_MM(0x0110)
226#define VPE_NS_REG REG_MM(0x0118)
227
228/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700229#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700230#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
231#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
232#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
233#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
234#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
235#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
236#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
237#define LCC_MI2S_MD_REG REG_LPA(0x004C)
238#define LCC_MI2S_NS_REG REG_LPA(0x0048)
239#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
240#define LCC_PCM_MD_REG REG_LPA(0x0058)
241#define LCC_PCM_NS_REG REG_LPA(0x0054)
242#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
243#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700244#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
245#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
246#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
247#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
248#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
249#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
250#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
251#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
252#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
253#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
254
Matt Wagantall8b38f942011-08-02 18:23:18 -0700255#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
256
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700257/* MUX source input identifiers. */
258#define pxo_to_bb_mux 0
259#define cxo_to_bb_mux pxo_to_bb_mux
260#define pll0_to_bb_mux 2
261#define pll8_to_bb_mux 3
262#define pll6_to_bb_mux 4
263#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700264#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700265#define pxo_to_mm_mux 0
266#define pll1_to_mm_mux 1
267#define pll2_to_mm_mux 1
268#define pll8_to_mm_mux 2
269#define pll0_to_mm_mux 3
270#define gnd_to_mm_mux 4
Stephen Boyd94625ef2011-07-12 17:06:01 -0700271#define pll3_to_mm_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700272#define hdmi_pll_to_mm_mux 3
273#define cxo_to_xo_mux 0
274#define pxo_to_xo_mux 1
275#define gnd_to_xo_mux 3
276#define pxo_to_lpa_mux 0
277#define cxo_to_lpa_mux 1
278#define pll4_to_lpa_mux 2
279#define gnd_to_lpa_mux 6
280
281/* Test Vector Macros */
282#define TEST_TYPE_PER_LS 1
283#define TEST_TYPE_PER_HS 2
284#define TEST_TYPE_MM_LS 3
285#define TEST_TYPE_MM_HS 4
286#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700287#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700288#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700289#define TEST_TYPE_SHIFT 24
290#define TEST_CLK_SEL_MASK BM(23, 0)
291#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
292#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
293#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
294#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
295#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
296#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700297#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700298#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700299
300#define MN_MODE_DUAL_EDGE 0x2
301
302/* MD Registers */
303#define MD4(m_lsb, m, n_lsb, n) \
304 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
305#define MD8(m_lsb, m, n_lsb, n) \
306 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
307#define MD16(m, n) (BVAL(31, 16, m) | BVAL(15, 0, ~(n)))
308
309/* NS Registers */
310#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
311 (BVAL(n_msb, n_lsb, ~(n-m)) \
312 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
313 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
314
315#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
316 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
317 | BVAL(s_msb, s_lsb, s))
318
319#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
320 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
321
322#define NS_DIV(d_msb , d_lsb, d) \
323 BVAL(d_msb, d_lsb, (d-1))
324
325#define NS_SRC_SEL(s_msb, s_lsb, s) \
326 BVAL(s_msb, s_lsb, s)
327
328#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
329 (BVAL((n0_lsb+3), n0_lsb, ~(n-m)) \
330 | BVAL((n1_lsb+3), n1_lsb, ~(n-m)) \
331 | BVAL((s0_lsb+2), s0_lsb, s) \
332 | BVAL((s1_lsb+2), s1_lsb, s))
333
334#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
335 (BVAL((n0_lsb+7), n0_lsb, ~(n-m)) \
336 | BVAL((n1_lsb+7), n1_lsb, ~(n-m)) \
337 | BVAL((s0_lsb+2), s0_lsb, s) \
338 | BVAL((s1_lsb+2), s1_lsb, s))
339
340#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
341 s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
342 (BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
343 | BVAL(s0_msb, s0_lsb, s) \
344 | BVAL(s1_msb, s1_lsb, s))
345
346/* CC Registers */
347#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
348#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
349 ((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
350 | BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
351 * !!(n))
352
353struct pll_rate {
354 const uint32_t l_val;
355 const uint32_t m_val;
356 const uint32_t n_val;
357 const uint32_t vco;
358 const uint32_t post_div;
359 const uint32_t i_bits;
360};
361#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
362
363/*
364 * Clock Descriptions
365 */
366
367static struct msm_xo_voter *xo_pxo, *xo_cxo;
368
369static int pxo_clk_enable(struct clk *clk)
370{
371 return msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_ON);
372}
373
374static void pxo_clk_disable(struct clk *clk)
375{
376 msm_xo_mode_vote(xo_pxo, MSM_XO_MODE_OFF);
377}
378
379static struct clk_ops clk_ops_pxo = {
380 .enable = pxo_clk_enable,
381 .disable = pxo_clk_disable,
382 .get_rate = fixed_clk_get_rate,
383 .is_local = local_clk_is_local,
384};
385
386static struct fixed_clk pxo_clk = {
387 .rate = 27000000,
388 .c = {
389 .dbg_name = "pxo_clk",
390 .ops = &clk_ops_pxo,
391 CLK_INIT(pxo_clk.c),
392 },
393};
394
395static int cxo_clk_enable(struct clk *clk)
396{
397 return msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_ON);
398}
399
400static void cxo_clk_disable(struct clk *clk)
401{
402 msm_xo_mode_vote(xo_cxo, MSM_XO_MODE_OFF);
403}
404
405static struct clk_ops clk_ops_cxo = {
406 .enable = cxo_clk_enable,
407 .disable = cxo_clk_disable,
408 .get_rate = fixed_clk_get_rate,
409 .is_local = local_clk_is_local,
410};
411
412static struct fixed_clk cxo_clk = {
413 .rate = 19200000,
414 .c = {
415 .dbg_name = "cxo_clk",
416 .ops = &clk_ops_cxo,
417 CLK_INIT(cxo_clk.c),
418 },
419};
420
421static struct pll_clk pll2_clk = {
422 .rate = 800000000,
423 .mode_reg = MM_PLL1_MODE_REG,
424 .parent = &pxo_clk.c,
425 .c = {
426 .dbg_name = "pll2_clk",
427 .ops = &clk_ops_pll,
428 CLK_INIT(pll2_clk.c),
429 },
430};
431
Stephen Boyd94625ef2011-07-12 17:06:01 -0700432static struct pll_clk pll3_clk = {
433 .rate = 1200000000,
434 .mode_reg = BB_MMCC_PLL2_MODE_REG,
435 .parent = &pxo_clk.c,
436 .c = {
437 .dbg_name = "pll3_clk",
438 .ops = &clk_ops_pll,
439 CLK_INIT(pll3_clk.c),
440 },
441};
442
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700443static struct pll_vote_clk pll4_clk = {
444 .rate = 393216000,
445 .en_reg = BB_PLL_ENA_SC0_REG,
446 .en_mask = BIT(4),
447 .status_reg = LCC_PLL0_STATUS_REG,
448 .parent = &pxo_clk.c,
449 .c = {
450 .dbg_name = "pll4_clk",
451 .ops = &clk_ops_pll_vote,
452 CLK_INIT(pll4_clk.c),
453 },
454};
455
456static struct pll_vote_clk pll8_clk = {
457 .rate = 384000000,
458 .en_reg = BB_PLL_ENA_SC0_REG,
459 .en_mask = BIT(8),
460 .status_reg = BB_PLL8_STATUS_REG,
461 .parent = &pxo_clk.c,
462 .c = {
463 .dbg_name = "pll8_clk",
464 .ops = &clk_ops_pll_vote,
465 CLK_INIT(pll8_clk.c),
466 },
467};
468
Stephen Boyd94625ef2011-07-12 17:06:01 -0700469static struct pll_vote_clk pll14_clk = {
470 .rate = 480000000,
471 .en_reg = BB_PLL_ENA_SC0_REG,
472 .en_mask = BIT(14),
473 .status_reg = BB_PLL14_STATUS_REG,
474 .parent = &pxo_clk.c,
475 .c = {
476 .dbg_name = "pll14_clk",
477 .ops = &clk_ops_pll_vote,
478 CLK_INIT(pll14_clk.c),
479 },
480};
481
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700482/*
483 * SoC-specific functions required by clock-local driver
484 */
485
486/* Update the sys_vdd voltage given a level. */
487static int msm8960_update_sys_vdd(enum sys_vdd_level level)
488{
489 static const int vdd_uv[] = {
490 [NONE...LOW] = 945000,
491 [NOMINAL] = 1050000,
492 [HIGH] = 1150000,
493 };
494
495 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
496 vdd_uv[level], vdd_uv[HIGH], 1);
497}
498
499static int soc_clk_reset(struct clk *clk, enum clk_reset_action action)
500{
501 return branch_reset(&to_rcg_clk(clk)->b, action);
502}
503
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700504static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700505 .enable = rcg_clk_enable,
506 .disable = rcg_clk_disable,
507 .auto_off = rcg_clk_auto_off,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700508 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700509 .set_rate = rcg_clk_set_rate,
510 .set_min_rate = rcg_clk_set_min_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700511 .get_rate = rcg_clk_get_rate,
512 .list_rate = rcg_clk_list_rate,
513 .is_enabled = rcg_clk_is_enabled,
514 .round_rate = rcg_clk_round_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700515 .reset = soc_clk_reset,
516 .is_local = local_clk_is_local,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700517 .get_parent = rcg_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700518};
519
520static struct clk_ops clk_ops_branch = {
521 .enable = branch_clk_enable,
522 .disable = branch_clk_disable,
523 .auto_off = branch_clk_auto_off,
524 .is_enabled = branch_clk_is_enabled,
525 .reset = branch_clk_reset,
526 .is_local = local_clk_is_local,
527 .get_parent = branch_clk_get_parent,
528 .set_parent = branch_clk_set_parent,
529};
530
531static struct clk_ops clk_ops_reset = {
532 .reset = branch_clk_reset,
533 .is_local = local_clk_is_local,
534};
535
536/* AXI Interfaces */
537static struct branch_clk gmem_axi_clk = {
538 .b = {
539 .ctl_reg = MAXI_EN_REG,
540 .en_mask = BIT(24),
541 .halt_reg = DBG_BUS_VEC_E_REG,
542 .halt_bit = 6,
543 },
544 .c = {
545 .dbg_name = "gmem_axi_clk",
546 .ops = &clk_ops_branch,
547 CLK_INIT(gmem_axi_clk.c),
548 },
549};
550
551static struct branch_clk ijpeg_axi_clk = {
552 .b = {
553 .ctl_reg = MAXI_EN_REG,
554 .en_mask = BIT(21),
555 .reset_reg = SW_RESET_AXI_REG,
556 .reset_mask = BIT(14),
557 .halt_reg = DBG_BUS_VEC_E_REG,
558 .halt_bit = 4,
559 },
560 .c = {
561 .dbg_name = "ijpeg_axi_clk",
562 .ops = &clk_ops_branch,
563 CLK_INIT(ijpeg_axi_clk.c),
564 },
565};
566
567static struct branch_clk imem_axi_clk = {
568 .b = {
569 .ctl_reg = MAXI_EN_REG,
570 .en_mask = BIT(22),
571 .reset_reg = SW_RESET_CORE_REG,
572 .reset_mask = BIT(10),
573 .halt_reg = DBG_BUS_VEC_E_REG,
574 .halt_bit = 7,
575 },
576 .c = {
577 .dbg_name = "imem_axi_clk",
578 .ops = &clk_ops_branch,
579 CLK_INIT(imem_axi_clk.c),
580 },
581};
582
583static struct branch_clk jpegd_axi_clk = {
584 .b = {
585 .ctl_reg = MAXI_EN_REG,
586 .en_mask = BIT(25),
587 .halt_reg = DBG_BUS_VEC_E_REG,
588 .halt_bit = 5,
589 },
590 .c = {
591 .dbg_name = "jpegd_axi_clk",
592 .ops = &clk_ops_branch,
593 CLK_INIT(jpegd_axi_clk.c),
594 },
595};
596
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700597static struct branch_clk vcodec_axi_b_clk = {
598 .b = {
599 .ctl_reg = MAXI_EN4_REG,
600 .en_mask = BIT(23),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700601 .halt_reg = DBG_BUS_VEC_I_REG,
602 .halt_bit = 25,
603 },
604 .c = {
605 .dbg_name = "vcodec_axi_b_clk",
606 .ops = &clk_ops_branch,
607 CLK_INIT(vcodec_axi_b_clk.c),
608 },
609};
610
Matt Wagantall91f42702011-07-14 12:01:15 -0700611static struct branch_clk vcodec_axi_a_clk = {
612 .b = {
613 .ctl_reg = MAXI_EN4_REG,
614 .en_mask = BIT(25),
Matt Wagantall91f42702011-07-14 12:01:15 -0700615 .halt_reg = DBG_BUS_VEC_I_REG,
616 .halt_bit = 26,
617 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700618 .c = {
619 .dbg_name = "vcodec_axi_a_clk",
620 .ops = &clk_ops_branch,
621 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700622 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700623 },
624};
625
626static struct branch_clk vcodec_axi_clk = {
627 .b = {
628 .ctl_reg = MAXI_EN_REG,
629 .en_mask = BIT(19),
630 .reset_reg = SW_RESET_AXI_REG,
Matt Wagantallfe2ee052011-07-14 13:33:44 -0700631 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700632 .halt_reg = DBG_BUS_VEC_E_REG,
633 .halt_bit = 3,
634 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700635 .c = {
636 .dbg_name = "vcodec_axi_clk",
637 .ops = &clk_ops_branch,
638 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700639 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700640 },
641};
642
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700643static struct branch_clk vfe_axi_clk = {
644 .b = {
645 .ctl_reg = MAXI_EN_REG,
646 .en_mask = BIT(18),
647 .reset_reg = SW_RESET_AXI_REG,
648 .reset_mask = BIT(9),
649 .halt_reg = DBG_BUS_VEC_E_REG,
650 .halt_bit = 0,
651 },
652 .c = {
653 .dbg_name = "vfe_axi_clk",
654 .ops = &clk_ops_branch,
655 CLK_INIT(vfe_axi_clk.c),
656 },
657};
658
659static struct branch_clk mdp_axi_clk = {
660 .b = {
661 .ctl_reg = MAXI_EN_REG,
662 .en_mask = BIT(23),
663 .reset_reg = SW_RESET_AXI_REG,
664 .reset_mask = BIT(13),
665 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700666 .halt_bit = 8,
667 },
668 .c = {
669 .dbg_name = "mdp_axi_clk",
670 .ops = &clk_ops_branch,
671 CLK_INIT(mdp_axi_clk.c),
672 },
673};
674
675static struct branch_clk rot_axi_clk = {
676 .b = {
677 .ctl_reg = MAXI_EN2_REG,
678 .en_mask = BIT(24),
679 .reset_reg = SW_RESET_AXI_REG,
680 .reset_mask = BIT(6),
681 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700682 .halt_bit = 2,
683 },
684 .c = {
685 .dbg_name = "rot_axi_clk",
686 .ops = &clk_ops_branch,
687 CLK_INIT(rot_axi_clk.c),
688 },
689};
690
691static struct branch_clk vpe_axi_clk = {
692 .b = {
693 .ctl_reg = MAXI_EN2_REG,
694 .en_mask = BIT(26),
695 .reset_reg = SW_RESET_AXI_REG,
696 .reset_mask = BIT(15),
697 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700698 .halt_bit = 1,
699 },
700 .c = {
701 .dbg_name = "vpe_axi_clk",
702 .ops = &clk_ops_branch,
703 CLK_INIT(vpe_axi_clk.c),
704 },
705};
706
707/* AHB Interfaces */
708static struct branch_clk amp_p_clk = {
709 .b = {
710 .ctl_reg = AHB_EN_REG,
711 .en_mask = BIT(24),
712 .halt_reg = DBG_BUS_VEC_F_REG,
713 .halt_bit = 18,
714 },
715 .c = {
716 .dbg_name = "amp_p_clk",
717 .ops = &clk_ops_branch,
718 CLK_INIT(amp_p_clk.c),
719 },
720};
721
Matt Wagantallc23eee92011-08-16 23:06:52 -0700722static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700723 .b = {
724 .ctl_reg = AHB_EN_REG,
725 .en_mask = BIT(7),
726 .reset_reg = SW_RESET_AHB_REG,
727 .reset_mask = BIT(17),
728 .halt_reg = DBG_BUS_VEC_F_REG,
729 .halt_bit = 16,
730 },
731 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700732 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700733 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700734 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700735 },
736};
737
738static struct branch_clk dsi1_m_p_clk = {
739 .b = {
740 .ctl_reg = AHB_EN_REG,
741 .en_mask = BIT(9),
742 .reset_reg = SW_RESET_AHB_REG,
743 .reset_mask = BIT(6),
744 .halt_reg = DBG_BUS_VEC_F_REG,
745 .halt_bit = 19,
746 },
747 .c = {
748 .dbg_name = "dsi1_m_p_clk",
749 .ops = &clk_ops_branch,
750 CLK_INIT(dsi1_m_p_clk.c),
751 },
752};
753
754static struct branch_clk dsi1_s_p_clk = {
755 .b = {
756 .ctl_reg = AHB_EN_REG,
757 .en_mask = BIT(18),
758 .reset_reg = SW_RESET_AHB_REG,
759 .reset_mask = BIT(5),
760 .halt_reg = DBG_BUS_VEC_F_REG,
761 .halt_bit = 21,
762 },
763 .c = {
764 .dbg_name = "dsi1_s_p_clk",
765 .ops = &clk_ops_branch,
766 CLK_INIT(dsi1_s_p_clk.c),
767 },
768};
769
770static struct branch_clk dsi2_m_p_clk = {
771 .b = {
772 .ctl_reg = AHB_EN_REG,
773 .en_mask = BIT(17),
774 .reset_reg = SW_RESET_AHB2_REG,
775 .reset_mask = BIT(1),
776 .halt_reg = DBG_BUS_VEC_E_REG,
777 .halt_bit = 18,
778 },
779 .c = {
780 .dbg_name = "dsi2_m_p_clk",
781 .ops = &clk_ops_branch,
782 CLK_INIT(dsi2_m_p_clk.c),
783 },
784};
785
786static struct branch_clk dsi2_s_p_clk = {
787 .b = {
788 .ctl_reg = AHB_EN_REG,
789 .en_mask = BIT(22),
790 .reset_reg = SW_RESET_AHB2_REG,
791 .reset_mask = BIT(0),
792 .halt_reg = DBG_BUS_VEC_F_REG,
793 .halt_bit = 20,
794 },
795 .c = {
796 .dbg_name = "dsi2_s_p_clk",
797 .ops = &clk_ops_branch,
798 CLK_INIT(dsi2_s_p_clk.c),
799 },
800};
801
802static struct branch_clk gfx2d0_p_clk = {
803 .b = {
804 .ctl_reg = AHB_EN_REG,
805 .en_mask = BIT(19),
806 .reset_reg = SW_RESET_AHB_REG,
807 .reset_mask = BIT(12),
808 .halt_reg = DBG_BUS_VEC_F_REG,
809 .halt_bit = 2,
810 },
811 .c = {
812 .dbg_name = "gfx2d0_p_clk",
813 .ops = &clk_ops_branch,
814 CLK_INIT(gfx2d0_p_clk.c),
815 },
816};
817
818static struct branch_clk gfx2d1_p_clk = {
819 .b = {
820 .ctl_reg = AHB_EN_REG,
821 .en_mask = BIT(2),
822 .reset_reg = SW_RESET_AHB_REG,
823 .reset_mask = BIT(11),
824 .halt_reg = DBG_BUS_VEC_F_REG,
825 .halt_bit = 3,
826 },
827 .c = {
828 .dbg_name = "gfx2d1_p_clk",
829 .ops = &clk_ops_branch,
830 CLK_INIT(gfx2d1_p_clk.c),
831 },
832};
833
834static struct branch_clk gfx3d_p_clk = {
835 .b = {
836 .ctl_reg = AHB_EN_REG,
837 .en_mask = BIT(3),
838 .reset_reg = SW_RESET_AHB_REG,
839 .reset_mask = BIT(10),
840 .halt_reg = DBG_BUS_VEC_F_REG,
841 .halt_bit = 4,
842 },
843 .c = {
844 .dbg_name = "gfx3d_p_clk",
845 .ops = &clk_ops_branch,
846 CLK_INIT(gfx3d_p_clk.c),
847 },
848};
849
850static struct branch_clk hdmi_m_p_clk = {
851 .b = {
852 .ctl_reg = AHB_EN_REG,
853 .en_mask = BIT(14),
854 .reset_reg = SW_RESET_AHB_REG,
855 .reset_mask = BIT(9),
856 .halt_reg = DBG_BUS_VEC_F_REG,
857 .halt_bit = 5,
858 },
859 .c = {
860 .dbg_name = "hdmi_m_p_clk",
861 .ops = &clk_ops_branch,
862 CLK_INIT(hdmi_m_p_clk.c),
863 },
864};
865
866static struct branch_clk hdmi_s_p_clk = {
867 .b = {
868 .ctl_reg = AHB_EN_REG,
869 .en_mask = BIT(4),
870 .reset_reg = SW_RESET_AHB_REG,
871 .reset_mask = BIT(9),
872 .halt_reg = DBG_BUS_VEC_F_REG,
873 .halt_bit = 6,
874 },
875 .c = {
876 .dbg_name = "hdmi_s_p_clk",
877 .ops = &clk_ops_branch,
878 CLK_INIT(hdmi_s_p_clk.c),
879 },
880};
881
882static struct branch_clk ijpeg_p_clk = {
883 .b = {
884 .ctl_reg = AHB_EN_REG,
885 .en_mask = BIT(5),
886 .reset_reg = SW_RESET_AHB_REG,
887 .reset_mask = BIT(7),
888 .halt_reg = DBG_BUS_VEC_F_REG,
889 .halt_bit = 9,
890 },
891 .c = {
892 .dbg_name = "ijpeg_p_clk",
893 .ops = &clk_ops_branch,
894 CLK_INIT(ijpeg_p_clk.c),
895 },
896};
897
898static struct branch_clk imem_p_clk = {
899 .b = {
900 .ctl_reg = AHB_EN_REG,
901 .en_mask = BIT(6),
902 .reset_reg = SW_RESET_AHB_REG,
903 .reset_mask = BIT(8),
904 .halt_reg = DBG_BUS_VEC_F_REG,
905 .halt_bit = 10,
906 },
907 .c = {
908 .dbg_name = "imem_p_clk",
909 .ops = &clk_ops_branch,
910 CLK_INIT(imem_p_clk.c),
911 },
912};
913
914static struct branch_clk jpegd_p_clk = {
915 .b = {
916 .ctl_reg = AHB_EN_REG,
917 .en_mask = BIT(21),
918 .reset_reg = SW_RESET_AHB_REG,
919 .reset_mask = BIT(4),
920 .halt_reg = DBG_BUS_VEC_F_REG,
921 .halt_bit = 7,
922 },
923 .c = {
924 .dbg_name = "jpegd_p_clk",
925 .ops = &clk_ops_branch,
926 CLK_INIT(jpegd_p_clk.c),
927 },
928};
929
930static struct branch_clk mdp_p_clk = {
931 .b = {
932 .ctl_reg = AHB_EN_REG,
933 .en_mask = BIT(10),
934 .reset_reg = SW_RESET_AHB_REG,
935 .reset_mask = BIT(3),
936 .halt_reg = DBG_BUS_VEC_F_REG,
937 .halt_bit = 11,
938 },
939 .c = {
940 .dbg_name = "mdp_p_clk",
941 .ops = &clk_ops_branch,
942 CLK_INIT(mdp_p_clk.c),
943 },
944};
945
946static struct branch_clk rot_p_clk = {
947 .b = {
948 .ctl_reg = AHB_EN_REG,
949 .en_mask = BIT(12),
950 .reset_reg = SW_RESET_AHB_REG,
951 .reset_mask = BIT(2),
952 .halt_reg = DBG_BUS_VEC_F_REG,
953 .halt_bit = 13,
954 },
955 .c = {
956 .dbg_name = "rot_p_clk",
957 .ops = &clk_ops_branch,
958 CLK_INIT(rot_p_clk.c),
959 },
960};
961
962static struct branch_clk smmu_p_clk = {
963 .b = {
964 .ctl_reg = AHB_EN_REG,
965 .en_mask = BIT(15),
966 .halt_reg = DBG_BUS_VEC_F_REG,
967 .halt_bit = 22,
968 },
969 .c = {
970 .dbg_name = "smmu_p_clk",
971 .ops = &clk_ops_branch,
972 CLK_INIT(smmu_p_clk.c),
973 },
974};
975
976static struct branch_clk tv_enc_p_clk = {
977 .b = {
978 .ctl_reg = AHB_EN_REG,
979 .en_mask = BIT(25),
980 .reset_reg = SW_RESET_AHB_REG,
981 .reset_mask = BIT(15),
982 .halt_reg = DBG_BUS_VEC_F_REG,
983 .halt_bit = 23,
984 },
985 .c = {
986 .dbg_name = "tv_enc_p_clk",
987 .ops = &clk_ops_branch,
988 CLK_INIT(tv_enc_p_clk.c),
989 },
990};
991
992static struct branch_clk vcodec_p_clk = {
993 .b = {
994 .ctl_reg = AHB_EN_REG,
995 .en_mask = BIT(11),
996 .reset_reg = SW_RESET_AHB_REG,
997 .reset_mask = BIT(1),
998 .halt_reg = DBG_BUS_VEC_F_REG,
999 .halt_bit = 12,
1000 },
1001 .c = {
1002 .dbg_name = "vcodec_p_clk",
1003 .ops = &clk_ops_branch,
1004 CLK_INIT(vcodec_p_clk.c),
1005 },
1006};
1007
1008static struct branch_clk vfe_p_clk = {
1009 .b = {
1010 .ctl_reg = AHB_EN_REG,
1011 .en_mask = BIT(13),
1012 .reset_reg = SW_RESET_AHB_REG,
1013 .reset_mask = BIT(0),
1014 .halt_reg = DBG_BUS_VEC_F_REG,
1015 .halt_bit = 14,
1016 },
1017 .c = {
1018 .dbg_name = "vfe_p_clk",
1019 .ops = &clk_ops_branch,
1020 CLK_INIT(vfe_p_clk.c),
1021 },
1022};
1023
1024static struct branch_clk vpe_p_clk = {
1025 .b = {
1026 .ctl_reg = AHB_EN_REG,
1027 .en_mask = BIT(16),
1028 .reset_reg = SW_RESET_AHB_REG,
1029 .reset_mask = BIT(14),
1030 .halt_reg = DBG_BUS_VEC_F_REG,
1031 .halt_bit = 15,
1032 },
1033 .c = {
1034 .dbg_name = "vpe_p_clk",
1035 .ops = &clk_ops_branch,
1036 CLK_INIT(vpe_p_clk.c),
1037 },
1038};
1039
1040/*
1041 * Peripheral Clocks
1042 */
1043#define CLK_GSBI_UART(i, n, h_r, h_b) \
1044 struct rcg_clk i##_clk = { \
1045 .b = { \
1046 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1047 .en_mask = BIT(9), \
1048 .reset_reg = GSBIn_RESET_REG(n), \
1049 .reset_mask = BIT(0), \
1050 .halt_reg = h_r, \
1051 .halt_bit = h_b, \
1052 }, \
1053 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1054 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1055 .root_en_mask = BIT(11), \
1056 .ns_mask = (BM(31, 16) | BM(6, 0)), \
1057 .set_rate = set_rate_mnd, \
1058 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001059 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001060 .c = { \
1061 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001062 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001063 CLK_INIT(i##_clk.c), \
1064 }, \
1065 }
1066#define F_GSBI_UART(f, s, d, m, n, v) \
1067 { \
1068 .freq_hz = f, \
1069 .src_clk = &s##_clk.c, \
1070 .md_val = MD16(m, n), \
1071 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1072 .mnd_en_mask = BIT(8) * !!(n), \
1073 .sys_vdd = v, \
1074 }
1075static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
1076 F_GSBI_UART( 0, gnd, 1, 0, 0, NONE),
1077 F_GSBI_UART( 1843200, pll8, 1, 3, 625, LOW),
1078 F_GSBI_UART( 3686400, pll8, 1, 6, 625, LOW),
1079 F_GSBI_UART( 7372800, pll8, 1, 12, 625, LOW),
1080 F_GSBI_UART(14745600, pll8, 1, 24, 625, LOW),
1081 F_GSBI_UART(16000000, pll8, 4, 1, 6, LOW),
1082 F_GSBI_UART(24000000, pll8, 4, 1, 4, LOW),
1083 F_GSBI_UART(32000000, pll8, 4, 1, 3, LOW),
1084 F_GSBI_UART(40000000, pll8, 1, 5, 48, NOMINAL),
1085 F_GSBI_UART(46400000, pll8, 1, 29, 240, NOMINAL),
1086 F_GSBI_UART(48000000, pll8, 4, 1, 2, NOMINAL),
1087 F_GSBI_UART(51200000, pll8, 1, 2, 15, NOMINAL),
1088 F_GSBI_UART(56000000, pll8, 1, 7, 48, NOMINAL),
1089 F_GSBI_UART(58982400, pll8, 1, 96, 625, NOMINAL),
1090 F_GSBI_UART(64000000, pll8, 2, 1, 3, NOMINAL),
1091 F_END
1092};
1093
1094static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1095static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1096static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1097static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1098static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1099static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1100static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1101static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1102static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1103static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1104static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1105static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1106
1107#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1108 struct rcg_clk i##_clk = { \
1109 .b = { \
1110 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1111 .en_mask = BIT(9), \
1112 .reset_reg = GSBIn_RESET_REG(n), \
1113 .reset_mask = BIT(0), \
1114 .halt_reg = h_r, \
1115 .halt_bit = h_b, \
1116 }, \
1117 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1118 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1119 .root_en_mask = BIT(11), \
1120 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1121 .set_rate = set_rate_mnd, \
1122 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001123 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001124 .c = { \
1125 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001126 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001127 CLK_INIT(i##_clk.c), \
1128 }, \
1129 }
1130#define F_GSBI_QUP(f, s, d, m, n, v) \
1131 { \
1132 .freq_hz = f, \
1133 .src_clk = &s##_clk.c, \
1134 .md_val = MD8(16, m, 0, n), \
1135 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1136 .mnd_en_mask = BIT(8) * !!(n), \
1137 .sys_vdd = v, \
1138 }
1139static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
1140 F_GSBI_QUP( 0, gnd, 1, 0, 0, NONE),
1141 F_GSBI_QUP( 1100000, pxo, 1, 2, 49, LOW),
1142 F_GSBI_QUP( 5400000, pxo, 1, 1, 5, LOW),
1143 F_GSBI_QUP(10800000, pxo, 1, 2, 5, LOW),
1144 F_GSBI_QUP(15060000, pll8, 1, 2, 51, LOW),
1145 F_GSBI_QUP(24000000, pll8, 4, 1, 4, LOW),
1146 F_GSBI_QUP(25600000, pll8, 1, 1, 15, NOMINAL),
1147 F_GSBI_QUP(27000000, pxo, 1, 0, 0, NOMINAL),
1148 F_GSBI_QUP(48000000, pll8, 4, 1, 2, NOMINAL),
1149 F_GSBI_QUP(51200000, pll8, 1, 2, 15, NOMINAL),
1150 F_END
1151};
1152
1153static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1154static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1155static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1156static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1157static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1158static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1159static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1160static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1161static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1162static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1163static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1164static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1165
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001166#define F_QDSS(f, s, d, v) \
1167 { \
1168 .freq_hz = f, \
1169 .src_clk = &s##_clk.c, \
1170 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
1171 .sys_vdd = v, \
1172 }
1173static struct clk_freq_tbl clk_tbl_qdss[] = {
1174 F_QDSS(128000000, pll8, 3, LOW),
1175 F_QDSS(300000000, pll3, 4, NOMINAL),
1176 F_END
1177};
1178
1179struct qdss_bank {
1180 const u32 bank_sel_mask;
1181 void __iomem *const ns_reg;
1182 const u32 ns_mask;
1183};
1184
1185static void set_rate_qdss(struct rcg_clk *clk, struct clk_freq_tbl *nf)
1186{
1187 const struct qdss_bank *bank = clk->bank_info;
1188 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1189
1190 /* Switch to bank 0 (always sourced from PXO) */
1191 reg = readl_relaxed(clk->ns_reg);
1192 reg &= ~bank_sel_mask;
1193 writel_relaxed(reg, clk->ns_reg);
1194 /*
1195 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1196 * MUX to fully switch sources.
1197 */
1198 mb();
1199 udelay(1);
1200
1201 /* Set source and divider */
1202 reg = readl_relaxed(bank->ns_reg);
1203 reg &= ~bank->ns_mask;
1204 reg |= nf->ns_val;
1205 writel_relaxed(reg, bank->ns_reg);
1206
1207 /* Switch to reprogrammed bank */
1208 reg = readl_relaxed(clk->ns_reg);
1209 reg |= bank_sel_mask;
1210 writel_relaxed(reg, clk->ns_reg);
1211 /*
1212 * Wait at least 6 cycles of slowest bank's clock for the glitch-free
1213 * MUX to fully switch sources.
1214 */
1215 mb();
1216 udelay(1);
1217}
1218
1219#define QDSS_CLK_ROOT_ENA BIT(1)
1220
1221static int qdss_clk_enable(struct clk *c)
1222{
1223 struct rcg_clk *clk = to_rcg_clk(c);
1224 const struct qdss_bank *bank = clk->bank_info;
1225 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1226 int ret;
1227
1228 /* Switch to bank 1 */
1229 reg = readl_relaxed(clk->ns_reg);
1230 reg |= bank_sel_mask;
1231 writel_relaxed(reg, clk->ns_reg);
1232 /* Enable root */
1233 reg |= QDSS_CLK_ROOT_ENA;
1234 writel_relaxed(reg, clk->ns_reg);
1235
1236 ret = rcg_clk_enable(c);
1237 if (ret) {
1238 /* Disable root */
1239 reg = readl_relaxed(clk->ns_reg);
1240 reg &= ~QDSS_CLK_ROOT_ENA;
1241 writel_relaxed(reg, clk->ns_reg);
1242 /* Switch to bank 0 */
1243 reg &= ~bank_sel_mask;
1244 writel_relaxed(reg, clk->ns_reg);
1245 }
1246 return ret;
1247}
1248
1249static void qdss_clk_disable(struct clk *c)
1250{
1251 struct rcg_clk *clk = to_rcg_clk(c);
1252 const struct qdss_bank *bank = clk->bank_info;
1253 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1254
1255 rcg_clk_disable(c);
1256 /* Disable root */
1257 reg = readl_relaxed(clk->ns_reg);
1258 reg &= ~QDSS_CLK_ROOT_ENA;
1259 writel_relaxed(reg, clk->ns_reg);
1260 /* Switch to bank 0 */
1261 reg &= ~bank_sel_mask;
1262 writel_relaxed(reg, clk->ns_reg);
1263}
1264
1265static void qdss_clk_auto_off(struct clk *c)
1266{
1267 struct rcg_clk *clk = to_rcg_clk(c);
1268 const struct qdss_bank *bank = clk->bank_info;
1269 u32 reg, bank_sel_mask = bank->bank_sel_mask;
1270
1271 rcg_clk_auto_off(c);
1272 /* Disable root */
1273 reg = readl_relaxed(clk->ns_reg);
1274 reg &= ~QDSS_CLK_ROOT_ENA;
1275 writel_relaxed(reg, clk->ns_reg);
1276 /* Switch to bank 0 */
1277 reg &= ~bank_sel_mask;
1278 writel_relaxed(reg, clk->ns_reg);
1279}
1280
1281static struct clk_ops clk_ops_qdss = {
1282 .enable = qdss_clk_enable,
1283 .disable = qdss_clk_disable,
1284 .auto_off = qdss_clk_auto_off,
1285 .set_rate = rcg_clk_set_rate,
1286 .set_min_rate = rcg_clk_set_min_rate,
1287 .get_rate = rcg_clk_get_rate,
1288 .list_rate = rcg_clk_list_rate,
1289 .is_enabled = rcg_clk_is_enabled,
1290 .round_rate = rcg_clk_round_rate,
1291 .reset = soc_clk_reset,
1292 .is_local = local_clk_is_local,
1293 .get_parent = rcg_clk_get_parent,
1294};
1295
1296static struct qdss_bank bdiv_info_qdss = {
1297 .bank_sel_mask = BIT(0),
1298 .ns_reg = QDSS_AT_CLK_SRC1_NS_REG,
1299 .ns_mask = BM(6, 0),
1300};
1301
1302static struct rcg_clk qdss_at_clk = {
1303 .b = {
1304 .ctl_reg = QDSS_AT_CLK_NS_REG,
1305 .en_mask = BIT(6),
1306 .reset_reg = QDSS_RESETS_REG,
1307 .reset_mask = BIT(0),
1308 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1309 .halt_bit = 10,
1310 .halt_check = HALT_VOTED,
1311 },
1312 .ns_reg = QDSS_AT_CLK_SRC_CTL_REG,
1313 .set_rate = set_rate_qdss,
1314 .freq_tbl = clk_tbl_qdss,
1315 .bank_info = &bdiv_info_qdss,
1316 .current_freq = &rcg_dummy_freq,
1317 .c = {
1318 .dbg_name = "qdss_at_clk",
1319 .ops = &clk_ops_qdss,
1320 CLK_INIT(qdss_at_clk.c),
Stephen Boyd078c9e32011-08-29 19:33:15 -07001321 .flags = CLKFLAG_SKIP_AUTO_OFF,
Stephen Boyd973e4ba2011-07-12 17:06:01 -07001322 },
1323};
1324
1325static struct branch_clk qdss_pclkdbg_clk = {
1326 .b = {
1327 .ctl_reg = QDSS_AT_CLK_NS_REG,
1328 .en_mask = BIT(4),
1329 .reset_reg = QDSS_RESETS_REG,
1330 .reset_mask = BIT(0),
1331 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1332 .halt_bit = 9,
1333 .halt_check = HALT_VOTED
1334 },
1335 .parent = &qdss_at_clk.c,
1336 .c = {
1337 .dbg_name = "qdss_pclkdbg_clk",
1338 .ops = &clk_ops_branch,
1339 CLK_INIT(qdss_pclkdbg_clk.c),
1340 },
1341};
1342
1343static struct qdss_bank bdiv_info_qdss_trace = {
1344 .bank_sel_mask = BIT(0),
1345 .ns_reg = QDSS_TRACECLKIN_CLK_SRC1_NS_REG,
1346 .ns_mask = BM(6, 0),
1347};
1348
1349static struct rcg_clk qdss_traceclkin_clk = {
1350 .b = {
1351 .ctl_reg = QDSS_TRACECLKIN_CTL_REG,
1352 .en_mask = BIT(4),
1353 .reset_reg = QDSS_RESETS_REG,
1354 .reset_mask = BIT(0),
1355 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1356 .halt_bit = 8,
1357 .halt_check = HALT_VOTED,
1358 },
1359 .ns_reg = QDSS_TRACECLKIN_CLK_SRC_CTL_REG,
1360 .set_rate = set_rate_qdss,
1361 .freq_tbl = clk_tbl_qdss,
1362 .bank_info = &bdiv_info_qdss_trace,
1363 .current_freq = &rcg_dummy_freq,
1364 .c = {
1365 .dbg_name = "qdss_traceclkin_clk",
1366 .ops = &clk_ops_qdss,
1367 CLK_INIT(qdss_traceclkin_clk.c),
1368 },
1369};
1370
1371static struct clk_freq_tbl clk_tbl_qdss_tsctr[] = {
1372 F_QDSS(200000000, pll3, 6, LOW),
1373 F_QDSS(400000000, pll3, 3, NOMINAL),
1374 F_END
1375};
1376
1377static struct qdss_bank bdiv_info_qdss_tsctr = {
1378 .bank_sel_mask = BIT(0),
1379 .ns_reg = QDSS_TSCTR_CLK_SRC1_NS_REG,
1380 .ns_mask = BM(6, 0),
1381};
1382
1383static struct rcg_clk qdss_tsctr_clk = {
1384 .b = {
1385 .ctl_reg = QDSS_TSCTR_CTL_REG,
1386 .en_mask = BIT(4),
1387 .reset_reg = QDSS_RESETS_REG,
1388 .reset_mask = BIT(3),
1389 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1390 .halt_bit = 7,
1391 .halt_check = HALT_VOTED,
1392 },
1393 .ns_reg = QDSS_TSCTR_CLK_SRC_CTL_REG,
1394 .set_rate = set_rate_qdss,
1395 .freq_tbl = clk_tbl_qdss_tsctr,
1396 .bank_info = &bdiv_info_qdss_tsctr,
1397 .current_freq = &rcg_dummy_freq,
1398 .c = {
1399 .dbg_name = "qdss_tsctr_clk",
1400 .ops = &clk_ops_qdss,
1401 CLK_INIT(qdss_tsctr_clk.c),
1402 },
1403};
1404
1405static struct branch_clk qdss_stm_clk = {
1406 .b = {
1407 .ctl_reg = QDSS_STM_CLK_CTL_REG,
1408 .en_mask = BIT(4),
1409 .reset_reg = QDSS_RESETS_REG,
1410 .reset_mask = BIT(1),
1411 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1412 .halt_bit = 20,
1413 .halt_check = HALT_VOTED,
1414 },
1415 .c = {
1416 .dbg_name = "qdss_stm_clk",
1417 .ops = &clk_ops_branch,
1418 CLK_INIT(qdss_stm_clk.c),
1419 },
1420};
1421
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001422#define F_PDM(f, s, d, v) \
1423 { \
1424 .freq_hz = f, \
1425 .src_clk = &s##_clk.c, \
1426 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1427 .sys_vdd = v, \
1428 }
1429static struct clk_freq_tbl clk_tbl_pdm[] = {
1430 F_PDM( 0, gnd, 1, NONE),
1431 F_PDM(27000000, pxo, 1, LOW),
1432 F_END
1433};
1434
1435static struct rcg_clk pdm_clk = {
1436 .b = {
1437 .ctl_reg = PDM_CLK_NS_REG,
1438 .en_mask = BIT(9),
1439 .reset_reg = PDM_CLK_NS_REG,
1440 .reset_mask = BIT(12),
1441 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1442 .halt_bit = 3,
1443 },
1444 .ns_reg = PDM_CLK_NS_REG,
1445 .root_en_mask = BIT(11),
1446 .ns_mask = BM(1, 0),
1447 .set_rate = set_rate_nop,
1448 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001449 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001450 .c = {
1451 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001452 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001453 CLK_INIT(pdm_clk.c),
1454 },
1455};
1456
1457static struct branch_clk pmem_clk = {
1458 .b = {
1459 .ctl_reg = PMEM_ACLK_CTL_REG,
1460 .en_mask = BIT(4),
1461 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1462 .halt_bit = 20,
1463 },
1464 .c = {
1465 .dbg_name = "pmem_clk",
1466 .ops = &clk_ops_branch,
1467 CLK_INIT(pmem_clk.c),
1468 },
1469};
1470
1471#define F_PRNG(f, s, v) \
1472 { \
1473 .freq_hz = f, \
1474 .src_clk = &s##_clk.c, \
1475 .sys_vdd = v, \
1476 }
1477static struct clk_freq_tbl clk_tbl_prng[] = {
1478 F_PRNG(64000000, pll8, NOMINAL),
1479 F_END
1480};
1481
1482static struct rcg_clk prng_clk = {
1483 .b = {
1484 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1485 .en_mask = BIT(10),
1486 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1487 .halt_check = HALT_VOTED,
1488 .halt_bit = 10,
1489 },
1490 .set_rate = set_rate_nop,
1491 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001492 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001493 .c = {
1494 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001495 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001496 CLK_INIT(prng_clk.c),
1497 },
1498};
1499
Stephen Boyda78a7402011-08-02 11:23:39 -07001500#define CLK_SDC(name, n, h_b, f_table) \
1501 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001502 .b = { \
1503 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1504 .en_mask = BIT(9), \
1505 .reset_reg = SDCn_RESET_REG(n), \
1506 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001507 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001508 .halt_bit = h_b, \
1509 }, \
1510 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1511 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1512 .root_en_mask = BIT(11), \
1513 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1514 .set_rate = set_rate_mnd, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001515 .freq_tbl = f_table, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001516 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001517 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001518 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001519 .ops = &clk_ops_rcg_8960, \
Stephen Boyda78a7402011-08-02 11:23:39 -07001520 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001521 }, \
1522 }
1523#define F_SDC(f, s, d, m, n, v) \
1524 { \
1525 .freq_hz = f, \
1526 .src_clk = &s##_clk.c, \
1527 .md_val = MD8(16, m, 0, n), \
1528 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1529 .mnd_en_mask = BIT(8) * !!(n), \
1530 .sys_vdd = v, \
1531 }
Stephen Boyda78a7402011-08-02 11:23:39 -07001532static struct clk_freq_tbl clk_tbl_sdc1_2[] = {
1533 F_SDC( 0, gnd, 1, 0, 0, NONE),
1534 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1535 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1536 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1537 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1538 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1539 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1540 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1541 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
1542 F_SDC( 96000000, pll8, 4, 0, 0, NOMINAL),
1543 F_END
1544};
1545
1546static CLK_SDC(sdc1_clk, 1, 6, clk_tbl_sdc1_2);
1547static CLK_SDC(sdc2_clk, 2, 5, clk_tbl_sdc1_2);
1548
1549static struct clk_freq_tbl clk_tbl_sdc3[] = {
1550 F_SDC( 0, gnd, 1, 0, 0, NONE),
1551 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1552 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1553 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1554 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1555 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1556 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1557 F_SDC( 48000000, pll8, 4, 1, 2, LOW),
1558 F_SDC( 64000000, pll8, 3, 1, 2, LOW),
1559 F_SDC( 96000000, pll8, 4, 0, 0, LOW),
1560 F_SDC(192000000, pll8, 2, 0, 0, NOMINAL),
1561 F_END
1562};
1563
1564static CLK_SDC(sdc3_clk, 3, 4, clk_tbl_sdc3);
1565
1566static struct clk_freq_tbl clk_tbl_sdc4_5[] = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001567 F_SDC( 0, gnd, 1, 0, 0, NONE),
1568 F_SDC( 144000, pxo, 3, 2, 125, LOW),
1569 F_SDC( 400000, pll8, 4, 1, 240, LOW),
1570 F_SDC( 16000000, pll8, 4, 1, 6, LOW),
1571 F_SDC( 17070000, pll8, 1, 2, 45, LOW),
1572 F_SDC( 20210000, pll8, 1, 1, 19, LOW),
1573 F_SDC( 24000000, pll8, 4, 1, 4, LOW),
1574 F_SDC( 48000000, pll8, 4, 1, 2, NOMINAL),
1575 F_SDC( 64000000, pll8, 3, 1, 2, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001576 F_END
1577};
1578
Stephen Boyda78a7402011-08-02 11:23:39 -07001579static CLK_SDC(sdc4_clk, 4, 3, clk_tbl_sdc4_5);
1580static CLK_SDC(sdc5_clk, 5, 2, clk_tbl_sdc4_5);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001581
1582#define F_TSIF_REF(f, s, d, m, n, v) \
1583 { \
1584 .freq_hz = f, \
1585 .src_clk = &s##_clk.c, \
1586 .md_val = MD16(m, n), \
1587 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1588 .mnd_en_mask = BIT(8) * !!(n), \
1589 .sys_vdd = v, \
1590 }
1591static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
1592 F_TSIF_REF( 0, gnd, 1, 0, 0, NONE),
1593 F_TSIF_REF(105000, pxo, 1, 1, 256, LOW),
1594 F_END
1595};
1596
1597static struct rcg_clk tsif_ref_clk = {
1598 .b = {
1599 .ctl_reg = TSIF_REF_CLK_NS_REG,
1600 .en_mask = BIT(9),
1601 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1602 .halt_bit = 5,
1603 },
1604 .ns_reg = TSIF_REF_CLK_NS_REG,
1605 .md_reg = TSIF_REF_CLK_MD_REG,
1606 .root_en_mask = BIT(11),
1607 .ns_mask = (BM(31, 16) | BM(6, 0)),
1608 .set_rate = set_rate_mnd,
1609 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001610 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001611 .c = {
1612 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001613 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001614 CLK_INIT(tsif_ref_clk.c),
1615 },
1616};
1617
1618#define F_TSSC(f, s, v) \
1619 { \
1620 .freq_hz = f, \
1621 .src_clk = &s##_clk.c, \
1622 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
1623 .sys_vdd = v, \
1624 }
1625static struct clk_freq_tbl clk_tbl_tssc[] = {
1626 F_TSSC( 0, gnd, NONE),
1627 F_TSSC(27000000, pxo, LOW),
1628 F_END
1629};
1630
1631static struct rcg_clk tssc_clk = {
1632 .b = {
1633 .ctl_reg = TSSC_CLK_CTL_REG,
1634 .en_mask = BIT(4),
1635 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1636 .halt_bit = 4,
1637 },
1638 .ns_reg = TSSC_CLK_CTL_REG,
1639 .ns_mask = BM(1, 0),
1640 .set_rate = set_rate_nop,
1641 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001642 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001643 .c = {
1644 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001645 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001646 CLK_INIT(tssc_clk.c),
1647 },
1648};
1649
1650#define F_USB(f, s, d, m, n, v) \
1651 { \
1652 .freq_hz = f, \
1653 .src_clk = &s##_clk.c, \
1654 .md_val = MD8(16, m, 0, n), \
1655 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
1656 .mnd_en_mask = BIT(8) * !!(n), \
1657 .sys_vdd = v, \
1658 }
1659static struct clk_freq_tbl clk_tbl_usb[] = {
1660 F_USB( 0, gnd, 1, 0, 0, NONE),
1661 F_USB(60000000, pll8, 1, 5, 32, NOMINAL),
1662 F_END
1663};
1664
1665static struct rcg_clk usb_hs1_xcvr_clk = {
1666 .b = {
1667 .ctl_reg = USB_HS1_XCVR_FS_CLK_NS_REG,
1668 .en_mask = BIT(9),
1669 .reset_reg = USB_HS1_RESET_REG,
1670 .reset_mask = BIT(0),
1671 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1672 .halt_bit = 0,
1673 },
1674 .ns_reg = USB_HS1_XCVR_FS_CLK_NS_REG,
1675 .md_reg = USB_HS1_XCVR_FS_CLK_MD_REG,
1676 .root_en_mask = BIT(11),
1677 .ns_mask = (BM(23, 16) | BM(6, 0)),
1678 .set_rate = set_rate_mnd,
1679 .freq_tbl = clk_tbl_usb,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001680 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001681 .c = {
1682 .dbg_name = "usb_hs1_xcvr_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001683 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001684 CLK_INIT(usb_hs1_xcvr_clk.c),
1685 },
1686};
1687
Stephen Boyd94625ef2011-07-12 17:06:01 -07001688static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
1689 F_USB( 0, gnd, 1, 0, 0, NONE),
1690 F_USB(60000000, pll8, 1, 5, 32, LOW),
1691 F_END
1692};
1693
1694static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1695 .b = {
1696 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1697 .en_mask = BIT(9),
1698 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1699 .halt_bit = 26,
1700 },
1701 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1702 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1703 .root_en_mask = BIT(11),
1704 .ns_mask = (BM(23, 16) | BM(6, 0)),
1705 .set_rate = set_rate_mnd,
1706 .freq_tbl = clk_tbl_usb_hsic,
1707 .current_freq = &rcg_dummy_freq,
1708 .c = {
1709 .dbg_name = "usb_hsic_xcvr_fs_clk",
1710 .ops = &clk_ops_rcg_8960,
1711 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1712 },
1713};
1714
1715static struct branch_clk usb_hsic_system_clk = {
1716 .b = {
1717 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1718 .en_mask = BIT(4),
1719 .reset_reg = USB_HSIC_RESET_REG,
1720 .reset_mask = BIT(0),
1721 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1722 .halt_bit = 24,
1723 },
1724 .parent = &usb_hsic_xcvr_fs_clk.c,
1725 .c = {
1726 .dbg_name = "usb_hsic_system_clk",
1727 .ops = &clk_ops_branch,
1728 CLK_INIT(usb_hsic_system_clk.c),
1729 },
1730};
1731
1732#define F_USB_HSIC(f, s, v) \
1733 { \
1734 .freq_hz = f, \
1735 .src_clk = &s##_clk.c, \
1736 .sys_vdd = v, \
1737 }
1738static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
1739 F_USB_HSIC(480000000, pll14, LOW),
1740 F_END
1741};
1742
1743static struct rcg_clk usb_hsic_hsic_src_clk = {
1744 .b = {
1745 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1746 .halt_check = NOCHECK,
1747 },
1748 .root_en_mask = BIT(0),
1749 .set_rate = set_rate_nop,
1750 .freq_tbl = clk_tbl_usb2_hsic,
1751 .current_freq = &rcg_dummy_freq,
1752 .c = {
1753 .dbg_name = "usb_hsic_hsic_src_clk",
1754 .ops = &clk_ops_rcg_8960,
1755 CLK_INIT(usb_hsic_hsic_src_clk.c),
1756 },
1757};
1758
1759static struct branch_clk usb_hsic_hsic_clk = {
1760 .b = {
1761 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1762 .en_mask = BIT(0),
1763 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1764 .halt_bit = 19,
1765 },
1766 .parent = &usb_hsic_hsic_src_clk.c,
1767 .c = {
1768 .dbg_name = "usb_hsic_hsic_clk",
1769 .ops = &clk_ops_branch,
1770 CLK_INIT(usb_hsic_hsic_clk.c),
1771 },
1772};
1773
1774#define F_USB_HSIO_CAL(f, s, v) \
1775 { \
1776 .freq_hz = f, \
1777 .src_clk = &s##_clk.c, \
1778 .sys_vdd = v, \
1779 }
1780static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
1781 F_USB_HSIO_CAL(9000000, pxo, LOW),
1782 F_END
1783};
1784
1785static struct rcg_clk usb_hsic_hsio_cal_clk = {
1786 .b = {
1787 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1788 .en_mask = BIT(0),
1789 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1790 .halt_bit = 23,
1791 },
1792 .set_rate = set_rate_nop,
1793 .freq_tbl = clk_tbl_usb_hsio_cal,
1794 .current_freq = &rcg_dummy_freq,
1795 .c = {
1796 .dbg_name = "usb_hsic_hsio_cal_clk",
1797 .ops = &clk_ops_branch,
1798 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1799 },
1800};
1801
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001802static struct branch_clk usb_phy0_clk = {
1803 .b = {
1804 .reset_reg = USB_PHY0_RESET_REG,
1805 .reset_mask = BIT(0),
1806 },
1807 .c = {
1808 .dbg_name = "usb_phy0_clk",
1809 .ops = &clk_ops_reset,
1810 CLK_INIT(usb_phy0_clk.c),
1811 },
1812};
1813
1814#define CLK_USB_FS(i, n) \
1815 struct rcg_clk i##_clk = { \
1816 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1817 .b = { \
1818 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1819 .halt_check = NOCHECK, \
1820 }, \
1821 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1822 .root_en_mask = BIT(11), \
1823 .ns_mask = (BM(23, 16) | BM(6, 0)), \
1824 .set_rate = set_rate_mnd, \
1825 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001826 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001827 .c = { \
1828 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001829 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001830 CLK_INIT(i##_clk.c), \
1831 }, \
1832 }
1833
1834static CLK_USB_FS(usb_fs1_src, 1);
1835static struct branch_clk usb_fs1_xcvr_clk = {
1836 .b = {
1837 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1838 .en_mask = BIT(9),
1839 .reset_reg = USB_FSn_RESET_REG(1),
1840 .reset_mask = BIT(1),
1841 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1842 .halt_bit = 15,
1843 },
1844 .parent = &usb_fs1_src_clk.c,
1845 .c = {
1846 .dbg_name = "usb_fs1_xcvr_clk",
1847 .ops = &clk_ops_branch,
1848 CLK_INIT(usb_fs1_xcvr_clk.c),
1849 },
1850};
1851
1852static struct branch_clk usb_fs1_sys_clk = {
1853 .b = {
1854 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1855 .en_mask = BIT(4),
1856 .reset_reg = USB_FSn_RESET_REG(1),
1857 .reset_mask = BIT(0),
1858 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1859 .halt_bit = 16,
1860 },
1861 .parent = &usb_fs1_src_clk.c,
1862 .c = {
1863 .dbg_name = "usb_fs1_sys_clk",
1864 .ops = &clk_ops_branch,
1865 CLK_INIT(usb_fs1_sys_clk.c),
1866 },
1867};
1868
1869static CLK_USB_FS(usb_fs2_src, 2);
1870static struct branch_clk usb_fs2_xcvr_clk = {
1871 .b = {
1872 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1873 .en_mask = BIT(9),
1874 .reset_reg = USB_FSn_RESET_REG(2),
1875 .reset_mask = BIT(1),
1876 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1877 .halt_bit = 12,
1878 },
1879 .parent = &usb_fs2_src_clk.c,
1880 .c = {
1881 .dbg_name = "usb_fs2_xcvr_clk",
1882 .ops = &clk_ops_branch,
1883 CLK_INIT(usb_fs2_xcvr_clk.c),
1884 },
1885};
1886
1887static struct branch_clk usb_fs2_sys_clk = {
1888 .b = {
1889 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1890 .en_mask = BIT(4),
1891 .reset_reg = USB_FSn_RESET_REG(2),
1892 .reset_mask = BIT(0),
1893 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1894 .halt_bit = 13,
1895 },
1896 .parent = &usb_fs2_src_clk.c,
1897 .c = {
1898 .dbg_name = "usb_fs2_sys_clk",
1899 .ops = &clk_ops_branch,
1900 CLK_INIT(usb_fs2_sys_clk.c),
1901 },
1902};
1903
1904/* Fast Peripheral Bus Clocks */
1905static struct branch_clk ce1_core_clk = {
1906 .b = {
1907 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1908 .en_mask = BIT(4),
1909 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1910 .halt_bit = 27,
1911 },
1912 .c = {
1913 .dbg_name = "ce1_core_clk",
1914 .ops = &clk_ops_branch,
1915 CLK_INIT(ce1_core_clk.c),
1916 },
1917};
1918static struct branch_clk ce1_p_clk = {
1919 .b = {
1920 .ctl_reg = CE1_HCLK_CTL_REG,
1921 .en_mask = BIT(4),
1922 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1923 .halt_bit = 1,
1924 },
1925 .c = {
1926 .dbg_name = "ce1_p_clk",
1927 .ops = &clk_ops_branch,
1928 CLK_INIT(ce1_p_clk.c),
1929 },
1930};
1931
1932static struct branch_clk dma_bam_p_clk = {
1933 .b = {
1934 .ctl_reg = DMA_BAM_HCLK_CTL,
1935 .en_mask = BIT(4),
1936 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1937 .halt_bit = 12,
1938 },
1939 .c = {
1940 .dbg_name = "dma_bam_p_clk",
1941 .ops = &clk_ops_branch,
1942 CLK_INIT(dma_bam_p_clk.c),
1943 },
1944};
1945
1946static struct branch_clk gsbi1_p_clk = {
1947 .b = {
1948 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
1949 .en_mask = BIT(4),
1950 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1951 .halt_bit = 11,
1952 },
1953 .c = {
1954 .dbg_name = "gsbi1_p_clk",
1955 .ops = &clk_ops_branch,
1956 CLK_INIT(gsbi1_p_clk.c),
1957 },
1958};
1959
1960static struct branch_clk gsbi2_p_clk = {
1961 .b = {
1962 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
1963 .en_mask = BIT(4),
1964 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1965 .halt_bit = 7,
1966 },
1967 .c = {
1968 .dbg_name = "gsbi2_p_clk",
1969 .ops = &clk_ops_branch,
1970 CLK_INIT(gsbi2_p_clk.c),
1971 },
1972};
1973
1974static struct branch_clk gsbi3_p_clk = {
1975 .b = {
1976 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
1977 .en_mask = BIT(4),
1978 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1979 .halt_bit = 3,
1980 },
1981 .c = {
1982 .dbg_name = "gsbi3_p_clk",
1983 .ops = &clk_ops_branch,
1984 CLK_INIT(gsbi3_p_clk.c),
1985 },
1986};
1987
1988static struct branch_clk gsbi4_p_clk = {
1989 .b = {
1990 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
1991 .en_mask = BIT(4),
1992 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
1993 .halt_bit = 27,
1994 },
1995 .c = {
1996 .dbg_name = "gsbi4_p_clk",
1997 .ops = &clk_ops_branch,
1998 CLK_INIT(gsbi4_p_clk.c),
1999 },
2000};
2001
2002static struct branch_clk gsbi5_p_clk = {
2003 .b = {
2004 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2005 .en_mask = BIT(4),
2006 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2007 .halt_bit = 23,
2008 },
2009 .c = {
2010 .dbg_name = "gsbi5_p_clk",
2011 .ops = &clk_ops_branch,
2012 CLK_INIT(gsbi5_p_clk.c),
2013 },
2014};
2015
2016static struct branch_clk gsbi6_p_clk = {
2017 .b = {
2018 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2019 .en_mask = BIT(4),
2020 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2021 .halt_bit = 19,
2022 },
2023 .c = {
2024 .dbg_name = "gsbi6_p_clk",
2025 .ops = &clk_ops_branch,
2026 CLK_INIT(gsbi6_p_clk.c),
2027 },
2028};
2029
2030static struct branch_clk gsbi7_p_clk = {
2031 .b = {
2032 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2033 .en_mask = BIT(4),
2034 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2035 .halt_bit = 15,
2036 },
2037 .c = {
2038 .dbg_name = "gsbi7_p_clk",
2039 .ops = &clk_ops_branch,
2040 CLK_INIT(gsbi7_p_clk.c),
2041 },
2042};
2043
2044static struct branch_clk gsbi8_p_clk = {
2045 .b = {
2046 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2047 .en_mask = BIT(4),
2048 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2049 .halt_bit = 11,
2050 },
2051 .c = {
2052 .dbg_name = "gsbi8_p_clk",
2053 .ops = &clk_ops_branch,
2054 CLK_INIT(gsbi8_p_clk.c),
2055 },
2056};
2057
2058static struct branch_clk gsbi9_p_clk = {
2059 .b = {
2060 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2061 .en_mask = BIT(4),
2062 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2063 .halt_bit = 7,
2064 },
2065 .c = {
2066 .dbg_name = "gsbi9_p_clk",
2067 .ops = &clk_ops_branch,
2068 CLK_INIT(gsbi9_p_clk.c),
2069 },
2070};
2071
2072static struct branch_clk gsbi10_p_clk = {
2073 .b = {
2074 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2075 .en_mask = BIT(4),
2076 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2077 .halt_bit = 3,
2078 },
2079 .c = {
2080 .dbg_name = "gsbi10_p_clk",
2081 .ops = &clk_ops_branch,
2082 CLK_INIT(gsbi10_p_clk.c),
2083 },
2084};
2085
2086static struct branch_clk gsbi11_p_clk = {
2087 .b = {
2088 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2089 .en_mask = BIT(4),
2090 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2091 .halt_bit = 18,
2092 },
2093 .c = {
2094 .dbg_name = "gsbi11_p_clk",
2095 .ops = &clk_ops_branch,
2096 CLK_INIT(gsbi11_p_clk.c),
2097 },
2098};
2099
2100static struct branch_clk gsbi12_p_clk = {
2101 .b = {
2102 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2103 .en_mask = BIT(4),
2104 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2105 .halt_bit = 14,
2106 },
2107 .c = {
2108 .dbg_name = "gsbi12_p_clk",
2109 .ops = &clk_ops_branch,
2110 CLK_INIT(gsbi12_p_clk.c),
2111 },
2112};
2113
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002114static struct branch_clk qdss_p_clk = {
2115 .b = {
2116 .ctl_reg = QDSS_HCLK_CTL_REG,
2117 .en_mask = BIT(4),
2118 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2119 .halt_bit = 11,
2120 .halt_check = HALT_VOTED,
2121 .reset_reg = QDSS_RESETS_REG,
2122 .reset_mask = BIT(2),
2123 },
2124 .c = {
2125 .dbg_name = "qdss_p_clk",
2126 .ops = &clk_ops_branch,
2127 CLK_INIT(qdss_p_clk.c),
2128 },
2129};
2130
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002131static struct branch_clk tsif_p_clk = {
2132 .b = {
2133 .ctl_reg = TSIF_HCLK_CTL_REG,
2134 .en_mask = BIT(4),
2135 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2136 .halt_bit = 7,
2137 },
2138 .c = {
2139 .dbg_name = "tsif_p_clk",
2140 .ops = &clk_ops_branch,
2141 CLK_INIT(tsif_p_clk.c),
2142 },
2143};
2144
2145static struct branch_clk usb_fs1_p_clk = {
2146 .b = {
2147 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2148 .en_mask = BIT(4),
2149 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2150 .halt_bit = 17,
2151 },
2152 .c = {
2153 .dbg_name = "usb_fs1_p_clk",
2154 .ops = &clk_ops_branch,
2155 CLK_INIT(usb_fs1_p_clk.c),
2156 },
2157};
2158
2159static struct branch_clk usb_fs2_p_clk = {
2160 .b = {
2161 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2162 .en_mask = BIT(4),
2163 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2164 .halt_bit = 14,
2165 },
2166 .c = {
2167 .dbg_name = "usb_fs2_p_clk",
2168 .ops = &clk_ops_branch,
2169 CLK_INIT(usb_fs2_p_clk.c),
2170 },
2171};
2172
2173static struct branch_clk usb_hs1_p_clk = {
2174 .b = {
2175 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2176 .en_mask = BIT(4),
2177 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2178 .halt_bit = 1,
2179 },
2180 .c = {
2181 .dbg_name = "usb_hs1_p_clk",
2182 .ops = &clk_ops_branch,
2183 CLK_INIT(usb_hs1_p_clk.c),
2184 },
2185};
2186
Stephen Boyd94625ef2011-07-12 17:06:01 -07002187static struct branch_clk usb_hsic_p_clk = {
2188 .b = {
2189 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2190 .en_mask = BIT(4),
2191 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2192 .halt_bit = 28,
2193 },
2194 .c = {
2195 .dbg_name = "usb_hsic_p_clk",
2196 .ops = &clk_ops_branch,
2197 CLK_INIT(usb_hsic_p_clk.c),
2198 },
2199};
2200
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002201static struct branch_clk sdc1_p_clk = {
2202 .b = {
2203 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2204 .en_mask = BIT(4),
2205 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2206 .halt_bit = 11,
2207 },
2208 .c = {
2209 .dbg_name = "sdc1_p_clk",
2210 .ops = &clk_ops_branch,
2211 CLK_INIT(sdc1_p_clk.c),
2212 },
2213};
2214
2215static struct branch_clk sdc2_p_clk = {
2216 .b = {
2217 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2218 .en_mask = BIT(4),
2219 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2220 .halt_bit = 10,
2221 },
2222 .c = {
2223 .dbg_name = "sdc2_p_clk",
2224 .ops = &clk_ops_branch,
2225 CLK_INIT(sdc2_p_clk.c),
2226 },
2227};
2228
2229static struct branch_clk sdc3_p_clk = {
2230 .b = {
2231 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2232 .en_mask = BIT(4),
2233 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2234 .halt_bit = 9,
2235 },
2236 .c = {
2237 .dbg_name = "sdc3_p_clk",
2238 .ops = &clk_ops_branch,
2239 CLK_INIT(sdc3_p_clk.c),
2240 },
2241};
2242
2243static struct branch_clk sdc4_p_clk = {
2244 .b = {
2245 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2246 .en_mask = BIT(4),
2247 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2248 .halt_bit = 8,
2249 },
2250 .c = {
2251 .dbg_name = "sdc4_p_clk",
2252 .ops = &clk_ops_branch,
2253 CLK_INIT(sdc4_p_clk.c),
2254 },
2255};
2256
2257static struct branch_clk sdc5_p_clk = {
2258 .b = {
2259 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2260 .en_mask = BIT(4),
2261 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2262 .halt_bit = 7,
2263 },
2264 .c = {
2265 .dbg_name = "sdc5_p_clk",
2266 .ops = &clk_ops_branch,
2267 CLK_INIT(sdc5_p_clk.c),
2268 },
2269};
2270
2271/* HW-Voteable Clocks */
2272static struct branch_clk adm0_clk = {
2273 .b = {
2274 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2275 .en_mask = BIT(2),
2276 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2277 .halt_check = HALT_VOTED,
2278 .halt_bit = 14,
2279 },
2280 .c = {
2281 .dbg_name = "adm0_clk",
2282 .ops = &clk_ops_branch,
2283 CLK_INIT(adm0_clk.c),
2284 },
2285};
2286
2287static struct branch_clk adm0_p_clk = {
2288 .b = {
2289 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2290 .en_mask = BIT(3),
2291 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2292 .halt_check = HALT_VOTED,
2293 .halt_bit = 13,
2294 },
2295 .c = {
2296 .dbg_name = "adm0_p_clk",
2297 .ops = &clk_ops_branch,
2298 CLK_INIT(adm0_p_clk.c),
2299 },
2300};
2301
2302static struct branch_clk pmic_arb0_p_clk = {
2303 .b = {
2304 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2305 .en_mask = BIT(8),
2306 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2307 .halt_check = HALT_VOTED,
2308 .halt_bit = 22,
2309 },
2310 .c = {
2311 .dbg_name = "pmic_arb0_p_clk",
2312 .ops = &clk_ops_branch,
2313 CLK_INIT(pmic_arb0_p_clk.c),
2314 },
2315};
2316
2317static struct branch_clk pmic_arb1_p_clk = {
2318 .b = {
2319 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2320 .en_mask = BIT(9),
2321 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2322 .halt_check = HALT_VOTED,
2323 .halt_bit = 21,
2324 },
2325 .c = {
2326 .dbg_name = "pmic_arb1_p_clk",
2327 .ops = &clk_ops_branch,
2328 CLK_INIT(pmic_arb1_p_clk.c),
2329 },
2330};
2331
2332static struct branch_clk pmic_ssbi2_clk = {
2333 .b = {
2334 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2335 .en_mask = BIT(7),
2336 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2337 .halt_check = HALT_VOTED,
2338 .halt_bit = 23,
2339 },
2340 .c = {
2341 .dbg_name = "pmic_ssbi2_clk",
2342 .ops = &clk_ops_branch,
2343 CLK_INIT(pmic_ssbi2_clk.c),
2344 },
2345};
2346
2347static struct branch_clk rpm_msg_ram_p_clk = {
2348 .b = {
2349 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2350 .en_mask = BIT(6),
2351 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2352 .halt_check = HALT_VOTED,
2353 .halt_bit = 12,
2354 },
2355 .c = {
2356 .dbg_name = "rpm_msg_ram_p_clk",
2357 .ops = &clk_ops_branch,
2358 CLK_INIT(rpm_msg_ram_p_clk.c),
2359 },
2360};
2361
2362/*
2363 * Multimedia Clocks
2364 */
2365
2366static struct branch_clk amp_clk = {
2367 .b = {
2368 .reset_reg = SW_RESET_CORE_REG,
2369 .reset_mask = BIT(20),
2370 },
2371 .c = {
2372 .dbg_name = "amp_clk",
2373 .ops = &clk_ops_reset,
2374 CLK_INIT(amp_clk.c),
2375 },
2376};
2377
Stephen Boyd94625ef2011-07-12 17:06:01 -07002378#define CLK_CAM(name, n, hb) \
2379 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002380 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002381 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002382 .en_mask = BIT(0), \
2383 .halt_reg = DBG_BUS_VEC_I_REG, \
2384 .halt_bit = hb, \
2385 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002386 .ns_reg = CAMCLK##n##_NS_REG, \
2387 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002388 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002389 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002390 .ctl_mask = BM(7, 6), \
2391 .set_rate = set_rate_mnd_8, \
2392 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002393 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002394 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002395 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002396 .ops = &clk_ops_rcg_8960, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002397 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002398 }, \
2399 }
2400#define F_CAM(f, s, d, m, n, v) \
2401 { \
2402 .freq_hz = f, \
2403 .src_clk = &s##_clk.c, \
2404 .md_val = MD8(8, m, 0, n), \
2405 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2406 .ctl_val = CC(6, n), \
2407 .mnd_en_mask = BIT(5) * !!(n), \
2408 .sys_vdd = v, \
2409 }
2410static struct clk_freq_tbl clk_tbl_cam[] = {
2411 F_CAM( 0, gnd, 1, 0, 0, NONE),
2412 F_CAM( 6000000, pll8, 4, 1, 16, LOW),
2413 F_CAM( 8000000, pll8, 4, 1, 12, LOW),
2414 F_CAM( 12000000, pll8, 4, 1, 8, LOW),
2415 F_CAM( 16000000, pll8, 4, 1, 6, LOW),
2416 F_CAM( 19200000, pll8, 4, 1, 5, LOW),
2417 F_CAM( 24000000, pll8, 4, 1, 4, LOW),
2418 F_CAM( 32000000, pll8, 4, 1, 3, LOW),
2419 F_CAM( 48000000, pll8, 4, 1, 2, LOW),
2420 F_CAM( 64000000, pll8, 3, 1, 2, LOW),
2421 F_CAM( 96000000, pll8, 4, 0, 0, NOMINAL),
2422 F_CAM(128000000, pll8, 3, 0, 0, NOMINAL),
2423 F_END
2424};
2425
Stephen Boyd94625ef2011-07-12 17:06:01 -07002426static CLK_CAM(cam0_clk, 0, 15);
2427static CLK_CAM(cam1_clk, 1, 16);
2428static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002429
2430#define F_CSI(f, s, d, m, n, v) \
2431 { \
2432 .freq_hz = f, \
2433 .src_clk = &s##_clk.c, \
2434 .md_val = MD8(8, m, 0, n), \
2435 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2436 .ctl_val = CC(6, n), \
2437 .mnd_en_mask = BIT(5) * !!(n), \
2438 .sys_vdd = v, \
2439 }
2440static struct clk_freq_tbl clk_tbl_csi[] = {
2441 F_CSI( 0, gnd, 1, 0, 0, NONE),
2442 F_CSI( 85330000, pll8, 1, 2, 9, LOW),
2443 F_CSI(177780000, pll2, 1, 2, 9, NOMINAL),
2444 F_END
2445};
2446
2447static struct rcg_clk csi0_src_clk = {
2448 .ns_reg = CSI0_NS_REG,
2449 .b = {
2450 .ctl_reg = CSI0_CC_REG,
2451 .halt_check = NOCHECK,
2452 },
2453 .md_reg = CSI0_MD_REG,
2454 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002455 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002456 .ctl_mask = BM(7, 6),
2457 .set_rate = set_rate_mnd,
2458 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002459 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002460 .c = {
2461 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002462 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002463 CLK_INIT(csi0_src_clk.c),
2464 },
2465};
2466
2467static struct branch_clk csi0_clk = {
2468 .b = {
2469 .ctl_reg = CSI0_CC_REG,
2470 .en_mask = BIT(0),
2471 .reset_reg = SW_RESET_CORE_REG,
2472 .reset_mask = BIT(8),
2473 .halt_reg = DBG_BUS_VEC_B_REG,
2474 .halt_bit = 13,
2475 },
2476 .parent = &csi0_src_clk.c,
2477 .c = {
2478 .dbg_name = "csi0_clk",
2479 .ops = &clk_ops_branch,
2480 CLK_INIT(csi0_clk.c),
2481 },
2482};
2483
2484static struct branch_clk csi0_phy_clk = {
2485 .b = {
2486 .ctl_reg = CSI0_CC_REG,
2487 .en_mask = BIT(8),
2488 .reset_reg = SW_RESET_CORE_REG,
2489 .reset_mask = BIT(29),
2490 .halt_reg = DBG_BUS_VEC_I_REG,
2491 .halt_bit = 9,
2492 },
2493 .parent = &csi0_src_clk.c,
2494 .c = {
2495 .dbg_name = "csi0_phy_clk",
2496 .ops = &clk_ops_branch,
2497 CLK_INIT(csi0_phy_clk.c),
2498 },
2499};
2500
2501static struct rcg_clk csi1_src_clk = {
2502 .ns_reg = CSI1_NS_REG,
2503 .b = {
2504 .ctl_reg = CSI1_CC_REG,
2505 .halt_check = NOCHECK,
2506 },
2507 .md_reg = CSI1_MD_REG,
2508 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002509 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002510 .ctl_mask = BM(7, 6),
2511 .set_rate = set_rate_mnd,
2512 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002513 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002514 .c = {
2515 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002516 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002517 CLK_INIT(csi1_src_clk.c),
2518 },
2519};
2520
2521static struct branch_clk csi1_clk = {
2522 .b = {
2523 .ctl_reg = CSI1_CC_REG,
2524 .en_mask = BIT(0),
2525 .reset_reg = SW_RESET_CORE_REG,
2526 .reset_mask = BIT(18),
2527 .halt_reg = DBG_BUS_VEC_B_REG,
2528 .halt_bit = 14,
2529 },
2530 .parent = &csi1_src_clk.c,
2531 .c = {
2532 .dbg_name = "csi1_clk",
2533 .ops = &clk_ops_branch,
2534 CLK_INIT(csi1_clk.c),
2535 },
2536};
2537
2538static struct branch_clk csi1_phy_clk = {
2539 .b = {
2540 .ctl_reg = CSI1_CC_REG,
2541 .en_mask = BIT(8),
2542 .reset_reg = SW_RESET_CORE_REG,
2543 .reset_mask = BIT(28),
2544 .halt_reg = DBG_BUS_VEC_I_REG,
2545 .halt_bit = 10,
2546 },
2547 .parent = &csi1_src_clk.c,
2548 .c = {
2549 .dbg_name = "csi1_phy_clk",
2550 .ops = &clk_ops_branch,
2551 CLK_INIT(csi1_phy_clk.c),
2552 },
2553};
2554
Stephen Boyd94625ef2011-07-12 17:06:01 -07002555static struct rcg_clk csi2_src_clk = {
2556 .ns_reg = CSI2_NS_REG,
2557 .b = {
2558 .ctl_reg = CSI2_CC_REG,
2559 .halt_check = NOCHECK,
2560 },
2561 .md_reg = CSI2_MD_REG,
2562 .root_en_mask = BIT(2),
2563 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
2564 .ctl_mask = BM(7, 6),
2565 .set_rate = set_rate_mnd,
2566 .freq_tbl = clk_tbl_csi,
2567 .current_freq = &rcg_dummy_freq,
2568 .c = {
2569 .dbg_name = "csi2_src_clk",
2570 .ops = &clk_ops_rcg_8960,
2571 CLK_INIT(csi2_src_clk.c),
2572 },
2573};
2574
2575static struct branch_clk csi2_clk = {
2576 .b = {
2577 .ctl_reg = CSI2_CC_REG,
2578 .en_mask = BIT(0),
2579 .reset_reg = SW_RESET_CORE2_REG,
2580 .reset_mask = BIT(2),
2581 .halt_reg = DBG_BUS_VEC_B_REG,
2582 .halt_bit = 29,
2583 },
2584 .parent = &csi2_src_clk.c,
2585 .c = {
2586 .dbg_name = "csi2_clk",
2587 .ops = &clk_ops_branch,
2588 CLK_INIT(csi2_clk.c),
2589 },
2590};
2591
2592static struct branch_clk csi2_phy_clk = {
2593 .b = {
2594 .ctl_reg = CSI2_CC_REG,
2595 .en_mask = BIT(8),
2596 .reset_reg = SW_RESET_CORE_REG,
2597 .reset_mask = BIT(31),
2598 .halt_reg = DBG_BUS_VEC_I_REG,
2599 .halt_bit = 29,
2600 },
2601 .parent = &csi2_src_clk.c,
2602 .c = {
2603 .dbg_name = "csi2_phy_clk",
2604 .ops = &clk_ops_branch,
2605 CLK_INIT(csi2_phy_clk.c),
2606 },
2607};
2608
2609/*
2610 * The csi pix and csi rdi clocks have two bits in two registers to control a
2611 * three input mux. So we have the generic rcg_clk_enable() path handle the
2612 * first bit, and this function handle the second bit.
2613 */
2614static void set_rate_pix_rdi(struct rcg_clk *clk, struct clk_freq_tbl *nf)
2615{
2616 u32 reg = readl_relaxed(MISC_CC3_REG);
2617 u32 bit = (u32)nf->extra_freq_data;
2618 if (nf->freq_hz == 2)
2619 reg |= bit;
2620 else
2621 reg &= ~bit;
2622 writel_relaxed(reg, MISC_CC3_REG);
2623}
2624
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002625#define F_CSI_PIX(s) \
2626 { \
2627 .src_clk = &csi##s##_clk.c, \
2628 .freq_hz = s, \
2629 .ns_val = BVAL(25, 25, s), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002630 .extra_freq_data = (void *)BIT(13), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002631 }
2632static struct clk_freq_tbl clk_tbl_csi_pix[] = {
2633 F_CSI_PIX(0), /* CSI0 source */
2634 F_CSI_PIX(1), /* CSI1 source */
Stephen Boyd94625ef2011-07-12 17:06:01 -07002635 F_CSI_PIX(2), /* CSI2 source */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002636 F_END
2637};
2638
2639static struct rcg_clk csi_pix_clk = {
2640 .b = {
2641 .ctl_reg = MISC_CC_REG,
2642 .en_mask = BIT(26),
2643 .halt_check = DELAY,
2644 .reset_reg = SW_RESET_CORE_REG,
2645 .reset_mask = BIT(26),
2646 },
2647 .ns_reg = MISC_CC_REG,
2648 .ns_mask = BIT(25),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002649 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002650 .freq_tbl = clk_tbl_csi_pix,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002651 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002652 .c = {
2653 .dbg_name = "csi_pix_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002654 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002655 CLK_INIT(csi_pix_clk.c),
2656 },
2657};
2658
Stephen Boyd94625ef2011-07-12 17:06:01 -07002659#define F_CSI_PIX1(s) \
2660 { \
2661 .src_clk = &csi##s##_clk.c, \
2662 .freq_hz = s, \
2663 .ns_val = BVAL(9, 8, s), \
2664 }
2665static struct clk_freq_tbl clk_tbl_csi_pix1[] = {
2666 F_CSI_PIX1(0), /* CSI0 source */
2667 F_CSI_PIX1(1), /* CSI1 source */
2668 F_CSI_PIX1(2), /* CSI2 source */
2669 F_END
2670};
2671
2672static struct rcg_clk csi_pix1_clk = {
2673 .b = {
2674 .ctl_reg = MISC_CC3_REG,
2675 .en_mask = BIT(10),
2676 .halt_check = DELAY,
2677 .reset_reg = SW_RESET_CORE_REG,
2678 .reset_mask = BIT(30),
2679 },
2680 .ns_reg = MISC_CC3_REG,
2681 .ns_mask = BM(9, 8),
2682 .set_rate = set_rate_nop,
2683 .freq_tbl = clk_tbl_csi_pix1,
2684 .current_freq = &rcg_dummy_freq,
2685 .c = {
2686 .dbg_name = "csi_pix1_clk",
2687 .ops = &clk_ops_rcg_8960,
2688 CLK_INIT(csi_pix1_clk.c),
2689 },
2690};
2691
2692#define F_CSI_RDI(s) \
2693 { \
2694 .src_clk = &csi##s##_clk.c, \
2695 .freq_hz = s, \
2696 .ns_val = BVAL(12, 12, s), \
2697 .extra_freq_data = (void *)BIT(12), \
2698 }
2699static struct clk_freq_tbl clk_tbl_csi_rdi[] = {
2700 F_CSI_RDI(0), /* CSI0 source */
2701 F_CSI_RDI(1), /* CSI1 source */
2702 F_CSI_RDI(2), /* CSI2 source */
2703 F_END
2704};
2705
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002706static struct rcg_clk csi_rdi_clk = {
2707 .b = {
2708 .ctl_reg = MISC_CC_REG,
2709 .en_mask = BIT(13),
2710 .halt_check = DELAY,
2711 .reset_reg = SW_RESET_CORE_REG,
2712 .reset_mask = BIT(27),
2713 },
2714 .ns_reg = MISC_CC_REG,
2715 .ns_mask = BIT(12),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002716 .set_rate = set_rate_pix_rdi,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002717 .freq_tbl = clk_tbl_csi_rdi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002718 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002719 .c = {
2720 .dbg_name = "csi_rdi_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002721 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002722 CLK_INIT(csi_rdi_clk.c),
2723 },
2724};
2725
Stephen Boyd94625ef2011-07-12 17:06:01 -07002726#define F_CSI_RDI1(s) \
2727 { \
2728 .src_clk = &csi##s##_clk.c, \
2729 .freq_hz = s, \
2730 .ns_val = BVAL(1, 0, s), \
2731 }
2732static struct clk_freq_tbl clk_tbl_csi_rdi1[] = {
2733 F_CSI_RDI1(0), /* CSI0 source */
2734 F_CSI_RDI1(1), /* CSI1 source */
2735 F_CSI_RDI1(2), /* CSI2 source */
2736 F_END
2737};
2738
2739static struct rcg_clk csi_rdi1_clk = {
2740 .b = {
2741 .ctl_reg = MISC_CC3_REG,
2742 .en_mask = BIT(2),
2743 .halt_check = DELAY,
2744 .reset_reg = SW_RESET_CORE2_REG,
2745 .reset_mask = BIT(1),
2746 },
2747 .ns_reg = MISC_CC3_REG,
2748 .ns_mask = BM(1, 0),
2749 .set_rate = set_rate_nop,
2750 .freq_tbl = clk_tbl_csi_rdi1,
2751 .current_freq = &rcg_dummy_freq,
2752 .c = {
2753 .dbg_name = "csi_rdi1_clk",
2754 .ops = &clk_ops_rcg_8960,
2755 CLK_INIT(csi_rdi1_clk.c),
2756 },
2757};
2758
2759#define F_CSI_RDI2(s) \
2760 { \
2761 .src_clk = &csi##s##_clk.c, \
2762 .freq_hz = s, \
2763 .ns_val = BVAL(5, 4, s), \
2764 }
2765static struct clk_freq_tbl clk_tbl_csi_rdi2[] = {
2766 F_CSI_RDI2(0), /* CSI0 source */
2767 F_CSI_RDI2(1), /* CSI1 source */
2768 F_CSI_RDI2(2), /* CSI2 source */
2769 F_END
2770};
2771
2772static struct rcg_clk csi_rdi2_clk = {
2773 .b = {
2774 .ctl_reg = MISC_CC3_REG,
2775 .en_mask = BIT(6),
2776 .halt_check = DELAY,
2777 .reset_reg = SW_RESET_CORE2_REG,
2778 .reset_mask = BIT(0),
2779 },
2780 .ns_reg = MISC_CC3_REG,
2781 .ns_mask = BM(5, 4),
2782 .set_rate = set_rate_nop,
2783 .freq_tbl = clk_tbl_csi_rdi2,
2784 .current_freq = &rcg_dummy_freq,
2785 .c = {
2786 .dbg_name = "csi_rdi2_clk",
2787 .ops = &clk_ops_rcg_8960,
2788 CLK_INIT(csi_rdi2_clk.c),
2789 },
2790};
2791
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002792#define F_CSI_PHYTIMER(f, s, d, m, n, v) \
2793 { \
2794 .freq_hz = f, \
2795 .src_clk = &s##_clk.c, \
2796 .md_val = MD8(8, m, 0, n), \
2797 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2798 .ctl_val = CC(6, n), \
2799 .mnd_en_mask = BIT(5) * !!(n), \
2800 .sys_vdd = v, \
2801 }
2802static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
2803 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0, NONE),
2804 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9, LOW),
2805 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9, NOMINAL),
2806 F_END
2807};
2808
2809static struct rcg_clk csiphy_timer_src_clk = {
2810 .ns_reg = CSIPHYTIMER_NS_REG,
2811 .b = {
2812 .ctl_reg = CSIPHYTIMER_CC_REG,
2813 .halt_check = NOCHECK,
2814 },
2815 .md_reg = CSIPHYTIMER_MD_REG,
2816 .root_en_mask = BIT(2),
2817 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
2818 .ctl_mask = BM(7, 6),
2819 .set_rate = set_rate_mnd_8,
2820 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002821 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002822 .c = {
2823 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002824 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002825 CLK_INIT(csiphy_timer_src_clk.c),
2826 },
2827};
2828
2829static struct branch_clk csi0phy_timer_clk = {
2830 .b = {
2831 .ctl_reg = CSIPHYTIMER_CC_REG,
2832 .en_mask = BIT(0),
2833 .halt_reg = DBG_BUS_VEC_I_REG,
2834 .halt_bit = 17,
2835 },
2836 .parent = &csiphy_timer_src_clk.c,
2837 .c = {
2838 .dbg_name = "csi0phy_timer_clk",
2839 .ops = &clk_ops_branch,
2840 CLK_INIT(csi0phy_timer_clk.c),
2841 },
2842};
2843
2844static struct branch_clk csi1phy_timer_clk = {
2845 .b = {
2846 .ctl_reg = CSIPHYTIMER_CC_REG,
2847 .en_mask = BIT(9),
2848 .halt_reg = DBG_BUS_VEC_I_REG,
2849 .halt_bit = 18,
2850 },
2851 .parent = &csiphy_timer_src_clk.c,
2852 .c = {
2853 .dbg_name = "csi1phy_timer_clk",
2854 .ops = &clk_ops_branch,
2855 CLK_INIT(csi1phy_timer_clk.c),
2856 },
2857};
2858
Stephen Boyd94625ef2011-07-12 17:06:01 -07002859static struct branch_clk csi2phy_timer_clk = {
2860 .b = {
2861 .ctl_reg = CSIPHYTIMER_CC_REG,
2862 .en_mask = BIT(11),
2863 .halt_reg = DBG_BUS_VEC_I_REG,
2864 .halt_bit = 30,
2865 },
2866 .parent = &csiphy_timer_src_clk.c,
2867 .c = {
2868 .dbg_name = "csi2phy_timer_clk",
2869 .ops = &clk_ops_branch,
2870 CLK_INIT(csi2phy_timer_clk.c),
2871 },
2872};
2873
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002874#define F_DSI(d) \
2875 { \
2876 .freq_hz = d, \
2877 .ns_val = BVAL(15, 12, (d-1)), \
2878 }
2879/*
2880 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
2881 * without this clock driver knowing. So, overload the clk_set_rate() to set
2882 * the divider (1 to 16) of the clock with respect to the PLL rate.
2883 */
2884static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
2885 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
2886 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
2887 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
2888 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
2889 F_END
2890};
2891
2892static struct rcg_clk dsi1_byte_clk = {
2893 .b = {
2894 .ctl_reg = DSI1_BYTE_CC_REG,
2895 .en_mask = BIT(0),
2896 .reset_reg = SW_RESET_CORE_REG,
2897 .reset_mask = BIT(7),
2898 .halt_reg = DBG_BUS_VEC_B_REG,
2899 .halt_bit = 21,
2900 },
2901 .ns_reg = DSI1_BYTE_NS_REG,
2902 .root_en_mask = BIT(2),
2903 .ns_mask = BM(15, 12),
2904 .set_rate = set_rate_nop,
2905 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002906 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002907 .c = {
2908 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002909 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002910 CLK_INIT(dsi1_byte_clk.c),
2911 },
2912};
2913
2914static struct rcg_clk dsi2_byte_clk = {
2915 .b = {
2916 .ctl_reg = DSI2_BYTE_CC_REG,
2917 .en_mask = BIT(0),
2918 .reset_reg = SW_RESET_CORE_REG,
2919 .reset_mask = BIT(25),
2920 .halt_reg = DBG_BUS_VEC_B_REG,
2921 .halt_bit = 20,
2922 },
2923 .ns_reg = DSI2_BYTE_NS_REG,
2924 .root_en_mask = BIT(2),
2925 .ns_mask = BM(15, 12),
2926 .set_rate = set_rate_nop,
2927 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002928 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002929 .c = {
2930 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002931 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002932 CLK_INIT(dsi2_byte_clk.c),
2933 },
2934};
2935
2936static struct rcg_clk dsi1_esc_clk = {
2937 .b = {
2938 .ctl_reg = DSI1_ESC_CC_REG,
2939 .en_mask = BIT(0),
2940 .reset_reg = SW_RESET_CORE_REG,
2941 .halt_reg = DBG_BUS_VEC_I_REG,
2942 .halt_bit = 1,
2943 },
2944 .ns_reg = DSI1_ESC_NS_REG,
2945 .root_en_mask = BIT(2),
2946 .ns_mask = BM(15, 12),
2947 .set_rate = set_rate_nop,
2948 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002949 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002950 .c = {
2951 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002952 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002953 CLK_INIT(dsi1_esc_clk.c),
2954 },
2955};
2956
2957static struct rcg_clk dsi2_esc_clk = {
2958 .b = {
2959 .ctl_reg = DSI2_ESC_CC_REG,
2960 .en_mask = BIT(0),
2961 .halt_reg = DBG_BUS_VEC_I_REG,
2962 .halt_bit = 3,
2963 },
2964 .ns_reg = DSI2_ESC_NS_REG,
2965 .root_en_mask = BIT(2),
2966 .ns_mask = BM(15, 12),
2967 .set_rate = set_rate_nop,
2968 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002969 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002970 .c = {
2971 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002972 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002973 CLK_INIT(dsi2_esc_clk.c),
2974 },
2975};
2976
2977#define F_GFX2D(f, s, m, n, v) \
2978 { \
2979 .freq_hz = f, \
2980 .src_clk = &s##_clk.c, \
2981 .md_val = MD4(4, m, 0, n), \
2982 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
2983 .ctl_val = CC_BANKED(9, 6, n), \
2984 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
2985 .sys_vdd = v, \
2986 }
2987static struct clk_freq_tbl clk_tbl_gfx2d[] = {
2988 F_GFX2D( 0, gnd, 0, 0, NONE),
2989 F_GFX2D( 27000000, pxo, 0, 0, LOW),
2990 F_GFX2D( 48000000, pll8, 1, 8, LOW),
2991 F_GFX2D( 54857000, pll8, 1, 7, LOW),
2992 F_GFX2D( 64000000, pll8, 1, 6, LOW),
2993 F_GFX2D( 76800000, pll8, 1, 5, LOW),
2994 F_GFX2D( 96000000, pll8, 1, 4, LOW),
2995 F_GFX2D(128000000, pll8, 1, 3, NOMINAL),
2996 F_GFX2D(145455000, pll2, 2, 11, NOMINAL),
2997 F_GFX2D(160000000, pll2, 1, 5, NOMINAL),
2998 F_GFX2D(177778000, pll2, 2, 9, NOMINAL),
2999 F_GFX2D(200000000, pll2, 1, 4, NOMINAL),
3000 F_GFX2D(228571000, pll2, 2, 7, HIGH),
3001 F_END
3002};
3003
3004static struct bank_masks bmnd_info_gfx2d0 = {
3005 .bank_sel_mask = BIT(11),
3006 .bank0_mask = {
3007 .md_reg = GFX2D0_MD0_REG,
3008 .ns_mask = BM(23, 20) | BM(5, 3),
3009 .rst_mask = BIT(25),
3010 .mnd_en_mask = BIT(8),
3011 .mode_mask = BM(10, 9),
3012 },
3013 .bank1_mask = {
3014 .md_reg = GFX2D0_MD1_REG,
3015 .ns_mask = BM(19, 16) | BM(2, 0),
3016 .rst_mask = BIT(24),
3017 .mnd_en_mask = BIT(5),
3018 .mode_mask = BM(7, 6),
3019 },
3020};
3021
3022static struct rcg_clk gfx2d0_clk = {
3023 .b = {
3024 .ctl_reg = GFX2D0_CC_REG,
3025 .en_mask = BIT(0),
3026 .reset_reg = SW_RESET_CORE_REG,
3027 .reset_mask = BIT(14),
3028 .halt_reg = DBG_BUS_VEC_A_REG,
3029 .halt_bit = 9,
3030 },
3031 .ns_reg = GFX2D0_NS_REG,
3032 .root_en_mask = BIT(2),
3033 .set_rate = set_rate_mnd_banked,
3034 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003035 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003036 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003037 .c = {
3038 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003039 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003040 CLK_INIT(gfx2d0_clk.c),
3041 },
3042};
3043
3044static struct bank_masks bmnd_info_gfx2d1 = {
3045 .bank_sel_mask = BIT(11),
3046 .bank0_mask = {
3047 .md_reg = GFX2D1_MD0_REG,
3048 .ns_mask = BM(23, 20) | BM(5, 3),
3049 .rst_mask = BIT(25),
3050 .mnd_en_mask = BIT(8),
3051 .mode_mask = BM(10, 9),
3052 },
3053 .bank1_mask = {
3054 .md_reg = GFX2D1_MD1_REG,
3055 .ns_mask = BM(19, 16) | BM(2, 0),
3056 .rst_mask = BIT(24),
3057 .mnd_en_mask = BIT(5),
3058 .mode_mask = BM(7, 6),
3059 },
3060};
3061
3062static struct rcg_clk gfx2d1_clk = {
3063 .b = {
3064 .ctl_reg = GFX2D1_CC_REG,
3065 .en_mask = BIT(0),
3066 .reset_reg = SW_RESET_CORE_REG,
3067 .reset_mask = BIT(13),
3068 .halt_reg = DBG_BUS_VEC_A_REG,
3069 .halt_bit = 14,
3070 },
3071 .ns_reg = GFX2D1_NS_REG,
3072 .root_en_mask = BIT(2),
3073 .set_rate = set_rate_mnd_banked,
3074 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003075 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003076 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003077 .c = {
3078 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003079 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003080 CLK_INIT(gfx2d1_clk.c),
3081 },
3082};
3083
3084#define F_GFX3D(f, s, m, n, v) \
3085 { \
3086 .freq_hz = f, \
3087 .src_clk = &s##_clk.c, \
3088 .md_val = MD4(4, m, 0, n), \
3089 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3090 .ctl_val = CC_BANKED(9, 6, n), \
3091 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3092 .sys_vdd = v, \
3093 }
3094static struct clk_freq_tbl clk_tbl_gfx3d[] = {
3095 F_GFX3D( 0, gnd, 0, 0, NONE),
3096 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3097 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3098 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3099 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3100 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3101 F_GFX3D( 96000000, pll8, 1, 4, LOW),
Stephen Boydd7797422011-08-10 16:01:45 -07003102 F_GFX3D(128000000, pll8, 1, 3, LOW),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003103 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3104 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3105 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3106 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3107 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3108 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
3109 F_GFX3D(320000000, pll2, 2, 5, HIGH),
3110 F_END
3111};
3112
Stephen Boyd94625ef2011-07-12 17:06:01 -07003113static struct clk_freq_tbl clk_tbl_gfx3d_v2[] = {
3114 F_GFX3D( 0, gnd, 0, 0, NONE),
3115 F_GFX3D( 27000000, pxo, 0, 0, LOW),
3116 F_GFX3D( 48000000, pll8, 1, 8, LOW),
3117 F_GFX3D( 54857000, pll8, 1, 7, LOW),
3118 F_GFX3D( 64000000, pll8, 1, 6, LOW),
3119 F_GFX3D( 76800000, pll8, 1, 5, LOW),
3120 F_GFX3D( 96000000, pll8, 1, 4, LOW),
3121 F_GFX3D(128000000, pll8, 1, 3, LOW),
3122 F_GFX3D(145455000, pll2, 2, 11, NOMINAL),
3123 F_GFX3D(160000000, pll2, 1, 5, NOMINAL),
3124 F_GFX3D(177778000, pll2, 2, 9, NOMINAL),
3125 F_GFX3D(200000000, pll2, 1, 4, NOMINAL),
3126 F_GFX3D(228571000, pll2, 2, 7, NOMINAL),
3127 F_GFX3D(266667000, pll2, 1, 3, NOMINAL),
3128 F_GFX3D(300000000, pll3, 1, 4, NOMINAL),
3129 F_GFX3D(320000000, pll2, 2, 5, HIGH),
3130 F_GFX3D(400000000, pll2, 1, 2, HIGH),
3131 F_END
3132};
3133
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003134static struct bank_masks bmnd_info_gfx3d = {
3135 .bank_sel_mask = BIT(11),
3136 .bank0_mask = {
3137 .md_reg = GFX3D_MD0_REG,
3138 .ns_mask = BM(21, 18) | BM(5, 3),
3139 .rst_mask = BIT(23),
3140 .mnd_en_mask = BIT(8),
3141 .mode_mask = BM(10, 9),
3142 },
3143 .bank1_mask = {
3144 .md_reg = GFX3D_MD1_REG,
3145 .ns_mask = BM(17, 14) | BM(2, 0),
3146 .rst_mask = BIT(22),
3147 .mnd_en_mask = BIT(5),
3148 .mode_mask = BM(7, 6),
3149 },
3150};
3151
3152static struct rcg_clk gfx3d_clk = {
3153 .b = {
3154 .ctl_reg = GFX3D_CC_REG,
3155 .en_mask = BIT(0),
3156 .reset_reg = SW_RESET_CORE_REG,
3157 .reset_mask = BIT(12),
3158 .halt_reg = DBG_BUS_VEC_A_REG,
3159 .halt_bit = 4,
3160 },
3161 .ns_reg = GFX3D_NS_REG,
3162 .root_en_mask = BIT(2),
3163 .set_rate = set_rate_mnd_banked,
3164 .freq_tbl = clk_tbl_gfx3d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003165 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003166 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003167 .c = {
3168 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003169 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003170 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003171 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003172 },
3173};
3174
3175#define F_IJPEG(f, s, d, m, n, v) \
3176 { \
3177 .freq_hz = f, \
3178 .src_clk = &s##_clk.c, \
3179 .md_val = MD8(8, m, 0, n), \
3180 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3181 .ctl_val = CC(6, n), \
3182 .mnd_en_mask = BIT(5) * !!(n), \
3183 .sys_vdd = v, \
3184 }
3185static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3186 F_IJPEG( 0, gnd, 1, 0, 0, NONE),
3187 F_IJPEG( 27000000, pxo, 1, 0, 0, LOW),
3188 F_IJPEG( 36570000, pll8, 1, 2, 21, LOW),
3189 F_IJPEG( 54860000, pll8, 7, 0, 0, LOW),
3190 F_IJPEG( 96000000, pll8, 4, 0, 0, LOW),
3191 F_IJPEG(109710000, pll8, 1, 2, 7, LOW),
3192 F_IJPEG(128000000, pll8, 3, 0, 0, NOMINAL),
3193 F_IJPEG(153600000, pll8, 1, 2, 5, NOMINAL),
3194 F_IJPEG(200000000, pll2, 4, 0, 0, NOMINAL),
3195 F_IJPEG(228571000, pll2, 1, 2, 7, NOMINAL),
Matt Wagantall393bdb52011-09-07 10:15:28 -07003196 F_IJPEG(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003197 F_IJPEG(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003198 F_END
3199};
3200
3201static struct rcg_clk ijpeg_clk = {
3202 .b = {
3203 .ctl_reg = IJPEG_CC_REG,
3204 .en_mask = BIT(0),
3205 .reset_reg = SW_RESET_CORE_REG,
3206 .reset_mask = BIT(9),
3207 .halt_reg = DBG_BUS_VEC_A_REG,
3208 .halt_bit = 24,
3209 },
3210 .ns_reg = IJPEG_NS_REG,
3211 .md_reg = IJPEG_MD_REG,
3212 .root_en_mask = BIT(2),
3213 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
3214 .ctl_mask = BM(7, 6),
3215 .set_rate = set_rate_mnd,
3216 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003217 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003218 .c = {
3219 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003220 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003221 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003222 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003223 },
3224};
3225
3226#define F_JPEGD(f, s, d, v) \
3227 { \
3228 .freq_hz = f, \
3229 .src_clk = &s##_clk.c, \
3230 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
3231 .sys_vdd = v, \
3232 }
3233static struct clk_freq_tbl clk_tbl_jpegd[] = {
3234 F_JPEGD( 0, gnd, 1, NONE),
3235 F_JPEGD( 64000000, pll8, 6, LOW),
3236 F_JPEGD( 76800000, pll8, 5, LOW),
3237 F_JPEGD( 96000000, pll8, 4, LOW),
3238 F_JPEGD(160000000, pll2, 5, NOMINAL),
3239 F_JPEGD(200000000, pll2, 4, NOMINAL),
3240 F_END
3241};
3242
3243static struct rcg_clk jpegd_clk = {
3244 .b = {
3245 .ctl_reg = JPEGD_CC_REG,
3246 .en_mask = BIT(0),
3247 .reset_reg = SW_RESET_CORE_REG,
3248 .reset_mask = BIT(19),
3249 .halt_reg = DBG_BUS_VEC_A_REG,
3250 .halt_bit = 19,
3251 },
3252 .ns_reg = JPEGD_NS_REG,
3253 .root_en_mask = BIT(2),
3254 .ns_mask = (BM(15, 12) | BM(2, 0)),
3255 .set_rate = set_rate_nop,
3256 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003257 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003258 .c = {
3259 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003260 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003261 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003262 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003263 },
3264};
3265
3266#define F_MDP(f, s, m, n, v) \
3267 { \
3268 .freq_hz = f, \
3269 .src_clk = &s##_clk.c, \
3270 .md_val = MD8(8, m, 0, n), \
3271 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3272 .ctl_val = CC_BANKED(9, 6, n), \
3273 .mnd_en_mask = (BIT(8) | BIT(5)) * !!(n), \
3274 .sys_vdd = v, \
3275 }
3276static struct clk_freq_tbl clk_tbl_mdp[] = {
3277 F_MDP( 0, gnd, 0, 0, NONE),
3278 F_MDP( 9600000, pll8, 1, 40, LOW),
3279 F_MDP( 13710000, pll8, 1, 28, LOW),
3280 F_MDP( 27000000, pxo, 0, 0, LOW),
3281 F_MDP( 29540000, pll8, 1, 13, LOW),
3282 F_MDP( 34910000, pll8, 1, 11, LOW),
3283 F_MDP( 38400000, pll8, 1, 10, LOW),
3284 F_MDP( 59080000, pll8, 2, 13, LOW),
3285 F_MDP( 76800000, pll8, 1, 5, LOW),
3286 F_MDP( 85330000, pll8, 2, 9, LOW),
3287 F_MDP( 96000000, pll8, 1, 4, NOMINAL),
3288 F_MDP(128000000, pll8, 1, 3, NOMINAL),
3289 F_MDP(160000000, pll2, 1, 5, NOMINAL),
3290 F_MDP(177780000, pll2, 2, 9, NOMINAL),
3291 F_MDP(200000000, pll2, 1, 4, NOMINAL),
3292 F_END
3293};
3294
3295static struct bank_masks bmnd_info_mdp = {
3296 .bank_sel_mask = BIT(11),
3297 .bank0_mask = {
3298 .md_reg = MDP_MD0_REG,
3299 .ns_mask = BM(29, 22) | BM(5, 3),
3300 .rst_mask = BIT(31),
3301 .mnd_en_mask = BIT(8),
3302 .mode_mask = BM(10, 9),
3303 },
3304 .bank1_mask = {
3305 .md_reg = MDP_MD1_REG,
3306 .ns_mask = BM(21, 14) | BM(2, 0),
3307 .rst_mask = BIT(30),
3308 .mnd_en_mask = BIT(5),
3309 .mode_mask = BM(7, 6),
3310 },
3311};
3312
3313static struct rcg_clk mdp_clk = {
3314 .b = {
3315 .ctl_reg = MDP_CC_REG,
3316 .en_mask = BIT(0),
3317 .reset_reg = SW_RESET_CORE_REG,
3318 .reset_mask = BIT(21),
3319 .halt_reg = DBG_BUS_VEC_C_REG,
3320 .halt_bit = 10,
3321 },
3322 .ns_reg = MDP_NS_REG,
3323 .root_en_mask = BIT(2),
3324 .set_rate = set_rate_mnd_banked,
3325 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003326 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003327 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003328 .c = {
3329 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003330 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003331 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003332 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003333 },
3334};
3335
3336static struct branch_clk lut_mdp_clk = {
3337 .b = {
3338 .ctl_reg = MDP_LUT_CC_REG,
3339 .en_mask = BIT(0),
3340 .halt_reg = DBG_BUS_VEC_I_REG,
3341 .halt_bit = 13,
3342 },
3343 .parent = &mdp_clk.c,
3344 .c = {
3345 .dbg_name = "lut_mdp_clk",
3346 .ops = &clk_ops_branch,
3347 CLK_INIT(lut_mdp_clk.c),
3348 },
3349};
3350
3351#define F_MDP_VSYNC(f, s, v) \
3352 { \
3353 .freq_hz = f, \
3354 .src_clk = &s##_clk.c, \
3355 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
3356 .sys_vdd = v, \
3357 }
3358static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
3359 F_MDP_VSYNC(27000000, pxo, LOW),
3360 F_END
3361};
3362
3363static struct rcg_clk mdp_vsync_clk = {
3364 .b = {
3365 .ctl_reg = MISC_CC_REG,
3366 .en_mask = BIT(6),
3367 .reset_reg = SW_RESET_CORE_REG,
3368 .reset_mask = BIT(3),
3369 .halt_reg = DBG_BUS_VEC_B_REG,
3370 .halt_bit = 22,
3371 },
3372 .ns_reg = MISC_CC2_REG,
3373 .ns_mask = BIT(13),
3374 .set_rate = set_rate_nop,
3375 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003376 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003377 .c = {
3378 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003379 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003380 CLK_INIT(mdp_vsync_clk.c),
3381 },
3382};
3383
3384#define F_ROT(f, s, d, v) \
3385 { \
3386 .freq_hz = f, \
3387 .src_clk = &s##_clk.c, \
3388 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3389 21, 19, 18, 16, s##_to_mm_mux), \
3390 .sys_vdd = v, \
3391 }
3392static struct clk_freq_tbl clk_tbl_rot[] = {
3393 F_ROT( 0, gnd, 1, NONE),
3394 F_ROT( 27000000, pxo, 1, LOW),
3395 F_ROT( 29540000, pll8, 13, LOW),
3396 F_ROT( 32000000, pll8, 12, LOW),
3397 F_ROT( 38400000, pll8, 10, LOW),
3398 F_ROT( 48000000, pll8, 8, LOW),
3399 F_ROT( 54860000, pll8, 7, LOW),
3400 F_ROT( 64000000, pll8, 6, LOW),
3401 F_ROT( 76800000, pll8, 5, LOW),
3402 F_ROT( 96000000, pll8, 4, NOMINAL),
3403 F_ROT(100000000, pll2, 8, NOMINAL),
3404 F_ROT(114290000, pll2, 7, NOMINAL),
3405 F_ROT(133330000, pll2, 6, NOMINAL),
3406 F_ROT(160000000, pll2, 5, NOMINAL),
Stephen Boyd8487f712011-08-29 12:10:09 -07003407 F_ROT(200000000, pll2, 4, NOMINAL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003408 F_END
3409};
3410
3411static struct bank_masks bdiv_info_rot = {
3412 .bank_sel_mask = BIT(30),
3413 .bank0_mask = {
3414 .ns_mask = BM(25, 22) | BM(18, 16),
3415 },
3416 .bank1_mask = {
3417 .ns_mask = BM(29, 26) | BM(21, 19),
3418 },
3419};
3420
3421static struct rcg_clk rot_clk = {
3422 .b = {
3423 .ctl_reg = ROT_CC_REG,
3424 .en_mask = BIT(0),
3425 .reset_reg = SW_RESET_CORE_REG,
3426 .reset_mask = BIT(2),
3427 .halt_reg = DBG_BUS_VEC_C_REG,
3428 .halt_bit = 15,
3429 },
3430 .ns_reg = ROT_NS_REG,
3431 .root_en_mask = BIT(2),
3432 .set_rate = set_rate_div_banked,
3433 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003434 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003435 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003436 .c = {
3437 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003438 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003439 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003440 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003441 },
3442};
3443
3444static int hdmi_pll_clk_enable(struct clk *clk)
3445{
3446 int ret;
3447 unsigned long flags;
3448 spin_lock_irqsave(&local_clock_reg_lock, flags);
3449 ret = hdmi_pll_enable();
3450 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3451 return ret;
3452}
3453
3454static void hdmi_pll_clk_disable(struct clk *clk)
3455{
3456 unsigned long flags;
3457 spin_lock_irqsave(&local_clock_reg_lock, flags);
3458 hdmi_pll_disable();
3459 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3460}
3461
3462static unsigned hdmi_pll_clk_get_rate(struct clk *clk)
3463{
3464 return hdmi_pll_get_rate();
3465}
3466
3467static struct clk_ops clk_ops_hdmi_pll = {
3468 .enable = hdmi_pll_clk_enable,
3469 .disable = hdmi_pll_clk_disable,
3470 .get_rate = hdmi_pll_clk_get_rate,
3471 .is_local = local_clk_is_local,
3472};
3473
3474static struct clk hdmi_pll_clk = {
3475 .dbg_name = "hdmi_pll_clk",
3476 .ops = &clk_ops_hdmi_pll,
3477 CLK_INIT(hdmi_pll_clk),
3478};
3479
3480#define F_TV_GND(f, s, p_r, d, m, n, v) \
3481 { \
3482 .freq_hz = f, \
3483 .src_clk = &s##_clk.c, \
3484 .md_val = MD8(8, m, 0, n), \
3485 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3486 .ctl_val = CC(6, n), \
3487 .mnd_en_mask = BIT(5) * !!(n), \
3488 .sys_vdd = v, \
3489 }
3490#define F_TV(f, s, p_r, d, m, n, v) \
3491 { \
3492 .freq_hz = f, \
3493 .src_clk = &s##_clk, \
3494 .md_val = MD8(8, m, 0, n), \
3495 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3496 .ctl_val = CC(6, n), \
3497 .mnd_en_mask = BIT(5) * !!(n), \
3498 .sys_vdd = v, \
3499 .extra_freq_data = (void *)p_r, \
3500 }
3501/* Switching TV freqs requires PLL reconfiguration. */
3502static struct clk_freq_tbl clk_tbl_tv[] = {
3503 F_TV_GND( 0, gnd, 0, 1, 0, 0, NONE),
3504 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0, LOW),
3505 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0, LOW),
3506 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0, LOW),
3507 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0, NOMINAL),
3508 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0, NOMINAL),
3509 F_END
3510};
3511
3512/*
3513 * Unlike other clocks, the TV rate is adjusted through PLL
3514 * re-programming. It is also routed through an MND divider.
3515 */
3516void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3517{
3518 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3519 if (pll_rate)
3520 hdmi_pll_set_rate(pll_rate);
3521 set_rate_mnd(clk, nf);
3522}
3523
3524static struct rcg_clk tv_src_clk = {
3525 .ns_reg = TV_NS_REG,
3526 .b = {
3527 .ctl_reg = TV_CC_REG,
3528 .halt_check = NOCHECK,
3529 },
3530 .md_reg = TV_MD_REG,
3531 .root_en_mask = BIT(2),
3532 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
3533 .ctl_mask = BM(7, 6),
3534 .set_rate = set_rate_tv,
3535 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003536 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003537 .c = {
3538 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003539 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003540 CLK_INIT(tv_src_clk.c),
3541 },
3542};
3543
3544static struct branch_clk tv_enc_clk = {
3545 .b = {
3546 .ctl_reg = TV_CC_REG,
3547 .en_mask = BIT(8),
3548 .reset_reg = SW_RESET_CORE_REG,
3549 .reset_mask = BIT(0),
3550 .halt_reg = DBG_BUS_VEC_D_REG,
3551 .halt_bit = 9,
3552 },
3553 .parent = &tv_src_clk.c,
3554 .c = {
3555 .dbg_name = "tv_enc_clk",
3556 .ops = &clk_ops_branch,
3557 CLK_INIT(tv_enc_clk.c),
3558 },
3559};
3560
3561static struct branch_clk tv_dac_clk = {
3562 .b = {
3563 .ctl_reg = TV_CC_REG,
3564 .en_mask = BIT(10),
3565 .halt_reg = DBG_BUS_VEC_D_REG,
3566 .halt_bit = 10,
3567 },
3568 .parent = &tv_src_clk.c,
3569 .c = {
3570 .dbg_name = "tv_dac_clk",
3571 .ops = &clk_ops_branch,
3572 CLK_INIT(tv_dac_clk.c),
3573 },
3574};
3575
3576static struct branch_clk mdp_tv_clk = {
3577 .b = {
3578 .ctl_reg = TV_CC_REG,
3579 .en_mask = BIT(0),
3580 .reset_reg = SW_RESET_CORE_REG,
3581 .reset_mask = BIT(4),
3582 .halt_reg = DBG_BUS_VEC_D_REG,
3583 .halt_bit = 12,
3584 },
3585 .parent = &tv_src_clk.c,
3586 .c = {
3587 .dbg_name = "mdp_tv_clk",
3588 .ops = &clk_ops_branch,
3589 CLK_INIT(mdp_tv_clk.c),
3590 },
3591};
3592
3593static struct branch_clk hdmi_tv_clk = {
3594 .b = {
3595 .ctl_reg = TV_CC_REG,
3596 .en_mask = BIT(12),
3597 .reset_reg = SW_RESET_CORE_REG,
3598 .reset_mask = BIT(1),
3599 .halt_reg = DBG_BUS_VEC_D_REG,
3600 .halt_bit = 11,
3601 },
3602 .parent = &tv_src_clk.c,
3603 .c = {
3604 .dbg_name = "hdmi_tv_clk",
3605 .ops = &clk_ops_branch,
3606 CLK_INIT(hdmi_tv_clk.c),
3607 },
3608};
3609
3610static struct branch_clk hdmi_app_clk = {
3611 .b = {
3612 .ctl_reg = MISC_CC2_REG,
3613 .en_mask = BIT(11),
3614 .reset_reg = SW_RESET_CORE_REG,
3615 .reset_mask = BIT(11),
3616 .halt_reg = DBG_BUS_VEC_B_REG,
3617 .halt_bit = 25,
3618 },
3619 .c = {
3620 .dbg_name = "hdmi_app_clk",
3621 .ops = &clk_ops_branch,
3622 CLK_INIT(hdmi_app_clk.c),
3623 },
3624};
3625
3626static struct bank_masks bmnd_info_vcodec = {
3627 .bank_sel_mask = BIT(13),
3628 .bank0_mask = {
3629 .md_reg = VCODEC_MD0_REG,
3630 .ns_mask = BM(18, 11) | BM(2, 0),
3631 .rst_mask = BIT(31),
3632 .mnd_en_mask = BIT(5),
3633 .mode_mask = BM(7, 6),
3634 },
3635 .bank1_mask = {
3636 .md_reg = VCODEC_MD1_REG,
3637 .ns_mask = BM(26, 19) | BM(29, 27),
3638 .rst_mask = BIT(30),
3639 .mnd_en_mask = BIT(10),
3640 .mode_mask = BM(12, 11),
3641 },
3642};
3643#define F_VCODEC(f, s, m, n, v) \
3644 { \
3645 .freq_hz = f, \
3646 .src_clk = &s##_clk.c, \
3647 .md_val = MD8(8, m, 0, n), \
3648 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
3649 .ctl_val = CC_BANKED(6, 11, n), \
3650 .mnd_en_mask = (BIT(10) | BIT(5)) * !!(n), \
3651 .sys_vdd = v, \
3652 }
3653static struct clk_freq_tbl clk_tbl_vcodec[] = {
3654 F_VCODEC( 0, gnd, 0, 0, NONE),
3655 F_VCODEC( 27000000, pxo, 0, 0, LOW),
3656 F_VCODEC( 32000000, pll8, 1, 12, LOW),
3657 F_VCODEC( 48000000, pll8, 1, 8, LOW),
3658 F_VCODEC( 54860000, pll8, 1, 7, LOW),
3659 F_VCODEC( 96000000, pll8, 1, 4, LOW),
3660 F_VCODEC(133330000, pll2, 1, 6, NOMINAL),
3661 F_VCODEC(200000000, pll2, 1, 4, NOMINAL),
3662 F_VCODEC(228570000, pll2, 2, 7, HIGH),
3663 F_END
3664};
3665
3666static struct rcg_clk vcodec_clk = {
3667 .b = {
3668 .ctl_reg = VCODEC_CC_REG,
3669 .en_mask = BIT(0),
3670 .reset_reg = SW_RESET_CORE_REG,
3671 .reset_mask = BIT(6),
3672 .halt_reg = DBG_BUS_VEC_C_REG,
3673 .halt_bit = 29,
3674 },
3675 .ns_reg = VCODEC_NS_REG,
3676 .root_en_mask = BIT(2),
3677 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003678 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003679 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003680 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003681 .c = {
3682 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003683 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003684 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003685 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003686 },
3687};
3688
3689#define F_VPE(f, s, d, v) \
3690 { \
3691 .freq_hz = f, \
3692 .src_clk = &s##_clk.c, \
3693 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
3694 .sys_vdd = v, \
3695 }
3696static struct clk_freq_tbl clk_tbl_vpe[] = {
3697 F_VPE( 0, gnd, 1, NONE),
3698 F_VPE( 27000000, pxo, 1, LOW),
3699 F_VPE( 34909000, pll8, 11, LOW),
3700 F_VPE( 38400000, pll8, 10, LOW),
3701 F_VPE( 64000000, pll8, 6, LOW),
3702 F_VPE( 76800000, pll8, 5, LOW),
3703 F_VPE( 96000000, pll8, 4, NOMINAL),
3704 F_VPE(100000000, pll2, 8, NOMINAL),
3705 F_VPE(160000000, pll2, 5, NOMINAL),
3706 F_END
3707};
3708
3709static struct rcg_clk vpe_clk = {
3710 .b = {
3711 .ctl_reg = VPE_CC_REG,
3712 .en_mask = BIT(0),
3713 .reset_reg = SW_RESET_CORE_REG,
3714 .reset_mask = BIT(17),
3715 .halt_reg = DBG_BUS_VEC_A_REG,
3716 .halt_bit = 28,
3717 },
3718 .ns_reg = VPE_NS_REG,
3719 .root_en_mask = BIT(2),
3720 .ns_mask = (BM(15, 12) | BM(2, 0)),
3721 .set_rate = set_rate_nop,
3722 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003723 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003724 .c = {
3725 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003726 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003727 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003728 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003729 },
3730};
3731
3732#define F_VFE(f, s, d, m, n, v) \
3733 { \
3734 .freq_hz = f, \
3735 .src_clk = &s##_clk.c, \
3736 .md_val = MD8(8, m, 0, n), \
3737 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
3738 .ctl_val = CC(6, n), \
3739 .mnd_en_mask = BIT(5) * !!(n), \
3740 .sys_vdd = v, \
3741 }
3742static struct clk_freq_tbl clk_tbl_vfe[] = {
3743 F_VFE( 0, gnd, 1, 0, 0, NONE),
3744 F_VFE( 13960000, pll8, 1, 2, 55, LOW),
3745 F_VFE( 27000000, pxo, 1, 0, 0, LOW),
3746 F_VFE( 36570000, pll8, 1, 2, 21, LOW),
3747 F_VFE( 38400000, pll8, 2, 1, 5, LOW),
3748 F_VFE( 45180000, pll8, 1, 2, 17, LOW),
3749 F_VFE( 48000000, pll8, 2, 1, 4, LOW),
3750 F_VFE( 54860000, pll8, 1, 1, 7, LOW),
3751 F_VFE( 64000000, pll8, 2, 1, 3, LOW),
3752 F_VFE( 76800000, pll8, 1, 1, 5, LOW),
3753 F_VFE( 96000000, pll8, 2, 1, 2, LOW),
3754 F_VFE(109710000, pll8, 1, 2, 7, LOW),
3755 F_VFE(128000000, pll8, 1, 1, 3, NOMINAL),
3756 F_VFE(153600000, pll8, 1, 2, 5, NOMINAL),
3757 F_VFE(200000000, pll2, 2, 1, 2, NOMINAL),
3758 F_VFE(228570000, pll2, 1, 2, 7, NOMINAL),
3759 F_VFE(266667000, pll2, 1, 1, 3, NOMINAL),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003760 F_VFE(320000000, pll2, 1, 2, 5, HIGH),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003761 F_END
3762};
3763
3764
3765static struct rcg_clk vfe_clk = {
3766 .b = {
3767 .ctl_reg = VFE_CC_REG,
3768 .reset_reg = SW_RESET_CORE_REG,
3769 .reset_mask = BIT(15),
3770 .halt_reg = DBG_BUS_VEC_B_REG,
3771 .halt_bit = 6,
3772 .en_mask = BIT(0),
3773 },
3774 .ns_reg = VFE_NS_REG,
3775 .md_reg = VFE_MD_REG,
3776 .root_en_mask = BIT(2),
3777 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
3778 .ctl_mask = BM(7, 6),
3779 .set_rate = set_rate_mnd,
3780 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003781 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003782 .c = {
3783 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003784 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003785 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003786 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003787 },
3788};
3789
Matt Wagantallc23eee92011-08-16 23:06:52 -07003790static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003791 .b = {
3792 .ctl_reg = VFE_CC_REG,
3793 .en_mask = BIT(12),
3794 .reset_reg = SW_RESET_CORE_REG,
3795 .reset_mask = BIT(24),
3796 .halt_reg = DBG_BUS_VEC_B_REG,
3797 .halt_bit = 8,
3798 },
3799 .parent = &vfe_clk.c,
3800 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07003801 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003802 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07003803 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003804 },
3805};
3806
3807/*
3808 * Low Power Audio Clocks
3809 */
3810#define F_AIF_OSR(f, s, d, m, n, v) \
3811 { \
3812 .freq_hz = f, \
3813 .src_clk = &s##_clk.c, \
3814 .md_val = MD8(8, m, 0, n), \
3815 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
3816 .mnd_en_mask = BIT(8) * !!(n), \
3817 .sys_vdd = v, \
3818 }
3819static struct clk_freq_tbl clk_tbl_aif_osr[] = {
3820 F_AIF_OSR( 0, gnd, 1, 0, 0, NONE),
3821 F_AIF_OSR( 768000, pll4, 4, 1, 128, LOW),
3822 F_AIF_OSR( 1024000, pll4, 4, 1, 96, LOW),
3823 F_AIF_OSR( 1536000, pll4, 4, 1, 64, LOW),
3824 F_AIF_OSR( 2048000, pll4, 4, 1, 48, LOW),
3825 F_AIF_OSR( 3072000, pll4, 4, 1, 32, LOW),
3826 F_AIF_OSR( 4096000, pll4, 4, 1, 24, LOW),
3827 F_AIF_OSR( 6144000, pll4, 4, 1, 16, LOW),
3828 F_AIF_OSR( 8192000, pll4, 4, 1, 12, LOW),
3829 F_AIF_OSR(12288000, pll4, 4, 1, 8, LOW),
3830 F_AIF_OSR(24576000, pll4, 4, 1, 4, LOW),
3831 F_END
3832};
3833
3834#define CLK_AIF_OSR(i, ns, md, h_r) \
3835 struct rcg_clk i##_clk = { \
3836 .b = { \
3837 .ctl_reg = ns, \
3838 .en_mask = BIT(17), \
3839 .reset_reg = ns, \
3840 .reset_mask = BIT(19), \
3841 .halt_reg = h_r, \
3842 .halt_check = ENABLE, \
3843 .halt_bit = 1, \
3844 }, \
3845 .ns_reg = ns, \
3846 .md_reg = md, \
3847 .root_en_mask = BIT(9), \
3848 .ns_mask = (BM(31, 24) | BM(6, 0)), \
3849 .set_rate = set_rate_mnd, \
3850 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003851 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003852 .c = { \
3853 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003854 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003855 CLK_INIT(i##_clk.c), \
3856 }, \
3857 }
3858#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
3859 struct rcg_clk i##_clk = { \
3860 .b = { \
3861 .ctl_reg = ns, \
3862 .en_mask = BIT(21), \
3863 .reset_reg = ns, \
3864 .reset_mask = BIT(23), \
3865 .halt_reg = h_r, \
3866 .halt_check = ENABLE, \
3867 .halt_bit = 1, \
3868 }, \
3869 .ns_reg = ns, \
3870 .md_reg = md, \
3871 .root_en_mask = BIT(9), \
3872 .ns_mask = (BM(31, 24) | BM(6, 0)), \
3873 .set_rate = set_rate_mnd, \
3874 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003875 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003876 .c = { \
3877 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003878 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003879 CLK_INIT(i##_clk.c), \
3880 }, \
3881 }
3882
3883#define F_AIF_BIT(d, s) \
3884 { \
3885 .freq_hz = d, \
3886 .ns_val = (BVAL(14, 14, s) | BVAL(13, 10, (d-1))) \
3887 }
3888static struct clk_freq_tbl clk_tbl_aif_bit[] = {
3889 F_AIF_BIT(0, 1), /* Use external clock. */
3890 F_AIF_BIT(1, 0), F_AIF_BIT(2, 0), F_AIF_BIT(3, 0), F_AIF_BIT(4, 0),
3891 F_AIF_BIT(5, 0), F_AIF_BIT(6, 0), F_AIF_BIT(7, 0), F_AIF_BIT(8, 0),
3892 F_AIF_BIT(9, 0), F_AIF_BIT(10, 0), F_AIF_BIT(11, 0), F_AIF_BIT(12, 0),
3893 F_AIF_BIT(13, 0), F_AIF_BIT(14, 0), F_AIF_BIT(15, 0), F_AIF_BIT(16, 0),
3894 F_END
3895};
3896
3897#define CLK_AIF_BIT(i, ns, h_r) \
3898 struct rcg_clk i##_clk = { \
3899 .b = { \
3900 .ctl_reg = ns, \
3901 .en_mask = BIT(15), \
3902 .halt_reg = h_r, \
3903 .halt_check = DELAY, \
3904 }, \
3905 .ns_reg = ns, \
3906 .ns_mask = BM(14, 10), \
3907 .set_rate = set_rate_nop, \
3908 .freq_tbl = clk_tbl_aif_bit, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003909 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003910 .c = { \
3911 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003912 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003913 CLK_INIT(i##_clk.c), \
3914 }, \
3915 }
3916
3917#define F_AIF_BIT_D(d, s) \
3918 { \
3919 .freq_hz = d, \
3920 .ns_val = (BVAL(18, 18, s) | BVAL(17, 10, (d-1))) \
3921 }
3922static struct clk_freq_tbl clk_tbl_aif_bit_div[] = {
3923 F_AIF_BIT_D(0, 1), /* Use external clock. */
3924 F_AIF_BIT_D(1, 0), F_AIF_BIT_D(2, 0), F_AIF_BIT_D(3, 0),
3925 F_AIF_BIT_D(4, 0), F_AIF_BIT_D(5, 0), F_AIF_BIT_D(6, 0),
3926 F_AIF_BIT_D(7, 0), F_AIF_BIT_D(8, 0), F_AIF_BIT_D(9, 0),
3927 F_AIF_BIT_D(10, 0), F_AIF_BIT_D(11, 0), F_AIF_BIT_D(12, 0),
3928 F_AIF_BIT_D(13, 0), F_AIF_BIT_D(14, 0), F_AIF_BIT_D(15, 0),
3929 F_AIF_BIT_D(16, 0),
3930 F_END
3931};
3932
3933#define CLK_AIF_BIT_DIV(i, ns, h_r) \
3934 struct rcg_clk i##_clk = { \
3935 .b = { \
3936 .ctl_reg = ns, \
3937 .en_mask = BIT(19), \
3938 .halt_reg = h_r, \
3939 .halt_check = ENABLE, \
3940 }, \
3941 .ns_reg = ns, \
3942 .ns_mask = BM(18, 10), \
3943 .set_rate = set_rate_nop, \
3944 .freq_tbl = clk_tbl_aif_bit_div, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003945 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003946 .c = { \
3947 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003948 .ops = &clk_ops_rcg_8960, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003949 CLK_INIT(i##_clk.c), \
3950 }, \
3951 }
3952
3953static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
3954 LCC_MI2S_STATUS_REG);
3955static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
3956
3957static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
3958 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
3959static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
3960 LCC_CODEC_I2S_MIC_STATUS_REG);
3961
3962static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
3963 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
3964static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
3965 LCC_SPARE_I2S_MIC_STATUS_REG);
3966
3967static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
3968 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
3969static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
3970 LCC_CODEC_I2S_SPKR_STATUS_REG);
3971
3972static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
3973 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
3974static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
3975 LCC_SPARE_I2S_SPKR_STATUS_REG);
3976
3977#define F_PCM(f, s, d, m, n, v) \
3978 { \
3979 .freq_hz = f, \
3980 .src_clk = &s##_clk.c, \
3981 .md_val = MD16(m, n), \
3982 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
3983 .mnd_en_mask = BIT(8) * !!(n), \
3984 .sys_vdd = v, \
3985 }
3986static struct clk_freq_tbl clk_tbl_pcm[] = {
3987 F_PCM( 0, gnd, 1, 0, 0, NONE),
3988 F_PCM( 512000, pll4, 4, 1, 192, LOW),
3989 F_PCM( 768000, pll4, 4, 1, 128, LOW),
3990 F_PCM( 1024000, pll4, 4, 1, 96, LOW),
3991 F_PCM( 1536000, pll4, 4, 1, 64, LOW),
3992 F_PCM( 2048000, pll4, 4, 1, 48, LOW),
3993 F_PCM( 3072000, pll4, 4, 1, 32, LOW),
3994 F_PCM( 4096000, pll4, 4, 1, 24, LOW),
3995 F_PCM( 6144000, pll4, 4, 1, 16, LOW),
3996 F_PCM( 8192000, pll4, 4, 1, 12, LOW),
3997 F_PCM(12288000, pll4, 4, 1, 8, LOW),
3998 F_PCM(24576000, pll4, 4, 1, 4, LOW),
3999 F_END
4000};
4001
4002static struct rcg_clk pcm_clk = {
4003 .b = {
4004 .ctl_reg = LCC_PCM_NS_REG,
4005 .en_mask = BIT(11),
4006 .reset_reg = LCC_PCM_NS_REG,
4007 .reset_mask = BIT(13),
4008 .halt_reg = LCC_PCM_STATUS_REG,
4009 .halt_check = ENABLE,
4010 .halt_bit = 0,
4011 },
4012 .ns_reg = LCC_PCM_NS_REG,
4013 .md_reg = LCC_PCM_MD_REG,
4014 .root_en_mask = BIT(9),
4015 .ns_mask = (BM(31, 16) | BM(6, 0)),
4016 .set_rate = set_rate_mnd,
4017 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004018 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004019 .c = {
4020 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004021 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004022 CLK_INIT(pcm_clk.c),
4023 },
4024};
4025
4026static struct rcg_clk audio_slimbus_clk = {
4027 .b = {
4028 .ctl_reg = LCC_SLIMBUS_NS_REG,
4029 .en_mask = BIT(10),
4030 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4031 .reset_mask = BIT(5),
4032 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4033 .halt_check = ENABLE,
4034 .halt_bit = 0,
4035 },
4036 .ns_reg = LCC_SLIMBUS_NS_REG,
4037 .md_reg = LCC_SLIMBUS_MD_REG,
4038 .root_en_mask = BIT(9),
4039 .ns_mask = (BM(31, 24) | BM(6, 0)),
4040 .set_rate = set_rate_mnd,
4041 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004042 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004043 .c = {
4044 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004045 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004046 CLK_INIT(audio_slimbus_clk.c),
4047 },
4048};
4049
4050static struct branch_clk sps_slimbus_clk = {
4051 .b = {
4052 .ctl_reg = LCC_SLIMBUS_NS_REG,
4053 .en_mask = BIT(12),
4054 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4055 .halt_check = ENABLE,
4056 .halt_bit = 1,
4057 },
4058 .parent = &audio_slimbus_clk.c,
4059 .c = {
4060 .dbg_name = "sps_slimbus_clk",
4061 .ops = &clk_ops_branch,
4062 CLK_INIT(sps_slimbus_clk.c),
4063 },
4064};
4065
4066static struct branch_clk slimbus_xo_src_clk = {
4067 .b = {
4068 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4069 .en_mask = BIT(2),
4070 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004071 .halt_bit = 28,
4072 },
4073 .parent = &sps_slimbus_clk.c,
4074 .c = {
4075 .dbg_name = "slimbus_xo_src_clk",
4076 .ops = &clk_ops_branch,
4077 CLK_INIT(slimbus_xo_src_clk.c),
4078 },
4079};
4080
Matt Wagantall735f01a2011-08-12 12:40:28 -07004081DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4082DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4083DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4084DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4085DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4086DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4087DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4088DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004089
4090static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4091static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
4092static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4093static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4094static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4095static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4096static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4097static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
4098
4099static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
4100/*
4101 * TODO: replace dummy_clk below with ebi1_clk.c once the
4102 * bus driver starts voting on ebi1 rates.
4103 */
4104static DEFINE_CLK_VOTER(ebi1_adm_clk, &dummy_clk);
4105
4106#ifdef CONFIG_DEBUG_FS
4107struct measure_sel {
4108 u32 test_vector;
4109 struct clk *clk;
4110};
4111
Matt Wagantall8b38f942011-08-02 18:23:18 -07004112static DEFINE_CLK_MEASURE(l2_m_clk);
4113static DEFINE_CLK_MEASURE(krait0_m_clk);
4114static DEFINE_CLK_MEASURE(krait1_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004115static DEFINE_CLK_MEASURE(q6sw_clk);
4116static DEFINE_CLK_MEASURE(q6fw_clk);
4117static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004118
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004119static struct measure_sel measure_mux[] = {
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004120 { TEST_PER_LS(0x05), &qdss_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004121 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4122 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4123 { TEST_PER_LS(0x13), &sdc1_clk.c },
4124 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4125 { TEST_PER_LS(0x15), &sdc2_clk.c },
4126 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4127 { TEST_PER_LS(0x17), &sdc3_clk.c },
4128 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4129 { TEST_PER_LS(0x19), &sdc4_clk.c },
4130 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4131 { TEST_PER_LS(0x1B), &sdc5_clk.c },
4132 { TEST_PER_LS(0x25), &dfab_clk.c },
4133 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4134 { TEST_PER_LS(0x26), &pmem_clk.c },
4135 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4136 { TEST_PER_LS(0x33), &cfpb_clk.c },
4137 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4138 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4139 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4140 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4141 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4142 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4143 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4144 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4145 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4146 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4147 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4148 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4149 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4150 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4151 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4152 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4153 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4154 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4155 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4156 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4157 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4158 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4159 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4160 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4161 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4162 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4163 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4164 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4165 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4166 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4167 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4168 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4169 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4170 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4171 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4172 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4173 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
4174 { TEST_PER_LS(0x78), &sfpb_clk.c },
4175 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4176 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4177 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4178 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4179 { TEST_PER_LS(0x7D), &prng_clk.c },
4180 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4181 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4182 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4183 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004184 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4185 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4186 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004187 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4188 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4189 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4190 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4191 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4192 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4193 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4194 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4195 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4196 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004197 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004198 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4199
4200 { TEST_PER_HS(0x07), &afab_clk.c },
4201 { TEST_PER_HS(0x07), &afab_a_clk.c },
4202 { TEST_PER_HS(0x18), &sfab_clk.c },
4203 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004204 { TEST_PER_HS(0x26), &q6sw_clk },
4205 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004206 { TEST_PER_HS(0x2A), &adm0_clk.c },
4207 { TEST_PER_HS(0x34), &ebi1_clk.c },
4208 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004209 { TEST_PER_HS(0x48), &qdss_at_clk.c },
4210 { TEST_PER_HS(0x49), &qdss_pclkdbg_clk.c },
4211 { TEST_PER_HS(0x4A), &qdss_traceclkin_clk.c },
4212 { TEST_PER_HS(0x4B), &qdss_tsctr_clk.c },
4213 { TEST_PER_HS(0x4F), &qdss_stm_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004214 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004215
4216 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4217 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4218 { TEST_MM_LS(0x02), &cam1_clk.c },
4219 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004220 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004221 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4222 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4223 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4224 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4225 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4226 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4227 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4228 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4229 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4230 { TEST_MM_LS(0x12), &imem_p_clk.c },
4231 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4232 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4233 { TEST_MM_LS(0x16), &rot_p_clk.c },
4234 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4235 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4236 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4237 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4238 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4239 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4240 { TEST_MM_LS(0x1D), &cam0_clk.c },
4241 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4242 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4243 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4244 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4245 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4246 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4247 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4248 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004249 { TEST_MM_LS(0x27), &cam2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004250
4251 { TEST_MM_HS(0x00), &csi0_clk.c },
4252 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004253 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004254 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4255 { TEST_MM_HS(0x06), &vfe_clk.c },
4256 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4257 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4258 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4259 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4260 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4261 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4262 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4263 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4264 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4265 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4266 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4267 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4268 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4269 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4270 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4271 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4272 { TEST_MM_HS(0x1A), &mdp_clk.c },
4273 { TEST_MM_HS(0x1B), &rot_clk.c },
4274 { TEST_MM_HS(0x1C), &vpe_clk.c },
4275 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4276 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4277 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4278 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4279 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4280 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4281 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4282 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4283 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4284 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4285 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004286 { TEST_MM_HS(0x2D), &csi2_clk.c },
4287 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4288 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4289 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4290 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4291 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004292
4293 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4294 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4295 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4296 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4297 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4298 { TEST_LPA(0x14), &pcm_clk.c },
4299 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004300
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004301 { TEST_LPA_HS(0x00), &q6_func_clk },
4302
Matt Wagantall8b38f942011-08-02 18:23:18 -07004303 { TEST_CPUL2(0x1), &l2_m_clk },
4304 { TEST_CPUL2(0x2), &krait0_m_clk },
4305 { TEST_CPUL2(0x3), &krait1_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004306};
4307
4308static struct measure_sel *find_measure_sel(struct clk *clk)
4309{
4310 int i;
4311
4312 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4313 if (measure_mux[i].clk == clk)
4314 return &measure_mux[i];
4315 return NULL;
4316}
4317
Matt Wagantall8b38f942011-08-02 18:23:18 -07004318static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004319{
4320 int ret = 0;
4321 u32 clk_sel;
4322 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004323 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004324 unsigned long flags;
4325
4326 if (!parent)
4327 return -EINVAL;
4328
4329 p = find_measure_sel(parent);
4330 if (!p)
4331 return -EINVAL;
4332
4333 spin_lock_irqsave(&local_clock_reg_lock, flags);
4334
Matt Wagantall8b38f942011-08-02 18:23:18 -07004335 /*
4336 * Program the test vector, measurement period (sample_ticks)
4337 * and scaling multiplier.
4338 */
4339 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004340 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004341 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004342 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4343 case TEST_TYPE_PER_LS:
4344 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4345 break;
4346 case TEST_TYPE_PER_HS:
4347 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4348 break;
4349 case TEST_TYPE_MM_LS:
4350 writel_relaxed(0x4030D97, CLK_TEST_REG);
4351 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4352 break;
4353 case TEST_TYPE_MM_HS:
4354 writel_relaxed(0x402B800, CLK_TEST_REG);
4355 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4356 break;
4357 case TEST_TYPE_LPA:
4358 writel_relaxed(0x4030D98, CLK_TEST_REG);
4359 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4360 LCC_CLK_LS_DEBUG_CFG_REG);
4361 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004362 case TEST_TYPE_LPA_HS:
4363 writel_relaxed(0x402BC00, CLK_TEST_REG);
4364 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4365 LCC_CLK_HS_DEBUG_CFG_REG);
4366 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004367 case TEST_TYPE_CPUL2:
4368 writel_relaxed(0x4030400, CLK_TEST_REG);
4369 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4370 clk->sample_ticks = 0x4000;
4371 clk->multiplier = 2;
4372 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004373 default:
4374 ret = -EPERM;
4375 }
4376 /* Make sure test vector is set before starting measurements. */
4377 mb();
4378
4379 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4380
4381 return ret;
4382}
4383
4384/* Sample clock for 'ticks' reference clock ticks. */
4385static u32 run_measurement(unsigned ticks)
4386{
4387 /* Stop counters and set the XO4 counter start value. */
4388 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4389 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4390
4391 /* Wait for timer to become ready. */
4392 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4393 cpu_relax();
4394
4395 /* Run measurement and wait for completion. */
4396 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4397 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4398 cpu_relax();
4399
4400 /* Stop counters. */
4401 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4402
4403 /* Return measured ticks. */
4404 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4405}
4406
4407
4408/* Perform a hardware rate measurement for a given clock.
4409 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004410static unsigned measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004411{
4412 unsigned long flags;
4413 u32 pdm_reg_backup, ringosc_reg_backup;
4414 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004415 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004416 unsigned ret;
4417
4418 spin_lock_irqsave(&local_clock_reg_lock, flags);
4419
4420 /* Enable CXO/4 and RINGOSC branch and root. */
4421 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4422 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4423 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4424 writel_relaxed(0xA00, RINGOSC_NS_REG);
4425
4426 /*
4427 * The ring oscillator counter will not reset if the measured clock
4428 * is not running. To detect this, run a short measurement before
4429 * the full measurement. If the raw results of the two are the same
4430 * then the clock must be off.
4431 */
4432
4433 /* Run a short measurement. (~1 ms) */
4434 raw_count_short = run_measurement(0x1000);
4435 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004436 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004437
4438 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4439 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4440
4441 /* Return 0 if the clock is off. */
4442 if (raw_count_full == raw_count_short)
4443 ret = 0;
4444 else {
4445 /* Compute rate in Hz. */
4446 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004447 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4448 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004449 }
4450
4451 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004452 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004453 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4454
4455 return ret;
4456}
4457#else /* !CONFIG_DEBUG_FS */
4458static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4459{
4460 return -EINVAL;
4461}
4462
4463static unsigned measure_clk_get_rate(struct clk *clk)
4464{
4465 return 0;
4466}
4467#endif /* CONFIG_DEBUG_FS */
4468
4469static struct clk_ops measure_clk_ops = {
4470 .set_parent = measure_clk_set_parent,
4471 .get_rate = measure_clk_get_rate,
4472 .is_local = local_clk_is_local,
4473};
4474
Matt Wagantall8b38f942011-08-02 18:23:18 -07004475static struct measure_clk measure_clk = {
4476 .c = {
4477 .dbg_name = "measure_clk",
4478 .ops = &measure_clk_ops,
4479 CLK_INIT(measure_clk.c),
4480 },
4481 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004482};
4483
Stephen Boyd94625ef2011-07-12 17:06:01 -07004484static struct clk_lookup msm_clocks_8960_v1[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004485 CLK_LOOKUP("cxo", cxo_clk.c, NULL),
4486 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4487 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4488 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
Matt Wagantall8b38f942011-08-02 18:23:18 -07004489 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004490
4491 CLK_LOOKUP("afab_clk", afab_clk.c, NULL),
4492 CLK_LOOKUP("afab_a_clk", afab_a_clk.c, NULL),
4493 CLK_LOOKUP("cfpb_clk", cfpb_clk.c, NULL),
4494 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, NULL),
4495 CLK_LOOKUP("dfab_clk", dfab_clk.c, NULL),
4496 CLK_LOOKUP("dfab_a_clk", dfab_a_clk.c, NULL),
4497 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
4498 CLK_LOOKUP("ebi1_a_clk", ebi1_a_clk.c, NULL),
4499 CLK_LOOKUP("mmfab_clk", mmfab_clk.c, NULL),
4500 CLK_LOOKUP("mmfab_a_clk", mmfab_a_clk.c, NULL),
4501 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
4502 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, NULL),
4503 CLK_LOOKUP("sfab_clk", sfab_clk.c, NULL),
4504 CLK_LOOKUP("sfab_a_clk", sfab_a_clk.c, NULL),
4505 CLK_LOOKUP("sfpb_clk", sfpb_clk.c, NULL),
4506 CLK_LOOKUP("sfpb_a_clk", sfpb_a_clk.c, NULL),
4507
Matt Wagantalle2522372011-08-17 14:52:21 -07004508 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, NULL),
4509 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, NULL),
4510 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, NULL),
4511 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, NULL),
4512 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
4513 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
4514 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, NULL),
4515 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, NULL),
4516 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, NULL),
4517 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, NULL),
4518 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, NULL),
4519 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004520 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004521 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004522 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
4523 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004524 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, NULL),
4525 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, NULL),
4526 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, NULL),
4527 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, NULL),
4528 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004529 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004530 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004531 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004532 CLK_LOOKUP("pdm_clk", pdm_clk.c, NULL),
Matt Wagantalld86d6832011-08-17 14:06:55 -07004533 CLK_LOOKUP("mem_clk", pmem_clk.c, NULL),
Matt Wagantallc1205292011-08-11 17:19:31 -07004534 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07004535 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4536 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4537 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4538 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
4539 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004540 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07004541 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004542 CLK_LOOKUP("tssc_clk", tssc_clk.c, NULL),
4543 CLK_LOOKUP("usb_hs_clk", usb_hs1_xcvr_clk.c, NULL),
4544 CLK_LOOKUP("usb_phy_clk", usb_phy0_clk.c, NULL),
4545 CLK_LOOKUP("usb_fs_clk", usb_fs1_xcvr_clk.c, NULL),
4546 CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
4547 CLK_LOOKUP("usb_fs_src_clk", usb_fs1_src_clk.c, NULL),
4548 CLK_LOOKUP("usb_fs_clk", usb_fs2_xcvr_clk.c, NULL),
4549 CLK_LOOKUP("usb_fs_sys_clk", usb_fs2_sys_clk.c, NULL),
4550 CLK_LOOKUP("usb_fs_src_clk", usb_fs2_src_clk.c, NULL),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07004551 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
4552 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004553 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004554 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004555 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004556 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
4557 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07004558 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
4559 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004560 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, NULL),
4561 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, NULL),
4562 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004563 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantall62cf63e2011-08-17 16:34:47 -07004564 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07004565 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -07004566 CLK_LOOKUP("iface_clk", tsif_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004567 CLK_LOOKUP("usb_fs_pclk", usb_fs1_p_clk.c, NULL),
4568 CLK_LOOKUP("usb_fs_pclk", usb_fs2_p_clk.c, NULL),
4569 CLK_LOOKUP("usb_hs_pclk", usb_hs1_p_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07004570 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4571 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4572 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4573 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
4574 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07004575 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
4576 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004577 CLK_LOOKUP("pmic_arb_pclk", pmic_arb0_p_clk.c, NULL),
4578 CLK_LOOKUP("pmic_arb_pclk", pmic_arb1_p_clk.c, NULL),
4579 CLK_LOOKUP("pmic_ssbi2", pmic_ssbi2_clk.c, NULL),
4580 CLK_LOOKUP("rpm_msg_ram_pclk", rpm_msg_ram_p_clk.c, NULL),
4581 CLK_LOOKUP("amp_clk", amp_clk.c, NULL),
4582 CLK_LOOKUP("cam_clk", cam0_clk.c, NULL),
4583 CLK_LOOKUP("cam_clk", cam1_clk.c, NULL),
4584 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_imx074.0"),
4585 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_ov2720.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004586 CLK_LOOKUP("cam_clk", cam0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004587 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, NULL),
4588 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, NULL),
4589 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004590 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004591 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_camera_ov2720.0"),
4592 CLK_LOOKUP("csi_clk", csi0_clk.c, NULL),
4593 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
4594 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004595 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004596 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_camera_ov2720.0"),
4597 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, NULL),
4598 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, NULL),
4599 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_imx074.0"),
Kevin Chandfecce22011-07-13 10:52:41 -07004600 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_camera_qs_mt9p017.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004601 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_camera_ov2720.0"),
4602 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, NULL),
4603 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, NULL),
4604 CLK_LOOKUP("csiphy_timer_src_clk", csiphy_timer_src_clk.c, NULL),
4605 CLK_LOOKUP("csi0phy_timer_clk", csi0phy_timer_clk.c, NULL),
4606 CLK_LOOKUP("csi1phy_timer_clk", csi1phy_timer_clk.c, NULL),
4607 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
4608 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
4609 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
4610 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
4611 CLK_LOOKUP("gfx2d0_clk", gfx2d0_clk.c, NULL),
4612 CLK_LOOKUP("gfx2d1_clk", gfx2d1_clk.c, NULL),
4613 CLK_LOOKUP("gfx3d_clk", gfx3d_clk.c, NULL),
4614 CLK_LOOKUP("ijpeg_axi_clk", ijpeg_axi_clk.c, NULL),
4615 CLK_LOOKUP("imem_axi_clk", imem_axi_clk.c, NULL),
4616 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
4617 CLK_LOOKUP("jpegd_clk", jpegd_clk.c, NULL),
4618 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
4619 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
4620 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07004621 CLK_LOOKUP("qdss_pclk", qdss_p_clk.c, NULL),
4622 CLK_LOOKUP("qdss_at_clk", qdss_at_clk.c, NULL),
4623 CLK_LOOKUP("qdss_pclkdbg_clk", qdss_pclkdbg_clk.c, NULL),
4624 CLK_LOOKUP("qdss_traceclkin_clk", qdss_traceclkin_clk.c, NULL),
4625 CLK_LOOKUP("qdss_tsctr_clk", qdss_tsctr_clk.c, NULL),
4626 CLK_LOOKUP("qdss_stm_clk", qdss_stm_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004627 CLK_LOOKUP("rot_clk", rot_clk.c, NULL),
4628 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
4629 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
4630 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
4631 CLK_LOOKUP("vcodec_clk", vcodec_clk.c, NULL),
4632 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
4633 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
4634 CLK_LOOKUP("hdmi_app_clk", hdmi_app_clk.c, NULL),
4635 CLK_LOOKUP("vpe_clk", vpe_clk.c, NULL),
4636 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07004637 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004638 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
4639 CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c, NULL),
4640 CLK_LOOKUP("rot_axi_clk", rot_axi_clk.c, NULL),
4641 CLK_LOOKUP("vcodec_axi_clk", vcodec_axi_clk.c, NULL),
4642 CLK_LOOKUP("vcodec_axi_a_clk", vcodec_axi_a_clk.c, NULL),
4643 CLK_LOOKUP("vcodec_axi_b_clk", vcodec_axi_b_clk.c, NULL),
4644 CLK_LOOKUP("vpe_axi_clk", vpe_axi_clk.c, NULL),
4645 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Matt Wagantallc23eee92011-08-16 23:06:52 -07004646 CLK_LOOKUP("csi_pclk", csi_p_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004647 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
4648 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
4649 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
4650 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
4651 CLK_LOOKUP("gfx2d0_pclk", gfx2d0_p_clk.c, NULL),
4652 CLK_LOOKUP("gfx2d1_pclk", gfx2d1_p_clk.c, NULL),
4653 CLK_LOOKUP("gfx3d_pclk", gfx3d_p_clk.c, NULL),
4654 CLK_LOOKUP("hdmi_m_pclk", hdmi_m_p_clk.c, NULL),
4655 CLK_LOOKUP("hdmi_s_pclk", hdmi_s_p_clk.c, NULL),
4656 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
4657 CLK_LOOKUP("jpegd_pclk", jpegd_p_clk.c, NULL),
4658 CLK_LOOKUP("imem_pclk", imem_p_clk.c, NULL),
4659 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
4660 CLK_LOOKUP("smmu_pclk", smmu_p_clk.c, NULL),
4661 CLK_LOOKUP("rotator_pclk", rot_p_clk.c, NULL),
4662 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
4663 CLK_LOOKUP("vcodec_pclk", vcodec_p_clk.c, NULL),
4664 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, NULL),
4665 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, NULL),
4666 CLK_LOOKUP("mi2s_bit_clk", mi2s_bit_clk.c, NULL),
4667 CLK_LOOKUP("mi2s_osr_clk", mi2s_osr_clk.c, NULL),
4668 CLK_LOOKUP("i2s_mic_bit_clk", codec_i2s_mic_bit_clk.c, NULL),
4669 CLK_LOOKUP("i2s_mic_osr_clk", codec_i2s_mic_osr_clk.c, NULL),
4670 CLK_LOOKUP("i2s_mic_bit_clk", spare_i2s_mic_bit_clk.c, NULL),
4671 CLK_LOOKUP("i2s_mic_osr_clk", spare_i2s_mic_osr_clk.c, NULL),
4672 CLK_LOOKUP("i2s_spkr_bit_clk", codec_i2s_spkr_bit_clk.c, NULL),
4673 CLK_LOOKUP("i2s_spkr_osr_clk", codec_i2s_spkr_osr_clk.c, NULL),
4674 CLK_LOOKUP("i2s_spkr_bit_clk", spare_i2s_spkr_bit_clk.c, NULL),
4675 CLK_LOOKUP("i2s_spkr_osr_clk", spare_i2s_spkr_osr_clk.c, NULL),
4676 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
4677 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
4678 CLK_LOOKUP("audio_slimbus_clk", audio_slimbus_clk.c, NULL),
4679 CLK_LOOKUP("iommu_clk", jpegd_axi_clk.c, "msm_iommu.0"),
4680 CLK_LOOKUP("iommu_clk", vpe_axi_clk.c, "msm_iommu.1"),
4681 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.2"),
4682 CLK_LOOKUP("iommu_clk", mdp_axi_clk.c, "msm_iommu.3"),
4683 CLK_LOOKUP("iommu_clk", rot_axi_clk.c, "msm_iommu.4"),
4684 CLK_LOOKUP("iommu_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
4685 CLK_LOOKUP("iommu_clk", vfe_axi_clk.c, "msm_iommu.6"),
4686 CLK_LOOKUP("iommu_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
4687 CLK_LOOKUP("iommu_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
4688 CLK_LOOKUP("iommu_clk", gfx3d_clk.c, "msm_iommu.9"),
4689 CLK_LOOKUP("iommu_clk", gfx2d0_clk.c, "msm_iommu.10"),
4690 CLK_LOOKUP("iommu_clk", gfx2d1_clk.c, "msm_iommu.11"),
4691 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
4692 CLK_LOOKUP("dfab_usb_hs_clk", dfab_usb_hs_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -07004693 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
4694 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
4695 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
4696 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
4697 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07004698 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004699
4700 CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -07004701 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07004702
4703 CLK_LOOKUP("l2_mclk", l2_m_clk, NULL),
4704 CLK_LOOKUP("krait0_mclk", krait0_m_clk, NULL),
4705 CLK_LOOKUP("krait1_mclk", krait1_m_clk, NULL),
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004706 CLK_LOOKUP("q6sw_clk", q6sw_clk, NULL),
4707 CLK_LOOKUP("q6fw_clk", q6fw_clk, NULL),
4708 CLK_LOOKUP("q6_func_clk", q6_func_clk, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004709};
4710
Stephen Boyd94625ef2011-07-12 17:06:01 -07004711static struct clk_lookup msm_clocks_8960_v2[] __initdata = {
4712 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
4713 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
4714 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
4715 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, NULL),
4716 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, NULL),
4717 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, NULL),
4718 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
4719 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
4720 CLK_LOOKUP("usb_hsic_xcvr_fs_clk", usb_hsic_xcvr_fs_clk.c, NULL),
4721 CLK_LOOKUP("usb_hsic_hsic_clk", usb_hsic_hsic_clk.c, NULL),
4722 CLK_LOOKUP("usb_hsic_hsio_cal_clk", usb_hsic_hsio_cal_clk.c, NULL),
4723 CLK_LOOKUP("usb_hsic_system_clk", usb_hsic_system_clk.c, NULL),
4724 CLK_LOOKUP("usb_hsic_p_clk", usb_hsic_p_clk.c, NULL),
4725};
4726
4727/* Add v2 clocks dynamically at runtime */
4728static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_v1) +
4729 ARRAY_SIZE(msm_clocks_8960_v2)];
4730
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004731/*
4732 * Miscellaneous clock register initializations
4733 */
4734
4735/* Read, modify, then write-back a register. */
4736static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
4737{
4738 uint32_t regval = readl_relaxed(reg);
4739 regval &= ~mask;
4740 regval |= val;
4741 writel_relaxed(regval, reg);
4742}
4743
4744static void __init reg_init(void)
4745{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004746 /* Deassert MM SW_RESET_ALL signal. */
4747 writel_relaxed(0, SW_RESET_ALL_REG);
4748
4749 /* Initialize MM AHB registers: Enable the FPB clock and disable HW
4750 * gating for all clocks. Also set VFE_AHB's FORCE_CORE_ON bit to
4751 * prevent its memory from being collapsed when the clock is halted.
4752 * The sleep and wake-up delays are set to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004753 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
4754 writel_relaxed(0x000007F9, AHB_EN2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004755
4756 /* Deassert all locally-owned MM AHB resets. */
4757 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
4758
4759 /* Initialize MM AXI registers: Enable HW gating for all clocks that
4760 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
4761 * delays to safe values. */
4762 /* TODO: Enable HW Gating */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004763 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
4764 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
4765 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
4766 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
4767 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004768
4769 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
4770 * memories retain state even when not clocked. Also, set sleep and
4771 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07004772 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
4773 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
4774 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
4775 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
4776 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
4777 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
4778 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
4779 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
4780 rmwreg(0x80FF0000, GFX3D_CC_REG, 0xE0FF0010);
4781 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
4782 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
4783 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
4784 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
4785 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
4786 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
4787 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
4788 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
4789 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07004790 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07004791 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004792
4793 /* De-assert MM AXI resets to all hardware blocks. */
4794 writel_relaxed(0, SW_RESET_AXI_REG);
4795
4796 /* Deassert all MM core resets. */
4797 writel_relaxed(0, SW_RESET_CORE_REG);
4798
4799 /* Reset 3D core once more, with its clock enabled. This can
4800 * eventually be done as part of the GDFS footswitch driver. */
4801 clk_set_rate(&gfx3d_clk.c, 27000000);
4802 clk_enable(&gfx3d_clk.c);
4803 writel_relaxed(BIT(12), SW_RESET_CORE_REG);
4804 mb();
4805 udelay(5);
4806 writel_relaxed(0, SW_RESET_CORE_REG);
4807 /* Make sure reset is de-asserted before clock is disabled. */
4808 mb();
4809 clk_disable(&gfx3d_clk.c);
4810
4811 /* Enable TSSC and PDM PXO sources. */
4812 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
4813 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
4814
4815 /* Source SLIMBus xo src from slimbus reference clock */
4816 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
4817
4818 /* Source the dsi_byte_clks from the DSI PHY PLLs */
4819 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
4820 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
4821}
4822
Stephen Boyd94625ef2011-07-12 17:06:01 -07004823struct clock_init_data msm8960_clock_init_data __initdata;
4824
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004825/* Local clock driver initialization. */
Stephen Boydbb600ae2011-08-02 20:11:40 -07004826static void __init msm8960_clock_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004827{
Stephen Boyd94625ef2011-07-12 17:06:01 -07004828 size_t num_lookups = ARRAY_SIZE(msm_clocks_8960_v1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004829 xo_pxo = msm_xo_get(MSM_XO_PXO, "clock-8960");
4830 if (IS_ERR(xo_pxo)) {
4831 pr_err("%s: msm_xo_get(PXO) failed.\n", __func__);
4832 BUG();
4833 }
4834 xo_cxo = msm_xo_get(MSM_XO_TCXO_D0, "clock-8960");
4835 if (IS_ERR(xo_cxo)) {
4836 pr_err("%s: msm_xo_get(CXO) failed.\n", __func__);
4837 BUG();
4838 }
4839
Stephen Boyd94625ef2011-07-12 17:06:01 -07004840 memcpy(msm_clocks_8960, msm_clocks_8960_v1, sizeof(msm_clocks_8960_v1));
4841 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
Tianyi Goubaf6d342011-08-30 21:49:02 -07004842 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_v2;
Stephen Boyd94625ef2011-07-12 17:06:01 -07004843 memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_v1),
4844 msm_clocks_8960_v2, sizeof(msm_clocks_8960_v2));
4845 num_lookups = ARRAY_SIZE(msm_clocks_8960);
4846 }
4847 msm8960_clock_init_data.size = num_lookups;
4848
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004849 soc_update_sys_vdd = msm8960_update_sys_vdd;
4850 local_vote_sys_vdd(HIGH);
4851
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07004852 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004853
4854 /* Initialize clock registers. */
4855 reg_init();
4856
4857 /* Initialize rates for clocks that only support one. */
4858 clk_set_rate(&pdm_clk.c, 27000000);
4859 clk_set_rate(&prng_clk.c, 64000000);
4860 clk_set_rate(&mdp_vsync_clk.c, 27000000);
4861 clk_set_rate(&tsif_ref_clk.c, 105000);
4862 clk_set_rate(&tssc_clk.c, 27000000);
4863 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
4864 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
4865 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07004866 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
4867 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
4868 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004869
4870 /*
4871 * The halt status bits for PDM and TSSC may be incorrect at boot.
4872 * Toggle these clocks on and off to refresh them.
4873 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07004874 rcg_clk_enable(&pdm_clk.c);
4875 rcg_clk_disable(&pdm_clk.c);
4876 rcg_clk_enable(&tssc_clk.c);
4877 rcg_clk_disable(&tssc_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004878
4879 if (machine_is_msm8960_sim()) {
4880 clk_set_rate(&sdc1_clk.c, 48000000);
4881 clk_enable(&sdc1_clk.c);
4882 clk_enable(&sdc1_p_clk.c);
4883 clk_set_rate(&sdc3_clk.c, 48000000);
4884 clk_enable(&sdc3_clk.c);
4885 clk_enable(&sdc3_p_clk.c);
4886 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004887}
4888
Stephen Boydbb600ae2011-08-02 20:11:40 -07004889static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004890{
4891 return local_unvote_sys_vdd(HIGH);
4892}
Stephen Boydbb600ae2011-08-02 20:11:40 -07004893
4894struct clock_init_data msm8960_clock_init_data __initdata = {
4895 .table = msm_clocks_8960,
4896 .size = ARRAY_SIZE(msm_clocks_8960),
4897 .init = msm8960_clock_init,
4898 .late_init = msm8960_clock_late_init,
4899};